More work on uart_rx and uart_tb

Author: oskarwires

.gitignore

@@ -1,2 +1,3 @@
 xcelium.d
 xrun.*
+*.vcd

filelist.f

@@ -2,5 +2,6 @@
 rtl/fifo_ctrl.sv
 rtl/fifo_mem.sv
 rtl/uart.sv
+rtl/uart_rx.sv
 rtl/uart_prescaler.sv
-test/uart_prescaler_tb.sv
+test/uart_tb.sv

rtl/uart.sv

@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
 // Configurable UART module
-module uart_axi #(
+module uart #(
   parameter FifoDepth = 8
 )(
   /* Main Signals */
@@ -20,8 +20,10 @@ module uart_axi #(
   input  logic        i_cts,
   output logic        o_rts    
 );
-  logic fifo_empty;  
+  logic prescaler_half, prescaler_strobe, prescaler_en;  
 
+  /*
+  logic fifo_empty;  
   fifo #(
     .DataWidth(8),
     .Depth(FifoDepth)
@@ -35,8 +37,28 @@ module uart_axi #(
     .o_full(),
     .o_empty(fifo_empty)
   );
+  */
+
+  uart_rx uart_rx (
+    .i_clk,
+    .i_rst_n,
+    .i_rx,
+    .o_rx_data(),
+    .i_strobe(prescaler_strobe),
+    .i_half(prescaler_half),
+    .o_prescaler_en(prescaler_en)
+  );
+
+  uart_prescaler uart_prescaler (
+    .i_clk,
+    .i_rst_n,
+    .i_en(prescaler_en),
+    .i_scaler(16'd8),
+    .o_strobe(prescaler_strobe),
+    .o_half(prescaler_half)
+  );
 
-  assign o_rx_rdy = ~fifo_empty;
+  //assign o_rx_rdy = ~fifo_empty;
 
 endmodule
 

rtl/uart_prescaler.sv

@@ -1,7 +1,8 @@
 `timescale 1ns / 1ps
 // Scales the clock signal according to scale factor
 module uart_prescaler #(
-  parameter InitialDivider = 16
+  parameter InitialDivider = 16,
+  parameter OverSample = 8
 )(
   input  logic        i_clk,
   input  logic        i_rst_n,
@@ -10,6 +11,7 @@ module uart_prescaler #(
   output logic        o_strobe, /* Strobe signal */
   output logic        o_half    /* Halfway signal */
 );
+
   logic [15:0] counter;
 
   /* Counter Logic */
@@ -18,7 +20,7 @@ module uart_prescaler #(
       counter <= '0;
     end else begin
       if (i_en) begin
-        if (counter == (i_scaler - 16'b1)) counter <= '0;
+        if (counter == (i_scaler - 16'd1)) counter <= '0;
         else counter <= counter + 16'b1;
       end
     end
@@ -29,7 +31,7 @@ module uart_prescaler #(
     if (!i_rst_n) begin
       o_half <= 1'b0;
     end else begin
-      o_half <= (counter == (i_scaler[15:1] - 16'b1));
+      o_half <= (counter == (i_scaler[15:1] - 16'd2));
     end
   end
 
@@ -38,7 +40,7 @@ module uart_prescaler #(
     if (!i_rst_n) begin
       o_strobe <= 1'b0;
     end else begin
-      o_strobe <= (counter == (i_scaler - 16'b1));
+      o_strobe <= (counter == (i_scaler - 16'd2));
     end
   end
 

rtl/uart_rx.sv

@@ -1,4 +1,7 @@
 module uart_rx #(
+  parameter Parity = 1'b0,
+  parameter StopBit = 1'b1,
+  parameter OverSample = 8
   //params
 )(
   //i/o
@@ -11,19 +14,28 @@ module uart_rx #(
   /* Sample Timing */
   input  logic       i_strobe,
   input  logic       i_half,
-  output logic       o_prescaler_en 
+  output logic       o_prescaler_en,
+  output logic       o_parity_error,
+  output logic       o_stop_bit_error 
 );
 
+  localparam counter_width = $clog2(OverSample);
+ 
   typedef enum logic [2:0] {
-    RESET = 3'b000,
-    WAIT  = 2'b001,
-    LOAD  = 3'b010,
-    STOP  = 3'b011,
-    READY = 3'b100
+    RESET  = 3'b000,
+    WAIT   = 2'b001,
+    LOAD   = 3'b010,
+    PARITY = 3'b011, 
+    STOP   = 3'b100,
+    READY  = 3'b101
   } states_t;
 
   states_t curr_state, next_state;
-  logic [2:0] counter;
+
+  logic [counter_width:0] counter;
+  logic counter_rst_n;
+
+  logic parity_bit;
 
   // State controller
   always_ff @(posedge i_clk) begin
@@ -33,45 +45,59 @@ module uart_rx #(
 
   // Next State Logic Controller
   always_comb begin
-    unique case (state)
+    unique case (curr_state)
       RESET:
         next_state   = WAIT;
       WAIT:
-        if (serial_in == '0)
+        if (i_rx == '0)
           next_state = LOAD;
         else 
           next_state = WAIT;
       LOAD:
         if (counter == '0)
-          next_state = STOP;
+          generate
+             case (Parity)
+               0: next_state = STOP;
+               1: next_state = PARITY;
+             endcase
+          endgenerate
         else 
           next_state = LOAD;
+      PARITY:
+        if (i_half) 
+          next_state = STOP;
+        else
+          next_state = PARITY; 
       STOP:
-        // wait for stop bit
+        if (i_half && i_rx) // halfway strobe AND rx == 1 (stop bit)
+          next_state = READY;
+        else
+          next_state = STOP;
       READY: 
         next_state   = WAIT;
     endcase
   end
 
   always_comb begin
-    unique case (state)
-      RESET: 
-      WAIT:  
-      LOAD:  
-      STOP:  
-      READY: 
+    unique case (curr_state)
+      RESET:  {o_prescaler_en, counter_rst_n} = 2'b00;
+      WAIT:   {o_prescaler_en, counter_rst_n} = 2'b00;
+      LOAD:   {o_prescaler_en, counter_rst_n} = 2'b11;
+      PARITY: {o_prescaler_en, counter_rst_n} = 2'b10;
+      STOP:   {o_prescaler_en, counter_rst_n} = 2'b10;
+      READY:  {o_prescaler_en, counter_rst_n} = 2'b00;
     endcase
   end
 
   always_ff @(posedge i_clk)
     if (!i_rst_n)
       o_rx_data <= 0;
     else if (i_half)
-      o_rx_data <= {rx, o_rx_data[7:1]};
+      o_rx_data <= {i_rx, o_rx_data[7:1]};
 
   always_ff @(posedge i_clk)
-    if (!i_rst_n)
-      counter <= '0;
+    if (!counter_rst_n)
+      counter <= '1;
     else if (i_half)
       counter <= counter - 3'b1;