1 file changed
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-1
lines changedSubmodule FPGA_PRIMITIVES_MODELS updated 35 files
- sim_models/primitives_mapping/FIFO/fifo18kx2_to_rs_tdp_36k_mapping.v+2-5
- sim_models/primitives_mapping/FIFO/fifo36k_to_rs_tdp_36k_mapping.v+2-4
- sim_models/tb/FIFO18KX2_tb.v+165-2.6k
- sim_models/verilog/BOOT_CLOCK.v+1-3
- sim_models/verilog/CARRY.v+7-15
- sim_models/verilog/CLK_BUF.v+5-9
- sim_models/verilog/DFFNRE.v+54-58
- sim_models/verilog/DFFRE.v+56-66
- sim_models/verilog/DLY_SEL_DECODER.v+1-88
- sim_models/verilog/DLY_VALUE_MUX.v-51
- sim_models/verilog/FCLK_BUF.v+5-9
- sim_models/verilog/FIFO18KX2.v+74-958
- sim_models/verilog/I_BUF.v+5-10
- sim_models/verilog/I_BUF_DS.v+3-8
- sim_models/verilog/I_DDR.v-40
- sim_models/verilog/I_DELAY.v-37
- sim_models/verilog/I_FAB.v-9
- sim_models/verilog/I_SERDES.v-61
- sim_models/verilog/LUT1.v-10
- sim_models/verilog/LUT2.v-10
- sim_models/verilog/LUT3.v-11
- sim_models/verilog/LUT4.v-10
- sim_models/verilog/LUT5.v-10
- sim_models/verilog/LUT6.v-9
- sim_models/verilog/MIPI_RX.v+9-4
- sim_models/verilog/O_BUF.v+5-10
- sim_models/verilog/O_BUFT.v+1-12
- sim_models/verilog/O_BUFT_DS.v-11
- sim_models/verilog/O_BUF_DS.v+5-10
- sim_models/verilog/O_DDR.v-41
- sim_models/verilog/O_DELAY.v-36
- sim_models/verilog/O_FAB.v-11
- sim_models/verilog/O_SERDES.v+1-54
- sim_models/verilog/PLL.v-26
- tb/FIFO18KX2/FIFO18KX2_tb.v+169-2.6k
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