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-1
lines changedSubmodule FPGA_PRIMITIVES_MODELS updated 37 files
- blackbox_models/cell_sim_blackbox.v+17
- sim_models/primitives_mapping/FIFO/fifo18kx2_to_rs_tdp_36k_mapping.v+5-2
- sim_models/primitives_mapping/FIFO/fifo36k_to_rs_tdp_36k_mapping.v+4-2
- sim_models/tb/FIFO18KX2_tb.v+2.1k-475
- sim_models/verilog/BOOT_CLOCK.v+3-1
- sim_models/verilog/CARRY.v+15-7
- sim_models/verilog/CARRY_BREAK.v+53
- sim_models/verilog/CLK_BUF.v+9-5
- sim_models/verilog/DFFNRE.v+58-54
- sim_models/verilog/DFFRE.v+66-56
- sim_models/verilog/DLY_SEL_DECODER.v+88-1
- sim_models/verilog/DLY_VALUE_MUX.v+53
- sim_models/verilog/FCLK_BUF.v+9-5
- sim_models/verilog/FIFO18KX2.v+1.6k-224
- sim_models/verilog/I_BUF.v+10-5
- sim_models/verilog/I_BUF_DS.v+8-3
- sim_models/verilog/I_DDR.v+40
- sim_models/verilog/I_DELAY.v+37
- sim_models/verilog/I_FAB.v+9
- sim_models/verilog/I_SERDES.v+61
- sim_models/verilog/LUT1.v+10
- sim_models/verilog/LUT2.v+10
- sim_models/verilog/LUT3.v+11
- sim_models/verilog/LUT4.v+10
- sim_models/verilog/LUT5.v+10
- sim_models/verilog/LUT6.v+9
- sim_models/verilog/MIPI_RX.v+4-9
- sim_models/verilog/O_BUF.v+10-5
- sim_models/verilog/O_BUFT.v+12-1
- sim_models/verilog/O_BUFT_DS.v+11
- sim_models/verilog/O_BUF_DS.v+10-5
- sim_models/verilog/O_DDR.v+41
- sim_models/verilog/O_DELAY.v+36
- sim_models/verilog/O_FAB.v+11
- sim_models/verilog/O_SERDES.v+54-1
- sim_models/verilog/PLL.v+26
- tb/FIFO18KX2/FIFO18KX2_tb.v+2.1k-481
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