Added content and screenshots for results section & updated certain screenshots for updated text and logo changes on RPE (#282)

Author: MustafaAbdaal

docs/source/user_guide/FPGA.rst

@@ -61,7 +61,7 @@ The BRAM section is located directly below the clocking section.
 
 Selecting the BRAM section displays an empty table, click the "Add" button above the table to fill out the BRAM info.
 
-.. image:: figures/FPGA-figures-BRAM-input_BRAM_info.JPG
+.. image:: figures/FPGA-figures-BRAM-input_BRAM_info_v2.JPG
 
 .. image:: figures/FPGA-figures-BRAM-input_BRAM_ports_info.JPG
 
@@ -84,7 +84,7 @@ The DSP section is located directly below the FLE section.
 
 Selecting the DSP section displays an empty table, click the "Add" button above the table to fill out the DSP info.
 
-.. image:: figures/FPGA-figures-DSP-input_DSP_info.JPG
+.. image:: figures/FPGA-figures-DSP-input_DSP_info_v2.JPG
 
 1. Provide a name to label the DSP function within the hierarchy (optional)
 2. Enter the no. of DSP multipliers 

docs/source/user_guide/FPGA_index.rst

@@ -20,7 +20,7 @@ Then click on each enabled peripheral's action column button to configure the pe
 
 For each peripheral, select it's usage as well as performance. 
 
-*Note:* For PWM, selecting an IO is also required to drive the PWM signal.
+*Note: For PWM, selecting an IO is also required to drive the PWM signal.*
 
 BCPU - Boot Central Processing Unit
 #######################################
@@ -29,12 +29,12 @@ The BCPU section is found at the top of the SoC input section, to the left of th
 
 Selecting the BCPU section will display the name of the CPU "N22 RISC-V", followed by it's configuration fields.
 
-.. image:: figures/SoC-figures-BCPU-BPCU_selected.JPG
+.. image:: figures/SoC-figures-BCPU-BCPU_selected_v2.JPG
 
 Enable/Disable encryption using the checkbox.
 
 Select Boot Mode, SPI is selected by default. 
-*note:* SPI is currently the only available mode.
+*note: SPI is currently the only available mode.*
 
 Select Clock, BOOT CLK is selected by default.
 
@@ -72,7 +72,7 @@ Selecting the memory section will display a table below with the available memor
 
 For each memory, select it's usage, then Memory Type, followed by required Data Rate & channel width. 
 
-*Note:* All devices will have OCM - on chip memory, DDR memory is only available on specific devices.
+*Note: All devices will have OCM - on chip memory, DDR memory is only available on specific devices.*
 
 .. image:: figures/memory-figures-input_DDR_memory_info.JPG
 
@@ -83,7 +83,7 @@ The ACPU section is found on the top left of the SoC input display.
 
 .. image:: figures/SoC-figures-ACPU-ACPU_selected.JPG
 
-Selecting the ACPU section will display the name of the CPU, followed by it's operating frequency & Load selection. *Note:* Application CPU is not available on all devices.
+Selecting the ACPU section will display the name of the CPU, followed by it's operating frequency & Load selection. *Note: Application CPU is not available on all devices.*
 
 Toggle the ACPU Power toggle switch on left hand side to enable ACPU, then select the load required from the Load dropdown. 
 

docs/source/user_guide/SoC.rst

@@ -3,12 +3,44 @@ Analyzing Results
 ====================
 
 This section will document the results on Rapid Power Estimator.
+The Rapid Power Estimator provides a comprehensive power data display on the right hand side of the user interface.
+
+.. image:: figures/results-figures-Display.JPG
+
 
 FPGA Complex & Core Power
 #########################
 
+The FPGA Power Data is displayed below the save icon and top level module input field.
+
+.. image:: figures/results-figures-FPGA_Complex_and_Core_Power.JPG
+
+The Display shows each FPGA input section label with 2 columns for power in watts & the percentage of power used by each respective part of the FPGA design.
+
+The last 2 rows show FPGA Dynamic Power & FPGA Static Power. The power data in these rows is the sum of the respective static and dynamic power values from each of the FPGA input sections. 
+
+At the bottom of the display, an overall percentage is given along with a percentage bar, this shows the percentage of power being used by the FPGA within the overall FPGA SoC.
+
 Processing Complex (SoC) Power
 ##############################
 
+The SoC Power Data is displayed on the far right of the screen, to the right of FPGA Power Data display. 
+
+.. image:: figures/results-figures-SoC_Processing_Complex_Power.JPG
+
+The display shows each SoC input section label with 2 columns for power in watts & the percentage of power used by each respective part of the SoC's Processing Complex.
+
+The last 2 rows shows overall Dynamic & Static Power. The Power data in these rows is the sum of the respective static and dynamic power values from each of the SoC input sections. 
+
+At the bottom of the display, an overall percentage is given along with a percentage bar, this shows the percentage of power being used by the Processing Complex within the overall FPGA SoC.
+
+
 Overall Typical & Worst Case Power 
-##################################
+##################################
+
+The Overall power budget numbers are displayed at the top right hand side of the screen, above the Processing Complex Power Display.
+
+.. image:: figures/results-figures-Overal_Power_Typical_and_Worst.JPG
+
+The displays show power in watts on a typical operating temperature of 25 degrees celcius as well as a power in watts on a worst case operating temperature of 81 degrees celcius. 
+

docs/source/user_guide/SoC_index.rst

@@ -9,7 +9,7 @@ Launching RPE
 
 To launch the Rapid Power Estimator, simply navigate to your start menu and search for "Rapid Power Estimator". Once the application is found, click on the application icon to launch the tool.
 
-.. image:: figures/setup-figures-launching_RPE_from_windows_start_menu.JPG
+.. image:: figures/setup-figures-launching_RPE_from_windows_start_menu_v2.JPG
     :alt: RPE icon on windows start menu
 
 The Rapid Power Estimator will display the following screen upon launch.