Precise Synchronization of multiple PIO Blocks

[mungewell]

Previously I have been using irq(block, x) and irq(clear, x) to use IRQs to sync StateMachines within one PIO block, but I now have logic which is too large for a single block and need to sync multiple blocks - unfortunately the IRQs on one don't seem to visible on the other.

I can allocate a GPIO pin and use jmp(pin,) so that a StateMachine in EACH block has a sync'ed trigger reference, and I have also discovered I can (pretty much) sync the fractional dividers:

    # reset the clock-phases with CLKDIV_RESTART
    mem32[0x50200000] = 0x00000f00
    mem32[0x50300000] = 0x00000f00

This gets me within ~5.15us delta between PIO Block-1 and Block-2, which I assume is the CPU time taken to do the 2 writes to memory...
sync_test.py.txt

Does anyone have a solution to tweak out that last 5us, so they are EXACTLY aligned?

Background: My app is looking at timing, referenced to GPS 1PPS and 10MHz clock. I want to produce an encoded clock signal which is accurate as possible (ie not delayed even by 5us) .

[GitHubsSilverBullet]

Haven't tested it, but this should sync'em down to a few ns.

#!/micropython
# -*- coding: UTF-8 -*-
# vim: fileencoding=utf-8: ts=4: sw=4: expandtab:

@micropython.asm_thumb
def syncem(r0, r1):
    mov(r2, 0xf)
    mov(r3, 8)
    lsl(r2, r3)
    str(r2, [r0, 0])
    str(r2, [r1, 0])

syncem(0x50200000, 0x50300000)

[mendenm]

To make absolutely, deterministically, sure, you need to disable interrupts before the two writes, so they never get separated.

[GitHubsSilverBullet]

Would still introduce a small variable difference (not even taking FLASH cache delays and possible DMA delays into the equation)
If they must run in sync, the correct way to achieve that would be:

1. Stop clocks for PIO[0…1]
2. Reset PIO clock counters (separately)
3. Start clocks for PIO[0…1] with a single write (they're bitmapped)

[mendenm]

I knew there was a way to do that exactly, but I couldn't find it quickly enough to post you solution. Thanks. On the other hand, no worries about flash cache on this, assuming it is hot-compiled using asm_thumb, and not built into a baked system. There are some advantages to making asm_thumb stuff that way, since it is then guaranteed to be in RAM.

[GitHubsSilverBullet]

Argh, you're right of course. The stuff sits in RAM.
Actually I have to modify the solution above, because the PIOs are directly connected to system clock. Would be a bad idea to stop that. ;-)
One really needs to put the PIOs into SUBSYSTEM RESET and take'em out again. I do not see any other cycle-precise solution to sync them perfectly.

[mungewell]

Thank you both for your suggestions....

I actually plan to do the sync inside an interrupt service routine. Those who know me won't be surprised to hear the whole process is rather complicated. ;-)

I'm still waiting for my GPSDO to arrive, but from what I understand the 1PPS pulse is the duration of one 10MHz clock cycle. So I plan to sync as follows.

first second from 'start':

• SM0 - 120MHz CPU clock, loops until 1PPS detected with jmp(pin,, cause CPU interrupt. This interrupt routine resets the CLOCKDIVs to align as closely as possible. Once this has completed, CPU will enable other StateMachines

second second from 'start':

• SM1 - 10MHz clock (now aligned to start of 1PPS signal), loops until 1PPS detected with jmp(pin,, cause SM interrupt to trigger other SMs
• SM2.. - 12KHz clock (now aligned to start of 1PPS signal), irq(block, until SM1 triggers.

After the 1PPS trigger happens (twice), the time is 'set' and the CPU code only has to load pre-calculated formated bit-data into a FIFO - ensuring that the FIFO is NEVER empty. The time is 'maintained' by the fact the state machines are clocked at known rate. For now I'll use the XTAL on the PICO, but know this is not the best and will replace with 10MHz clock from GPSDO.

Regarding getting Block-1 and Block-2 precisely aligned... I have FIFO outputting the bit-stream data early (on the last clock cycle before it loops back to start), so this data is actually available before the other SMs need it.

This means that technically the PIO block with 'FIFO' can actually be slightly behind the other PIO block doing 'Modulation', from the initial sync without issue.

    out(pins, 2)					# output first bit-pair of frame
    jmp(not_osre, "frame")
    jmp("fail")

[mungewell]

@GitHubsSilverBullet I re-wrote the routine a bit, using a previous posting:
https://forum.micropython.org/viewtopic.php?t=12931#p70466

@micropython.asm_thumb

def sync_sm(r0):
    align   (4)             # DO NOT MODIFY
    mov     (r7, pc)        #   PC points to the table, so does r7 now
    b       (func_entry)    # DO NOT MODIFY

    # embedded table with constants
    align   (4)
    data    (2, 0x0f00)     #  0 - align SM's dividers, but also stop them
    data    (2, 0x0000)     #  2
    data    (2, 0x0000)     #  4 - Block 1 - CTRL Register
    data    (2, 0x5020)     #  6
    data    (2, 0x0000)     #  8 - Block 2 - CTRL Register
    data    (2, 0x5030)     #  A

    align   (2)
    label   (func_entry)
    ldr     (r0, [r7, 4])       # gets 0x50200000 into r0
    ldr     (r1, [r7, 8])       # gets 0x50300000 into r1
    ldr     (r2, [r7, 0])       # gets 0x00000f00 into r2

    str     (r2, [r0, 0])
    str     (r2, [r1, 0])

    # when fuction returns, r0 is the return value

My reason was that I wanted to this to be called as the interrupt handler, as it would be called as quickly as possible after the trigger edge was first detected... but that would not be able to present the R0, R1 values. Hence they need to be hard coded.

        # Stage-1 trigger, via IRQ handler
        irig_sm[2].irq(handler=sync_sm, hard=True)

        while pps.value() == 1:
            # wait for PPS to deassert first, as some are 1Hz signals...
            utime.sleep(0.25)

        # start just one SM
        mem32[0x50200000] = 0x00000002

        # StateMachine is stopped when IRQ triggers
        while mem32[0x50200000]  & (1 << 2):        # Block-1 SM2 active
            utime.sleep(0.1)

        print("Stage-1 complete")

[EDIT] I realized that I was starting the WRONG statemachine and triggering a error in a different part of the system...

[mendenm]

Don't you still want to wrap the final two instructions in an interrupt disable/enable so a higher priority interrupt can't break them up?