XiangShan

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71 repositories

XiangShan
Public
Open-source high-performance RISC-V processor
chisel risc-v microarchitecture
Scala
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Other
•733•6.1k•64•59•Updated Feb 10, 2025Feb 10, 2025
Utility
Public
Scala
•17•9•0•7•Updated Feb 10, 2025Feb 10, 2025
ChiselAIA
Public
RISC-V AIA in Chisel
chisel riscv interrupt aia
Scala
•
Mulan Permissive Software License, Version 2
•2•3•11•0•Updated Feb 10, 2025Feb 10, 2025
difftest
Public
Modern co-simulation framework for RISC-V CPUs
C++
•
Mulan Permissive Software License, Version 2
•71•132•5•6•Updated Feb 10, 2025Feb 10, 2025
NEMU
Public
C
•
Other
•99•256•30•18•Updated Feb 10, 2025Feb 10, 2025
CPU2017LiteWrapper
Public
Makefile
•0•1•0•2•Updated Feb 8, 2025Feb 8, 2025
CoupledL2
Public
Open-source non-blocking L2 cache
Scala
•
Other
•21•36•0•6•Updated Feb 8, 2025Feb 8, 2025
rocket-chip
Public
Rocket Chip Generator
Scala
•
Other
•1.1k•4•0•2•Updated Feb 8, 2025Feb 8, 2025
OpenLLC
Public
Scala
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Other
•6•5•0•0•Updated Feb 8, 2025Feb 8, 2025
HuanCun
Public
Open-source high-performance non-blocking cache
Scala
•
Other
•34•73•2•1•Updated Feb 8, 2025Feb 8, 2025
riscv-rootfs
Public
C
•10•1•0•2•Updated Feb 8, 2025Feb 8, 2025
GEM5
Public
C++
•
BSD 3-Clause "New" or "Revised" License
•32•74•13•7•Updated Feb 7, 2025Feb 7, 2025
llvm-project
Public
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
LLVM
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Other
•13k•0•0•0•Updated Feb 7, 2025Feb 7, 2025
ready-to-run
Public
Shell
•9•6•3•1•Updated Feb 6, 2025Feb 6, 2025
nemu_board
Public
Shell
•0•1•0•0•Updated Feb 6, 2025Feb 6, 2025
XiangShan-doc
Public
Documentation for XiangShan
Markdown
•
Creative Commons Attribution 4.0 International
•138•398•7•2•Updated Feb 4, 2025Feb 4, 2025
XiangShan-User-Guide
Public
The User Guide of XiangShan.
Markdown
•
Creative Commons Attribution 4.0 International
•1•5•0•0•Updated Jan 27, 2025Jan 27, 2025
docs-utils
Public
Utilities for XiangShan Document
TeX
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Mulan Permissive Software License, Version 2
•1•1•0•0•Updated Jan 26, 2025Jan 26, 2025
OpenNCB
Public
Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)
bus chisel chisel3 soc axi4 amba-axi amba-chi protocol-bridge
Scala
•0•2•0•1•Updated Jan 26, 2025Jan 26, 2025
Deterload
Public
Xiangshan deterministic workloads generator
nix checkpoint deterministic workloads workload checkpoints xiangshan simpoint
Nix
•
Mulan Permissive Software License, Version 2
•4•16•2•0•Updated Jan 23, 2025Jan 23, 2025
riscv-isa-sim
Public
Spike, a RISC-V ISA Simulator
C
•
Other
•897•7•0•2•Updated Jan 23, 2025Jan 23, 2025
CPU2006LiteWrapper
Public
Makefile
•4•9•1•2•Updated Jan 21, 2025Jan 21, 2025
LibCheckpointAlpha
Public
C
•0•1•0•0•Updated Jan 21, 2025Jan 21, 2025
tl-test-new
Public
The Unified TileLink Memory Subsystem Tester for XiangShan
C++
•
Mulan Permissive Software License, Version 2
•1•3•0•0•Updated Jan 21, 2025Jan 21, 2025
riscv-arch-test
Public
Assembly
•
Apache License 2.0
•217•2•0•0•Updated Jan 20, 2025Jan 20, 2025
YunSuan
Public
This repo includes XiangShan's function units
Scala
•
Mulan Permissive Software License, Version 2
•12•18•0•0•Updated Jan 17, 2025Jan 17, 2025
riscv-hyp-tests
Public
A bare-metal application to test specific features of the risc-v hypervisor extension
C
•
GNU General Public License v3.0
•22•2•0•1•Updated Jan 17, 2025Jan 17, 2025
env-scripts
Public
Scripts for XiangShan
Verilog
•14•13•0•0•Updated Jan 14, 2025Jan 14, 2025
nexus-am
Public
C
•30•33•5•4•Updated Jan 14, 2025Jan 14, 2025
xfuzz
Public
Fuzzing General-Purpose Hardware Designs with Software Fuzzers
Scala
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Other
•1•14•2•0•Updated Jan 10, 2025Jan 10, 2025