Listen mode MCU clock signal loss during Idle period

[wrh2]

From the MKW01Z128 reference manual: "In Idle mode (a phase of Listen mode), the 32 MHz crystal oscillator of the transceiver is disabled. If this signal, or a derivative thereof, is used as the MCU clock via CLKOUT to EXTAL0, care should be taken in firmware to configure the MCU clock to an internal low-power clock immediately prior to asserting Listen mode to prevent loss of clock affecting MCU performance."

This is not something I was aware of when I created the listen mode portion of the transceiver driver and I need to fix it to deal with this.