diff --git a/bin/Makefile b/bin/Makefile index 4ebc3cab..02e4b4ec 100644 --- a/bin/Makefile +++ b/bin/Makefile @@ -1,5 +1,5 @@ -VER=$(VNAME)1.3.4 -BID=4140 +VER=$(VNAME)1.3.7 +BID=4144 CC=gcc SED=sed @@ -14,7 +14,7 @@ ifeq ("$(GRLIB_CONFIG)","") GRLIB_CONFIG = dummy endif ifeq ("$(GRLIB_SIMULATOR)","") -GRLIB_SIMULATOR = Xilinx +GRLIB_SIMULATOR = ModelSim endif # Select LEON3 version @@ -117,7 +117,7 @@ help: @echo " make quartus-launch-synp : start Quartus for synplify project" @echo " make synplify-launch : start synplify" @echo " make vivado-launch : start Vivado project navigator" - @echo " make planAhead-launch : start PlanAhead project navigator" + @echo " make planahead-launch : start PlanAhead project navigator" @echo " make xgrlib : start grlib GUI" @echo @echo " batch targets:" @@ -142,7 +142,7 @@ help: @echo " make precision : synthesize design using precision" @echo " make synplify : synthesize design using synplify" @echo " make vivado : synthesize and place&route with Xilinx Vivado" - @echo " make planAhead : synthesize and place&route with Xilinx PlanAhead" + @echo " make planahead : synthesize and place&route with Xilinx PlanAhead" @echo " make dc : synthesize design usign Synopsys Design Compiler" @echo " make fm : Formal equivalence check using Synopsys Formality" @echo " make scripts : generate compile scripts only" @@ -693,6 +693,9 @@ remove-unimacro: @-rm $(GRLIB)/lib/tech/unimacro/ise/*.vhd; echo "" > $(GRLIB)/lib/tech/unimacro/ise/vhdlsyn.txt install-unisim: +ifeq ("$(GRLIB_SIMULATOR)","Xilinx") + @echo "GRLIB_SIMULATOR is Xilinx. Unisim installation not required, aborted." +else @echo UNISIM source path: $(UNISIM); \ for i in $(UNISIMFILES); do \ if test -r $(UNISIM)/$$i; then \ @@ -709,7 +712,11 @@ install-unisim: fi ; \ fi ; \ fi ; \ - done; \ + done +endif + +# Undocumented target, functionality was previously part of install-unisim target. +patch-unisim: if (test -r $(GRUNISIM)/unisim_VITAL.vhd); then \ cat $(GRUNISIM)/unisim_VITAL.vhd | sed -e s/'SIM_COLLISION_CHECK : string := "ALL"'/'SIM_COLLISION_CHECK : string := "GENERATE_X_ONLY"'/ \ > $(GRUNISIM)/unisim_vitalx.vhd;\ @@ -719,6 +726,9 @@ install-unisim: fi install-secureip: install-unisim +ifeq ("$(GRLIB_SIMULATOR)","Xilinx") + @echo "GRLIB_SIMULATOR is Xilinx. SecureIP installation not required, aborted." +else ifeq ("$(GRLIB_SIMULATOR)","ALDEC") @if (test -r $(XILINX)/secureip/aldec/mcb_aldec); then \ echo installing $(XILINX)/secureip ;\ @@ -742,6 +752,7 @@ else cp $(XILINX)/secureip/mti/pcie_a1_mti/*.vp $(GRLIB)/lib/tech/secureip/ise; \ fi endif +endif remove-secureip uninstall-secureip remove-unisim uninstall-unisim: @-rm $(GRLIB)/lib/tech/secureip/ise/*.vp @@ -904,97 +915,111 @@ GRLIB_XIL_PlanAhead_Simulator=ISim endif endif +#PLANAHEAD_SIMSET=sim_$(DESIGN) +PLANAHEAD_SIMSET=sim_1 -planAhead/$(TOP)_planAhead.tcl: compile.planAhead - @-mkdir -p planAhead - @echo "# Xilinx planAhead script for LEON/GRLIB" > ./planAhead/$(TOP)_planAhead.tcl - @echo "# Create a new project" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "create_project $(DESIGN) ./planAhead/$(DESIGN) -part ${DEVICE} -force" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "# Board, part and design properties" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property target_simulator $(GRLIB_XIL_PlanAhead_Simulator) [current_project]" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property top_lib work [current_fileset]" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property top_arch rtl [current_fileset]" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property top $(TOP) [current_fileset]" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property target_language VHDL [current_project]" >> ./planAhead/$(TOP)_planAhead.tcl -ifneq ("$(PROTOBOARD)","") - @echo "set_property board $(PROTOBOARD) [current_project]" >> ./planAhead/$(TOP)_planAhead.tcl +planahead/$(TOP)_planAhead.tcl: compile.planAhead + @-mkdir -p planahead + @echo "# Xilinx planAhead script for LEON/GRLIB" > ./planahead/$(TOP)_planAhead.tcl + @echo "# Create a new project" >> ./planahead/$(TOP)_planAhead.tcl + @echo "create_project $(DESIGN) ./planahead/$(DESIGN) -part ${DEVICE} -force" >> ./planahead/$(TOP)_planAhead.tcl +ifneq ("$(PLANAHEAD_SIMSET)","sim_1") + @echo "create_fileset -simset $(PLANAHEAD_SIMSET)" >> ./planahead/$(TOP)_planAhead.tcl endif - @echo "# Add files for simulation and synthesis" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "create_fileset -simset sim_$(DESIGN)" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property top $(SIMTOP) [get_filesets sim_$(DESIGN)]" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "source ./compile.planAhead" >> ./planAhead/$(TOP)_planAhead.tcl + @echo "# Board, part and design properties" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property target_simulator $(GRLIB_XIL_PlanAhead_Simulator) [current_project]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property top_lib work [current_fileset]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property top_arch rtl [current_fileset]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property top $(TOP) [current_fileset]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property target_language VHDL [current_project]" >> ./planahead/$(TOP)_planAhead.tcl +ifneq ("$(PROTOBOARD)","") + @echo "set_property board $(PROTOBOARD) [current_project]" >> ./planahead/$(TOP)_planAhead.tcl +endif +# @echo "# Use manual compile order" >> ./planahead/$(TOP)_planAhead.tcl +# @echo "set_property source_mgmt_mode DisplayOnly [current_project]" >> ./planahead/$(TOP)_planAhead.tcl +# @echo "# Disable option: Include all design sources for simulation" >> ./planahead/$(TOP)_planAhead.tcl +# @echo "set_property SOURCE_SET {} [get_filesets $(PLANAHEAD_SIMSET)]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "# Add files for simulation and synthesis" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property top $(SIMTOP) [get_filesets $(PLANAHEAD_SIMSET)]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "source ./compile.planAhead" >> ./planahead/$(TOP)_planAhead.tcl @for i in $(VERILOGOPTSYNFILES) $(VERILOGSYNFILES); do \ if test -r $$i; then \ - echo read_verilog "-library work" $$i >> ./planAhead/$(TOP)_planAhead.tcl; \ + echo read_verilog "-library work" $$i >> ./planahead/$(TOP)_planAhead.tcl; \ fi; \ done @for i in $(VHDLOPTSYNFILES) $(VHDLSYNFILES); do \ if test -r $$i; then \ - echo read_vhdl "-library work" $$i >> ./planAhead/$(TOP)_planAhead.tcl; \ + echo read_vhdl "-library work" $$i >> ./planahead/$(TOP)_planAhead.tcl; \ fi; \ done - @echo "add_files -fileset sim_$(DESIGN) $(VHDLSIMFILES)" >> ./planAhead/$(TOP)_planAhead.tcl + @echo "add_files -fileset $(PLANAHEAD_SIMSET) $(VHDLSIMFILES)" >> ./planahead/$(TOP)_planAhead.tcl + @echo "add_files -fileset $(PLANAHEAD_SIMSET) prom.srec ram.srec" >> ./planahead/$(TOP)_planAhead.tcl ifneq ("$(GRLIB_XIL_PlanAhead_sim_verilog_define)","") - @echo "set_property verilog_define {$(GRLIB_XIL_PlanAhead_sim_verilog_define)} [get_filesets sim_$(DESIGN)]" >> ./planAhead/$(TOP)_planAhead.tcl + @echo "set_property verilog_define {$(GRLIB_XIL_PlanAhead_sim_verilog_define)} [get_filesets $(PLANAHEAD_SIMSET)]" >> ./planahead/$(TOP)_planAhead.tcl endif @if test -r $(GRLIB)/netlists/xilinx/$(NETLISTTECH); then \ - echo "import_files $(GRLIB)/netlists/xilinx/$(NETLISTTECH)" >> ./planAhead/$(TOP)_planAhead.tcl; \ + echo "import_files $(GRLIB)/netlists/xilinx/$(NETLISTTECH)" >> ./planahead/$(TOP)_planAhead.tcl; \ fi ifeq ("$(PROTOBOARD)","zedBoard") - @-mkdir -p planAhead/xps_files + @-mkdir -p planahead/xps_files @cp -r ./edk_files/leon3_zedboard planAhead/xps_files/ - @echo "# Add Leon3 PS Zedboard Design" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "add_files ./planAhead/xps_files/leon3_zedboard/leon3_zedboard.xmp" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "make_wrapper -files [get_files ./planAhead/xps_files/leon3_zedboard/leon3_zedboard.xmp] -top -fileset [get_filesets sources_1] -import" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "update_compile_order -fileset sources_1" >> ./planAhead/$(TOP)_planAhead.tcl + @echo "# Add Leon3 PS Zedboard Design" >> ./planahead/$(TOP)_planAhead.tcl + @echo "add_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp" >> ./planahead/$(TOP)_planAhead.tcl + @echo "make_wrapper -files [get_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp] -top -fileset [get_filesets sources_1] -import" >> ./planahead/$(TOP)_planAhead.tcl + @echo "update_compile_order -fileset sources_1" >> ./planahead/$(TOP)_planAhead.tcl endif - @echo "# Read board specific constraints" >> ./planAhead/$(TOP)_planAhead.tcl + @echo "# Read board specific constraints" >> ./planahead/$(TOP)_planAhead.tcl #ifneq ("$(UCF_PLANAHEAD)","") @for i in $(UCF_PLANAHEAD); do \ if test -r $$i; then \ - echo "read_ucf $$i" >> ./planAhead/$(TOP)_planAhead.tcl; \ + echo "read_ucf $$i" >> ./planahead/$(TOP)_planAhead.tcl; \ fi; \ done #endif ifeq ($(CONFIG_MIG_DDR2),y) @if test -r mig/user_design/par/mig.ucf; then \ - echo "read_ucf mig/user_design/par/mig.ucf" >> ./planAhead/$(TOP)_planAhead.tcl; \ + echo "read_ucf mig/user_design/par/mig.ucf" >> ./planahead/$(TOP)_planAhead.tcl; \ fi; endif - @echo "create_run synth_$(DESIGN) -flow {$(PLANAHEAD_SYNTH_FLOW)} -strategy {$(PLANAHEAD_SYNTH_STRATEGY)}" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "set_property steps.xst.args.netlist_hierarchy as_optimized [get_runs synth_1]" >> ./planAhead/$(TOP)_planAhead.tcl - @echo "# Elaborate design to be able to apply SDC to top level" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "launch_runs -jobs 4 synth_1" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "wait_on_run -timeout 120 synth_1" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "# Launch place and route" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "set_property strategy $(PLANAHEAD_IMPL_STRATEGY) [get_runs impl_1]" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "set_property steps.map.args.mt on [get_runs impl_1]" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "set_property steps.par.args.mt 4 [get_runs impl_1]" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "set_property steps.bitgen.args.m true [get_runs impl_1]" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "launch_runs -jobs 4 impl_1 -to_step Bitgen" >> ./planAhead/$(TOP)_planAhead_run.tcl - @echo "wait_on_run -timeout 120 impl_1" >> ./planAhead/$(TOP)_planAhead_run.tcl +# @echo "create_run synth_$(DESIGN) -flow {$(PLANAHEAD_SYNTH_FLOW)} -strategy {$(PLANAHEAD_SYNTH_STRATEGY)}" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property steps.xst.args.netlist_hierarchy as_optimized [get_runs synth_1]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "set_property strategy $(PLANAHEAD_SYNTH_STRATEGY) [get_runs synth_1]" >> ./planahead/$(TOP)_planAhead.tcl + @echo "# Elaborate design to be able to apply SDC to top level" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "launch_runs -jobs 1 synth_1" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "wait_on_run -timeout 120 synth_1" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "# Launch place and route" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "set_property strategy $(PLANAHEAD_IMPL_STRATEGY) [get_runs impl_1]" >> ./planahead/$(TOP)_planAhead_run.tcl +# @echo "set_property steps.map.args.mt on [get_runs impl_1]" >> ./planahead/$(TOP)_planAhead_run.tcl +# @echo "set_property steps.par.args.mt 4 [get_runs impl_1]" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "set_property steps.bitgen.args.m true [get_runs impl_1]" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "launch_runs -jobs 1 impl_1 -to_step Bitgen" >> ./planahead/$(TOP)_planAhead_run.tcl + @echo "wait_on_run -timeout 120 impl_1" >> ./planahead/$(TOP)_planAhead_run.tcl ifeq ("$(PROTOBOARD)","zedBoard") - @echo "export_hardware [get_files ./planAhead/xps_files/leon3_zedboard/leon3_zedboard.xmp] [get_runs impl_1] -bitstream" >> ./planAhead/$(TOP)_planAhead_run.tcl + @echo "export_hardware [get_files ./planahead/xps_files/leon3_zedboard/leon3_zedboard.xmp] [get_runs impl_1] -bitstream" >> ./planahead/$(TOP)_planAhead_run.tcl endif - @echo "exit" >> ./planAhead/$(TOP)_planAhead_end.tcl + @echo "exit" >> ./planahead/$(TOP)_planAhead_end.tcl -planAhead-launch: planAhead/$(TOP)_planAhead.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES) - planAhead -mode gui -source ./planAhead/$(TOP)_planAhead.tcl - cp ./planAhead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . - cp ./planAhead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . +planahead-launch: planahead/$(TOP)_planAhead.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES) + planAhead -mode gui -source ./planahead/$(TOP)_planAhead.tcl + @if test -r ./planahead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit; then \ + cp ./planahead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . ; \ + cp ./planahead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . ; \ + fi; -planAhead planahead: planAhead/$(TOP)_planAhead.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES) - planAhead -mode batch -source ./planAhead/$(TOP)_planAhead.tcl ./planAhead/$(TOP)_planAhead_run.tcl ./planAhead/$(TOP)_planAhead_end.tcl - cp ./planAhead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . - cp ./planAhead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . +planahead: planahead/$(TOP)_planAhead.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES) + planAhead -mode batch -source ./planahead/$(TOP)_planAhead.tcl ./planahead/$(TOP)_planAhead_run.tcl ./planahead/$(TOP)_planAhead_end.tcl + @if test -r ./planahead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit; then \ + cp ./planahead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . ; \ + cp ./planahead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . ; \ + fi; planAhead-clean: - -rm -rf ./planAhead planAhead.log planAhead*.jou planAhead*.*.log + -rm -rf ./planahead planAhead.log planAhead*.jou planAhead*.*.log ######### Xilinx Vivado targets ############ VIVADOVHDL = read_vhdl -library -VIVADOVLOG = read_verilog -library +VIVADOVLOG = read_verilog -library work VIVADOLIBSKIPX = $(ASICLIBS) $(BRMLIBS) $(ACTELLIBS) $(ALTERALIBS) \ $(LATTICELIBS) $(COREPCILIB) $(SIMLIBS) @@ -1023,20 +1048,25 @@ GRLIB_XIL_Vivado_Simulator=XSim endif endif +#VIVADO_SIMSET=sim_$(DESIGN) +VIVADO_SIMSET=sim_1 + vivado/$(TOP)_vivado.tcl: compile.vivado @-mkdir -p vivado @echo "# Xilinx Vivado script for LEON/GRLIB" > ./vivado/$(TOP)_vivado.tcl @echo "# Create a new project" >> ./vivado/$(TOP)_vivado.tcl @echo "create_project $(DESIGN) ./vivado/$(DESIGN) -part ${DEVICE} -force" > ./vivado/$(TOP)_vivado.tcl - @echo "create_fileset -simset sim_$(DESIGN)" >> ./vivado/$(TOP)_vivado.tcl - @echo "set_property top $(SIMTOP) [get_filesets sim_$(DESIGN)]" >> ./vivado/$(TOP)_vivado.tcl +ifneq ("$(VIVADO_SIMSET)","sim_1") + @echo "create_fileset -simset $(VIVADO_SIMSET)" >> ./vivado/$(TOP)_vivado.tcl +endif + @echo "set_property top $(SIMTOP) [get_filesets $(VIVADO_SIMSET)]" >> ./vivado/$(TOP)_vivado.tcl @echo "set_property target_language verilog [current_project]" >> ./vivado/$(TOP)_vivado.tcl @echo "# Add files for simulation and synthesis" >> ./vivado/$(TOP)_vivado.tcl @echo "source ./compile.vivado" >> ./vivado/$(TOP)_vivado.tcl - @echo "add_files -fileset sim_$(DESIGN) $(VHDLSIMFILES)" >> ./vivado/$(TOP)_vivado.tcl - @echo "add_files -fileset sim_$(DESIGN) prom.srec ram.srec" >> ./vivado/$(TOP)_vivado.tcl + @echo "add_files -fileset $(VIVADO_SIMSET) $(VHDLSIMFILES)" >> ./vivado/$(TOP)_vivado.tcl + @echo "add_files -fileset $(VIVADO_SIMSET) prom.srec ram.srec" >> ./vivado/$(TOP)_vivado.tcl ifneq ("$(GRLIB_XIL_Vivado_sim_verilog_define)","") - @echo "set_property verilog_define {$(GRLIB_XIL_Vivado_sim_verilog_define)} [get_filesets sim_$(DESIGN)]" >> ./vivado/$(TOP)_vivado.tcl + @echo "set_property verilog_define {$(GRLIB_XIL_Vivado_sim_verilog_define)} [get_filesets $(VIVADO_SIMSET)]" >> ./vivado/$(TOP)_vivado.tcl endif # @echo "create_run synth_$(DESIGN) -flow {$(VIVADO_SYNTH_FLOW)} -strategy {$(VIVADO_SYNTH_STRATEGY)}" >> ./vivado/$(TOP)_vivado.tcl @for i in $(VERILOGOPTSYNFILES) $(VERILOGSYNFILES); do \ @@ -1059,13 +1089,14 @@ ifneq ("$(XDC)","") endif ifneq ("$(TCL)","") @for i in $(TCL); do \ - echo "import_files -fileset constrs_1 -force $$i" >> ./vivado/$(TOP)_vivado.tcl; \ + echo "source $$i" >> ./vivado/$(TOP)_vivado.tcl; \ +# echo "import_files -fileset constrs_1 -force $$i" >> ./vivado/$(TOP)_vivado.tcl; \ # echo "set_property used_in_synthesis true [get_files $$i]" >> ./vivado/$(TOP)_vivado.tcl; \ # echo "set_property used_in_implementation true [get_files $$i]" >> ./vivado/$(TOP)_vivado.tcl; \ done; endif -ifneq ("$(UCF)","") - @for i in $(UCF); do \ +ifneq ("$(VIVADO_UCF)","") + @for i in $(VIVADO_UCF); do \ echo "import_files $$i" >> ./vivado/$(TOP)_vivado.tcl; \ echo "set_property used_in_synthesis true [get_files $$i]" >> ./vivado/$(TOP)_vivado.tcl; \ echo "set_property used_in_implementation true [get_files $$i]" >> ./vivado/$(TOP)_vivado.tcl; \ @@ -1116,13 +1147,17 @@ endif vivado-launch: vivado/$(TOP)_vivado.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES) vivado -mode gui -source ./vivado/$(TOP)_vivado.tcl - cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . - cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . + @if test -r ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit; then \ + cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . ; \ + cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . ; \ + fi; vivado: vivado/$(TOP)_vivado.tcl $(VHDLSYNFILES) $(VERILOGSYNFILES) vivado -mode batch -source ./vivado/$(TOP)_vivado.tcl ./vivado/$(TOP)_vivado_run.tcl | tee $(TOP)_vivado.log - cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . - cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . + @if test -r ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit; then \ + cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit . ; \ + cp ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).msk . ; \ + fi; vivado-clean: -rm -rf ./vivado *vivado.log vivado*.jou vivado*.backup.log vivado*.str .Xil @@ -1763,7 +1798,7 @@ compile.etools $(TOP).ldf make.riviera : if test -r $$k/$$l; then \ echo -n " "$$l; \ fi; \ - for i in vlogsyn vhdlsyn vhdlmtie vhdlsynpe vhdldce vhdlcdse vhdlxile vhdlprec vlogsim vhdlsim ; do \ + for i in vlogsyn vhdlsyn svlogsyn vhdlmtie vhdlsynpe vhdldce vhdlcdse vhdlxile vhdlprec vlogsim vhdlsim svlogsim ; do \ m=$$k/$$l/$$i; \ if test -r $$m.txt; then \ for q in `cat $$m.txt` $(FILEADD) ; do \ @@ -1778,7 +1813,7 @@ compile.etools $(TOP).ldf make.riviera : case $$i in \ vhdlmtie) \ echo Project_File_$$nfiles = $$f >> tmp.mpf; \ - echo Project_File_P_$$nfiles = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 1 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $$bn compile_order $$nfiles dont_compile 0 cover_stmt 1 vhdl_use93 93 >> tmp.mpf; \ + echo Project_File_P_$$nfiles = vhdl_novitalcheck 0 file_type VHDL group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 folder {Top Level} last_compile 0 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 0 vhdl_warn2 1 vhdl_explicit 0 vhdl_showsource 1 vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 0 vhdl_warn5 0 compile_to $$bn compile_order $$nfiles dont_compile 0 cover_stmt 1 vhdl_use93 93 >> tmp.mpf; \ nfiles=`expr $$nfiles + 1`; \ printf "\t$(VCOM) $(VHDLOPT) -work $$bn $$f\n" >> compile.vsim; \ riv_fs="$$riv_fs $$f"; \ @@ -1815,7 +1850,8 @@ compile.etools $(TOP).ldf make.riviera : echo vhdl $$bn $$f >> $(TOP)_files.prj; \ xfiles=`expr $$xfiles + 1`; \ echo $(VIVADOVHDL) $$bn $$f >> compile.vivado; \ - echo $(VIVADOVHDL) $$bn $$f >> compile.planAhead;; \ + echo $(VIVADOVHDL) $$bn $$f >> compile.planAhead; \ + printf "set_property file_type VHDL [get_files $$f]\n" >> compile.planAhead;; \ vhdlprec) \ echo add_input_file -format VHDL -work $$bn -enc $$f >> $(TOP)_precision.tcl;; \ vhdlsyn) \ @@ -1968,6 +2004,43 @@ compile.etools $(TOP).ldf make.riviera : echo $(SYNPVLOG) $$f >> compile.synp; \ echo $(VIVADOVLOG) $$f >> compile.vivado; \ echo $(VIVADOVLOG) $$f >> compile.planAhead; \ + printf "set_property file_type Verilog [get_files $$f]\n" >> compile.planAhead; \ + echo add_input_file -format VERILOG -work $$bn $$f >> $(TOP)_precision.tcl; \ + echo set_global_assignment -name VERILOG_FILE $$f -library $$bn >> $(TOP)_quartus.qsf;; \ + svlogsyn) \ + echo Project_File_$$nfiles = $$f >> tmp.mpf; \ + echo Project_File_P_$$nfiles = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 compile_to $$bn vlog_upper 0 vlog_options {} compile_order $$nfiles dont_compile 0 >> tmp.mpf; \ + nfiles=`expr $$nfiles + 1`; \ + printf "\t$(VLOG) -sv -work $$bn +incdir+$$k/$$l $$f\n" >> compile.vsim; \ + riv_fs="$$riv_fs $$f"; \ + printf "\t$(ALOG) $$bn ../../$$f\n" >> compile.asim; \ + printf "\t$(NCVLOG) $$bn -INCDIR $$k/$$l $$f\n" >> compile.ncsim; \ + echo $(XSTVLOG) $$bn -ifn $$f >> compile.xst; \ + echo verilog $$bn $$f >> $(TOP)_files.prj; \ + case $$bn in $(LIBEROLIBSKIP) )\ + uu=0;; \ + *) \ + case $$q in $(LIBEROSKIP) ) ;; *) \ + echo VALUE \"\/$$f,hdl\" >> libero_syn_files; \ + echo VALUE \"\/$$f,hdl\" >> libero_synlist; \ + echo VALUE \"\/$$f,hdl\" >> libero_simlist; \ + echo STATE=\"utd\" >> libero_syn_files; \ + echo TIME=\"1310766027\" >> libero_syn_files; \ + echo LIBRARY=\"$$bn\" >> libero_syn_files; \ + echo ENDFILE >> libero_syn_files;; \ + esac; \ + esac; \ + echo $$f >> verilog.txt; \ + echo $(DCVLOG) $$bn $$f >> compile.dc; \ + echo $(FMVLOG) $$bn $$f >> fmref.tcl; \ + echo $$f >> easic.vlog; \ + echo $(RTLCVLOG) $$f >> compile.rc; \ + echo LIBFILE $$f $$bn verilog >> tmp.npl; \ + echo xfile add \"$$f\" >> $(TOP)_ise.tcl; \ + echo puts \"$$f\" >> $(TOP)_ise.tcl; \ + echo $(SYNPVLOG) -vlog_std sysv $$f >> compile.synp; \ + echo $(VIVADOVLOG) $$f >> compile.vivado; \ + echo $(VIVADOVLOG) $$f >> compile.planAhead; \ echo add_input_file -format VERILOG -work $$bn $$f >> $(TOP)_precision.tcl; \ echo set_global_assignment -name VERILOG_FILE $$f -library $$bn >> $(TOP)_quartus.qsf;; \ vhdlsim) \ @@ -1999,13 +2072,14 @@ compile.etools $(TOP).ldf make.riviera : uu=0;; \ *) \ case $$q in $(VIVADOSKIP) ) ;; *) \ - printf "add_files -fileset sim_$(DESIGN) -norecurse $$f\n" >> compile.vivado; \ + printf "add_files -fileset $(VIVADO_SIMSET) -norecurse $$f\n" >> compile.vivado; \ printf "set_property library $$bn [get_files $$f]\n" >> compile.vivado; \ + printf "add_files -fileset $(PLANAHEAD_SIMSET) -norecurse $$f\n" >> compile.planAhead; \ + printf "set_property library $$bn [get_files $$f]\n" >> compile.planAhead; \ + printf "set_property file_type VHDL [get_files $$f]\n" >> compile.planAhead; \ esac; \ esac; \ esac; \ - printf "add_files -fileset sim_$(DESIGN) -norecurse $$f\n" >> compile.planAhead; \ - printf "set_property library $$bn [get_files $$f]\n" >> compile.planAhead; \ if (test $$bn = "work"); then \ printf "\t$(VHDLP) $(VHDLOPT) sonata $$f\n" >> compile.son; \ else \ @@ -2040,9 +2114,35 @@ compile.etools $(TOP).ldf make.riviera : esac; \ printf "\t$(VLOG) -work $$bn $$f\n" >> compile.vsim; \ riv_fs="$$riv_fs $$f"; \ - printf "add_files -fileset sim_$(DESIGN) -norecurse $$f\n" >> compile.vivado; \ + printf "add_files -fileset $(VIVADO_SIMSET) -norecurse $$f\n" >> compile.vivado; \ printf "set_property library $$bn [get_files $$f]\n" >> compile.vivado; \ - printf "add_files -fileset sim_$(DESIGN) -norecurse $$f\n" >> compile.planAhead; \ + printf "add_files -fileset $(PLANAHEAD_SIMSET) -norecurse $$f\n" >> compile.planAhead; \ + printf "set_property library $$bn [get_files $$f]\n" >> compile.planAhead; \ + printf "set_property file_type Verilog [get_files $$f]\n" >> compile.planAhead; \ + printf "\t$(ALOG) $$bn ../../$$f\n" >> compile.asim; \ + printf "\t$(NCVLOG) $$bn $$f\n" >> compile.ncsim;; \ + svlogsim) \ + echo Project_File_$$nfiles = $$f >> tmp.mpf; \ + echo Project_File_P_$$nfiles = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} vlog_noload 0 last_compile 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 compile_to $$bn vlog_upper 0 vlog_options {} compile_order $$nfiles dont_compile 0 >> tmp.mpf; \ + nfiles=`expr $$nfiles + 1`; \ + case $$bn in $(LIBEROLIBSKIP) )\ + uu=0;; \ + *) \ + case $$q in $(LIBEROSKIP) ) ;; *) \ + echo VALUE \"\/$$f,hdl\" >> libero_syn_files; \ + echo VALUE \"\/$$f,hdl\" >> libero_sim_files; \ + echo VALUE \"\/$$f,hdl\" >> libero_simlist; \ + echo STATE=\"utd\" >> libero_syn_files; \ + echo TIME=\"1310766027\" >> libero_syn_files; \ + echo LIBRARY=\"$$bn\" >> libero_syn_files; \ + echo ENDFILE >> libero_syn_files;; \ + esac; \ + esac; \ + printf "\t$(VLOG) -sv -work $$bn $$f\n" >> compile.vsim; \ + riv_fs="$$riv_fs $$f"; \ + printf "add_files -fileset $(VIVADO_SIMSET) -norecurse $$f\n" >> compile.vivado; \ + printf "set_property library $$bn [get_files $$f]\n" >> compile.vivado; \ + printf "add_files -fileset $(PLANAHEAD_SIMSET) -norecurse $$f\n" >> compile.planAhead; \ printf "set_property library $$bn [get_files $$f]\n" >> compile.planAhead; \ printf "\t$(ALOG) $$bn ../../$$f\n" >> compile.asim; \ printf "\t$(NCVLOG) $$bn $$f\n" >> compile.ncsim;; \ @@ -2060,6 +2160,9 @@ compile.etools $(TOP).ldf make.riviera : if [ "$$i" = 'vlogsim' -o "$$i" = 'vlogsyn' ]; then \ printf "\t$(VLOG) -work $$bn $$riv_fs\n" >> make.riviera; \ fi; \ + if [ "$$i" = 'svlogsim' -o "$$i" = 'svlogsyn' ]; then \ + printf "\t$(VLOG) -work $$bn $$riv_fs\n" >> make.riviera; \ + fi; \ unset riv_fs; \ fi; \ fi ; \ diff --git a/bin/gpl.sed b/bin/gpl.sed index 2bf32d2d..10ebe0b1 100644 --- a/bin/gpl.sed +++ b/bin/gpl.sed @@ -1,7 +1,7 @@ s/--GAISLER_LICENSE/------------------------------------------------------------------------------\ -- This file is a part of the GRLIB VHDL IP LIBRARY\ -- Copyright (C) 2003 - 2008, Gaisler Research\ --- Copyright (C) 2008 - 2013, Aeroflex Gaisler\ +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler\ --\ -- This program is free software\; you can redistribute it and\/or modify\ -- it under the terms of the GNU General Public License as published by\ diff --git a/bin/gr.sed b/bin/gr.sed index b05f28f5..b8e75af9 100644 --- a/bin/gr.sed +++ b/bin/gr.sed @@ -1,6 +1,6 @@ s/--GAISLER_LICENSE/------------------------------------------------------------------------------\ -- This file is a part of the GRLIB VHDL IP LIBRARY\ --- Copyright (C) 2013, Aeroflex Gaisler AB - all rights reserved.\ +-- Copyright (C) 2014, Aeroflex Gaisler AB - all rights reserved.\ --\ -- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN \ -- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED \ diff --git a/boards/gr-cpci-xc4v/leon3mp.ucf b/boards/gr-cpci-xc4v/leon3mp.ucf index 3470a2b4..153b9fbb 100644 --- a/boards/gr-cpci-xc4v/leon3mp.ucf +++ b/boards/gr-cpci-xc4v/leon3mp.ucf @@ -382,12 +382,12 @@ NET "pci_arb_gnt(6)" LOC = "AT25" | IOSTANDARD=PCI33_3; #pci_gntn(6) NET "pci_arb_gnt(7)" LOC = "AU21" | IOSTANDARD=PCI33_3; #pci_gntn(7) NET "pci_arb_req(0)" LOC = "AV22" | IOSTANDARD=PCI33_3; #pci_reqn(0) -NET "pci_arb_req(1)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(1) +NET "pci_arb_req(1)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(1) NET "pci_arb_req(2)" LOC = "AW26" | IOSTANDARD=PCI33_3; #pci_reqn(2) NET "pci_arb_req(3)" LOC = "AV24" | IOSTANDARD=PCI33_3; #pci_reqn(3) NET "pci_arb_req(4)" LOC = "AV25" | IOSTANDARD=PCI33_3; #pci_reqn(4) -NET "pci_arb_req(5)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(5) -NET "pci_arb_req(6)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(6) +NET "pci_arb_req(5)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(5) +NET "pci_arb_req(6)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(6) NET "pci_arb_req(7)" LOC = "AW22" | IOSTANDARD=PCI33_3; #pci_reqn(7) NET "pci_idsel" LOC = "AV9" | IOSTANDARD=PCI33_3 | BYPASS; diff --git a/boards/gr-cpci-xc4vlx200/leon3mp.ucf b/boards/gr-cpci-xc4vlx200/leon3mp.ucf index 0bae6c37..5810303d 100644 --- a/boards/gr-cpci-xc4vlx200/leon3mp.ucf +++ b/boards/gr-cpci-xc4vlx200/leon3mp.ucf @@ -217,14 +217,14 @@ NET "sd(61)" LOC = "C29" | IOSTANDARD=LVTTL; NET "sd(62)" LOC = "J22" | IOSTANDARD=LVTTL; NET "sd(63)" LOC = "G30" | IOSTANDARD=LVTTL; -NET "sdcke(0)" LOC = "A18" | IOSTANDARD=LVTTL; -NET "sdcke(1)" LOC = "B18" | IOSTANDARD=LVTTL; +NET "sdcke(0)" LOC = "B18" | IOSTANDARD=LVTTL; +NET "sdcke(1)" LOC = "A18" | IOSTANDARD=LVTTL; NET "sdcke(2)" LOC = "D22" | IOSTANDARD=LVTTL; -NET "sdcke(3)" LOC = "F29" | IOSTANDARD=LVTTL; +NET "sdcke(3)" LOC = "E26" | IOSTANDARD=LVTTL; NET "sdcsn(0)" LOC = "D21" | IOSTANDARD=LVTTL; NET "sdcsn(1)" LOC = "A24" | IOSTANDARD=LVTTL; -NET "sdcsn(2)" LOC = "E21" | IOSTANDARD=LVTTL; +NET "sdcsn(2)" LOC = "D20" | IOSTANDARD=LVTTL; NET "sdcsn(3)" LOC = "E22" | IOSTANDARD=LVTTL; NET "sddqm(0)" LOC = "E11" | IOSTANDARD=LVTTL; @@ -240,9 +240,9 @@ NET "sdcasn" LOC = "G22" | IOSTANDARD=LVTTL; NET "sdrasn" LOC = "B25" | IOSTANDARD=LVTTL; NET "sdwen" LOC = "A25" | IOSTANDARD=LVTTL; -NET "sdscl" LOC = "B36" | IOSTANDARD=LVTTL; -NET "sdsda(0)" LOC = "B37" | IOSTANDARD=LVTTL; -NET "sdsda(1)" LOC = "G33" | IOSTANDARD=LVTTL; +NET "sdscl" LOC = "C39" | IOSTANDARD=LVTTL; +NET "sdsda(0)" LOC = "C38" | IOSTANDARD=LVTTL; +NET "sdsda(1)" LOC = "C37" | IOSTANDARD=LVTTL; NET "dsuact" LOC = "D34" | IOSTANDARD=LVTTL; @@ -318,10 +318,10 @@ NET "pci_ad(40)" LOC = "AR38" | IOSTANDARD=PCI33_3; NET "pci_ad(41)" LOC = "AP36" | IOSTANDARD=PCI33_3; NET "pci_ad(42)" LOC = "AR36" | IOSTANDARD=PCI33_3; NET "pci_ad(43)" LOC = "AT36" | IOSTANDARD=PCI33_3; -NET "pci_ad(44)" LOC = "AN33" | IOSTANDARD=PCI33_3; -NET "pci_ad(45)" LOC = "AR34" | IOSTANDARD=PCI33_3; +NET "pci_ad(44)" LOC = "AP34" | IOSTANDARD=PCI33_3; +NET "pci_ad(45)" LOC = "AT35" | IOSTANDARD=PCI33_3; NET "pci_ad(46)" LOC = "AU36" | IOSTANDARD=PCI33_3; -NET "pci_ad(47)" LOC = "AT35" | IOSTANDARD=PCI33_3; +NET "pci_ad(47)" LOC = "AR34" | IOSTANDARD=PCI33_3; NET "pci_ad(48)" LOC = "AT39" | IOSTANDARD=PCI33_3; NET "pci_ad(49)" LOC = "AT38" | IOSTANDARD=PCI33_3; NET "pci_ad(50)" LOC = "AU38" | IOSTANDARD=PCI33_3; @@ -332,12 +332,12 @@ NET "pci_ad(54)" LOC = "AU33" | IOSTANDARD=PCI33_3; NET "pci_ad(55)" LOC = "AU35" | IOSTANDARD=PCI33_3; NET "pci_ad(56)" LOC = "AV37" | IOSTANDARD=PCI33_3; NET "pci_ad(57)" LOC = "AW37" | IOSTANDARD=PCI33_3; -NET "pci_ad(58)" LOC = "AM35" | IOSTANDARD=PCI33_3; +NET "pci_ad(58)" LOC = "AN34" | IOSTANDARD=PCI33_3; NET "pci_ad(59)" LOC = "AW35" | IOSTANDARD=PCI33_3; NET "pci_ad(60)" LOC = "AW36" | IOSTANDARD=PCI33_3; NET "pci_ad(61)" LOC = "AV35" | IOSTANDARD=PCI33_3; NET "pci_ad(62)" LOC = "AT33" | IOSTANDARD=PCI33_3; -NET "pci_ad(63)" LOC = "AP34" | IOSTANDARD=PCI33_3; +NET "pci_ad(63)" LOC = "AR33" | IOSTANDARD=PCI33_3; NET "pci_cbe(0)" LOC = "AT13" | IOSTANDARD=PCI33_3; NET "pci_cbe(1)" LOC = "AU12" | IOSTANDARD=PCI33_3; NET "pci_cbe(2)" LOC = "AR13" | IOSTANDARD=PCI33_3; @@ -367,12 +367,12 @@ NET "pci_arb_gnt(6)" LOC = "AT25" | IOSTANDARD=PCI33_3; #pci_gntn(6) NET "pci_arb_gnt(7)" LOC = "AU21" | IOSTANDARD=PCI33_3; #pci_gntn(7) NET "pci_arb_req(0)" LOC = "AV22" | IOSTANDARD=PCI33_3; #pci_reqn(0) -NET "pci_arb_req(1)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(1) +NET "pci_arb_req(1)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(1) NET "pci_arb_req(2)" LOC = "AW26" | IOSTANDARD=PCI33_3; #pci_reqn(2) NET "pci_arb_req(3)" LOC = "AV24" | IOSTANDARD=PCI33_3; #pci_reqn(3) NET "pci_arb_req(4)" LOC = "AV25" | IOSTANDARD=PCI33_3; #pci_reqn(4) -NET "pci_arb_req(5)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(5) -NET "pci_arb_req(6)" LOC = "AW25" | IOSTANDARD=PCI33_3; #pci_reqn(6) +NET "pci_arb_req(5)" LOC = "AW24" | IOSTANDARD=PCI33_3; #pci_reqn(5) +NET "pci_arb_req(6)" LOC = "AV23" | IOSTANDARD=PCI33_3; #pci_reqn(6) NET "pci_arb_req(7)" LOC = "AW22" | IOSTANDARD=PCI33_3; #pci_reqn(7) NET "pci_idsel" LOC = "AV9" | IOSTANDARD=LVTTL; diff --git a/boards/gr-xc6s/Makefile.inc b/boards/gr-xc6s/Makefile.inc index 10e7bd22..41f2a278 100644 --- a/boards/gr-xc6s/Makefile.inc +++ b/boards/gr-xc6s/Makefile.inc @@ -16,4 +16,4 @@ PLANAHEAD_SYNTH_FLOW="XST 14" PLANAHEAD_SYNTH_STRATEGY="TimingWithIOBPacking" # Set PlanAhead Implementation strategy -PLANAHEAD_IMPL_STRATEGY="MapLogicOptParHighExtra" +PLANAHEAD_IMPL_STRATEGY="MapGlobalOptLogicOptRetimingDupParHigh" diff --git a/boards/terasic-de4/ddr2ctrl.vhd b/boards/terasic-de4/ddr2ctrl.vhd index 4be87ee5..c65edc43 100644 --- a/boards/terasic-de4/ddr2ctrl.vhd +++ b/boards/terasic-de4/ddr2ctrl.vhd @@ -2,7 +2,7 @@ -- GENERATION: XML -- ddr2ctrl.vhd --- Generated using ACDS version 13.1 162 at 2013.12.06.15:39:20 +-- Generated using ACDS version 13.1 162 at 2014.03.03.20:01:23 library IEEE; use IEEE.std_logic_1164.all; @@ -40,7 +40,7 @@ entity ddr2ctrl is avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable avl_read_req : in std_logic := '0'; -- .read avl_write_req : in std_logic := '0'; -- .write - avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount + avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount local_init_done : out std_logic; -- status.local_init_done local_cal_success : out std_logic; -- .local_cal_success local_cal_fail : out std_logic; -- .local_cal_fail @@ -82,7 +82,7 @@ architecture rtl of ddr2ctrl is avl_be : in std_logic_vector(31 downto 0) := (others => 'X'); -- byteenable avl_read_req : in std_logic := 'X'; -- read avl_write_req : in std_logic := 'X'; -- write - avl_size : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount + avl_size : in std_logic_vector(3 downto 0) := (others => 'X'); -- burstcount local_init_done : out std_logic; -- local_init_done local_cal_success : out std_logic; -- local_cal_success local_cal_fail : out std_logic; -- local_cal_fail @@ -140,7 +140,7 @@ end architecture rtl; -- of ddr2ctrl -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ --- Copyright (C) 1991-2013 Altera Corporation +-- Copyright (C) 1991-2014 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner @@ -211,9 +211,9 @@ end architecture rtl; -- of ddr2ctrl -- Retrieval info: -- Retrieval info: -- Retrieval info: --- Retrieval info: +-- Retrieval info: -- Retrieval info: --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: @@ -252,7 +252,7 @@ end architecture rtl; -- of ddr2ctrl -- Retrieval info: -- Retrieval info: -- Retrieval info: --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: @@ -265,7 +265,7 @@ end architecture rtl; -- of ddr2ctrl -- Retrieval info: -- Retrieval info: -- Retrieval info: --- Retrieval info: +-- Retrieval info: -- Retrieval info: -- Retrieval info: -- Retrieval info: diff --git a/boards/xilinx-ac701-xc7a200t/Makefile.inc b/boards/xilinx-ac701-xc7a200t/Makefile.inc new file mode 100644 index 00000000..3df14cd0 --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/Makefile.inc @@ -0,0 +1,29 @@ +# FPGA and Dev Board used in Design +TECHNOLOGY=kintex7 +PART=xc7a200t +PACKAGE=fbg676 +PROTOBOARD=xilinx.com:artix7:ac701:1.0 +SPEED=2 +PROMGENPAR=-x xcf08p -u 0 $(TOP).bit -p mcs -w -o $(BOARD) + +# Set Vivado Synthesis Flow and Strategy used for build +# Choose 'XST 14' or 'Vivado Synthesis 2012' +#VIVADO_SYNTH_FLOW="Vivado Synthesis 2012" + +# For 'Vivado Synthesis 2012' flow set: +# 1. 'Vivado Synthesis Defaults' +# For 'XST 14'flow set: +# 1. 'TimingWithIOBPacking' +# 2. 'TimingWithoutIOBPacking' +# 3. 'AreaReduction' +# 4. 'PowerOptimization' +# 5. 'XST Defaults' +#VIVADO_SYNTH_STRATEGY="Vivado Synthesis Defaults" + +# Set Vivado Implementation strategy +# 1. 'HighEffort' +# 2. 'HighEffortPhySynth' +# 3. 'Vivado Implemnation Defaults' +# 4. 'LowEffort' +# 5. 'QuickEffort' +#VIVADO_IMPL_STRATEGY="HighEffortPhySynth" diff --git a/boards/xilinx-ac701-xc7a200t/default.ut b/boards/xilinx-ac701-xc7a200t/default.ut new file mode 100644 index 00000000..5ce9cedc --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/default.ut @@ -0,0 +1,26 @@ +-g DebugBitstream:No +-g Binary:no +-b +-g CRC:Enable +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g Persist:No +-g ReadBack +-g DonePipe:No +-g DriveDone:Yes diff --git a/boards/xilinx-ac701-xc7a200t/fpga-usb.cmd b/boards/xilinx-ac701-xc7a200t/fpga-usb.cmd new file mode 100644 index 00000000..8b9f362b --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/fpga-usb.cmd @@ -0,0 +1,25 @@ +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref StartupCLock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref svfUseTime:FALSE +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref StartupCLock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref svfUseTime:FALSE +setMode -bs +setCable -port usb21 +Identify +setAttribute -position 1 -attr configFileName -value "xilinx-ac701-xc7a200t.bit" +Program -p 1 -v +setMode -bs +quit diff --git a/boards/xilinx-ac701-xc7a200t/fpga.cmd b/boards/xilinx-ac701-xc7a200t/fpga.cmd new file mode 100644 index 00000000..bc56e882 --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/fpga.cmd @@ -0,0 +1,25 @@ +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref StartupCLock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref svfUseTime:FALSE +setPreference -pref UserLevel:NOVICE +setPreference -pref MessageLevel:DETAILED +setPreference -pref ConcurrentMode:FALSE +setPreference -pref UseHighz:FALSE +setPreference -pref ConfigOnFailure:STOP +setPreference -pref StartupCLock:AUTO_CORRECTION +setPreference -pref AutoSignature:FALSE +setPreference -pref KeepSVF:FALSE +setPreference -pref svfUseTime:FALSE +setMode -bs +setCable -port auto +Identify +setAttribute -position 1 -attr configFileName -value "xilinx-ac701-xc7a200t.bit" +Program -p 1 -v +setMode -bs +quit diff --git a/boards/xilinx-ac701-xc7a200t/mig.prj b/boards/xilinx-ac701-xc7a200t/mig.prj new file mode 100644 index 00000000..7855d06b --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/mig.prj @@ -0,0 +1,195 @@ + + + + mig + 1 + 1 + OFF + 1024 + ON + Enabled + xc7a200t-fbg676/-2 + 2.0 + Differential + No Buffer + ACTIVE LOW + FALSE + 0 + 40 Ohms + 0 + + DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6 + 2500 + 1.8V + 4:1 + 200 + 0 + 1.000 + 1 + 1 + 1 + 1 + 64 + 1 + 1 + Disabled + Strict + FALSE + + 14 + 10 + 3 + 1.5V + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 6 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/6 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 5 + Enabled + Normal + Dynamic ODT off + NATIVE + + + + diff --git a/boards/xilinx-ac701-xc7a200t/mig.xci b/boards/xilinx-ac701-xc7a200t/mig.xci new file mode 100644 index 00000000..9cc02abc --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/mig.xci @@ -0,0 +1,1175 @@ + + + xilinx.com + xci + unknown + 1.0 + + + mig + + + mig.prj + Custom + Custom + mig + 1 + 0 + NOBUF + DDR3 + INTERNAL + ACTIVE_HIGH + FALSE + DIFF + 0 + OFF + 64 + 8 + 14 + 3 + 1 + 1 + 1 + 1 + 8 + 1 + 1 + 1 + 1 + OFF + 3 + ON + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + ON + 8 + 2 + 8 + 28 + 4 + 64 + 8 + 2 + 8 + 8 + 2 + 8 + 100000000 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + DDR3 + FALSE + DIFF + 0 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + ACTIVE_LOW + DDR3 + FALSE + DIFF + 0 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + 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1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + ACTIVE_LOW + DDR3 + FALSE + DIFF + 0 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + ACTIVE_LOW + DDR3 + FALSE + DIFF + 0 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + ACTIVE_LOW + DDR3 + FALSE + DIFF + 0 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + ACTIVE_LOW + DDR3 + FALSE + DIFF + 0 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 8 + 1 + 14 + 3 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + OFF + 1 + OFF + 1 + OFF + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 8 + 2 + 8 + 100.0 + 0.000 + FALSE + 10.0 + 10 + 10 + 10 + 10 + FALSE + FALSE + FALSE + FALSE + FALSE + 4 + 32 + 32 + 1048576 + 4 + 32 + 32 + 1048576 + 1 + 18 + 29 + 8 + OFF + 1 + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 8 + 1 + 1 + 1 + 2 + 1 + OFF + 1 + 18 + 29 + 2 + 1 + 1 + 1 + 29 + 1 + 1 + 29 + 1 + ACTIVE_LOW + artix7 + xc7a200t + fbg676 + -2 + C + + VERILOG + MIXED + TRUE + TRUE + + xilinx.com:artix7:ac701:1.0 + TRUE + 2013.3 + 1 + GLOBAL + . + + + + + diff --git a/boards/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc b/boards/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc new file mode 100644 index 00000000..6449aa93 --- /dev/null +++ b/boards/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc @@ -0,0 +1,229 @@ +# Define and contraint system clock +create_clock -period 5.000 -name clk200 [get_ports clk200p] +set_propagated_clock [get_clocks clk200] + +# --- Clock Domain Crossings + +# --- False paths +set_false_path -to [get_ports {led[*]}] +set_false_path -from [get_ports {button[*]}] +set_false_path -from [get_ports reset] +set_false_path -from [get_ports switch*] + +# --- SPI +#set_input_delay -clock [get_generated_clocks clk_pll_i] -max 3.000 [get_ports spi_sel_n] +#set_output_delay -clock [get_generated_clocks clk_pll_i] -max 1.000 [get_ports spi_clk] +#set_output_delay -clock [get_generated_clocks clk_pll_i] -max 1.000 [get_ports spi_clk] +#set_input_delay -clock [get_generated_clocks clk_pll_i] -max 3.000 [get_ports spi_miso ] + +# --- UART +# Inputs +set_input_delay -clock [get_generated_clocks clk_pll_i] -max 3.000 [get_ports dsurx] +set_input_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay 1.000 [get_ports dsurx] +set_input_delay -clock [get_generated_clocks clk_pll_i] -max 3.000 [get_ports dsuctsn] +set_input_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay 1.000 [get_ports dsuctsn] + +# Outputs +set_output_delay -clock [get_generated_clocks clk_pll_i] -max 1.000 [get_ports dsutx] +set_output_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports dsutx] +set_output_delay -clock [get_generated_clocks clk_pll_i] -max 1.000 [get_ports dsurtsn] +set_output_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports dsurtsn] + +# --- JTAG +# N/A + +# --- I2C +# BiDir +set_input_delay -clock [get_generated_clocks clk_pll_i] -max 3.000 [get_ports iic_scl*] +set_input_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay 1.000 [get_ports iic_scl*] +set_output_delay -clock [get_generated_clocks clk_pll_i] -max -add_delay 1.000 [get_ports iic_scl*] +set_output_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports iic_scl*] +set_input_delay -clock [get_generated_clocks clk_pll_i] -max 3.000 [get_ports iic_sda*] +set_input_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay 1.000 [get_ports iic_sda*] +set_output_delay -clock [get_generated_clocks clk_pll_i] -max -add_delay 1.000 [get_ports iic_sda*] +set_output_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports iic_sda*] + +#----------------------------------------------------------- +# Ethernet / GMII - +#----------------------------------------------------------- + +# The RGMII receive interface requirement allows a 1ns setup and 1ns hold - this is met but only just so constraints are relaxed +#set_input_delay -clock [get_clocks ac701_ethernet_rgmii_rgmii_rx_clk] -max -1.5 [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] +#set_input_delay -clock [get_clocks ac701_ethernet_rgmii_rgmii_rx_clk] -min -2.8 [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] +#set_input_delay -clock [get_clocks ac701_ethernet_rgmii_rgmii_rx_clk] -clock_fall -max -1.5 -add_delay [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] +#set_input_delay -clock [get_clocks ac701_ethernet_rgmii_rgmii_rx_clk] -clock_fall -min -2.8 -add_delay [get_ports {rgmii_rxd[*] rgmii_rx_ctl}] + +# the following properties can be adjusted if requried to adjuct the IO timing +# the value shown is the default used by the IP +# increasing this value will improve the hold timing but will also add jitter. +#set_property IDELAY_VALUE 12 [get_cells {trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/*/rgmii_interface/delay_rgmii_rx* trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_i/*/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}] + +set_property IOSTANDARD LVCMOS18 [get_ports phy_*] +set_property IOSTANDARD LVDS_25 [get_ports gtrefclk_*] + +set_property PACKAGE_PIN AA13 [get_ports gtrefclk_p] +set_property PACKAGE_PIN AB13 [get_ports gtrefclk_n] + +set_property PACKAGE_PIN U22 [get_ports phy_txclk] +set_property PACKAGE_PIN T17 [get_ports {phy_txd[3]}] +set_property PACKAGE_PIN T18 [get_ports {phy_txd[2]}] +set_property PACKAGE_PIN U15 [get_ports {phy_txd[1]}] +set_property PACKAGE_PIN U16 [get_ports {phy_txd[0]}] +set_property PACKAGE_PIN T15 [get_ports phy_txctl_txen] + +set_property PACKAGE_PIN V14 [get_ports {phy_rxd[3]}] +set_property PACKAGE_PIN V16 [get_ports {phy_rxd[2]}] +set_property PACKAGE_PIN V17 [get_ports {phy_rxd[1]}] +set_property PACKAGE_PIN U17 [get_ports {phy_rxd[0]}] +set_property PACKAGE_PIN U14 [get_ports phy_rxctl_rxdv] +set_property PACKAGE_PIN U21 [get_ports phy_rxclk] + +set_property PACKAGE_PIN V18 [get_ports phy_reset] + +set_property PACKAGE_PIN T14 [get_ports phy_mdio] +set_property PACKAGE_PIN W18 [get_ports phy_mdc] + +# Clock select +# Should be set to constant '0' to get 125Mhz GTX clock +set_property PACKAGE_PIN B26 [get_ports {sfp_clock_mux[0]}] +set_property IOSTANDARD LVCMOS25 [get_ports {sfp_clock_mux[0]}] +set_property PACKAGE_PIN C24 [get_ports {sfp_clock_mux[1]}] +set_property IOSTANDARD LVCMOS25 [get_ports {sfp_clock_mux[1]}] + +# The following are required to maximise setup/hold +set_property SLEW FAST [get_ports phy_tx*] + +create_clock -period 8.000 -name phy_rxclk [get_ports phy_rxclk] +set_propagated_clock [get_clocks phy_rxclk] + +#create_clock -period 8.000 -name phy_txclk [get_pins eth0.gtrefclk_pad/xcv.u0/*/O] +create_clock -period 8.000 -name phy_txclk [get_pins eth0.ibufds_gtrefclk/O] +set_propagated_clock [get_clocks phy_txclk] + +# CDC +set_max_delay -datapath_only -from [all_registers -clock [get_clocks -include_generated_clocks clk200] ] -to [all_registers -clock [get_clocks phy_rxclk] ] 8.000 +set_max_delay -datapath_only -from [all_registers -clock [get_clocks -include_generated_clocks clk200] ] -to [all_registers -clock [get_clocks -include_generated_clocks phy_txclk] ] 8.000 +set_max_delay -datapath_only -from [all_registers -clock [get_clocks phy_rxclk] ] -to [all_registers -clock [get_clocks -include_generated_clocks clk200] ] 8.000 +set_max_delay -datapath_only -from [all_registers -clock [get_clocks -include_generated_clocks phy_txclk]] -to [all_registers -clock [get_clocks -include_generated_clocks clk200] ] 8.000 + +set_false_path -from [get_clocks {CLKOUT0_1}] -to [get_clocks {CLKOUT1_1}] +set_false_path -from [get_clocks {CLKOUT0_1}] -to [get_clocks {CLKOUT1_1}] + +# Output MUX +# Data and Control +set_false_path -from [get_clocks -include_generated_clocks clk200] -through [get_ports phy_tx*] -to [get_clocks -include_generated_clocks phy_txclk] +set_false_path -from [get_clocks -include_generated_clocks phy_txclk] -through [get_ports phy_tx*] -to [get_clocks -include_generated_clocks clk200] + +# Outputs +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -max 2.000 [get_ports phy_txd[*]] +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -min 1.000 [get_ports phy_txd[*]] +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -max 2.000 [get_ports phy_txd[*]] -add_delay -clock_fall +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -min 1.000 [get_ports phy_txd[*]] -add_delay -clock_fall + +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -max 2.000 [get_ports phy_txctl_txen] +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -min 1.000 [get_ports phy_txctl_txen] +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -max 2.000 [get_ports phy_txctl_txen] -add_delay -clock_fall +#set_output_delay -clock [get_clocks -include_generated_clocks phy_txclk] -min 1.000 [get_ports phy_txctl_txen] -add_delay -clock_fall + +#output timing for rgmii - derated slightly due to pessimism in the tools +create_generated_clock -name rgmii_tx_clk -divide_by 1 -source [get_pins eth0.rgmii0/rgmii_tx_clk/*/*/C] [get_ports phy_txclk] + +set_output_delay 0.75 -max -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] +set_output_delay -0.7 -min -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] +set_output_delay 0.75 -max -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -clock_fall -add_delay +set_output_delay -0.7 -min -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -clock_fall -add_delay + + +# Inputs +set_input_delay -clock [get_clocks phy_rxclk] -max 1.000 [get_ports {phy_rxd[*] phy_rxctl_rxdv}] +set_input_delay -clock [get_clocks phy_rxclk] -min 0.000 [get_ports {phy_rxd[*] phy_rxctl_rxdv}] +set_input_delay -clock [get_clocks phy_rxclk] -max 1.000 [get_ports {phy_rxd[*] phy_rxctl_rxdv}] -add_delay -clock_fall +set_input_delay -clock [get_clocks phy_rxclk] -min 0.000 [get_ports {phy_rxd[*] phy_rxctl_rxdv}] -add_delay -clock_fall + +# False paths +set_false_path -to [get_ports phy_reset] + +# MDIO BiDir +set_input_delay -clock [get_generated_clocks clk_pll_i] -max 8.000 [get_ports phy_mdio] +set_input_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay 1.000 [get_ports phy_mdio] +set_output_delay -clock [get_generated_clocks clk_pll_i] -max -add_delay 1.000 [get_ports phy_mdio] +set_output_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports phy_mdio] + +# MDIO - Outputs +set_output_delay -clock [get_generated_clocks clk_pll_i] -max 1.000 [get_ports phy_mdc] +set_output_delay -clock [get_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports phy_mdc] + +# apply the same IDELAY_VALUE to all GMII RX inputs +set_property IDELAY_VALUE 20 [get_cells {eth0.delay* eth0.rgmii*.delay*}] + +# Group IODELAY and IDELAYCTRL components to aid placement +set_property IODELAY_GROUP kc705_ethernet_rgmii_grp1 [get_cells {eth0.delay* eth0.rgmii*.delay*}] +set_property IODELAY_GROUP kc705_ethernet_rgmii_grp1 [get_cells {eth0.dlyctrl0}] + + +#----------------------------------------------------------- +# Pins etc. +#----------------------------------------------------------- + +# System Clock +set_property PACKAGE_PIN R3 [get_ports clk200p] +set_property PACKAGE_PIN P3 [get_ports clk200n] +set_property IOSTANDARD DIFF_SSTL15 [get_ports clk200p] +set_property IOSTANDARD DIFF_SSTL15 [get_ports clk200n] +set_property VCCAUX_IO DONTCARE [get_ports clk200p] +set_property VCCAUX_IO DONTCARE [get_ports clk200n] + +#set_property slave_banks {32 34} [get_iobanks 33] +#set_property DCI_CASCADE {32 34} [get_iobanks 33] + +# Reset is set to CPU_RESET +set_property PACKAGE_PIN U4 [get_ports reset] +set_property IOSTANDARD LVCMOS15 [get_ports reset] + +# --- SPI +#set_property PACKAGE_PIN P18 [get_ports spi_sel_n] +#set_property PACKAGE_PIN H13 [get_ports spi_clk] +#set_property PACKAGE_PIN R14 [get_ports spi_miso] +#set_property IOSTANDARD LVCMOS33 [get_ports spi_*] + +# UART - Checked +set_property PACKAGE_PIN T19 [get_ports dsutx] +set_property PACKAGE_PIN W19 [get_ports dsuctsn] +set_property PACKAGE_PIN U19 [get_ports dsurx] +set_property PACKAGE_PIN V19 [get_ports dsurtsn] + +set_property IOSTANDARD LVCMOS18 [get_ports dsu*] + +# Buttons +set_property PACKAGE_PIN P6 [get_ports {button[0]}] +set_property PACKAGE_PIN T5 [get_ports {button[1]}] +set_property PACKAGE_PIN R5 [get_ports {button[2]}] +set_property PACKAGE_PIN U6 [get_ports {button[3]}] + +set_property IOSTANDARD LVCMOS15 [get_ports {button[0]}] +set_property IOSTANDARD SSTL15 [get_ports {button[1]}] +set_property IOSTANDARD SSTL15 [get_ports {button[2]}] +set_property IOSTANDARD SSTL15 [get_ports {button[3]}] + +# LED Interface +set_property PACKAGE_PIN M26 [get_ports {led[0]}] +set_property PACKAGE_PIN T24 [get_ports {led[1]}] +set_property PACKAGE_PIN T25 [get_ports {led[2]}] +set_property PACKAGE_PIN R26 [get_ports {led[3]}] + +set_property IOSTANDARD LVCMOS33 [get_ports led*] + +# Switches +set_property PACKAGE_PIN R8 [get_ports {switch[0]}] +set_property PACKAGE_PIN P8 [get_ports {switch[1]}] +set_property PACKAGE_PIN R7 [get_ports {switch[2]}] +set_property PACKAGE_PIN R6 [get_ports {switch[3]}] + +set_property IOSTANDARD SSTL15 [get_ports switch*] + +# I2C +set_property PACKAGE_PIN N18 [get_ports iic_scl] +set_property PACKAGE_PIN K25 [get_ports iic_sda] + +set_property IOSTANDARD LVCMOS33 [get_ports iic*] + diff --git a/boards/xilinx-kc705-xc7k325t/xilinx-kc705-xc7k325t.xdc b/boards/xilinx-kc705-xc7k325t/xilinx-kc705-xc7k325t.xdc index d423e101..efbe38c0 100644 --- a/boards/xilinx-kc705-xc7k325t/xilinx-kc705-xc7k325t.xdc +++ b/boards/xilinx-kc705-xc7k325t/xilinx-kc705-xc7k325t.xdc @@ -121,12 +121,12 @@ set_false_path -from [get_clocks -include_generated_clocks phy_gtxclk] -through #set_output_delay -clock [get_clocks -include_generated_clocks phy_gtxclk] -min 1.000 [get_ports phy_txctl_txen] -add_delay -clock_fall #output timing for rgmii - derated slightly due to pessimism in the tools -create_generated_clock -name rgmii_tx_clk -divide_by 1 -source [get_pins eth0.rgmii0/rgmii_tx_clk/*/*/C] [get_ports phy_gtxclk] +#create_generated_clock -name rgmii_tx_clk -divide_by 1 -source [get_pins eth0.rgmii0/rgmii_tx_clk/*/*/C] [get_ports phy_gtxclk] -set_output_delay 0.75 -max -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -set_output_delay -0.7 -min -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -set_output_delay 0.75 -max -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -clock_fall -add_delay -set_output_delay -0.7 -min -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -clock_fall -add_delay +#set_output_delay 0.75 -max -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] +#set_output_delay -0.7 -min -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] +#set_output_delay 0.75 -max -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -clock_fall -add_delay +#set_output_delay -0.7 -min -clock [get_clocks rgmii_tx_clk] [get_ports {phy_txd[*] phy_txctl_txen}] -clock_fall -add_delay # Inputs @@ -170,7 +170,7 @@ set_output_delay -clock [get_clocks -include_generated_clocks clk_pll_i] -max 1. set_output_delay -clock [get_clocks -include_generated_clocks clk_pll_i] -min -add_delay -1.000 [get_ports phy_mdc] # apply the same IDELAY_VALUE to all GMII RX inputs -set_property IDELAY_VALUE 20 [get_cells {eth0.delay* eth0.rgmii*.delay*}] +#set_property IDELAY_VALUE 20 [get_cells {eth0.delay* eth0.rgmii*.delay*}] # Group IODELAY and IDELAYCTRL components to aid placement set_property IODELAY_GROUP kc705_ethernet_rgmii_grp1 [get_cells {eth0.delay* eth0.rgmii*.delay*}] diff --git a/designs/leon3-altera-c5ekit/.config b/designs/leon3-altera-c5ekit/.config index e4d1892e..43b95f4b 100644 --- a/designs/leon3-altera-c5ekit/.config +++ b/designs/leon3-altera-c5ekit/.config @@ -133,7 +133,6 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_LZ16 is not set CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set @@ -198,7 +197,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000000 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-altera-c5ekit/clkgen_c5ekit.vhd b/designs/leon3-altera-c5ekit/clkgen_c5ekit.vhd index 4c710568..0ad39263 100644 --- a/designs/leon3-altera-c5ekit/clkgen_c5ekit.vhd +++ b/designs/leon3-altera-c5ekit/clkgen_c5ekit.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/config.h b/designs/leon3-altera-c5ekit/config.h index 3dd6e1e8..57fe7dff 100644 --- a/designs/leon3-altera-c5ekit/config.h +++ b/designs/leon3-altera-c5ekit/config.h @@ -129,7 +129,6 @@ #undef CONFIG_DCACHE_LZ16 #define CONFIG_DCACHE_LZ32 1 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM @@ -188,7 +187,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000000 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-altera-c5ekit/config.help b/designs/leon3-altera-c5ekit/config.help index 4433548b..1c6f3477 100644 --- a/designs/leon3-altera-c5ekit/config.help +++ b/designs/leon3-altera-c5ekit/config.help @@ -348,19 +348,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -368,10 +369,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-c5ekit/config.vhd b/designs/leon3-altera-c5ekit/config.vhd index c63fa434..108d2957 100644 --- a/designs/leon3-altera-c5ekit/config.vhd +++ b/designs/leon3-altera-c5ekit/config.vhd @@ -48,7 +48,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-c5ekit/config.vhd.h b/designs/leon3-altera-c5ekit/config.vhd.h index 7c0cc5c6..1adffb8a 100644 --- a/designs/leon3-altera-c5ekit/config.vhd.h +++ b/designs/leon3-altera-c5ekit/config.vhd.h @@ -35,7 +35,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-c5ekit/ddr3if.vhd b/designs/leon3-altera-c5ekit/ddr3if.vhd index e77eca27..2bfcc348 100644 --- a/designs/leon3-altera-c5ekit/ddr3if.vhd +++ b/designs/leon3-altera-c5ekit/ddr3if.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/lconfig.tk b/designs/leon3-altera-c5ekit/lconfig.tk index 4f0e4632..3299a8fd 100755 --- a/designs/leon3-altera-c5ekit/lconfig.tk +++ b/designs/leon3-altera-c5ekit/lconfig.tk @@ -1867,24 +1867,23 @@ proc menu5 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 5 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 5 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 5 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 5 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 5 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 5 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 5 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 5 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 5 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_17 - minimenu $w.config.f 5 20 "Local data RAM size (kbytes)" tmpvar_17 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_17 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_17 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_17 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_17 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_17 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_17 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_17 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_17 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_17 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 5 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 5 19 "Local data RAM size (kbytes)" tmpvar_17 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_17 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_17 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_17 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_17 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_17 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_17 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_17 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_17 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_17 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 5 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -1956,20 +1955,17 @@ proc update_menu5 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu5.config.f.x15 normal {n l y}} else {configure_entry .menu5.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu5.config.f.x16 normal {n l y}} else {configure_entry .menu5.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu5.config.f.x17 normal {n l y}} else {configure_entry .menu5.config.f.x17 disabled {y n l}} + configure_entry .menu5.config.f.x16 normal {n l y}} else {configure_entry .menu5.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu5.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu5.config.f.x18.l configure -state normal; } else {.menu5.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu5.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu5.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu5.config.f.x17.l configure -state normal; } else {.menu5.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu5.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu5.config.f.x19 normal {n l y}} else {configure_entry .menu5.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu5.config.f.x20 normal {x l}} else {configure_entry .menu5.config.f.x20 disabled {x l}} + configure_entry .menu5.config.f.x18 normal {n l y}} else {configure_entry .menu5.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu5.config.f.x19 normal {x l}} else {configure_entry .menu5.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu5.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu5.config.f.x21.l configure -state normal; } else {.menu5.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu5.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu5.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu5.config.f.x20.l configure -state normal; } else {.menu5.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu5.config.f.x20.l configure -state disabled} } @@ -2102,9 +2098,6 @@ proc update_define_menu5 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -2915,7 +2908,7 @@ proc menu11 {w title} { hex $w.config.f 11 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 11 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 11 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 11 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 11 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -2965,12 +2958,11 @@ proc update_menu11 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu11.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu11.config.f.x6.l configure -state normal; } else {.menu11.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu11.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu11.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu11.config.f.x7.l configure -state normal; } else {.menu11.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu11.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu11.config.f.x8 normal {n l y}} else {configure_entry .menu11.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu11.config.f.x9 normal {n l y}} else {configure_entry .menu11.config.f.x9 disabled {y n l}} } @@ -3001,12 +2993,11 @@ proc update_define_menu11 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4116,7 +4107,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4265,6 +4255,7 @@ set CONFIG_GRGPIO_WIDTH 8 set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4674,7 +4665,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_16 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -4797,10 +4787,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Synchronous SRAM controller " @@ -4840,6 +4829,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_29 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-altera-c5ekit/leon3mp.vhd b/designs/leon3-altera-c5ekit/leon3mp.vhd index 76905ee8..ff328639 100644 --- a/designs/leon3-altera-c5ekit/leon3mp.vhd +++ b/designs/leon3-altera-c5ekit/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/lpddr2if.vhd b/designs/leon3-altera-c5ekit/lpddr2if.vhd index 08734941..c0baf30c 100644 --- a/designs/leon3-altera-c5ekit/lpddr2if.vhd +++ b/designs/leon3-altera-c5ekit/lpddr2if.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/memifsim.vhd b/designs/leon3-altera-c5ekit/memifsim.vhd index c78bfdc4..9841a9fb 100644 --- a/designs/leon3-altera-c5ekit/memifsim.vhd +++ b/designs/leon3-altera-c5ekit/memifsim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/pllsim.vhd b/designs/leon3-altera-c5ekit/pllsim.vhd index 098c63b7..737a29f8 100644 --- a/designs/leon3-altera-c5ekit/pllsim.vhd +++ b/designs/leon3-altera-c5ekit/pllsim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/testbench.vhd b/designs/leon3-altera-c5ekit/testbench.vhd index 0a44bcf0..7d4ccf22 100644 --- a/designs/leon3-altera-c5ekit/testbench.vhd +++ b/designs/leon3-altera-c5ekit/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-c5ekit/tkconfig.h b/designs/leon3-altera-c5ekit/tkconfig.h index 9bce099b..d3499b3c 100644 --- a/designs/leon3-altera-c5ekit/tkconfig.h +++ b/designs/leon3-altera-c5ekit/tkconfig.h @@ -407,10 +407,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd b/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd index e2293e4c..5973947e 100644 --- a/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd +++ b/designs/leon3-altera-de2-ep2c35/clkgen_de2.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-de2-ep2c35/config.help b/designs/leon3-altera-de2-ep2c35/config.help index fc485609..0d7c416a 100644 --- a/designs/leon3-altera-de2-ep2c35/config.help +++ b/designs/leon3-altera-de2-ep2c35/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-de2-ep2c35/config.vhd b/designs/leon3-altera-de2-ep2c35/config.vhd index 8ad142c2..95e13021 100644 --- a/designs/leon3-altera-de2-ep2c35/config.vhd +++ b/designs/leon3-altera-de2-ep2c35/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-de2-ep2c35/config.vhd.h b/designs/leon3-altera-de2-ep2c35/config.vhd.h index f71de1e8..cb31cda6 100644 --- a/designs/leon3-altera-de2-ep2c35/config.vhd.h +++ b/designs/leon3-altera-de2-ep2c35/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-de2-ep2c35/lconfig.tk b/designs/leon3-altera-de2-ep2c35/lconfig.tk index e51e5651..772fe14d 100755 --- a/designs/leon3-altera-de2-ep2c35/lconfig.tk +++ b/designs/leon3-altera-de2-ep2c35/lconfig.tk @@ -2086,24 +2086,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2175,20 +2174,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2321,9 +2317,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4429,7 +4422,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4568,6 +4560,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -5024,7 +5017,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-altera-de2-ep2c35/leon3mp.vhd b/designs/leon3-altera-de2-ep2c35/leon3mp.vhd index c99b91f3..7f0f673a 100644 --- a/designs/leon3-altera-de2-ep2c35/leon3mp.vhd +++ b/designs/leon3-altera-de2-ep2c35/leon3mp.vhd @@ -5,7 +5,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-de2-ep2c35/sdctrl16.vhd b/designs/leon3-altera-de2-ep2c35/sdctrl16.vhd index ba718144..f0253087 100644 --- a/designs/leon3-altera-de2-ep2c35/sdctrl16.vhd +++ b/designs/leon3-altera-de2-ep2c35/sdctrl16.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-de2-ep2c35/testbench.vhd b/designs/leon3-altera-de2-ep2c35/testbench.vhd index b50eeb56..1c84dfc0 100644 --- a/designs/leon3-altera-de2-ep2c35/testbench.vhd +++ b/designs/leon3-altera-de2-ep2c35/testbench.vhd @@ -5,7 +5,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-de2-ep2c35/tkconfig.h b/designs/leon3-altera-de2-ep2c35/tkconfig.h index 1376c626..b52aae60 100644 --- a/designs/leon3-altera-de2-ep2c35/tkconfig.h +++ b/designs/leon3-altera-de2-ep2c35/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep1c20/.config b/designs/leon3-altera-ep1c20/.config index b64e4117..843f1589 100755 --- a/designs/leon3-altera-ep1c20/.config +++ b/designs/leon3-altera-ep1c20/.config @@ -156,7 +156,6 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_LZ16 is not set CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 diff --git a/designs/leon3-altera-ep1c20/clkgen_ep1c20board.vhd b/designs/leon3-altera-ep1c20/clkgen_ep1c20board.vhd index 4fb664c2..b6f90d93 100644 --- a/designs/leon3-altera-ep1c20/clkgen_ep1c20board.vhd +++ b/designs/leon3-altera-ep1c20/clkgen_ep1c20board.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep1c20/config.h b/designs/leon3-altera-ep1c20/config.h index a26c2a8d..a8436a62 100644 --- a/designs/leon3-altera-ep1c20/config.h +++ b/designs/leon3-altera-ep1c20/config.h @@ -151,7 +151,6 @@ #undef CONFIG_DCACHE_LZ16 #define CONFIG_DCACHE_LZ32 1 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* diff --git a/designs/leon3-altera-ep1c20/config.help b/designs/leon3-altera-ep1c20/config.help index e2fa3b28..a2717715 100644 --- a/designs/leon3-altera-ep1c20/config.help +++ b/designs/leon3-altera-ep1c20/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep1c20/config.vhd b/designs/leon3-altera-ep1c20/config.vhd index 820bd5c0..91bff3e9 100644 --- a/designs/leon3-altera-ep1c20/config.vhd +++ b/designs/leon3-altera-ep1c20/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-ep1c20/config.vhd.h b/designs/leon3-altera-ep1c20/config.vhd.h index aaa50a89..25edebc1 100644 --- a/designs/leon3-altera-ep1c20/config.vhd.h +++ b/designs/leon3-altera-ep1c20/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep1c20/lconfig.tk b/designs/leon3-altera-ep1c20/lconfig.tk index b7ba674f..9dc37437 100755 --- a/designs/leon3-altera-ep1c20/lconfig.tk +++ b/designs/leon3-altera-ep1c20/lconfig.tk @@ -2077,24 +2077,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2166,20 +2165,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2312,9 +2308,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4381,7 +4374,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4537,6 +4529,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4991,7 +4984,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-altera-ep1c20/leon3mp.vhd b/designs/leon3-altera-ep1c20/leon3mp.vhd index 033c3406..5184c15e 100644 --- a/designs/leon3-altera-ep1c20/leon3mp.vhd +++ b/designs/leon3-altera-ep1c20/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep1c20/testbench.vhd b/designs/leon3-altera-ep1c20/testbench.vhd index 1a86e7be..51729e96 100644 --- a/designs/leon3-altera-ep1c20/testbench.vhd +++ b/designs/leon3-altera-ep1c20/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep1c20/tkconfig.h b/designs/leon3-altera-ep1c20/tkconfig.h index a337a676..39896331 100644 --- a/designs/leon3-altera-ep1c20/tkconfig.h +++ b/designs/leon3-altera-ep1c20/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep2s60-ddr/.config b/designs/leon3-altera-ep2s60-ddr/.config index 4b9fe3da..6f24d3bf 100755 --- a/designs/leon3-altera-ep2s60-ddr/.config +++ b/designs/leon3-altera-ep2s60-ddr/.config @@ -165,7 +165,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 diff --git a/designs/leon3-altera-ep2s60-ddr/config.h b/designs/leon3-altera-ep2s60-ddr/config.h index f1073b2f..6f3e53cd 100644 --- a/designs/leon3-altera-ep2s60-ddr/config.h +++ b/designs/leon3-altera-ep2s60-ddr/config.h @@ -160,7 +160,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* diff --git a/designs/leon3-altera-ep2s60-ddr/config.help b/designs/leon3-altera-ep2s60-ddr/config.help index 74748ed6..cb0596d3 100644 --- a/designs/leon3-altera-ep2s60-ddr/config.help +++ b/designs/leon3-altera-ep2s60-ddr/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep2s60-ddr/config.vhd b/designs/leon3-altera-ep2s60-ddr/config.vhd index 729ac747..49c677d1 100644 --- a/designs/leon3-altera-ep2s60-ddr/config.vhd +++ b/designs/leon3-altera-ep2s60-ddr/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-ep2s60-ddr/config.vhd.h b/designs/leon3-altera-ep2s60-ddr/config.vhd.h index fb1465ad..70e7f6a2 100644 --- a/designs/leon3-altera-ep2s60-ddr/config.vhd.h +++ b/designs/leon3-altera-ep2s60-ddr/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep2s60-ddr/lconfig.tk b/designs/leon3-altera-ep2s60-ddr/lconfig.tk index 713e1f43..945a41c2 100755 --- a/designs/leon3-altera-ep2s60-ddr/lconfig.tk +++ b/designs/leon3-altera-ep2s60-ddr/lconfig.tk @@ -2077,24 +2077,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2166,20 +2165,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2312,9 +2308,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4317,7 +4310,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4451,6 +4443,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4905,7 +4898,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-altera-ep2s60-ddr/leon3mp.vhd b/designs/leon3-altera-ep2s60-ddr/leon3mp.vhd index 182e4ac0..317b1882 100644 --- a/designs/leon3-altera-ep2s60-ddr/leon3mp.vhd +++ b/designs/leon3-altera-ep2s60-ddr/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep2s60-ddr/testbench.vhd b/designs/leon3-altera-ep2s60-ddr/testbench.vhd index cbf17da5..0ceffb93 100644 --- a/designs/leon3-altera-ep2s60-ddr/testbench.vhd +++ b/designs/leon3-altera-ep2s60-ddr/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -28,8 +28,6 @@ use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.components.all; library cypress; use cypress.components.all; @@ -159,13 +157,14 @@ begin dsubren, dsuact, rxd1, txd1, eth_aen, eth_readn, eth_writen, eth_nbe); - ddr0 : mt46v16m16 - generic map (index => -1, fname => sdramfile) - port map( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); + ddr2: ddrram + generic map (width => 16, abits => 13, + colbits => 9, rowbits => 12, implbanks => 1, + fname => sdramfile, igndqs => 1) + port map ( + ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs); datazz <= "HHHH"; diff --git a/designs/leon3-altera-ep2s60-ddr/tkconfig.h b/designs/leon3-altera-ep2s60-ddr/tkconfig.h index df3ca55b..0973a38a 100644 --- a/designs/leon3-altera-ep2s60-ddr/tkconfig.h +++ b/designs/leon3-altera-ep2s60-ddr/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep2s60-sdr/.config b/designs/leon3-altera-ep2s60-sdr/.config index 65225f58..ad196a3a 100755 --- a/designs/leon3-altera-ep2s60-sdr/.config +++ b/designs/leon3-altera-ep2s60-sdr/.config @@ -166,7 +166,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 diff --git a/designs/leon3-altera-ep2s60-sdr/config.h b/designs/leon3-altera-ep2s60-sdr/config.h index fc34ff6e..bb7d8d17 100644 --- a/designs/leon3-altera-ep2s60-sdr/config.h +++ b/designs/leon3-altera-ep2s60-sdr/config.h @@ -161,7 +161,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* diff --git a/designs/leon3-altera-ep2s60-sdr/config.help b/designs/leon3-altera-ep2s60-sdr/config.help index e2fa3b28..a2717715 100644 --- a/designs/leon3-altera-ep2s60-sdr/config.help +++ b/designs/leon3-altera-ep2s60-sdr/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep2s60-sdr/config.vhd b/designs/leon3-altera-ep2s60-sdr/config.vhd index 3511897e..f90b5b28 100644 --- a/designs/leon3-altera-ep2s60-sdr/config.vhd +++ b/designs/leon3-altera-ep2s60-sdr/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-ep2s60-sdr/config.vhd.h b/designs/leon3-altera-ep2s60-sdr/config.vhd.h index aaa50a89..25edebc1 100644 --- a/designs/leon3-altera-ep2s60-sdr/config.vhd.h +++ b/designs/leon3-altera-ep2s60-sdr/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep2s60-sdr/lconfig.tk b/designs/leon3-altera-ep2s60-sdr/lconfig.tk index b7ba674f..9dc37437 100755 --- a/designs/leon3-altera-ep2s60-sdr/lconfig.tk +++ b/designs/leon3-altera-ep2s60-sdr/lconfig.tk @@ -2077,24 +2077,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2166,20 +2165,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2312,9 +2308,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4381,7 +4374,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4537,6 +4529,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4991,7 +4984,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd b/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd index 3dd6a44b..819ad797 100644 --- a/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd +++ b/designs/leon3-altera-ep2s60-sdr/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep2s60-sdr/testbench.vhd b/designs/leon3-altera-ep2s60-sdr/testbench.vhd index 38ecb78d..a2d37e3a 100644 --- a/designs/leon3-altera-ep2s60-sdr/testbench.vhd +++ b/designs/leon3-altera-ep2s60-sdr/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep2s60-sdr/tkconfig.h b/designs/leon3-altera-ep2s60-sdr/tkconfig.h index a337a676..39896331 100644 --- a/designs/leon3-altera-ep2s60-sdr/tkconfig.h +++ b/designs/leon3-altera-ep2s60-sdr/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep2sgx90-av/.config b/designs/leon3-altera-ep2sgx90-av/.config index 39d9b5ad..5837d40b 100644 --- a/designs/leon3-altera-ep2sgx90-av/.config +++ b/designs/leon3-altera-ep2sgx90-av/.config @@ -251,7 +251,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=02007A CONFIG_DSU_ETHLSB=CC0001 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-altera-ep2sgx90-av/README.txt b/designs/leon3-altera-ep2sgx90-av/README.txt index a4bd19d9..eb211f41 100644 --- a/designs/leon3-altera-ep2sgx90-av/README.txt +++ b/designs/leon3-altera-ep2sgx90-av/README.txt @@ -3,6 +3,13 @@ This Leon3 design is tailored to the Altera Audio Video Development Kit, Stratix II GX Edition. --------------------------------------------------------------------- + +NOTE: This design was contributed to GRLIB. Aeroflex Gaisler does not +have a board to test the design and it is not kept up to +date. Currently the design testbench does not allow simulation. + + + Development board product page: http://www.altera.com/products/devkits/altera/kit-dsp-professional.html diff --git a/designs/leon3-altera-ep2sgx90-av/config.h b/designs/leon3-altera-ep2sgx90-av/config.h index 4f2dfc1b..cf74a5a5 100644 --- a/designs/leon3-altera-ep2sgx90-av/config.h +++ b/designs/leon3-altera-ep2sgx90-av/config.h @@ -240,7 +240,6 @@ #define CONFIG_DSU_ETHMSB 02007A #define CONFIG_DSU_ETHLSB CC0001 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-altera-ep2sgx90-av/config.help b/designs/leon3-altera-ep2sgx90-av/config.help index f974a7d6..ecfcf8a1 100644 --- a/designs/leon3-altera-ep2sgx90-av/config.help +++ b/designs/leon3-altera-ep2sgx90-av/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep2sgx90-av/config.vhd b/designs/leon3-altera-ep2sgx90-av/config.vhd index 0d0b9a47..cc4b26de 100644 --- a/designs/leon3-altera-ep2sgx90-av/config.vhd +++ b/designs/leon3-altera-ep2sgx90-av/config.vhd @@ -68,7 +68,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-ep2sgx90-av/config.vhd.h b/designs/leon3-altera-ep2sgx90-av/config.vhd.h index cfad4c23..35ea51d0 100644 --- a/designs/leon3-altera-ep2sgx90-av/config.vhd.h +++ b/designs/leon3-altera-ep2sgx90-av/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep2sgx90-av/lconfig.tk b/designs/leon3-altera-ep2sgx90-av/lconfig.tk index db0640ea..86847392 100755 --- a/designs/leon3-altera-ep2sgx90-av/lconfig.tk +++ b/designs/leon3-altera-ep2sgx90-av/lconfig.tk @@ -2078,24 +2078,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2167,20 +2166,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2313,9 +2309,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3126,7 +3119,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3176,12 +3169,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3212,12 +3204,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4591,7 +4582,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4762,6 +4752,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5219,7 +5210,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5342,10 +5332,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5445,6 +5434,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-altera-ep2sgx90-av/sram32.vhd b/designs/leon3-altera-ep2sgx90-av/sram32.vhd index d7dd68de..19a4bd1e 100644 --- a/designs/leon3-altera-ep2sgx90-av/sram32.vhd +++ b/designs/leon3-altera-ep2sgx90-av/sram32.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep2sgx90-av/testbench.vhd b/designs/leon3-altera-ep2sgx90-av/testbench.vhd index 746670dc..41f3782e 100644 --- a/designs/leon3-altera-ep2sgx90-av/testbench.vhd +++ b/designs/leon3-altera-ep2sgx90-av/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -32,8 +32,6 @@ library micron; use micron.components.all; library cypress; use cypress.components.all; -library hynix; -use hynix.components.all; use work.debug.all; @@ -293,25 +291,16 @@ begin --DDR2 - ddr2mem : for i in 0 to 3 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => false, PUSCheckFlag => false, - index => 3-i, fname => sdramfile) - port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqs(i*2), - LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqs(i*2+1), - UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2), - WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(0), - BA => ddr_ba, ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(0), - CLK => ddr_clk(0), CLKB => ddr_clkb(0), UDM => ddr_dm(i*2+1)); - --- PORT MAP( --- ck => ddr_clk(0), ck_n => ddr_clkb(0), cke => ddr_cke(0), cs_n => ddr_csb(0), --- ras_n => ddr_rasb, cas_n => ddr_casb, we_n => ddr_web, --- dm_rdqs => ddr_dm(i*2+1 downto i*2), ba => ddr_ba, --- addr => ddr_ad(12 downto 0), dq => ddr_dq(i*16+15 downto i*16), --- dqs => ddr_dqs(i*2+1 downto i*2), dqs_n => ddr_dqsn(i*2+1 downto i*2), --- rdqs_n => ddr_rdqs(i*2+1 downto i*2), odt => ddr_odt(0)); - end generate; + ddr2mem0: ddr2ram + generic map ( + width => 64, abits => 14, babits => 2, + colbits => 10, implbanks => 1, fname => sdramfile + ) + port map ( + ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), odt => ddr_odt(0), + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, dm => ddr_dm, ba => ddr_ba, a => ddr_ad, + dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn + ); -- ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns; ddr_dqsn <= (others => 'U'); diff --git a/designs/leon3-altera-ep2sgx90-av/tkconfig.h b/designs/leon3-altera-ep2sgx90-av/tkconfig.h index 3e144981..65043cd2 100644 --- a/designs/leon3-altera-ep2sgx90-av/tkconfig.h +++ b/designs/leon3-altera-ep2sgx90-av/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep3c25-eek/.config b/designs/leon3-altera-ep3c25-eek/.config index 8d3d2a34..def59344 100755 --- a/designs/leon3-altera-ep3c25-eek/.config +++ b/designs/leon3-altera-ep3c25-eek/.config @@ -166,7 +166,6 @@ CONFIG_DCACHE_ALGOLRR=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -252,7 +251,6 @@ CONFIG_DSU_IPLSB=0039 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000011 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals @@ -283,7 +281,7 @@ CONFIG_DDRSP=y CONFIG_DDRSP_INIT=y CONFIG_DDRSP_FREQ=100 CONFIG_DDRSP_COL=9 -CONFIG_DDRSP_MBYTE=8 +CONFIG_DDRSP_MBYTE=32 CONFIG_DDRSP_RSKEW=2500 # diff --git a/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd b/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd index b33793ad..465c1248 100644 --- a/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd +++ b/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep3c25-eek/config.h b/designs/leon3-altera-ep3c25-eek/config.h index 7ecd5855..9a06bf16 100644 --- a/designs/leon3-altera-ep3c25-eek/config.h +++ b/designs/leon3-altera-ep3c25-eek/config.h @@ -161,7 +161,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -241,7 +240,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000011 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ @@ -267,7 +265,7 @@ #define CONFIG_DDRSP_INIT 1 #define CONFIG_DDRSP_FREQ (100) #define CONFIG_DDRSP_COL (9) -#define CONFIG_DDRSP_MBYTE (8) +#define CONFIG_DDRSP_MBYTE (32) #define CONFIG_DDRSP_RSKEW (2500) /* * SPI memory controller diff --git a/designs/leon3-altera-ep3c25-eek/config.help b/designs/leon3-altera-ep3c25-eek/config.help index 5dc6f663..110aab9c 100644 --- a/designs/leon3-altera-ep3c25-eek/config.help +++ b/designs/leon3-altera-ep3c25-eek/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep3c25-eek/config.vhd b/designs/leon3-altera-ep3c25-eek/config.vhd index 1a64c152..60b0340d 100644 --- a/designs/leon3-altera-ep3c25-eek/config.vhd +++ b/designs/leon3-altera-ep3c25-eek/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 1; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -121,7 +121,7 @@ package config is constant CFG_DDRSP_INIT : integer := 1; constant CFG_DDRSP_FREQ : integer := (100); constant CFG_DDRSP_COL : integer := (9); - constant CFG_DDRSP_SIZE : integer := (8); + constant CFG_DDRSP_SIZE : integer := (32); constant CFG_DDRSP_RSKEW : integer := (2500); -- SPI memory controller constant CFG_SPIMCTRL : integer := 0; diff --git a/designs/leon3-altera-ep3c25-eek/config.vhd.h b/designs/leon3-altera-ep3c25-eek/config.vhd.h index 51d935ce..82e9c704 100644 --- a/designs/leon3-altera-ep3c25-eek/config.vhd.h +++ b/designs/leon3-altera-ep3c25-eek/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep3c25-eek/lconfig.tk b/designs/leon3-altera-ep3c25-eek/lconfig.tk index 491440f7..49cf7883 100755 --- a/designs/leon3-altera-ep3c25-eek/lconfig.tk +++ b/designs/leon3-altera-ep3c25-eek/lconfig.tk @@ -2083,24 +2083,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2172,20 +2171,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2318,9 +2314,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3131,7 +3124,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3181,12 +3174,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3217,12 +3209,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5152,7 +5143,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5338,6 +5328,7 @@ set CONFIG_SVGA_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5794,7 +5785,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5917,10 +5907,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6017,6 +6006,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-altera-ep3c25-eek/leon3mp.vhd b/designs/leon3-altera-ep3c25-eek/leon3mp.vhd index 680fff58..55fe468d 100644 --- a/designs/leon3-altera-ep3c25-eek/leon3mp.vhd +++ b/designs/leon3-altera-ep3c25-eek/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep3c25-eek/serializer.vhd b/designs/leon3-altera-ep3c25-eek/serializer.vhd index 83728b0d..7ea4a4b7 100644 --- a/designs/leon3-altera-ep3c25-eek/serializer.vhd +++ b/designs/leon3-altera-ep3c25-eek/serializer.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep3c25-eek/testbench.vhd b/designs/leon3-altera-ep3c25-eek/testbench.vhd index 6961f900..e22e6c87 100644 --- a/designs/leon3-altera-ep3c25-eek/testbench.vhd +++ b/designs/leon3-altera-ep3c25-eek/testbench.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -255,14 +255,21 @@ begin hc_sd_dat <= 'Z'; hc_sd_cmd <= 'Z'; -- hc_sd_dat <= hc_sd_cmd; -- Loopback - ddr0 : mt46v16m16 - generic map (index => -1, fname => sdramfile) - port map( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); - + -- ddr0 : mt46v16m16 + -- generic map (index => -1, fname => sdramfile) + -- port map( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + ddr0 : ddrram + generic map(width => 16, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 1) + port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); + datazz <= "HHHH"; ssram_adsp_n <= '1'; ssram_adv_n <= '1'; diff --git a/designs/leon3-altera-ep3c25-eek/tkconfig.h b/designs/leon3-altera-ep3c25-eek/tkconfig.h index ee536574..e2234350 100644 --- a/designs/leon3-altera-ep3c25-eek/tkconfig.h +++ b/designs/leon3-altera-ep3c25-eek/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep3c25/.config b/designs/leon3-altera-ep3c25/.config index 376eac18..950a2e77 100755 --- a/designs/leon3-altera-ep3c25/.config +++ b/designs/leon3-altera-ep3c25/.config @@ -165,7 +165,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -263,7 +262,7 @@ CONFIG_DDRSP=y CONFIG_DDRSP_INIT=y CONFIG_DDRSP_FREQ=100 CONFIG_DDRSP_COL=9 -CONFIG_DDRSP_MBYTE=8 +CONFIG_DDRSP_MBYTE=32 CONFIG_DDRSP_RSKEW=2500 # diff --git a/designs/leon3-altera-ep3c25/config.h b/designs/leon3-altera-ep3c25/config.h index d0e61e93..3005264f 100644 --- a/designs/leon3-altera-ep3c25/config.h +++ b/designs/leon3-altera-ep3c25/config.h @@ -160,7 +160,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -247,7 +246,7 @@ #define CONFIG_DDRSP_INIT 1 #define CONFIG_DDRSP_FREQ (100) #define CONFIG_DDRSP_COL (9) -#define CONFIG_DDRSP_MBYTE (8) +#define CONFIG_DDRSP_MBYTE (32) #define CONFIG_DDRSP_RSKEW (2500) /* * On-chip RAM/ROM diff --git a/designs/leon3-altera-ep3c25/config.help b/designs/leon3-altera-ep3c25/config.help index c939820f..b68d7b3a 100644 --- a/designs/leon3-altera-ep3c25/config.help +++ b/designs/leon3-altera-ep3c25/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep3c25/config.vhd b/designs/leon3-altera-ep3c25/config.vhd index d7838abc..881c3d23 100644 --- a/designs/leon3-altera-ep3c25/config.vhd +++ b/designs/leon3-altera-ep3c25/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -114,7 +114,7 @@ package config is constant CFG_DDRSP_INIT : integer := 1; constant CFG_DDRSP_FREQ : integer := (100); constant CFG_DDRSP_COL : integer := (9); - constant CFG_DDRSP_SIZE : integer := (8); + constant CFG_DDRSP_SIZE : integer := (32); constant CFG_DDRSP_RSKEW : integer := (2500); -- AHB ROM constant CFG_AHBROMEN : integer := 0; diff --git a/designs/leon3-altera-ep3c25/config.vhd.h b/designs/leon3-altera-ep3c25/config.vhd.h index 7b55e5c6..3a8bcf7a 100644 --- a/designs/leon3-altera-ep3c25/config.vhd.h +++ b/designs/leon3-altera-ep3c25/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep3c25/lconfig.tk b/designs/leon3-altera-ep3c25/lconfig.tk index 84b0963d..47bf243a 100755 --- a/designs/leon3-altera-ep3c25/lconfig.tk +++ b/designs/leon3-altera-ep3c25/lconfig.tk @@ -2078,24 +2078,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2167,20 +2166,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2313,9 +2309,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4426,7 +4419,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4562,6 +4554,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5016,7 +5009,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-altera-ep3c25/leon3mp.vhd b/designs/leon3-altera-ep3c25/leon3mp.vhd index dd72c1bd..463b2644 100644 --- a/designs/leon3-altera-ep3c25/leon3mp.vhd +++ b/designs/leon3-altera-ep3c25/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep3c25/testbench.vhd b/designs/leon3-altera-ep3c25/testbench.vhd index 570ee97d..68052c6a 100644 --- a/designs/leon3-altera-ep3c25/testbench.vhd +++ b/designs/leon3-altera-ep3c25/testbench.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -163,13 +163,21 @@ begin ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, dsubren, dsuact, rxd1, txd1, gpio); - ddr0 : mt46v16m16 - generic map (index => -1, fname => sdramfile) - port map( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); + -- ddr0 : mt46v16m16 + -- generic map (index => -1, fname => sdramfile) + -- port map( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + + ddr0 : ddrram + generic map(width => 16, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 1) + port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); datazz <= "HHHH"; diff --git a/designs/leon3-altera-ep3c25/tkconfig.h b/designs/leon3-altera-ep3c25/tkconfig.h index ff7fd183..01e11fa2 100644 --- a/designs/leon3-altera-ep3c25/tkconfig.h +++ b/designs/leon3-altera-ep3c25/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-altera-ep3sl150/.config b/designs/leon3-altera-ep3sl150/.config index 93dd62b9..43636db4 100755 --- a/designs/leon3-altera-ep3sl150/.config +++ b/designs/leon3-altera-ep3sl150/.config @@ -166,7 +166,6 @@ CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set @@ -231,7 +230,6 @@ CONFIG_DSU_IPLSB=0058 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000012 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-altera-ep3sl150/config.h b/designs/leon3-altera-ep3sl150/config.h index 331c707c..43192eb3 100644 --- a/designs/leon3-altera-ep3sl150/config.h +++ b/designs/leon3-altera-ep3sl150/config.h @@ -161,7 +161,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM @@ -220,7 +219,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000012 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-altera-ep3sl150/config.help b/designs/leon3-altera-ep3sl150/config.help index 024b8af0..6dc7fdc8 100644 --- a/designs/leon3-altera-ep3sl150/config.help +++ b/designs/leon3-altera-ep3sl150/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-altera-ep3sl150/config.vhd b/designs/leon3-altera-ep3sl150/config.vhd index 38e89c32..61d2f0ee 100644 --- a/designs/leon3-altera-ep3sl150/config.vhd +++ b/designs/leon3-altera-ep3sl150/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-altera-ep3sl150/config.vhd.h b/designs/leon3-altera-ep3sl150/config.vhd.h index 2a9fe422..0d4570bf 100644 --- a/designs/leon3-altera-ep3sl150/config.vhd.h +++ b/designs/leon3-altera-ep3sl150/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-altera-ep3sl150/lconfig.tk b/designs/leon3-altera-ep3sl150/lconfig.tk index fb44bf6d..3d1521bc 100755 --- a/designs/leon3-altera-ep3sl150/lconfig.tk +++ b/designs/leon3-altera-ep3sl150/lconfig.tk @@ -2079,24 +2079,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2168,20 +2167,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2314,9 +2310,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3127,7 +3120,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3177,12 +3170,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3213,12 +3205,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4700,7 +4691,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4873,6 +4863,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5330,7 +5321,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5453,10 +5443,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5561,6 +5550,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-altera-ep3sl150/leon3mp.vhd b/designs/leon3-altera-ep3sl150/leon3mp.vhd index a63fe694..acd3eecc 100644 --- a/designs/leon3-altera-ep3sl150/leon3mp.vhd +++ b/designs/leon3-altera-ep3sl150/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-altera-ep3sl150/testbench.vhd b/designs/leon3-altera-ep3sl150/testbench.vhd index 05270ca0..4e8260f4 100644 --- a/designs/leon3-altera-ep3sl150/testbench.vhd +++ b/designs/leon3-altera-ep3sl150/testbench.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -32,8 +32,6 @@ library micron; use micron.components.all; library cypress; use cypress.components.all; -library hynix; -use hynix.components.all; use work.debug.all; @@ -196,19 +194,14 @@ begin generic map(data_width => dbits, delay_atob => 0.0, delay_btoa => 5.5) port map(a => ddr_dq(dbits-1 downto 0), b => ddr_dq2(dbits-1 downto 0)); - ddr2mem : for i in 0 to dbits/16-1 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, - fname => sdramfile, bbits => CFG_DDR2SP_DATAWIDTH) - PORT MAP( - clk => ddr_clk(0), clkb => ddr_clkb(0), cke => ddr_cke(0), - csb => ddr_csb(0), rasb => ddr_rasb, casb => ddr_casb, web => ddr_web, - LDM => ddr_dm(i*2), UDM => ddr_dm(i*2+1), ba => ddr_ba(1 downto 0), - addr => ddr_ad(12 downto 0), dq => ddr_dq2(i*16+15 downto i*16), - LDQS => ddr_dqsp(i*2), LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1), - UDQSB => ddr_dqsn(i*2+1)); - end generate; + ddr0 : ddr2ram + generic map(width => dbits, abits => 13, babits =>2, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>1, density => 2) + port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), + odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm(dbits/8-1 downto 0), ba => ddr_ba(1 downto 0), + a => ddr_ad(12 downto 0), dq => ddr_dq2(dbits-1 downto 0), + dqs => ddr_dqsp(dbits/8-1 downto 0), dqsn =>ddr_dqsn(dbits/8-1 downto 0)); -- 16 bit prom prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-altera-ep3sl150/tkconfig.h b/designs/leon3-altera-ep3sl150/tkconfig.h index 2ac7457c..6c5b101c 100644 --- a/designs/leon3-altera-ep3sl150/tkconfig.h +++ b/designs/leon3-altera-ep3sl150/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-arrow-bemicro-sdk/.config b/designs/leon3-arrow-bemicro-sdk/.config index c27d4c48..ccfa8b54 100755 --- a/designs/leon3-arrow-bemicro-sdk/.config +++ b/designs/leon3-arrow-bemicro-sdk/.config @@ -156,7 +156,6 @@ CONFIG_DCACHE_SZ4=y CONFIG_DCACHE_LZ16=y # CONFIG_DCACHE_LZ32 is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -240,8 +239,8 @@ CONFIG_DSU_JTAG=y CONFIG_DDRSP=y CONFIG_DDRSP_INIT=y CONFIG_DDRSP_FREQ=100 -CONFIG_DDRSP_COL=9 -CONFIG_DDRSP_MBYTE=8 +CONFIG_DDRSP_COL=10 +CONFIG_DDRSP_MBYTE=64 CONFIG_DDRSP_RSKEW=0 # diff --git a/designs/leon3-arrow-bemicro-sdk/config.h b/designs/leon3-arrow-bemicro-sdk/config.h index e94d1229..8fb448b6 100644 --- a/designs/leon3-arrow-bemicro-sdk/config.h +++ b/designs/leon3-arrow-bemicro-sdk/config.h @@ -151,7 +151,6 @@ #define CONFIG_DCACHE_LZ16 1 #undef CONFIG_DCACHE_LZ32 #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -226,8 +225,8 @@ #define CONFIG_DDRSP 1 #define CONFIG_DDRSP_INIT 1 #define CONFIG_DDRSP_FREQ (100) -#define CONFIG_DDRSP_COL (9) -#define CONFIG_DDRSP_MBYTE (8) +#define CONFIG_DDRSP_COL (10) +#define CONFIG_DDRSP_MBYTE (64) #define CONFIG_DDRSP_RSKEW (0) /* * SPI memory controller diff --git a/designs/leon3-arrow-bemicro-sdk/config.help b/designs/leon3-arrow-bemicro-sdk/config.help index f5ffbcf2..1f6dd531 100644 --- a/designs/leon3-arrow-bemicro-sdk/config.help +++ b/designs/leon3-arrow-bemicro-sdk/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-arrow-bemicro-sdk/config.vhd b/designs/leon3-arrow-bemicro-sdk/config.vhd index 252e515a..dc4fba5a 100644 --- a/designs/leon3-arrow-bemicro-sdk/config.vhd +++ b/designs/leon3-arrow-bemicro-sdk/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -107,8 +107,8 @@ package config is constant CFG_DDRSP : integer := 1; constant CFG_DDRSP_INIT : integer := 1; constant CFG_DDRSP_FREQ : integer := (100); - constant CFG_DDRSP_COL : integer := (9); - constant CFG_DDRSP_SIZE : integer := (8); + constant CFG_DDRSP_COL : integer := (10); + constant CFG_DDRSP_SIZE : integer := (64); constant CFG_DDRSP_RSKEW : integer := (0); -- SPI memory controller constant CFG_SPIMCTRL : integer := 1; diff --git a/designs/leon3-arrow-bemicro-sdk/config.vhd.h b/designs/leon3-arrow-bemicro-sdk/config.vhd.h index 3346f590..c62f40ca 100644 --- a/designs/leon3-arrow-bemicro-sdk/config.vhd.h +++ b/designs/leon3-arrow-bemicro-sdk/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-arrow-bemicro-sdk/lconfig.tk b/designs/leon3-arrow-bemicro-sdk/lconfig.tk index cc544a89..015e1907 100755 --- a/designs/leon3-arrow-bemicro-sdk/lconfig.tk +++ b/designs/leon3-arrow-bemicro-sdk/lconfig.tk @@ -2079,24 +2079,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2168,20 +2167,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2314,9 +2310,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3127,7 +3120,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3177,12 +3170,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3213,12 +3205,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4675,7 +4666,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4844,6 +4834,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5300,7 +5291,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5423,10 +5413,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "DDR266 SDRAM controller " @@ -5497,6 +5486,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd b/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd index b21ebeb8..a1cebad6 100644 --- a/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd +++ b/designs/leon3-arrow-bemicro-sdk/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-arrow-bemicro-sdk/testbench.vhd b/designs/leon3-arrow-bemicro-sdk/testbench.vhd index 5e68953c..65095a2a 100644 --- a/designs/leon3-arrow-bemicro-sdk/testbench.vhd +++ b/designs/leon3-arrow-bemicro-sdk/testbench.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -18,7 +18,7 @@ -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ -- LEON3 BeMicro SDK design testbench --- Copyright (C) 2011 Aeroflex Gaisler +-- Copyright (C) 2011 - 2013 Aeroflex Gaisler ------------------------------------------------------------------------------ library ieee; @@ -27,8 +27,6 @@ library gaisler; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.components.all; use work.config.all; -- configuration @@ -176,14 +174,14 @@ begin temp_sc <= 'H'; temp_sio <= 'H'; -- DDR memory - ddr0 : mt46v16m16 - generic map (index => -1, fname => sdramfile) - port map( - Dq => ram_d(15 downto 0), Dqs => ram_dqs(1 downto 0), Addr => ram_a(12 downto 0), - Ba => ram_ba, Clk => ram_ck_p, Clk_n => ram_ck_n, Cke => ram_cke, - Cs_n => ram_cs_n, Ras_n => ram_ras_n, Cas_n => ram_cas_n, We_n => ram_ws_n, - Dm => ram_dm(1 downto 0)); - + ddr0 : ddrram + generic map(width => 16, abits => 14, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 2) + port map (ck => ram_ck_p, cke => ram_cke, csn => ram_cs_n, + rasn => ram_ras_n, casn => ram_cas_n, wen => ram_ws_n, + dm => ram_dm, ba => ram_ba, a => ram_a, dq => ram_d, + dqs => ram_dqs); + -- Ethernet PHY mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0'; txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0); diff --git a/designs/leon3-arrow-bemicro-sdk/tkconfig.h b/designs/leon3-arrow-bemicro-sdk/tkconfig.h index de98212e..ee8498dc 100644 --- a/designs/leon3-arrow-bemicro-sdk/tkconfig.h +++ b/designs/leon3-arrow-bemicro-sdk/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-asic/.config b/designs/leon3-asic/.config index dfa8242f..08255996 100644 --- a/designs/leon3-asic/.config +++ b/designs/leon3-asic/.config @@ -108,10 +108,9 @@ CONFIG_LEON3_CUSTOM=y # CONFIG_IU_NWINDOWS=8 CONFIG_IU_V8MULDIV=y -# CONFIG_IU_MUL_LATENCY_2 is not set +CONFIG_IU_MUL_LATENCY_2=y # CONFIG_IU_MUL_LATENCY_4 is not set -CONFIG_IU_MUL_LATENCY_5=y -# CONFIG_IU_MUL_MAC is not set +# CONFIG_IU_MUL_LATENCY_5 is not set CONFIG_IU_MUL_INFERRED=y # CONFIG_IU_MUL_MODGEN is not set # CONFIG_IU_MUL_TECHSPEC is not set @@ -120,7 +119,7 @@ CONFIG_IU_BP=y CONFIG_IU_SVT=y # CONFIG_NOTAG is not set CONFIG_IU_LDELAY=1 -CONFIG_IU_WATCHPOINTS=2 +CONFIG_IU_WATCHPOINTS=4 CONFIG_PWD=y CONFIG_IU_RSTADDR=00000 @@ -133,8 +132,8 @@ CONFIG_IU_RSTADDR=00000 # Cache system # CONFIG_ICACHE_ENABLE=y -CONFIG_ICACHE_ASSO1=y -# CONFIG_ICACHE_ASSO2 is not set +# CONFIG_ICACHE_ASSO1 is not set +CONFIG_ICACHE_ASSO2=y # CONFIG_ICACHE_ASSO3 is not set # CONFIG_ICACHE_ASSO4 is not set # CONFIG_ICACHE_SZ1 is not set @@ -146,12 +145,17 @@ CONFIG_ICACHE_SZ4=y # CONFIG_ICACHE_SZ64 is not set # CONFIG_ICACHE_SZ128 is not set # CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y +CONFIG_ICACHE_LZ16=y +# CONFIG_ICACHE_LZ32 is not set +# CONFIG_ICACHE_ALGORND is not set +# CONFIG_ICACHE_ALGODIR is not set +# CONFIG_ICACHE_ALGOLRR is not set +CONFIG_ICACHE_ALGOLRU=y +# CONFIG_ICACHE_LOCK is not set # CONFIG_ICACHE_LRAM is not set CONFIG_DCACHE_ENABLE=y -CONFIG_DCACHE_ASSO1=y -# CONFIG_DCACHE_ASSO2 is not set +# CONFIG_DCACHE_ASSO1 is not set +CONFIG_DCACHE_ASSO2=y # CONFIG_DCACHE_ASSO3 is not set # CONFIG_DCACHE_ASSO4 is not set # CONFIG_DCACHE_SZ1 is not set @@ -163,9 +167,15 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_SZ64 is not set # CONFIG_DCACHE_SZ128 is not set # CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_SNOOP is not set +CONFIG_DCACHE_LZ16=y +# CONFIG_DCACHE_LZ32 is not set +# CONFIG_DCACHE_ALGORND is not set +# CONFIG_DCACHE_ALGODIR is not set +# CONFIG_DCACHE_ALGOLRR is not set +CONFIG_DCACHE_ALGOLRU=y +# CONFIG_DCACHE_LOCK is not set +CONFIG_DCACHE_SNOOP=y +CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set @@ -179,17 +189,12 @@ CONFIG_CACHE_FIXED=0 # CONFIG_DSU_ENABLE=y CONFIG_DSU_ITRACE=y -CONFIG_DSU_ITRACESZ1=y +# CONFIG_DSU_ITRACESZ1 is not set # CONFIG_DSU_ITRACESZ2 is not set -# CONFIG_DSU_ITRACESZ4 is not set +CONFIG_DSU_ITRACESZ4=y # CONFIG_DSU_ITRACESZ8 is not set # CONFIG_DSU_ITRACESZ16 is not set -CONFIG_DSU_ATRACE=y -CONFIG_DSU_ATRACESZ1=y -# CONFIG_DSU_ATRACESZ2 is not set -# CONFIG_DSU_ATRACESZ4 is not set -# CONFIG_DSU_ATRACESZ8 is not set -# CONFIG_DSU_ATRACESZ16 is not set +# CONFIG_DSU_ATRACE is not set # # Fault-tolerance @@ -217,8 +222,18 @@ CONFIG_APB_HADDR=800 # Debug Link # CONFIG_DSU_UART=y -# CONFIG_DSU_JTAG is not set -# CONFIG_DSU_ETH is not set +CONFIG_DSU_JTAG=y +CONFIG_DSU_ETH=y +# CONFIG_DSU_ETHSZ1 is not set +# CONFIG_DSU_ETHSZ2 is not set +# CONFIG_DSU_ETHSZ4 is not set +CONFIG_DSU_ETHSZ8=y +# CONFIG_DSU_ETHSZ16 is not set +CONFIG_DSU_IPMSB=C0A8 +CONFIG_DSU_IPLSB=0033 +CONFIG_DSU_ETHMSB=020000 +CONFIG_DSU_ETHLSB=000000 +# CONFIG_DSU_ETH_PROG is not set # # Memory controllers @@ -309,8 +324,8 @@ CONFIG_GPT_ENABLE=y CONFIG_GPT_NTIM=4 CONFIG_GPT_SW=12 CONFIG_GPT_TW=32 -CONFIG_GPT_IRQ=6 -CONFIG_GPT_SEPIRQ=y +CONFIG_GPT_IRQ=8 +# CONFIG_GPT_SEPIRQ is not set CONFIG_GPT_WDOGEN=y CONFIG_GPT_WDOG=FFFFF CONFIG_GRGPIO_ENABLE=y diff --git a/designs/leon3-asic/Makefile b/designs/leon3-asic/Makefile index 550732e2..da72329f 100644 --- a/designs/leon3-asic/Makefile +++ b/designs/leon3-asic/Makefile @@ -2,7 +2,7 @@ include .config GRLIB=../.. TOP=leon3mp -GRLIB_SIMULATOR=ModelSim-SE +#GRLIB_SIMULATOR=ModelSim-SE # For FPGA Prototyping # FPGA and Dev Board used in Design @@ -41,7 +41,7 @@ DIRSKIP = b1553 pci/pcif leon2 leon2ft leon4 leon4v0 l2cache iommu \ FILESKIP = -VLOGOPT = -suppress 2902 +VLOGOPT = DCOPT += -x "set argv [lindex [list $(TECHLIBS)] 0]; set top $(TOP)" DCSCRIPT=dc.tcl @@ -116,11 +116,11 @@ gtl-vsim-launch : gtl-vsim # Compile SAED32 SIM Library comp_saed32_sim: - -@vlib modelsim - -@vlib ./modelsim/saed32 + -@MTI_DEFAULT_LIB_TYPE=0 vlib modelsim + -@MTI_DEFAULT_LIB_TYPE=0 vlib ./modelsim/saed32 vmap saed32 ./modelsim/saed32 - vlog -quiet -suppress 2902 -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/pll/verilog/PLL.v - vlog -quiet -suppress 2902 -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/io_std/verilog/saed32nm_io_wb.v - vlog -quiet -suppress 2902 -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/stdcell_lvt/verilog/saed32nm_lvt.v - vlog -quiet -suppress 2902 -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/sram/verilog/saed32sram.v + vlog -quiet -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/pll/verilog/PLL.v + vlog -quiet -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/io_std/verilog/saed32nm_io_wb.v + vlog -quiet -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/stdcell_lvt/verilog/saed32nm_lvt.v + vlog -quiet -work saed32 $(SAED32_HOME)/SAED32_EDK/lib/sram/verilog/saed32sram.v diff --git a/designs/leon3-asic/README.txt b/designs/leon3-asic/README.txt index 4f2d2966..896945b8 100644 --- a/designs/leon3-asic/README.txt +++ b/designs/leon3-asic/README.txt @@ -32,9 +32,9 @@ containing SAED32_EDK. To simulate using Modelsim/Aldec and run systest.c on the LEON3 ASIC design: - make soft make comp_saed32_sim (If SAED32 is used) make vsim + make soft make vsim-launch Synthesis has been tested using Design Compiler 2013.3-SP1 installed or newer, and diff --git a/designs/leon3-asic/bschain.vhd b/designs/leon3-asic/bschain.vhd index 58cdad79..20896b2b 100644 --- a/designs/leon3-asic/bschain.vhd +++ b/designs/leon3-asic/bschain.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-asic/config.h b/designs/leon3-asic/config.h index 16684a5f..69c4fb93 100644 --- a/designs/leon3-asic/config.h +++ b/designs/leon3-asic/config.h @@ -105,10 +105,9 @@ */ #define CONFIG_IU_NWINDOWS (8) #define CONFIG_IU_V8MULDIV 1 -#undef CONFIG_IU_MUL_LATENCY_2 +#define CONFIG_IU_MUL_LATENCY_2 1 #undef CONFIG_IU_MUL_LATENCY_4 -#define CONFIG_IU_MUL_LATENCY_5 1 -#undef CONFIG_IU_MUL_MAC +#undef CONFIG_IU_MUL_LATENCY_5 #define CONFIG_IU_MUL_INFERRED 1 #undef CONFIG_IU_MUL_MODGEN #undef CONFIG_IU_MUL_TECHSPEC @@ -117,7 +116,7 @@ #define CONFIG_IU_SVT 1 #undef CONFIG_NOTAG #define CONFIG_IU_LDELAY (1) -#define CONFIG_IU_WATCHPOINTS (2) +#define CONFIG_IU_WATCHPOINTS (4) #define CONFIG_PWD 1 #define CONFIG_IU_RSTADDR 00000 /* @@ -128,8 +127,8 @@ * Cache system */ #define CONFIG_ICACHE_ENABLE 1 -#define CONFIG_ICACHE_ASSO1 1 -#undef CONFIG_ICACHE_ASSO2 +#undef CONFIG_ICACHE_ASSO1 +#define CONFIG_ICACHE_ASSO2 1 #undef CONFIG_ICACHE_ASSO3 #undef CONFIG_ICACHE_ASSO4 #undef CONFIG_ICACHE_SZ1 @@ -141,12 +140,17 @@ #undef CONFIG_ICACHE_SZ64 #undef CONFIG_ICACHE_SZ128 #undef CONFIG_ICACHE_SZ256 -#undef CONFIG_ICACHE_LZ16 -#define CONFIG_ICACHE_LZ32 1 +#define CONFIG_ICACHE_LZ16 1 +#undef CONFIG_ICACHE_LZ32 +#undef CONFIG_ICACHE_ALGORND +#undef CONFIG_ICACHE_ALGODIR +#undef CONFIG_ICACHE_ALGOLRR +#define CONFIG_ICACHE_ALGOLRU 1 +#undef CONFIG_ICACHE_LOCK #undef CONFIG_ICACHE_LRAM #define CONFIG_DCACHE_ENABLE 1 -#define CONFIG_DCACHE_ASSO1 1 -#undef CONFIG_DCACHE_ASSO2 +#undef CONFIG_DCACHE_ASSO1 +#define CONFIG_DCACHE_ASSO2 1 #undef CONFIG_DCACHE_ASSO3 #undef CONFIG_DCACHE_ASSO4 #undef CONFIG_DCACHE_SZ1 @@ -158,9 +162,15 @@ #undef CONFIG_DCACHE_SZ64 #undef CONFIG_DCACHE_SZ128 #undef CONFIG_DCACHE_SZ256 -#undef CONFIG_DCACHE_LZ16 -#define CONFIG_DCACHE_LZ32 1 -#undef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_LZ16 1 +#undef CONFIG_DCACHE_LZ32 +#undef CONFIG_DCACHE_ALGORND +#undef CONFIG_DCACHE_ALGODIR +#undef CONFIG_DCACHE_ALGOLRR +#define CONFIG_DCACHE_ALGOLRU 1 +#undef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_SNOOP 1 +#define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM /* @@ -172,17 +182,12 @@ */ #define CONFIG_DSU_ENABLE 1 #define CONFIG_DSU_ITRACE 1 -#define CONFIG_DSU_ITRACESZ1 1 +#undef CONFIG_DSU_ITRACESZ1 #undef CONFIG_DSU_ITRACESZ2 -#undef CONFIG_DSU_ITRACESZ4 +#define CONFIG_DSU_ITRACESZ4 1 #undef CONFIG_DSU_ITRACESZ8 #undef CONFIG_DSU_ITRACESZ16 -#define CONFIG_DSU_ATRACE 1 -#define CONFIG_DSU_ATRACESZ1 1 -#undef CONFIG_DSU_ATRACESZ2 -#undef CONFIG_DSU_ATRACESZ4 -#undef CONFIG_DSU_ATRACESZ8 -#undef CONFIG_DSU_ATRACESZ16 +#undef CONFIG_DSU_ATRACE /* * Fault-tolerance */ @@ -206,8 +211,18 @@ * Debug Link */ #define CONFIG_DSU_UART 1 -#undef CONFIG_DSU_JTAG -#undef CONFIG_DSU_ETH +#define CONFIG_DSU_JTAG 1 +#define CONFIG_DSU_ETH 1 +#undef CONFIG_DSU_ETHSZ1 +#undef CONFIG_DSU_ETHSZ2 +#undef CONFIG_DSU_ETHSZ4 +#define CONFIG_DSU_ETHSZ8 1 +#undef CONFIG_DSU_ETHSZ16 +#define CONFIG_DSU_IPMSB C0A8 +#define CONFIG_DSU_IPLSB 0033 +#define CONFIG_DSU_ETHMSB 020000 +#define CONFIG_DSU_ETHLSB 000000 +#undef CONFIG_DSU_ETH_PROG /* * Memory controllers */ @@ -288,8 +303,8 @@ #define CONFIG_GPT_NTIM (4) #define CONFIG_GPT_SW (12) #define CONFIG_GPT_TW (32) -#define CONFIG_GPT_IRQ (6) -#define CONFIG_GPT_SEPIRQ 1 +#define CONFIG_GPT_IRQ (8) +#undef CONFIG_GPT_SEPIRQ #define CONFIG_GPT_WDOGEN 1 #define CONFIG_GPT_WDOG FFFFF #define CONFIG_GRGPIO_ENABLE 1 diff --git a/designs/leon3-asic/config.help b/designs/leon3-asic/config.help index e368ac60..ed90da10 100644 --- a/designs/leon3-asic/config.help +++ b/designs/leon3-asic/config.help @@ -453,19 +453,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -473,10 +474,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-asic/config.vhd b/designs/leon3-asic/config.vhd index 5433e529..e610455e 100644 --- a/designs/leon3-asic/config.vhd +++ b/designs/leon3-asic/config.vhd @@ -1,7 +1,5 @@ - - ----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2013 Aeroflex Gaisler @@ -34,33 +32,33 @@ package config is constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); - constant CFG_V8 : integer := 2 + 4*0; + constant CFG_V8 : integer := 16#32# + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; - constant CFG_NWP : integer := (2); + constant CFG_NWP : integer := (4); constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 1; + constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 8; + constant CFG_ILINE : integer := 4; constant CFG_IREPL : integer := 0; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 1; + constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 8; + constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -72,8 +70,8 @@ package config is constant CFG_TLB_REP : integer := 1; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 1; - constant CFG_ATBSZ : integer := 1; + constant CFG_ITBSZ : integer := 4; + constant CFG_ATBSZ : integer := 0; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; @@ -97,14 +95,14 @@ package config is -- DSU UART constant CFG_AHB_UART : integer := 1; -- JTAG based DSU interface - constant CFG_AHB_JTAG : integer := 0; + constant CFG_AHB_JTAG : integer := 1; -- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0 + 0; - constant CFG_ETH_BUF : integer := 1; + constant CFG_DSU_ETH : integer := 1 + 0 + 0; + constant CFG_ETH_BUF : integer := 8; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; - constant CFG_ETH_ENL : integer := 16#000009#; + constant CFG_ETH_ENL : integer := 16#000000#; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 1; @@ -192,8 +190,8 @@ package config is constant CFG_GPT_NTIM : integer := (4); constant CFG_GPT_SW : integer := (12); constant CFG_GPT_TW : integer := (32); - constant CFG_GPT_IRQ : integer := (6); - constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 0; constant CFG_GPT_WDOGEN : integer := 1; constant CFG_GPT_WDOG : integer := 16#FFFFF#; diff --git a/designs/leon3-asic/config.vhd.h b/designs/leon3-asic/config.vhd.h index 65f957f3..f71cc3a6 100644 --- a/designs/leon3-asic/config.vhd.h +++ b/designs/leon3-asic/config.vhd.h @@ -49,7 +49,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-asic/core.vhd b/designs/leon3-asic/core.vhd index 1185c0f9..6a7d6ada 100644 --- a/designs/leon3-asic/core.vhd +++ b/designs/leon3-asic/core.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-asic/core_clock_mux.vhd b/designs/leon3-asic/core_clock_mux.vhd index dc36434e..adb3c62e 100644 --- a/designs/leon3-asic/core_clock_mux.vhd +++ b/designs/leon3-asic/core_clock_mux.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-asic/lconfig.tk b/designs/leon3-asic/lconfig.tk index 9a51b312..dd2a90fd 100755 --- a/designs/leon3-asic/lconfig.tk +++ b/designs/leon3-asic/lconfig.tk @@ -2081,24 +2081,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2170,20 +2169,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2316,9 +2312,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3129,7 +3122,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3179,12 +3172,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3215,12 +3207,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5055,7 +5046,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5263,6 +5253,7 @@ set CONFIG_I2C_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5721,7 +5712,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5844,10 +5834,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -5932,6 +5921,7 @@ proc writeconfig {file1 file2} { if { $tmpvar_34 == "Aeroflex" } then { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPW_TX_AFLEX 0 [list $notmod] 2 }} write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_35 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-asic/leon3core.vhd b/designs/leon3-asic/leon3core.vhd index 84c7282a..b0887f6b 100644 --- a/designs/leon3-asic/leon3core.vhd +++ b/designs/leon3-asic/leon3core.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -364,13 +364,10 @@ begin memo.ramsn <= (others => '1'); memo.romsn <= (others => '1'); end generate; - ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- ---------------------------------------------------------------------- - - apbctrl0 : apbctrl -- AHB/APB bridge generic map (hindex => 1, haddr => CFG_APBADDR) port map (rstapbn, clkapb, ahbsi, ahbso(1), apbi, apbo ); @@ -387,11 +384,11 @@ begin ua2 : if CFG_UART2_ENABLE /= 0 generate uart2 : apbuart -- UART 2 - generic map (pindex => 4, paddr => 4, pirq => 3, fifosize => CFG_UART2_FIFO) - port map (rstapbn, clkapb, apbi, apbo(4), u2i, u2o); + generic map (pindex => 9, paddr => 9, pirq => 9, fifosize => CFG_UART2_FIFO) + port map (rstapbn, clkapb, apbi, apbo(9), u2i, u2o); u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd; end generate; - noua1 : if CFG_UART2_ENABLE = 0 generate apbo(4) <= apb_none; end generate; + noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate; irqctrl : if CFG_IRQ3_ENABLE /= 0 generate irqctrl0 : irqmp -- interrupt controller @@ -757,6 +754,11 @@ begin end generate; end generate; + nospw : if CFG_SPW_EN = 0 generate + spw_txd <= (others => '0'); + spw_txs <= (others => '0'); + end generate; + ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- diff --git a/designs/leon3-asic/leon3mp.vhd b/designs/leon3-asic/leon3mp.vhd index 5c305100..8f7e78c2 100644 --- a/designs/leon3-asic/leon3mp.vhd +++ b/designs/leon3-asic/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-asic/pads.vhd b/designs/leon3-asic/pads.vhd index 1b95859b..377080aa 100644 --- a/designs/leon3-asic/pads.vhd +++ b/designs/leon3-asic/pads.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -294,8 +294,8 @@ begin oepol => oepol) port map( pad => wdogn, - en => gnd, - i => lwdogn); + en => lwdogn, + i => gnd); testen_pad : inpad generic map( @@ -329,8 +329,8 @@ begin oepol => oepol) port map( pad => errorn, - en => gnd, - i => lerrorn); + en => lerrorn, + i => gnd); ------------------------------------------------------------------------------ -- JTAG pads @@ -671,6 +671,13 @@ begin lspw_txs => lspw_txs); end generate; + nospwpads0 : if CFG_SPW_EN = 0 generate + spw_txd <= (others => '0'); + spw_txs <= (others => '0'); + lspw_rxd <= (others => '0'); + lspw_rxs <= (others => '0'); + end generate; + ------------------------------------------------------------------------------ -- ETHERNET ------------------------------------------------------------------------------ diff --git a/designs/leon3-asic/ram.srec b/designs/leon3-asic/ram.srec index 7e37ab8e..e5327045 100755 --- a/designs/leon3-asic/ram.srec +++ b/designs/leon3-asic/ram.srec @@ -1,14 +1,14 @@ -S00D0000736472616D2E7372656300 -S31540000000881000000910006F81C123EC0100000038 -S31540000010A1480000A75000001080403EAC102001CF +S00B000072616D2E73726563D9 +S31540000000881000000910007181C121DC0100000048 +S31540000010A1480000A75000001080203EAC102001EF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006F81C52340010000002F -S31540000050A14800002910006D81C522BC01000000A6 -S31540000060A14800002910006D81C523280100000029 +S31540000040A14800002910007181C52130010000003F +S31540000050A14800002910006F81C520AC01000000B6 +S31540000060A14800002910006F81C521180100000039 S3154000007091D02000010000000100000001000000B6 S3154000008091D02000010000000100000001000000A6 -S31540000090A1480000A75000001080401EAC10200967 +S31540000090A1480000A75000001080201EAC10200987 S315400000A091D0200001000000010000000100000086 S315400000B091D0200001000000010000000100000076 S315400000C091D0200001000000010000000100000066 @@ -16,21 +16,21 @@ S315400000D091D0200001000000010000000100000056 S315400000E091D0200001000000010000000100000046 S315400000F091D0200001000000010000000100000036 S3154000010091D0200001000000010000000100000025 -S31540000110AE102001A148000010806E30A7500000AC -S31540000120AE102002A148000010806E2CA75000009F -S31540000130AE102003A148000010806E28A750000092 -S31540000140AE102004A148000010806E24A750000085 -S31540000150AE102005A148000010806E20A750000078 -S31540000160AE102006A148000010806E1CA75000006B -S31540000170AE102007A148000010806E18A75000005E -S31540000180AE102008A148000010806E14A750000051 -S31540000190AE102009A148000010806E10A750000044 -S315400001A0AE10200AA148000010806E0CA750000037 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+S31540048B4000000000000000000000000000000000DB +S31540048B5000000000000000000000000000000000CB +S31540048B6000000000000000000000000000000000BB +S31540048B7000000000000000000000000000000000AB +S31540048B80000000000000000000000000000000009B +S31540048B90000000000000000000000000000000008B S31540048BA0000000000000000000000000000000007B S31540048BB0000000000000000000000000000000006B S31540048BC0000000000000000000000000000000005B @@ -18626,7 +18626,7 @@ S31540048BF0000000000000000000000000000000002B S31540048C00000000000000000000000000000000001A S31540048C10000000000000000000000000000000000A S31540048C2000000000000000000000000000000000FA -S31540048C308000010000000008000000070000000654 -S31540048C40000000030000000000000000FFFF8AD07F +S31540048C30000000008000010000000008000000075A +S31540048C40000000060000000300000000FFFF8AD079 S30940048C508000031043 S70540000000BA diff --git a/designs/leon3-asic/spw_lvttl_pads.vhd b/designs/leon3-asic/spw_lvttl_pads.vhd index 191642f8..918d840f 100644 --- a/designs/leon3-asic/spw_lvttl_pads.vhd +++ b/designs/leon3-asic/spw_lvttl_pads.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-asic/systest.c b/designs/leon3-asic/systest.c index e5a5a837..0dde056f 100644 --- a/designs/leon3-asic/systest.c +++ b/designs/leon3-asic/systest.c @@ -2,13 +2,8 @@ main() { - report_start(); - - leon3_test(1, 0x80000200, 0); - irqtest(0x80000200); - apbuart_test(0x80000100); - apbuart_test(0x80000900); - gptimer_test(0x80000300, 6); - - report_end(); + report_start(); + base_test(); + greth_test(0x80000d00); + report_end(); } diff --git a/designs/leon3-asic/testbench.vhd b/designs/leon3-asic/testbench.vhd index 41133103..18120212 100644 --- a/designs/leon3-asic/testbench.vhd +++ b/designs/leon3-asic/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -119,14 +119,14 @@ signal spw_txs : std_logic_vector(0 to CFG_SPW_NUM-1); signal i2c_scl : std_ulogic; signal i2c_sda : std_ulogic; -signal spi_miso : std_ulogic; -signal spi_mosi : std_ulogic; -signal spi_sck : std_ulogic; +signal spi_miso : std_logic; +signal spi_mosi : std_logic; +signal spi_sck : std_logic; signal spi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0); signal trst,tck,tms,tdi,tdo: std_ulogic; -signal gtx_clk : std_ulogic; +signal gtx_clk : std_ulogic := '0'; signal erx_clk : std_ulogic; signal erxd : std_logic_vector(7 downto 0); signal erx_dv : std_ulogic; @@ -160,6 +160,7 @@ begin gnd <= "0000"; clk <= not clk after ct * 1 ns; spw_clk <= not spw_clk after ct * 1 ns; + gtx_clk <= not gtx_clk after 8 ns; rst <= dsurst; bexcn <= '1'; wdogn <= 'H'; gpio(2 downto 0) <= "HHL"; @@ -233,13 +234,49 @@ begin rwen(0), ramoen(0)); end generate; + phy0 : if (CFG_GRETH = 1) generate + emdio <= 'H'; + emdint <= '0'; + p0: phy + generic map ( + address => 7, + extended_regs => 1, + aneg => 1, + base100_t4 => 1, + base100_x_fd => 1, + base100_x_hd => 1, + fd_10 => 1, + hd_10 => 1, + base100_t2_fd => 1, + base100_t2_hd => 1, + base1000_x_fd => 0, + base1000_x_hd => 0, + base1000_t_fd => 0, + base1000_t_hd => 0, + rmii => 0, + rgmii => 0 + ) + port map(rst, emdio, etx_clk, erx_clk, erxd, + erx_dv, erx_er, erx_col, erx_crs, etxd, + etx_en, etx_er, emdc, gtx_clk); + + end generate; + + spimem0: if (CFG_SPICTRL_ENABLE = 1) generate + s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile, + readcmd => CFG_SPIMCTRL_READCMD, + dummybyte => CFG_SPIMCTRL_DUMMYBYTE, + dualoutput => 0) + port map (spi_sck, spi_mosi, spi_miso, spi_slvsel(0)); + end generate spimem0; + iuerr : process begin wait for 2500 ns; if to_x01(error) = '1' then wait on error; end if; --- assert (to_x01(error) = '1') --- report "*** IU in error mode, simulation halted ***" --- severity failure ; + assert (to_x01(error) = '1') + report "*** IU in error mode, simulation halted ***" + severity failure ; end process; bst0: process diff --git a/designs/leon3-asic/testbench_netlist.vhd b/designs/leon3-asic/testbench_netlist.vhd index 628aafc1..d4756518 100644 --- a/designs/leon3-asic/testbench_netlist.vhd +++ b/designs/leon3-asic/testbench_netlist.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-asic/tkconfig.h b/designs/leon3-asic/tkconfig.h index 4237ec8d..02342b36 100644 --- a/designs/leon3-asic/tkconfig.h +++ b/designs/leon3-asic/tkconfig.h @@ -479,10 +479,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-avnet-3s1500/.config b/designs/leon3-avnet-3s1500/.config index f3d8a0ee..dd928261 100644 --- a/designs/leon3-avnet-3s1500/.config +++ b/designs/leon3-avnet-3s1500/.config @@ -169,7 +169,6 @@ CONFIG_DCACHE_SZ4=y CONFIG_DCACHE_LZ16=y # CONFIG_DCACHE_LZ32 is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set @@ -234,7 +233,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000013 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Memory controllers diff --git a/designs/leon3-avnet-3s1500/config.h b/designs/leon3-avnet-3s1500/config.h index 0637c194..be128e22 100644 --- a/designs/leon3-avnet-3s1500/config.h +++ b/designs/leon3-avnet-3s1500/config.h @@ -163,7 +163,6 @@ #define CONFIG_DCACHE_LZ16 1 #undef CONFIG_DCACHE_LZ32 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM @@ -222,7 +221,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000013 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Memory controllers */ diff --git a/designs/leon3-avnet-3s1500/config.help b/designs/leon3-avnet-3s1500/config.help index f76cc9e1..a3fbfac7 100644 --- a/designs/leon3-avnet-3s1500/config.help +++ b/designs/leon3-avnet-3s1500/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-avnet-3s1500/config.vhd b/designs/leon3-avnet-3s1500/config.vhd index b540fe6b..174d6ea3 100644 --- a/designs/leon3-avnet-3s1500/config.vhd +++ b/designs/leon3-avnet-3s1500/config.vhd @@ -62,7 +62,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-avnet-3s1500/config.vhd.h b/designs/leon3-avnet-3s1500/config.vhd.h index 5e0b24e3..57bbd483 100644 --- a/designs/leon3-avnet-3s1500/config.vhd.h +++ b/designs/leon3-avnet-3s1500/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-avnet-3s1500/lconfig.tk b/designs/leon3-avnet-3s1500/lconfig.tk index 8e0d1601..34bc6db8 100755 --- a/designs/leon3-avnet-3s1500/lconfig.tk +++ b/designs/leon3-avnet-3s1500/lconfig.tk @@ -2176,24 +2176,23 @@ proc menu7 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 7 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 7 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 7 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 7 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 7 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 7 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 7 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 7 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 7 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 7 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 7 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 7 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 7 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2265,20 +2264,17 @@ proc update_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu7.config.f.x15 normal {n l y}} else {configure_entry .menu7.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x17 normal {n l y}} else {configure_entry .menu7.config.f.x17 disabled {y n l}} + configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x18.l configure -state normal; } else {.menu7.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x17.l configure -state normal; } else {.menu7.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu7.config.f.x19 normal {n l y}} else {configure_entry .menu7.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x20 normal {x l}} else {configure_entry .menu7.config.f.x20 disabled {x l}} + configure_entry .menu7.config.f.x18 normal {n l y}} else {configure_entry .menu7.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x19 normal {x l}} else {configure_entry .menu7.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x21.l configure -state normal; } else {.menu7.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x20.l configure -state normal; } else {.menu7.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x20.l configure -state disabled} } @@ -2411,9 +2407,6 @@ proc update_define_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3224,7 +3217,7 @@ proc menu13 {w title} { hex $w.config.f 13 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 13 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 13 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3274,12 +3267,11 @@ proc update_menu13 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x6.l configure -state normal; } else {.menu13.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x7.l configure -state normal; } else {.menu13.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu13.config.f.x8 normal {n l y}} else {configure_entry .menu13.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu13.config.f.x9 normal {n l y}} else {configure_entry .menu13.config.f.x9 disabled {y n l}} } @@ -3310,12 +3302,11 @@ proc update_define_menu13 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4896,7 +4887,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5074,6 +5064,7 @@ set CONFIG_SVGA_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5534,7 +5525,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5657,10 +5647,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -5714,6 +5703,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-avnet-3s1500/leon3mp.vhd b/designs/leon3-avnet-3s1500/leon3mp.vhd index 6ad7cdff..961acfc0 100644 --- a/designs/leon3-avnet-3s1500/leon3mp.vhd +++ b/designs/leon3-avnet-3s1500/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-avnet-3s1500/testbench.vhd b/designs/leon3-avnet-3s1500/testbench.vhd index 6e901ef6..272e324c 100644 --- a/designs/leon3-avnet-3s1500/testbench.vhd +++ b/designs/leon3-avnet-3s1500/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-avnet-3s1500/tkconfig.h b/designs/leon3-avnet-3s1500/tkconfig.h index dca3aefa..e791ea3f 100644 --- a/designs/leon3-avnet-3s1500/tkconfig.h +++ b/designs/leon3-avnet-3s1500/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-avnet-eval-xc4vlx25/.config b/designs/leon3-avnet-eval-xc4vlx25/.config index 5d7b3b19..206151f1 100755 --- a/designs/leon3-avnet-eval-xc4vlx25/.config +++ b/designs/leon3-avnet-eval-xc4vlx25/.config @@ -167,7 +167,6 @@ CONFIG_DCACHE_ALGOLRR=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -253,7 +252,6 @@ CONFIG_DSU_IPLSB=0045 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000014 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-avnet-eval-xc4vlx25/config.h b/designs/leon3-avnet-eval-xc4vlx25/config.h index 46a0b10b..d08143e4 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/config.h +++ b/designs/leon3-avnet-eval-xc4vlx25/config.h @@ -162,7 +162,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -242,7 +241,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000014 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-avnet-eval-xc4vlx25/config.help b/designs/leon3-avnet-eval-xc4vlx25/config.help index 9f6c85f6..d318bf00 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/config.help +++ b/designs/leon3-avnet-eval-xc4vlx25/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-avnet-eval-xc4vlx25/config.vhd b/designs/leon3-avnet-eval-xc4vlx25/config.vhd index 207d35c6..5d1053b2 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/config.vhd +++ b/designs/leon3-avnet-eval-xc4vlx25/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 1; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-avnet-eval-xc4vlx25/config.vhd.h b/designs/leon3-avnet-eval-xc4vlx25/config.vhd.h index 921e92d3..96859c38 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/config.vhd.h +++ b/designs/leon3-avnet-eval-xc4vlx25/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-avnet-eval-xc4vlx25/lconfig.tk b/designs/leon3-avnet-eval-xc4vlx25/lconfig.tk index 13548069..23af9006 100755 --- a/designs/leon3-avnet-eval-xc4vlx25/lconfig.tk +++ b/designs/leon3-avnet-eval-xc4vlx25/lconfig.tk @@ -2078,24 +2078,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2167,20 +2166,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2313,9 +2309,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3126,7 +3119,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3176,12 +3169,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3212,12 +3204,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4513,7 +4504,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4668,6 +4658,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5124,7 +5115,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5247,10 +5237,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5323,6 +5312,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd b/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd index 50456350..2fb4c196 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd +++ b/designs/leon3-avnet-eval-xc4vlx25/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd b/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd index e8c68630..eb17a569 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd +++ b/designs/leon3-avnet-eval-xc4vlx25/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -191,13 +191,20 @@ begin ddr_clk_fb <= ddr_clk; - u1 : mt46v16m16 - generic map (index => -1, fname => sdramfile) - port map( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); + -- u1 : mt46v16m16 + -- generic map (index => -1, fname => sdramfile) + -- port map( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + ddr0 : ddrram + generic map(width => 16, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 1) + port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); prom0 : for i in 0 to (romwidth/8)-1 generate sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-avnet-eval-xc4vlx25/tkconfig.h b/designs/leon3-avnet-eval-xc4vlx25/tkconfig.h index efadb815..f8ebf50c 100644 --- a/designs/leon3-avnet-eval-xc4vlx25/tkconfig.h +++ b/designs/leon3-avnet-eval-xc4vlx25/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-avnet-eval-xc4vlx60/.config b/designs/leon3-avnet-eval-xc4vlx60/.config index c7b4b911..c6401097 100755 --- a/designs/leon3-avnet-eval-xc4vlx60/.config +++ b/designs/leon3-avnet-eval-xc4vlx60/.config @@ -252,7 +252,6 @@ CONFIG_DSU_IPLSB=010a CONFIG_DSU_ETHMSB=020060 CONFIG_DSU_ETHLSB=000015 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd b/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd index 709e5805..363c7ec2 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd +++ b/designs/leon3-avnet-eval-xc4vlx60/ahb2mig_avnet_eval.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-avnet-eval-xc4vlx60/config.h b/designs/leon3-avnet-eval-xc4vlx60/config.h index 932b6600..699bfe68 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/config.h +++ b/designs/leon3-avnet-eval-xc4vlx60/config.h @@ -241,7 +241,6 @@ #define CONFIG_DSU_ETHMSB 020060 #define CONFIG_DSU_ETHLSB 000015 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-avnet-eval-xc4vlx60/config.help b/designs/leon3-avnet-eval-xc4vlx60/config.help index 9f6c85f6..d318bf00 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/config.help +++ b/designs/leon3-avnet-eval-xc4vlx60/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-avnet-eval-xc4vlx60/config.vhd b/designs/leon3-avnet-eval-xc4vlx60/config.vhd index fa1722f2..0c0e3d6f 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/config.vhd +++ b/designs/leon3-avnet-eval-xc4vlx60/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-avnet-eval-xc4vlx60/config.vhd.h b/designs/leon3-avnet-eval-xc4vlx60/config.vhd.h index e6677ac5..8b2f01b6 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/config.vhd.h +++ b/designs/leon3-avnet-eval-xc4vlx60/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-avnet-eval-xc4vlx60/lconfig.tk b/designs/leon3-avnet-eval-xc4vlx60/lconfig.tk index 95040ed6..685b1bf6 100755 --- a/designs/leon3-avnet-eval-xc4vlx60/lconfig.tk +++ b/designs/leon3-avnet-eval-xc4vlx60/lconfig.tk @@ -2088,24 +2088,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2177,20 +2176,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2323,9 +2319,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3136,7 +3129,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3186,12 +3179,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3222,12 +3214,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4650,7 +4641,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4812,6 +4802,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -5270,7 +5261,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5393,10 +5383,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5482,6 +5471,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd b/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd index c806e6d7..7db25f01 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd +++ b/designs/leon3-avnet-eval-xc4vlx60/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd b/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd index 8550fea8..c2639fac 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd +++ b/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -29,8 +29,6 @@ use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.components.all; use work.config.all; -- configuration use work.debug.all; @@ -198,13 +196,13 @@ begin ddr_clk_fb <= ddr_clk; - u1 : mt46v16m16 - generic map (index => -1, fname => sdramfile, fdelay => 300*CFG_MIG_DDR2) - port map( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); + ddr0: ddrram + generic map (width => 16, abits => 13, colbits => 9, rowbits => 12, implbanks => 1, + fname => sdramfile, lddelay => (300 us)*CFG_MIG_DDR2) + port map ( + ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs); prom0 : for i in 0 to (romwidth/8)-1 generate sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-avnet-eval-xc4vlx60/tkconfig.h b/designs/leon3-avnet-eval-xc4vlx60/tkconfig.h index ef6f4100..522a28a7 100644 --- a/designs/leon3-avnet-eval-xc4vlx60/tkconfig.h +++ b/designs/leon3-avnet-eval-xc4vlx60/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-avnet-xc2v1500/.config b/designs/leon3-avnet-xc2v1500/.config index 556de6c8..159e85e7 100644 --- a/designs/leon3-avnet-xc2v1500/.config +++ b/designs/leon3-avnet-xc2v1500/.config @@ -151,7 +151,6 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_LZ16 is not set CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set diff --git a/designs/leon3-avnet-xc2v1500/config.h b/designs/leon3-avnet-xc2v1500/config.h index 84289b09..f236b526 100644 --- a/designs/leon3-avnet-xc2v1500/config.h +++ b/designs/leon3-avnet-xc2v1500/config.h @@ -146,7 +146,6 @@ #undef CONFIG_DCACHE_LZ16 #define CONFIG_DCACHE_LZ32 1 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM diff --git a/designs/leon3-avnet-xc2v1500/config.help b/designs/leon3-avnet-xc2v1500/config.help index 3a173e3d..ba267c82 100644 --- a/designs/leon3-avnet-xc2v1500/config.help +++ b/designs/leon3-avnet-xc2v1500/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-avnet-xc2v1500/config.vhd b/designs/leon3-avnet-xc2v1500/config.vhd index 9d8bbf45..81d55e2a 100644 --- a/designs/leon3-avnet-xc2v1500/config.vhd +++ b/designs/leon3-avnet-xc2v1500/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-avnet-xc2v1500/config.vhd.h b/designs/leon3-avnet-xc2v1500/config.vhd.h index 964cf46d..c83ebd6a 100644 --- a/designs/leon3-avnet-xc2v1500/config.vhd.h +++ b/designs/leon3-avnet-xc2v1500/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-avnet-xc2v1500/lconfig.tk b/designs/leon3-avnet-xc2v1500/lconfig.tk index d945bfeb..3a94e7fe 100755 --- a/designs/leon3-avnet-xc2v1500/lconfig.tk +++ b/designs/leon3-avnet-xc2v1500/lconfig.tk @@ -2078,24 +2078,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2167,20 +2166,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2313,9 +2309,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4494,7 +4487,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4647,6 +4639,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5102,7 +5095,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-avnet-xc2v1500/leon3mp.vhd b/designs/leon3-avnet-xc2v1500/leon3mp.vhd index d89569e2..843a86a6 100644 --- a/designs/leon3-avnet-xc2v1500/leon3mp.vhd +++ b/designs/leon3-avnet-xc2v1500/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-avnet-xc2v1500/testbench.vhd b/designs/leon3-avnet-xc2v1500/testbench.vhd index de59b56f..e81ed8a7 100644 --- a/designs/leon3-avnet-xc2v1500/testbench.vhd +++ b/designs/leon3-avnet-xc2v1500/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -146,36 +146,43 @@ begin ); ddrmem : for i in 0 to 1 generate - u3 : mt46v16m16 - generic map (index => 3, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); - - u2 : mt46v16m16 - generic map (index => 2, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(3 downto 2)); - u1 : mt46v16m16 - generic map (index => 1, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(5 downto 4)); - - u0 : mt46v16m16 - generic map (index => 0, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(7 downto 6)); + -- u3 : mt46v16m16 + -- generic map (index => 3, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + + -- u2 : mt46v16m16 + -- generic map (index => 2, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(3 downto 2)); + -- u1 : mt46v16m16 + -- generic map (index => 1, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(5 downto 4)); + + -- u0 : mt46v16m16 + -- generic map (index => 0, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(7 downto 6)); + ddr0 : ddrram + generic map(width => 64, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 1) + port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i), + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); end generate; prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-avnet-xc2v1500/tkconfig.h b/designs/leon3-avnet-xc2v1500/tkconfig.h index 69e9548d..d1e056ce 100644 --- a/designs/leon3-avnet-xc2v1500/tkconfig.h +++ b/designs/leon3-avnet-xc2v1500/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-clock-gate/.config b/designs/leon3-clock-gate/.config index d17da22f..7d3075db 100644 --- a/designs/leon3-clock-gate/.config +++ b/designs/leon3-clock-gate/.config @@ -151,7 +151,6 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_LZ16 is not set CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set @@ -216,7 +215,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000017 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-clock-gate/clkgate.vhd b/designs/leon3-clock-gate/clkgate.vhd index d6a5448a..63886b31 100644 --- a/designs/leon3-clock-gate/clkgate.vhd +++ b/designs/leon3-clock-gate/clkgate.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-clock-gate/config.h b/designs/leon3-clock-gate/config.h index e6523904..4a8ffd08 100644 --- a/designs/leon3-clock-gate/config.h +++ b/designs/leon3-clock-gate/config.h @@ -146,7 +146,6 @@ #undef CONFIG_DCACHE_LZ16 #define CONFIG_DCACHE_LZ32 1 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM @@ -205,7 +204,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000017 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-clock-gate/config.help b/designs/leon3-clock-gate/config.help index 088f5249..acc4dd0f 100644 --- a/designs/leon3-clock-gate/config.help +++ b/designs/leon3-clock-gate/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-clock-gate/config.vhd b/designs/leon3-clock-gate/config.vhd index f039ee2f..ae2c6bab 100644 --- a/designs/leon3-clock-gate/config.vhd +++ b/designs/leon3-clock-gate/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-clock-gate/config.vhd.h b/designs/leon3-clock-gate/config.vhd.h index 21647e25..527910bf 100644 --- a/designs/leon3-clock-gate/config.vhd.h +++ b/designs/leon3-clock-gate/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-clock-gate/lconfig.tk b/designs/leon3-clock-gate/lconfig.tk index 1e5e4ad7..76878003 100755 --- a/designs/leon3-clock-gate/lconfig.tk +++ b/designs/leon3-clock-gate/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5324,7 +5315,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5580,6 +5570,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -6037,7 +6028,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6160,10 +6150,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " @@ -6266,6 +6255,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_32 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-clock-gate/leon3mp.vhd b/designs/leon3-clock-gate/leon3mp.vhd index ef39fa35..ff41a785 100644 --- a/designs/leon3-clock-gate/leon3mp.vhd +++ b/designs/leon3-clock-gate/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-clock-gate/testbench.vhd b/designs/leon3-clock-gate/testbench.vhd index 11758800..95a8cb74 100644 --- a/designs/leon3-clock-gate/testbench.vhd +++ b/designs/leon3-clock-gate/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-clock-gate/tkconfig.h b/designs/leon3-clock-gate/tkconfig.h index a800c20b..2f1ffa8f 100644 --- a/designs/leon3-clock-gate/tkconfig.h +++ b/designs/leon3-clock-gate/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-digilent-atlys/.config b/designs/leon3-digilent-atlys/.config index 35dd57d5..e5285eb2 100644 --- a/designs/leon3-digilent-atlys/.config +++ b/designs/leon3-digilent-atlys/.config @@ -167,7 +167,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -253,7 +252,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020765 CONFIG_DSU_ETHLSB=003456 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-digilent-atlys/config.h b/designs/leon3-digilent-atlys/config.h index abcadd75..cde50910 100644 --- a/designs/leon3-digilent-atlys/config.h +++ b/designs/leon3-digilent-atlys/config.h @@ -162,7 +162,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -242,7 +241,6 @@ #define CONFIG_DSU_ETHMSB 020765 #define CONFIG_DSU_ETHLSB 003456 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-digilent-atlys/config.help b/designs/leon3-digilent-atlys/config.help index 191c34bf..c5ac54ed 100644 --- a/designs/leon3-digilent-atlys/config.help +++ b/designs/leon3-digilent-atlys/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-digilent-atlys/config.vhd b/designs/leon3-digilent-atlys/config.vhd index d8ebcd51..8f61cfa5 100644 --- a/designs/leon3-digilent-atlys/config.vhd +++ b/designs/leon3-digilent-atlys/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-digilent-atlys/config.vhd.h b/designs/leon3-digilent-atlys/config.vhd.h index 3029ab01..eb77372d 100644 --- a/designs/leon3-digilent-atlys/config.vhd.h +++ b/designs/leon3-digilent-atlys/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-digilent-atlys/lconfig.tk b/designs/leon3-digilent-atlys/lconfig.tk index 4e670f8a..d03d0529 100755 --- a/designs/leon3-digilent-atlys/lconfig.tk +++ b/designs/leon3-digilent-atlys/lconfig.tk @@ -2081,24 +2081,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2170,20 +2169,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2316,9 +2312,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3129,7 +3122,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3179,12 +3172,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3215,12 +3207,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4963,7 +4954,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5148,6 +5138,7 @@ set CONFIG_SPIMCTRL_PWRUPCNT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5605,7 +5596,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5728,10 +5718,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5835,6 +5824,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-digilent-atlys/testbench.vhd b/designs/leon3-digilent-atlys/testbench.vhd index 2ae20ee4..661acf9e 100644 --- a/designs/leon3-digilent-atlys/testbench.vhd +++ b/designs/leon3-digilent-atlys/testbench.vhd @@ -34,8 +34,6 @@ use gaisler.sim.all; library techmap; use techmap.gencomp.all; use work.debug.all; -library hynix; -use hynix.components.all; library grlib; use grlib.stdlib.all; @@ -210,19 +208,17 @@ begin csn => spi_sel_n ); -- NOTE: LEON3 expects DDR2 memory chip with eight banks, but simulation - -- model has only four banks. Therefore 2nd block of 64 MByte will alias - -- to first block. + -- model has only one (implbanks) bank. Therefore other banks will alias + -- to bank 0.. ddr2mem0 : for i in 0 to 0 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => false, PUSCheckFlag => false, - index => i, bbits => 16, fname => sdramfile, fdelay => 340) - port map (DQ => ddr_dq(i*16+15 downto i*16), - LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2), - UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1), - LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas, - RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0), - ADDR => ddr_ad(12 downto 0), CKE => ddr_cke, - CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1)); + u1: ddr2ram + generic map (width => 16, abits => 13, babits => 3, + colbits => 10, rowbits => 13, implbanks => 1, + fname => sdramfile, speedbin => 1) + port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, + odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, + dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn); end generate; ps2devs: for i in 0 to 1 generate diff --git a/designs/leon3-digilent-atlys/tkconfig.h b/designs/leon3-digilent-atlys/tkconfig.h index f34b33f4..460a05b6 100644 --- a/designs/leon3-digilent-atlys/tkconfig.h +++ b/designs/leon3-digilent-atlys/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-digilent-nexys3/.config b/designs/leon3-digilent-nexys3/.config index a6c529a7..77153c67 100755 --- a/designs/leon3-digilent-nexys3/.config +++ b/designs/leon3-digilent-nexys3/.config @@ -231,7 +231,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000000 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-digilent-nexys3/config.h b/designs/leon3-digilent-nexys3/config.h index 69ebfd7a..9a8b7564 100644 --- a/designs/leon3-digilent-nexys3/config.h +++ b/designs/leon3-digilent-nexys3/config.h @@ -220,7 +220,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000000 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-digilent-nexys3/config.help b/designs/leon3-digilent-nexys3/config.help index 458bbd81..81b3d19a 100644 --- a/designs/leon3-digilent-nexys3/config.help +++ b/designs/leon3-digilent-nexys3/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-digilent-nexys3/config.vhd b/designs/leon3-digilent-nexys3/config.vhd index 9b0d4be5..7ec4101d 100644 --- a/designs/leon3-digilent-nexys3/config.vhd +++ b/designs/leon3-digilent-nexys3/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-digilent-nexys3/config.vhd.h b/designs/leon3-digilent-nexys3/config.vhd.h index 368a9909..4937ee54 100644 --- a/designs/leon3-digilent-nexys3/config.vhd.h +++ b/designs/leon3-digilent-nexys3/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-digilent-nexys3/lconfig.tk b/designs/leon3-digilent-nexys3/lconfig.tk index 15c1f1df..4899f30e 100755 --- a/designs/leon3-digilent-nexys3/lconfig.tk +++ b/designs/leon3-digilent-nexys3/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5144,7 +5135,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5345,6 +5335,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5801,7 +5792,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5924,10 +5914,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6039,6 +6028,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-digilent-nexys3/leon3mp.vhd b/designs/leon3-digilent-nexys3/leon3mp.vhd index 13ae7655..07ccc3ee 100644 --- a/designs/leon3-digilent-nexys3/leon3mp.vhd +++ b/designs/leon3-digilent-nexys3/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-nexys3/ram.srec b/designs/leon3-digilent-nexys3/ram.srec index a896a74b..2c229af3 100755 --- a/designs/leon3-digilent-nexys3/ram.srec +++ b/designs/leon3-digilent-nexys3/ram.srec @@ -1,11 +1,11 @@ S00B000072616D2E73726563D9 -S31540000000881000000910006C81C1234401000000E3 +S31540000000881000000910006C81C120B0010000007A S31540000010A1480000A75000001080203EAC102001EF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006C81C5229801000000DB -S31540000050A14800002910006981C523500100000015 -S31540000060A14800002910006981C523BC0100000099 +S31540000040A14800002910006C81C520040100000071 +S31540000050A14800002910006981C5232C0100000039 +S31540000060A14800002910006981C5239801000000BD S3154000007091D02000010000000100000001000000B6 S3154000008091D02000010000000100000001000000A6 S31540000090A1480000A75000001080201EAC10200987 @@ -16,21 +16,21 @@ S315400000D091D0200001000000010000000100000056 S315400000E091D0200001000000010000000100000046 S315400000F091D0200001000000010000000100000036 S3154000010091D0200001000000010000000100000025 -S31540000110AE102001A148000010806A55A75000008B -S31540000120AE102002A148000010806A51A75000007E -S31540000130AE102003A148000010806A4DA750000071 -S31540000140AE102004A148000010806A49A750000064 -S31540000150AE102005A148000010806A45A750000057 -S31540000160AE102006A148000010806A41A75000004A -S31540000170AE102007A148000010806A3DA75000003D -S31540000180AE102008A148000010806A39A750000030 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S3154001C1D00000000000000000000000000000000018 @@ -18468,7 +18468,7 @@ S315400482100000000000000000000000000000000014 S315400482204004822800000000000000004004851439 S31540048230400485E0400486AC0000000000000000D5 S3154004824000000000000000000000000000000000E4 -S315400482500000000000000000000000004001C1785A +S315400482500000000000000000000000004001BD488E S3154004826000000000000000000000000000000000C4 S3154004827000000000000000000000000000000000B4 S3154004828000000000000000000000000000000000A4 @@ -18625,7 +18625,8 @@ S31540048BE0000000000000000000000000000000003B S31540048BF0000000000000000000000000000000002B S31540048C00000000000000000000000000000000001A S31540048C10000000000000000000000000000000000A -S31540048C200000000000000000800003100000000067 -S31540048C30000000008000010000000008000000075A -S31540048C40000000060000000300000000FFFF8AD079 +S31540048C2000000000000000000000000000000000FA +S31540048C308000010000000008000000070000000654 +S31540048C40000000030000000000000000FFFF8AD07F +S30940048C508000031043 S70540000000BA diff --git a/designs/leon3-digilent-nexys3/testbench.vhd b/designs/leon3-digilent-nexys3/testbench.vhd index 5414fd30..c526a28e 100644 --- a/designs/leon3-digilent-nexys3/testbench.vhd +++ b/designs/leon3-digilent-nexys3/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -28,17 +28,10 @@ use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -library hynix; -use hynix.components.all; - entity testbench is generic ( fabtech : integer := CFG_FABTECH; diff --git a/designs/leon3-digilent-nexys3/tkconfig.h b/designs/leon3-digilent-nexys3/tkconfig.h index 2a5a32c5..d5a3e41a 100644 --- a/designs/leon3-digilent-nexys3/tkconfig.h +++ b/designs/leon3-digilent-nexys3/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-digilent-nexys4/.config b/designs/leon3-digilent-nexys4/.config index 6bf0711d..5a0e0bb6 100755 --- a/designs/leon3-digilent-nexys4/.config +++ b/designs/leon3-digilent-nexys4/.config @@ -232,7 +232,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000000 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-digilent-nexys4/Makefile b/designs/leon3-digilent-nexys4/Makefile index 90df2935..d35186b9 100644 --- a/designs/leon3-digilent-nexys4/Makefile +++ b/designs/leon3-digilent-nexys4/Makefile @@ -9,6 +9,7 @@ DEVICE=$(PART)-$(PACKAGE)$(SPEED) #UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf UCF=$(TOP).ucf UCF_PLANAHEAD=$(UCF) +XDC=$(TOP).xdc QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf EFFORT=high XSTOPT=-uc leon3mp.xcf diff --git a/designs/leon3-digilent-nexys4/README.txt b/designs/leon3-digilent-nexys4/README.txt index 3cb73880..1a47ba34 100644 --- a/designs/leon3-digilent-nexys4/README.txt +++ b/designs/leon3-digilent-nexys4/README.txt @@ -1,40 +1,17 @@ -This leon3 design is tailored to the Digilent Nexys4 board - +This LEON design is tailored to the Digilent Nexys4 board +--------------------------------------------------------- Simulation and synthesis ------------------------ -The design currently supports synthesis though with xilinx ise and synplify. -Make scripts do not work for vivado. +The design currently supports synthesis with Xilinx ISE/Synplify and +Vivado. -Compile Modelsim simulation: make vsim -Synthesise with Xilinx ISE: make ise -Program the FPGA: make ise-prog-fpga -Program the PROM make ise-prog-prom - -Connecting to USB-UART ----------------------- -The USB/JTAG and USB/UART shares the same port and can cause problems. - -If the output from the dmsg includes the output below, it is possible that -it is caused by a linux driver incompaiblity. - -Dmesg output: ftdi_sio ttyUSB0: FTDI USB Serial Device converter - now disconnected from ttyUSB<#> - -Procedure: - * Power the board with a power supply - * (Program the board over JTAG) - * rmmod the ftdi drivers - sudo rmmod ftdi_sio - sudo rmmod usbserial - * Replug the micro-USB cable. The /dev/ttyUSB0 and/or /dev/ttyUSB1 - should now exist. (JTAG over USB is temporarily lost) - * Run GRMON: grmon -uart /dev/ttyUSB1 -u - * Reconnecting the micro-USB cable migth load back the ftdi_sio and usbserial - drivers. Thefore the procedure might have to be repeated. - -RECOMENDED SOLUTION use other pins for UART and not over USB/UART. +Compile with ModelSim: make vsim +Synthesise and p&r with Xilinx ISE: make ise +Program the FPGA: make ise-prog-fpga +Program the PROM make ise-prog-prom +Synthesise and p&r with Xilinx Vivado: make vivado Design specifics ---------------- @@ -50,18 +27,18 @@ Design specifics * LED 3 indicate processor in error mode -* The SRAM is accessed asynchronously and has an accestime of 70ns. It is therefore - necesssssary to add extra wait states for the SRAM. This can be done by starting - GRMON with the parameters: -ramrws 3 -ramwws 3 - One or two waitstates might also work. +* The SRAM is accessed asynchronously and has an access time of 70ns. + It is therefore necessary to add extra wait states for the SRAM. This + can be done by starting GRMON with the parameters: -ramrws 3 -ramwws 3 * The design has no flash/ROM. An AHBROM is therefore instatiated. - Curently there is no SPI or SDcard support. + Currently there is no SPI or SD card support. -* The application UART1 is unconnected. To enable it uncomment the in/out +* The application UART1 is unconnected. To enable it, uncomment the in/out pads for the apbuart and comment out the ahbuart pads. -* The JTAG DSU interface is enabled and accesible via the USB/JTAG port and USB/UART. +* The JTAG DSU interface is enabled and accessible via the USB/JTAG port + and USB/UART. Start grmon with -digilent to connect with USB/JTAG. * Output from GRMON is: @@ -73,12 +50,6 @@ grmon -eth 192.168.0.51 -u Copyright (C) 2013 Aeroflex Gaisler - All rights reserved. For latest updates, go to http://www.gaisler.com/ Comments or bug-reports to support@gaisler.com - -Parsing -eth 192.168.0.51 -Parsing -u - -Commands missing help: - datacache Ethernet startup... GRLIB build version: 4137 diff --git a/designs/leon3-digilent-nexys4/config.h b/designs/leon3-digilent-nexys4/config.h index 80d7d5c9..abf85730 100644 --- a/designs/leon3-digilent-nexys4/config.h +++ b/designs/leon3-digilent-nexys4/config.h @@ -221,7 +221,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000000 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-digilent-nexys4/config.help b/designs/leon3-digilent-nexys4/config.help index 458bbd81..81b3d19a 100644 --- a/designs/leon3-digilent-nexys4/config.help +++ b/designs/leon3-digilent-nexys4/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-digilent-nexys4/config.vhd b/designs/leon3-digilent-nexys4/config.vhd index ba812615..37926e3b 100644 --- a/designs/leon3-digilent-nexys4/config.vhd +++ b/designs/leon3-digilent-nexys4/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-digilent-nexys4/config.vhd.h b/designs/leon3-digilent-nexys4/config.vhd.h index 368a9909..4937ee54 100644 --- a/designs/leon3-digilent-nexys4/config.vhd.h +++ b/designs/leon3-digilent-nexys4/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-digilent-nexys4/lconfig.tk b/designs/leon3-digilent-nexys4/lconfig.tk index 15c1f1df..4899f30e 100755 --- a/designs/leon3-digilent-nexys4/lconfig.tk +++ b/designs/leon3-digilent-nexys4/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5144,7 +5135,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5345,6 +5335,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5801,7 +5792,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5924,10 +5914,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6039,6 +6028,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-digilent-nexys4/leon3mp.ucf b/designs/leon3-digilent-nexys4/leon3mp.ucf index 3e2157fd..694d7cbe 100644 --- a/designs/leon3-digilent-nexys4/leon3mp.ucf +++ b/designs/leon3-digilent-nexys4/leon3mp.ucf @@ -8,6 +8,10 @@ NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; #Bank = 35, Pin name = IO_ NET "clk" TNM_NET = sys_clk_pin; TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100 MHz HIGH 50%; +NET "eth_clk" TNM_NET = eth_clk; +NET "eth_clk90" TNM_NET = eth_clk; +TIMESPEC TS_eth_clk = PERIOD eth_clk 50 MHz HIGH 50%; + ## Switches NET "sw<0>" LOC = "U9" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 NET "sw<1>" LOC = "U8" | IOSTANDARD = "LVCMOS33"; #Bank = 34, Pin name = IO_25_34, Sch name = SW1 diff --git a/designs/leon3-digilent-nexys4/leon3mp.vhd b/designs/leon3-digilent-nexys4/leon3mp.vhd index d28a5d82..d731a511 100644 --- a/designs/leon3-digilent-nexys4/leon3mp.vhd +++ b/designs/leon3-digilent-nexys4/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-nexys4/leon3mp.xdc b/designs/leon3-digilent-nexys4/leon3mp.xdc new file mode 100644 index 00000000..3d6cae83 --- /dev/null +++ b/designs/leon3-digilent-nexys4/leon3mp.xdc @@ -0,0 +1,1448 @@ +## This file is a general .xdc for the Nexys4 rev B board + +## To use it in a project: + +## - uncomment the lines corresponding to used pins + +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + + + +## Clock signal + +##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ + +set_property PACKAGE_PIN E3 [get_ports clk] + + set_property IOSTANDARD LVCMOS33 [get_ports clk] + + create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] + +create_generated_clock -name eth_clk90 -source [get_pins PLLE2_ADV_inst/CLKIN1] [get_pins PLLE2_ADV_inst/CLKOUT1] +create_generated_clock -name clkm -source [get_pins clkgen0/xc7l.v/PLLE2_ADV_inst/CLKIN1] [get_pins clkgen0/xc7l.v/PLLE2_ADV_inst/CLKOUT0] + +set_false_path -from [get_clocks eth_clk90] -to [get_clocks clkm] +set_false_path -from [get_clocks clkm] -to [get_clocks eth_clk90] + +## Switches + +##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 + +set_property PACKAGE_PIN U9 [get_ports {sw[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] + +##Bank = 34, Pin name = IO_25_34, Sch name = SW1 + +set_property PACKAGE_PIN U8 [get_ports {sw[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] + +##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 + +set_property PACKAGE_PIN R7 [get_ports {sw[2]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] + +##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 + +set_property PACKAGE_PIN R6 [get_ports {sw[3]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] + +##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 + +set_property PACKAGE_PIN R5 [get_ports {sw[4]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] + +##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 + +set_property PACKAGE_PIN V7 [get_ports {sw[5]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] + +##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 + +set_property PACKAGE_PIN V6 [get_ports {sw[6]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] + +##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 + +set_property PACKAGE_PIN V5 [get_ports {sw[7]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] + +##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 + +set_property PACKAGE_PIN U4 [get_ports {sw[8]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] + +##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 + +set_property PACKAGE_PIN V2 [get_ports {sw[9]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] + +##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 + +set_property PACKAGE_PIN U2 [get_ports {sw[10]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] + +##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 + +set_property PACKAGE_PIN T3 [get_ports {sw[11]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] + +##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 + +set_property PACKAGE_PIN T1 [get_ports {sw[12]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] + +##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 + +set_property PACKAGE_PIN R3 [get_ports {sw[13]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] + +##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 + +set_property PACKAGE_PIN P3 [get_ports {sw[14]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] + +##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 + +set_property PACKAGE_PIN P4 [get_ports {sw[15]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] + + + + + + + +## LEDs + +##Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 + +set_property PACKAGE_PIN T8 [get_ports {Led[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[0]}] + +##Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 + +set_property PACKAGE_PIN V9 [get_ports {Led[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[1]}] + +##Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 + +set_property PACKAGE_PIN R8 [get_ports {Led[2]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[2]}] + +##Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 + +set_property PACKAGE_PIN T6 [get_ports {Led[3]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[3]}] + +##Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 + +set_property PACKAGE_PIN T5 [get_ports {Led[4]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[4]}] + +##Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 + +set_property PACKAGE_PIN T4 [get_ports {Led[5]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[5]}] + +##Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 + +set_property PACKAGE_PIN U7 [get_ports {Led[6]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[6]}] + +##Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 + +set_property PACKAGE_PIN U6 [get_ports {Led[7]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[7]}] + +##Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 + +set_property PACKAGE_PIN V4 [get_ports {Led[8]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[8]}] + +##Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 + +set_property PACKAGE_PIN U3 [get_ports {Led[9]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[9]}] + +##Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 + +set_property PACKAGE_PIN V1 [get_ports {Led[10]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[10]}] + +##Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 + +set_property PACKAGE_PIN R1 [get_ports {Led[11]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[11]}] + +##Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 + +set_property PACKAGE_PIN P5 [get_ports {Led[12]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[12]}] + +##Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 + +set_property PACKAGE_PIN U1 [get_ports {Led[13]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[13]}] + +##Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 + +set_property PACKAGE_PIN R2 [get_ports {Led[14]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[14]}] + +##Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 + +set_property PACKAGE_PIN P2 [get_ports {Led[15]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {Led[15]}] + + + +##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R + +#set_property PACKAGE_PIN K5 [get_ports RGB1_Red] + + #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red] + +##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G + +#set_property PACKAGE_PIN F13 [get_ports RGB1_Green] + + #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green] + +##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B + +#set_property PACKAGE_PIN F6 [get_ports RGB1_Blue] + + #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue] + +##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R + +#set_property PACKAGE_PIN K6 [get_ports RGB2_Red] + + #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red] + +##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G + +#set_property PACKAGE_PIN H6 [get_ports RGB2_Green] + + #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green] + +##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B + +#set_property PACKAGE_PIN L16 [get_ports RGB2_Blue] + + #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue] + + + + + + + +##7 segment display + +##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA + +#set_property PACKAGE_PIN L3 [get_ports {seg[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] + +##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB + +#set_property PACKAGE_PIN N1 [get_ports {seg[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] + +##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC + +#set_property PACKAGE_PIN L5 [get_ports {seg[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] + +##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD + +#set_property PACKAGE_PIN L4 [get_ports {seg[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] + +##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE + +#set_property PACKAGE_PIN K3 [get_ports {seg[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] + +##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF + +#set_property PACKAGE_PIN M2 [get_ports {seg[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] + +##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG + +#set_property PACKAGE_PIN L6 [get_ports {seg[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] + + + +##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP + +#set_property PACKAGE_PIN M4 [get_ports dp] + + #set_property IOSTANDARD LVCMOS33 [get_ports dp] + + + +##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 + +#set_property PACKAGE_PIN N6 [get_ports {an[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] + +##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 + +#set_property PACKAGE_PIN M6 [get_ports {an[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] + +##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 + +#set_property PACKAGE_PIN M3 [get_ports {an[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] + +##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 + +#set_property PACKAGE_PIN N5 [get_ports {an[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] + +##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 + +#set_property PACKAGE_PIN N2 [get_ports {an[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] + +##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 + +#set_property PACKAGE_PIN N4 [get_ports {an[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] + +##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 + +#set_property PACKAGE_PIN L1 [get_ports {an[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] + +##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 + +#set_property PACKAGE_PIN M1 [get_ports {an[7]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] + + + + + + + +##Buttons + +##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET + +set_property PACKAGE_PIN C12 [get_ports btnCpuResetn] + + set_property IOSTANDARD LVCMOS33 [get_ports btnCpuResetn] + +##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC + +set_property PACKAGE_PIN E16 [get_ports {btn[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {btn[0]}] + +##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU + +set_property PACKAGE_PIN F15 [get_ports {btn[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {btn[1]}] + +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL + +set_property PACKAGE_PIN T16 [get_ports {btn[2]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {btn[2]}] + +##Bank = 14, Pin name = IO_25_14, Sch name = BTNR + +set_property PACKAGE_PIN R10 [get_ports {btn[4]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {btn[4]}] + +##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND + +set_property PACKAGE_PIN V10 [get_ports {btn[3]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {btn[3]}] + + + + + + + +##Pmod Header JA + +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 + +#set_property PACKAGE_PIN B13 [get_ports {JA[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] + +##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 + +#set_property PACKAGE_PIN F14 [get_ports {JA[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] + +##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 + +#set_property PACKAGE_PIN D17 [get_ports {JA[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] + +##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 + +#set_property PACKAGE_PIN E17 [get_ports {JA[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] + +##Bank = 15, Pin name = IO_0_15, Sch name = JA7 + +#set_property PACKAGE_PIN G13 [get_ports {JA[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] + +##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 + +#set_property PACKAGE_PIN C17 [get_ports {JA[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] + +##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 + +#set_property PACKAGE_PIN D18 [get_ports {JA[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] + +##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 + +#set_property PACKAGE_PIN E18 [get_ports {JA[7]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] + + + + + + + +##Pmod Header JB + +##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 + +#set_property PACKAGE_PIN G14 [get_ports {JB[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] + +##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 + +#set_property PACKAGE_PIN P15 [get_ports {JB[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] + +##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 + +#set_property PACKAGE_PIN V11 [get_ports {JB[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] + +##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 + +#set_property PACKAGE_PIN V15 [get_ports {JB[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] + +##Bank = 15, Pin name = IO_25_15, Sch name = JB7 + +#set_property PACKAGE_PIN K16 [get_ports {JB[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] + +##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 + +#set_property PACKAGE_PIN R16 [get_ports {JB[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] + +##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 + +#set_property PACKAGE_PIN T9 [get_ports {JB[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] + +##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 + +#set_property PACKAGE_PIN U11 [get_ports {JB[7]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] + + + + + + + +##Pmod Header JC + +##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 + +#set_property PACKAGE_PIN K2 [get_ports {JC[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] + +##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 + +#set_property PACKAGE_PIN E7 [get_ports {JC[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] + +##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 + +#set_property PACKAGE_PIN J3 [get_ports {JC[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] + +##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 + +#set_property PACKAGE_PIN J4 [get_ports {JC[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] + +##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 + +#set_property PACKAGE_PIN K1 [get_ports {JC[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] + +##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 + +#set_property PACKAGE_PIN E6 [get_ports {JC[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] + +##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 + +#set_property PACKAGE_PIN J2 [get_ports {JC[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] + +##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 + +#set_property PACKAGE_PIN G6 [get_ports {JC[7]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] + + + + + + + +##Pmod Header JD + +##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 + +#set_property PACKAGE_PIN H4 [get_ports {JD[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] + +##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 + +#set_property PACKAGE_PIN H1 [get_ports {JD[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] + +##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 + +#set_property PACKAGE_PIN G1 [get_ports {JD[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] + +##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 + +#set_property PACKAGE_PIN G3 [get_ports {JD[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] + +##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 + +#set_property PACKAGE_PIN H2 [get_ports {JD[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] + +##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 + +#set_property PACKAGE_PIN G4 [get_ports {JD[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] + +##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 + +#set_property PACKAGE_PIN G2 [get_ports {JD[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] + +##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 + +#set_property PACKAGE_PIN F3 [get_ports {JD[7]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] + + + + + + + +##Pmod Header JXADC + +##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P + +#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] + +##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P + +#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] + +##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P + +#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] + +##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P + +#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] + +##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N + +#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] + +##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N + +#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] + +##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N + +#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] + +##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N + +#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] + + + + + + + +##VGA Connector + +##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 + +#set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] + +##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 + +#set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] + +##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 + +#set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] + +##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 + +#set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] + +##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 + +#set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] + +##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 + +#set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] + +##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 + +#set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] + +##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 + +#set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] + +##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 + +#set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] + +##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 + +#set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] + +##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 + +#set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] + +##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 + +#set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] + +##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS + +#set_property PACKAGE_PIN B11 [get_ports Hsync] + + #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] + +##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS + +#set_property PACKAGE_PIN B12 [get_ports Vsync] + + #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] + + + + + + + +##Micro SD Connector + +##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET + +#set_property PACKAGE_PIN E2 [get_ports sdReset] + + #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] + +##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD + +#set_property PACKAGE_PIN A1 [get_ports sdCD] + + #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] + +##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK + +#set_property PACKAGE_PIN B1 [get_ports sdSCK] + + #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] + +##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD + +#set_property PACKAGE_PIN C1 [get_ports sdCmd] + + #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] + +##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 + +#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] + +##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 + +#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] + +##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 + +#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] + +##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 + +#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] + + + + + + + +##Accelerometer + +##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO + +#set_property PACKAGE_PIN D13 [get_ports aclMISO] + + #set_property IOSTANDARD LVCMOS33 [get_ports aclMISO] + +##Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI + +#set_property PACKAGE_PIN B14 [get_ports aclMOSI] + + #set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI] + +##Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK + +#set_property PACKAGE_PIN D15 [get_ports aclSCK] + + #set_property IOSTANDARD LVCMOS33 [get_ports aclSCK] + +##Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN + +#set_property PACKAGE_PIN C15 [get_ports aclSS] + + #set_property IOSTANDARD LVCMOS33 [get_ports aclSS] + +##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 + +#set_property PACKAGE_PIN C16 [get_ports aclInt1] + + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] + +##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 + +#set_property PACKAGE_PIN E15 [get_ports aclInt2] + + #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] + + + + + + + +##Temperature Sensor + +##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL + +#set_property PACKAGE_PIN F16 [get_ports tmpSCL] + + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] + +##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA + +#set_property PACKAGE_PIN G16 [get_ports tmpSDA] + + #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] + +##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT + +#set_property PACKAGE_PIN D14 [get_ports tmpInt] + + #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] + +##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT + +#set_property PACKAGE_PIN C14 [get_ports tmpCT] + + #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] + + + + + + + +##Omnidirectional Microphone + +##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK + +#set_property PACKAGE_PIN J5 [get_ports micClk] + + #set_property IOSTANDARD LVCMOS33 [get_ports micClk] + +##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA + +#set_property PACKAGE_PIN H5 [get_ports micData] + + #set_property IOSTANDARD LVCMOS33 [get_ports micData] + +##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL + +#set_property PACKAGE_PIN F5 [get_ports micLRSel] + + #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] + + + + + + + +##PWM Audio Amplifier + +##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM + +#set_property PACKAGE_PIN A11 [get_ports ampPWM] + + #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] + +##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD + +#set_property PACKAGE_PIN D12 [get_ports ampSD] + + #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] + + + + + +##USB-RS232 Interface + +##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN + +set_property PACKAGE_PIN C4 [get_ports RsRx] + + set_property IOSTANDARD LVCMOS33 [get_ports RsRx] + +##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT + +set_property PACKAGE_PIN D4 [get_ports RsTx] + + set_property IOSTANDARD LVCMOS33 [get_ports RsTx] + +##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS + +#set_property PACKAGE_PIN D3 [get_ports RsCts] + + #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] + +##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS + +#set_property PACKAGE_PIN E5 [get_ports RsRts] + + #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] + + + + + + + +##USB HID (PS/2) + +##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK + +#set_property PACKAGE_PIN F4 [get_ports PS2Clk] + + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] + + #set_property PULLUP true [get_ports PS2Clk] + +##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA + +#set_property PACKAGE_PIN B2 [get_ports PS2Data] + + #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] + + #set_property PULLUP true [get_ports PS2Data] + + + + + + + +##SMSC Ethernet PHY + +##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC + +set_property PACKAGE_PIN C9 [get_ports PhyMdc] + + set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] + +##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO + +set_property PACKAGE_PIN A9 [get_ports PhyMdio] + + set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] + +##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN + +set_property PACKAGE_PIN B3 [get_ports PhyRstn] + + set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] + +##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV + +set_property PACKAGE_PIN D9 [get_ports PhyCrs] + + set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] + +##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR + +#set_property PACKAGE_PIN C10 [get_ports PhyRxErr] + + #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] + +##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 + +set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] + +##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 + +set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] + +##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN + +set_property PACKAGE_PIN B9 [get_ports PhyTxEn] + + set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] + +##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 + +set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] + +##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 + +set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] + +##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK + +set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] + + set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] + +##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN + +#set_property PACKAGE_PIN B8 [get_ports PhyIntn] + + #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] + + + + + + + +##Quad SPI Flash + +##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK + +#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] + +##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 + +#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] + +##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 + +#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] + +##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 + +#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] + +##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 + +#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] + + #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] + +##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN + +#set_property PACKAGE_PIN L13 [get_ports QspiCSn] + + #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] + + + + + + + +##Cellular RAM + +##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK + +set_property PACKAGE_PIN T15 [get_ports RamClk] + + set_property IOSTANDARD LVCMOS33 [get_ports RamClk] + +##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN + +set_property PACKAGE_PIN T13 [get_ports RamAdv] + + set_property IOSTANDARD LVCMOS33 [get_ports RamAdv] + +##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN + +set_property PACKAGE_PIN L18 [get_ports RamCE] + + set_property IOSTANDARD LVCMOS33 [get_ports RamCE] + +##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE + +set_property PACKAGE_PIN J14 [get_ports RamCRE] + + set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] + +##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN + +set_property PACKAGE_PIN H14 [get_ports RamOE] + + set_property IOSTANDARD LVCMOS33 [get_ports RamOE] + +##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN + +set_property PACKAGE_PIN R11 [get_ports RamWE] + + set_property IOSTANDARD LVCMOS33 [get_ports RamWE] + +##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN + +set_property PACKAGE_PIN J15 [get_ports RamLB] + + set_property IOSTANDARD LVCMOS33 [get_ports RamLB] + +##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN + +set_property PACKAGE_PIN J13 [get_ports RamUB] + + set_property IOSTANDARD LVCMOS33 [get_ports RamUB] + +##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT + +#set_property PACKAGE_PIN T14 [get_ports RamWait] + + #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] + + + +##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 + +set_property PACKAGE_PIN R12 [get_ports {data[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[0]}] + +##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 + +set_property PACKAGE_PIN T11 [get_ports {data[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[1]}] + +##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 + +set_property PACKAGE_PIN U12 [get_ports {data[2]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[2]}] + +##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 + +set_property PACKAGE_PIN R13 [get_ports {data[3]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[3]}] + +##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 + +set_property PACKAGE_PIN U18 [get_ports {data[4]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[4]}] + +##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 + +set_property PACKAGE_PIN R17 [get_ports {data[5]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[5]}] + +##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 + +set_property PACKAGE_PIN T18 [get_ports {data[6]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[6]}] + +##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 + +set_property PACKAGE_PIN R18 [get_ports {data[7]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[7]}] + +##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 + +set_property PACKAGE_PIN F18 [get_ports {data[8]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[8]}] + +##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 + +set_property PACKAGE_PIN G18 [get_ports {data[9]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[9]}] + +##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 + +set_property PACKAGE_PIN G17 [get_ports {data[10]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[10]}] + +##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 + +set_property PACKAGE_PIN M18 [get_ports {data[11]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[11]}] + +##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 + +set_property PACKAGE_PIN M17 [get_ports {data[12]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[12]}] + +##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 + +set_property PACKAGE_PIN P18 [get_ports {data[13]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[13]}] + +##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 + +set_property PACKAGE_PIN N17 [get_ports {data[14]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[14]}] + +##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 + +set_property PACKAGE_PIN P17 [get_ports {data[15]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {data[15]}] + + + +##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 + +set_property PACKAGE_PIN J18 [get_ports {address[0]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[0]}] + +##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 + +set_property PACKAGE_PIN H17 [get_ports {address[1]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[1]}] + +##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 + +set_property PACKAGE_PIN H15 [get_ports {address[2]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[2]}] + +##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 + +set_property PACKAGE_PIN J17 [get_ports {address[3]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[3]}] + +##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 + +set_property PACKAGE_PIN H16 [get_ports {address[4]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[4]}] + +##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 + +set_property PACKAGE_PIN K15 [get_ports {address[5]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[5]}] + +##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 + +set_property PACKAGE_PIN K13 [get_ports {address[6]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[6]}] + +##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 + +set_property PACKAGE_PIN N15 [get_ports {address[7]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[7]}] + +##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 + +set_property PACKAGE_PIN V16 [get_ports {address[8]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[8]}] + +##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 + +set_property PACKAGE_PIN U14 [get_ports {address[9]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[9]}] + +##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 + +set_property PACKAGE_PIN V14 [get_ports {address[10]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[10]}] + +##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 + +set_property PACKAGE_PIN V12 [get_ports {address[11]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[11]}] + +##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 + +set_property PACKAGE_PIN P14 [get_ports {address[12]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[12]}] + +##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 + +set_property PACKAGE_PIN U16 [get_ports {address[13]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[13]}] + +##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 + +set_property PACKAGE_PIN R15 [get_ports {address[14]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[14]}] + +##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 + +set_property PACKAGE_PIN N14 [get_ports {address[15]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[15]}] + +##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 + +set_property PACKAGE_PIN N16 [get_ports {address[16]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[16]}] + +##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 + +set_property PACKAGE_PIN M13 [get_ports {address[17]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[17]}] + +##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 + +set_property PACKAGE_PIN V17 [get_ports {address[18]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[18]}] + +##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 + +set_property PACKAGE_PIN U17 [get_ports {address[19]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[19]}] + +##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 + +set_property PACKAGE_PIN T10 [get_ports {address[20]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[20]}] + +##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 + +set_property PACKAGE_PIN M16 [get_ports {address[21]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[21]}] + +##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 + +set_property PACKAGE_PIN U13 [get_ports {address[22]}] + + set_property IOSTANDARD LVCMOS33 [get_ports {address[22]}] + + + diff --git a/designs/leon3-digilent-nexys4/ram.srec b/designs/leon3-digilent-nexys4/ram.srec index a896a74b..2c229af3 100755 --- a/designs/leon3-digilent-nexys4/ram.srec +++ b/designs/leon3-digilent-nexys4/ram.srec @@ -1,11 +1,11 @@ S00B000072616D2E73726563D9 -S31540000000881000000910006C81C1234401000000E3 +S31540000000881000000910006C81C120B0010000007A S31540000010A1480000A75000001080203EAC102001EF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006C81C5229801000000DB -S31540000050A14800002910006981C523500100000015 -S31540000060A14800002910006981C523BC0100000099 +S31540000040A14800002910006C81C520040100000071 +S31540000050A14800002910006981C5232C0100000039 +S31540000060A14800002910006981C5239801000000BD S3154000007091D02000010000000100000001000000B6 S3154000008091D02000010000000100000001000000A6 S31540000090A1480000A75000001080201EAC10200987 @@ -16,21 +16,21 @@ S315400000D091D0200001000000010000000100000056 S315400000E091D0200001000000010000000100000046 S315400000F091D0200001000000010000000100000036 S3154000010091D0200001000000010000000100000025 -S31540000110AE102001A148000010806A55A75000008B -S31540000120AE102002A148000010806A51A75000007E -S31540000130AE102003A148000010806A4DA750000071 -S31540000140AE102004A148000010806A49A750000064 -S31540000150AE102005A148000010806A45A750000057 -S31540000160AE102006A148000010806A41A75000004A -S31540000170AE102007A148000010806A3DA75000003D -S31540000180AE102008A148000010806A39A750000030 -S31540000190AE102009A148000010806A35A750000023 -S315400001A0AE10200AA148000010806A31A750000016 -S315400001B0AE10200BA148000010806A2DA750000009 -S315400001C0AE10200CA148000010806A29A7500000FC -S315400001D0AE10200DA148000010806A25A7500000EF -S315400001E0AE10200EA148000010806A21A7500000E2 -S315400001F0AE10200FA148000010806A1DA7500000D5 +S31540000110AE102001A148000010806A4CA750000094 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+S3154001C11000000000000000000000000000000000D8 +S3154001C12000000000000000000000000000000000C8 +S3154001C13000000000000000000000000000000000B8 +S3154001C14000000000000000000000000000000000A8 +S3154001C1500000000000000000000000000000000098 +S3154001C1600000000000000000000000000000000088 +S3154001C1700000000000000000000000000000000078 +S3154001C1800000000000000000000000000000000068 +S3154001C1900000000000000000000000000000000058 +S3154001C1A00000000000000000000000000000000048 S3154001C1B00000000000000000000000000000000038 S3154001C1C00000000000000000000000000000000028 S3154001C1D00000000000000000000000000000000018 @@ -18468,7 +18468,7 @@ S315400482100000000000000000000000000000000014 S315400482204004822800000000000000004004851439 S31540048230400485E0400486AC0000000000000000D5 S3154004824000000000000000000000000000000000E4 -S315400482500000000000000000000000004001C1785A +S315400482500000000000000000000000004001BD488E S3154004826000000000000000000000000000000000C4 S3154004827000000000000000000000000000000000B4 S3154004828000000000000000000000000000000000A4 @@ -18625,7 +18625,8 @@ S31540048BE0000000000000000000000000000000003B S31540048BF0000000000000000000000000000000002B S31540048C00000000000000000000000000000000001A S31540048C10000000000000000000000000000000000A -S31540048C200000000000000000800003100000000067 -S31540048C30000000008000010000000008000000075A -S31540048C40000000060000000300000000FFFF8AD079 +S31540048C2000000000000000000000000000000000FA +S31540048C308000010000000008000000070000000654 +S31540048C40000000030000000000000000FFFF8AD07F +S30940048C508000031043 S70540000000BA diff --git a/designs/leon3-digilent-nexys4/testbench.vhd b/designs/leon3-digilent-nexys4/testbench.vhd index c1711cd9..7ba83783 100644 --- a/designs/leon3-digilent-nexys4/testbench.vhd +++ b/designs/leon3-digilent-nexys4/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -28,17 +28,10 @@ use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -library hynix; -use hynix.components.all; - entity testbench is generic ( fabtech : integer := CFG_FABTECH; diff --git a/designs/leon3-digilent-nexys4/tkconfig.h b/designs/leon3-digilent-nexys4/tkconfig.h index 2a5a32c5..d5a3e41a 100644 --- a/designs/leon3-digilent-nexys4/tkconfig.h +++ b/designs/leon3-digilent-nexys4/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-digilent-xc3s1000/Makefile b/designs/leon3-digilent-xc3s1000/Makefile index b8fb4cfa..27bbd845 100644 --- a/designs/leon3-digilent-xc3s1000/Makefile +++ b/designs/leon3-digilent-xc3s1000/Makefile @@ -23,7 +23,7 @@ LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF usbhc \ DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \ spacewire ddr can usb grusbhc hcan \ leon4 leon4v0 l2cache slink ascs pwm gr1553b iommu -FILESKIP = grcan.vhd i2cmst.vhd +FILESKIP = grcan.vhd i2cmst.vhd sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/leon3-digilent-xc3s1000/config.help b/designs/leon3-digilent-xc3s1000/config.help index 72f00950..5c5caba4 100644 --- a/designs/leon3-digilent-xc3s1000/config.help +++ b/designs/leon3-digilent-xc3s1000/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-digilent-xc3s1000/config.vhd b/designs/leon3-digilent-xc3s1000/config.vhd index 8cf5452b..85493845 100644 --- a/designs/leon3-digilent-xc3s1000/config.vhd +++ b/designs/leon3-digilent-xc3s1000/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-digilent-xc3s1000/config.vhd.h b/designs/leon3-digilent-xc3s1000/config.vhd.h index 062c2963..b89fa3ad 100644 --- a/designs/leon3-digilent-xc3s1000/config.vhd.h +++ b/designs/leon3-digilent-xc3s1000/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-digilent-xc3s1000/lconfig.tk b/designs/leon3-digilent-xc3s1000/lconfig.tk index c6eb63d3..72835997 100755 --- a/designs/leon3-digilent-xc3s1000/lconfig.tk +++ b/designs/leon3-digilent-xc3s1000/lconfig.tk @@ -2077,24 +2077,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2166,20 +2165,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2312,9 +2308,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4285,7 +4278,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4415,6 +4407,7 @@ set CONFIG_SVGA_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4869,7 +4862,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-digilent-xc3s1000/leon3mp.vhd b/designs/leon3-digilent-xc3s1000/leon3mp.vhd index 516ef5f0..638b7c4e 100644 --- a/designs/leon3-digilent-xc3s1000/leon3mp.vhd +++ b/designs/leon3-digilent-xc3s1000/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-xc3s1000/testbench.vhd b/designs/leon3-digilent-xc3s1000/testbench.vhd index 16736608..5e313eab 100644 --- a/designs/leon3-digilent-xc3s1000/testbench.vhd +++ b/designs/leon3-digilent-xc3s1000/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-xc3s1000/tkconfig.h b/designs/leon3-digilent-xc3s1000/tkconfig.h index 41645ded..6b8baab9 100644 --- a/designs/leon3-digilent-xc3s1000/tkconfig.h +++ b/designs/leon3-digilent-xc3s1000/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd b/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd index 54adefa8..0b52cea3 100644 --- a/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd +++ b/designs/leon3-digilent-xc3s1000/vga_clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-xc3s1600e/.config b/designs/leon3-digilent-xc3s1600e/.config index 86feb2c2..7a7d9e4b 100755 --- a/designs/leon3-digilent-xc3s1600e/.config +++ b/designs/leon3-digilent-xc3s1600e/.config @@ -168,7 +168,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -254,7 +253,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000018 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-digilent-xc3s1600e/Makefile b/designs/leon3-digilent-xc3s1600e/Makefile index 9eba95aa..15563f6f 100644 --- a/designs/leon3-digilent-xc3s1600e/Makefile +++ b/designs/leon3-digilent-xc3s1600e/Makefile @@ -27,7 +27,7 @@ LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \ usb grusbhc spacewire synplicity hcan leon4 leon4v0 \ l2cache slink ascs pwm hynix gr1553b iommu -FILESKIP = grcan.vhd i2cmst.vhd +FILESKIP = grcan.vhd i2cmst.vhd sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/leon3-digilent-xc3s1600e/config.h b/designs/leon3-digilent-xc3s1600e/config.h index ed44bf09..1f8aa8c7 100644 --- a/designs/leon3-digilent-xc3s1600e/config.h +++ b/designs/leon3-digilent-xc3s1600e/config.h @@ -163,7 +163,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -243,7 +242,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000018 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-digilent-xc3s1600e/config.help b/designs/leon3-digilent-xc3s1600e/config.help index 268ba468..e28f9064 100644 --- a/designs/leon3-digilent-xc3s1600e/config.help +++ b/designs/leon3-digilent-xc3s1600e/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-digilent-xc3s1600e/config.vhd b/designs/leon3-digilent-xc3s1600e/config.vhd index 8198bb21..5426e52a 100644 --- a/designs/leon3-digilent-xc3s1600e/config.vhd +++ b/designs/leon3-digilent-xc3s1600e/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-digilent-xc3s1600e/config.vhd.h b/designs/leon3-digilent-xc3s1600e/config.vhd.h index e2625d87..8e70b344 100644 --- a/designs/leon3-digilent-xc3s1600e/config.vhd.h +++ b/designs/leon3-digilent-xc3s1600e/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-digilent-xc3s1600e/lconfig.tk b/designs/leon3-digilent-xc3s1600e/lconfig.tk index e4ce67d8..9c05afd6 100755 --- a/designs/leon3-digilent-xc3s1600e/lconfig.tk +++ b/designs/leon3-digilent-xc3s1600e/lconfig.tk @@ -2079,24 +2079,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2168,20 +2167,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2314,9 +2310,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3127,7 +3120,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3177,12 +3170,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3213,12 +3205,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4623,7 +4614,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4781,6 +4771,7 @@ set CONFIG_SVGA_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5237,7 +5228,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5360,10 +5350,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5436,6 +5425,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-digilent-xc3s1600e/leon3mp.vhd b/designs/leon3-digilent-xc3s1600e/leon3mp.vhd index 5565e789..72657cc1 100644 --- a/designs/leon3-digilent-xc3s1600e/leon3mp.vhd +++ b/designs/leon3-digilent-xc3s1600e/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-xc3s1600e/testbench.vhd b/designs/leon3-digilent-xc3s1600e/testbench.vhd index bf9cc679..b3c367f4 100644 --- a/designs/leon3-digilent-xc3s1600e/testbench.vhd +++ b/designs/leon3-digilent-xc3s1600e/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -194,13 +194,21 @@ begin ddr_clk_fb <= ddr_clk; - u1 : mt46v16m16 - generic map (index => -1, fname => sdramfile) - port map( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); + -- u1 : mt46v16m16 + -- generic map (index => -1, fname => sdramfile) + -- port map( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad, + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + + ddr0 : ddrram + generic map(width => 16, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin => 1, density => 2) + port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); prom0 : for i in 0 to (romwidth/8)-1 generate sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-digilent-xc3s1600e/tkconfig.h b/designs/leon3-digilent-xc3s1600e/tkconfig.h index b4c5809b..3badcc7c 100644 --- a/designs/leon3-digilent-xc3s1600e/tkconfig.h +++ b/designs/leon3-digilent-xc3s1600e/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-digilent-xc7z020/.config b/designs/leon3-digilent-xc7z020/.config index 92cbec5a..14fdca41 100644 --- a/designs/leon3-digilent-xc7z020/.config +++ b/designs/leon3-digilent-xc7z020/.config @@ -99,19 +99,18 @@ CONFIG_LEON3_CUSTOM=y # CONFIG_IU_NWINDOWS=8 CONFIG_IU_V8MULDIV=y -# CONFIG_IU_MUL_LATENCY_2 is not set +CONFIG_IU_MUL_LATENCY_2=y # CONFIG_IU_MUL_LATENCY_4 is not set -CONFIG_IU_MUL_LATENCY_5=y -# CONFIG_IU_MUL_MAC is not set +# CONFIG_IU_MUL_LATENCY_5 is not set CONFIG_IU_MUL_INFERRED=y # CONFIG_IU_MUL_MODGEN is not set # CONFIG_IU_MUL_TECHSPEC is not set # CONFIG_IU_MUL_DW is not set CONFIG_IU_BP=y CONFIG_IU_SVT=y -# CONFIG_NOTAG is not set -CONFIG_IU_LDELAY=2 -CONFIG_IU_WATCHPOINTS=2 +CONFIG_NOTAG=y +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=1 CONFIG_PWD=y CONFIG_IU_RSTADDR=00000 @@ -130,21 +129,20 @@ CONFIG_ICACHE_ASSO2=y # CONFIG_ICACHE_ASSO4 is not set # CONFIG_ICACHE_SZ1 is not set # CONFIG_ICACHE_SZ2 is not set -CONFIG_ICACHE_SZ4=y -# CONFIG_ICACHE_SZ8 is not set +# CONFIG_ICACHE_SZ4 is not set +CONFIG_ICACHE_SZ8=y # CONFIG_ICACHE_SZ16 is not set # CONFIG_ICACHE_SZ32 is not set # CONFIG_ICACHE_SZ64 is not set # CONFIG_ICACHE_SZ128 is not set # CONFIG_ICACHE_SZ256 is not set -CONFIG_ICACHE_LZ16=y -# CONFIG_ICACHE_LZ32 is not set -CONFIG_ICACHE_ALGORND=y +# CONFIG_ICACHE_LZ16 is not set +CONFIG_ICACHE_LZ32=y +# CONFIG_ICACHE_ALGORND is not set # CONFIG_ICACHE_ALGODIR is not set # CONFIG_ICACHE_ALGOLRR is not set -# CONFIG_ICACHE_ALGOLRU is not set +CONFIG_ICACHE_ALGOLRU=y # CONFIG_ICACHE_LOCK is not set -# CONFIG_ICACHE_LRAM is not set CONFIG_DCACHE_ENABLE=y # CONFIG_DCACHE_ASSO1 is not set CONFIG_DCACHE_ASSO2=y @@ -159,37 +157,58 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_SZ64 is not set # CONFIG_DCACHE_SZ128 is not set # CONFIG_DCACHE_SZ256 is not set -CONFIG_DCACHE_LZ16=y -# CONFIG_DCACHE_LZ32 is not set -CONFIG_DCACHE_ALGORND=y +# CONFIG_DCACHE_LZ16 is not set +CONFIG_DCACHE_LZ32=y +# CONFIG_DCACHE_ALGORND is not set # CONFIG_DCACHE_ALGODIR is not set # CONFIG_DCACHE_ALGOLRR is not set -# CONFIG_DCACHE_ALGOLRU is not set +CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 -# CONFIG_DCACHE_LRAM is not set # # MMU # -# CONFIG_MMU_ENABLE is not set +CONFIG_MMU_ENABLE=y +# CONFIG_MMU_COMBINED is not set +CONFIG_MMU_SPLIT=y +CONFIG_MMU_REPARRAY=y +# CONFIG_MMU_REPINCREMENT is not set +# CONFIG_MMU_I2 is not set +# CONFIG_MMU_I4 is not set +CONFIG_MMU_I8=y +# CONFIG_MMU_I16 is not set +# CONFIG_MMU_I32 is not set +# CONFIG_MMU_I64 is not set +# CONFIG_MMU_D2 is not set +# CONFIG_MMU_D4 is not set +CONFIG_MMU_D8=y +# CONFIG_MMU_D16 is not set +# CONFIG_MMU_D32 is not set +# CONFIG_MMU_D64 is not set +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +# CONFIG_MMU_PAGE_8K is not set +# CONFIG_MMU_PAGE_16K is not set +# CONFIG_MMU_PAGE_32K is not set +# CONFIG_MMU_PAGE_PROG is not set # # Debug Support Unit # CONFIG_DSU_ENABLE=y CONFIG_DSU_ITRACE=y -CONFIG_DSU_ITRACESZ1=y -# CONFIG_DSU_ITRACESZ2 is not set +# CONFIG_DSU_ITRACESZ1 is not set +CONFIG_DSU_ITRACESZ2=y # CONFIG_DSU_ITRACESZ4 is not set # CONFIG_DSU_ITRACESZ8 is not set # CONFIG_DSU_ITRACESZ16 is not set CONFIG_DSU_ATRACE=y -CONFIG_DSU_ATRACESZ1=y -# CONFIG_DSU_ATRACESZ2 is not set +# CONFIG_DSU_ATRACESZ1 is not set +CONFIG_DSU_ATRACESZ2=y # CONFIG_DSU_ATRACESZ4 is not set # CONFIG_DSU_ATRACESZ8 is not set # CONFIG_DSU_ATRACESZ16 is not set @@ -208,7 +227,7 @@ CONFIG_DSU_ATRACESZ1=y # AMBA configuration # CONFIG_AHB_DEFMST=0 -# CONFIG_AHB_RROBIN is not set +CONFIG_AHB_RROBIN=y # CONFIG_AHB_SPLIT is not set # CONFIG_AHB_FPNPEN is not set CONFIG_AHB_IOADDR=FFF @@ -228,28 +247,16 @@ CONFIG_DSU_JTAG=y # # Memory controller # -# CONFIG_AHBSTAT_ENABLE is not set +CONFIG_AHBSTAT_ENABLE=y +CONFIG_AHBSTAT_NFTSLV=1 # # On-chip RAM/ROM # -# CONFIG_AHBROM_ENABLE is not set -CONFIG_AHBRAM_ENABLE=y -CONFIG_AHBRAM_SZ1=y -# CONFIG_AHBRAM_SZ2 is not set -# CONFIG_AHBRAM_SZ4 is not set -# CONFIG_AHBRAM_SZ8 is not set -# CONFIG_AHBRAM_SZ16 is not set -# CONFIG_AHBRAM_SZ32 is not set -# CONFIG_AHBRAM_SZ64 is not set -# CONFIG_AHBRAM_SZ128 is not set -# CONFIG_AHBRAM_SZ256 is not set -# CONFIG_AHBRAM_SZ512 is not set -# CONFIG_AHBRAM_SZ1024 is not set -# CONFIG_AHBRAM_SZ2048 is not set -# CONFIG_AHBRAM_SZ4096 is not set -CONFIG_AHBRAM_START=A00 -# CONFIG_AHBRAM_PIPE is not set +CONFIG_AHBROM_ENABLE=y +CONFIG_AHBROM_START=000 +CONFIG_AHBROM_PIPE=y +# CONFIG_AHBRAM_ENABLE is not set # # UARTs, timers and irq control @@ -268,7 +275,7 @@ CONFIG_GPT_NTIM=2 CONFIG_GPT_SW=8 CONFIG_GPT_TW=32 CONFIG_GPT_IRQ=8 -# CONFIG_GPT_SEPIRQ is not set +CONFIG_GPT_SEPIRQ=y # CONFIG_GPT_WDOGEN is not set CONFIG_GRGPIO_ENABLE=y CONFIG_GRGPIO_WIDTH=16 diff --git a/designs/leon3-digilent-xc7z020/Makefile b/designs/leon3-digilent-xc7z020/Makefile index 7d5bff96..4e29e878 100644 --- a/designs/leon3-digilent-xc7z020/Makefile +++ b/designs/leon3-digilent-xc7z020/Makefile @@ -5,31 +5,30 @@ TOP=leon3mp BOARD=digilent-zedboard-xc7z020 DESIGN=leon3-zedboard-xc7z020 include $(GRLIB)/boards/$(BOARD)/Makefile.inc +PROTOBOARD=em.avnet.com:zynq:zed:c + DEVICE=$(PART)$(PACKAGE)-$(SPEED) UCF_PLANAHEAD=$(GRLIB)/boards/$(BOARD)/$(BOARD).ucf +XDC=leon3mp.xdc +TCL=stub.tcl VHDLSYNFILES= \ - config.vhd ahbrom.vhd leon3mp.vhd + config.vhd ahbrom.vhd ahb2axi.vhd leon3mp.vhd VHDLSIMFILES= \ - testbench.vhd leon3_zedboard_stub_sim.vhd + leon3_zedboard_stub_sim.vhd testbench.vhd SIMTOP=testbench BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean VCOMOPT=-explicit -VLOGOPT= +define+x1Gb +define+sg125 +define+x8 -VSIMOPT= -t ps -novopt +notimingchecks $(SIMTOP) TECHLIBS = secureip unisim -BOPT=-DRAMSTART=0x00000000 -LDFLAGS=-Wl,-msparcleon0 - LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ - tmtc openchip ihp usbhc spw gsi cypress hynix \ - spansion leon4 leon4v0 secureip + tmtc openchip ihp usbhc gsi cypress hynix \ + spansion leon4 leon4v0 secureip spw DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci ambatest can \ - usb grusbhc spacewire ascs slink spi hcan \ + usb grusbhc ascs slink spi hcan spacewire \ leon4 leon4v0 l2cache pwm gr1553b iommu ac97 secureip FILESKIP = grcan.vhd ddr2.v mobile_ddr.v @@ -49,9 +48,18 @@ help-local: help @echo program-zedboard: - @echo "fpga -f ./planAhead/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit" > ./xmd.ini + @echo "fpga -f ./vivado/$(DESIGN)/$(DESIGN).runs/impl_1/$(TOP).bit" > ./xmd.ini + @echo "connect arm hw" >> ./xmd.ini + @echo "source ./vivado/$(DESIGN)/$(DESIGN).sdk/SDK/SDK_Export/hw/ps7_init.tcl" >> ./xmd.ini + @echo "ps7_init" >> ./xmd.ini + @echo "init_user" >> ./xmd.ini + @echo "exit" >> ./xmd.ini + xmd + +program-zedboard-ref: + @echo "fpga -f ./bitfiles/$(TOP).bit" > ./xmd.ini @echo "connect arm hw" >> ./xmd.ini - @echo "source ./planAhead/$(DESIGN)/$(DESIGN).sdk/SDK/SDK_Export/hw/ps7_init.tcl" >> ./xmd.ini + @echo "source ./vivado/$(DESIGN)/$(DESIGN).sdk/SDK/SDK_Export/hw/ps7_init.tcl" >> ./xmd.ini @echo "ps7_init" >> ./xmd.ini @echo "init_user" >> ./xmd.ini @echo "exit" >> ./xmd.ini diff --git a/designs/leon3-digilent-xc7z020/README.txt b/designs/leon3-digilent-xc7z020/README.txt index 12e1df0b..5affa892 100644 --- a/designs/leon3-digilent-xc7z020/README.txt +++ b/designs/leon3-digilent-xc7z020/README.txt @@ -2,54 +2,70 @@ This leon3 design is tailored to the Digilent Zedboard board www.zedboard.org +Overview +-------- -NOTE: This design is experimental and not kept up to date. +This design implements a typical LEON3 system on a Xilinx Zynq device. +The DDR3 memory attached to the Cortex-A9 processor system (PS) is +uased as LEON3 memory, and accessed through a custom AHB/AXI bridge +(ahb2axi.vhd). -Simulation and synthesis ------------------------- -please note that no system test or simulation enviroment are present at the moment -but it should be possible to compile and load the design into modelsim +Simulation +---------- -To build and load the design into the simulator: +Simulation sjould work with any supported VHDL simultor. +To build and load the design with the modelsim simulator, do: make vsim make vsim-launch -Synthesis will ONLY work with PlanAhead 14.2 installed or newer, and -the XILINX variable properly set in the shell. To synthesize the design, do +The PS and external memory is be emulated by a simple model +(leon3_zedboard_stub_sim.vhd) that provides clocks, reset and + 1 Mbyte or memory. No other PS functionality is emulated. - make planAhead +The standard testbench will only work when the AHBROM module +is enabled in xconfig (default on) as it will provide the boot +strap code and jump to RAM. -and then +Synthesis +--------- - make vivado-zedboard +Synthesis will ONLY work with Vivado 2013.4. To synthesize the design, do: + + make vivado -to program the FPGA. +or -Simulation options ------------------- + make vivado-launch + + (interactive run). + +To program the board, do: + + make vivado-zedboard -N/A Design specifics ---------------- -* Synthesis should be done using PlanAhead 14.2 or newer +* The top 256 Mnyte of the DDR3 (0x10000000 - 0x20000000) is + mapped into AHB address space at 0x40000000 - 0x50000000 using + an AHB/AXI bridge and the S_AXI_GP0 interface on the PS. -* The Leon3 processor is not able to read/write from/to external - DDR3 interface at the moment. (This will be fixed in future - releases) +* System reset is mapped on the south button (button[0]). -* System reset is mapped to the CPU RESET button +* DSU break is mapped to switch[0] -* DSU break is mapped to GPIO east button +* The LEON3 system is clocked at 83.3333 MHz, using FCLK_CLK0 + from the PS. Other frequencies can be used by re-configuring the + PS in Vivado and re-running synthesis. * LED 0 indicates processor in debug mode * LED 1 indicates processor in error mode, execution halted -* LED 2 UART1 RX +* LED 2 indicates AHB HREADY signal. * LED 3 UART1 TX @@ -61,7 +77,12 @@ Design specifics * LED 7 GPIO 14 -* Always program the Zedboard via the make target 'program-zedboard' + +Board programming +----------------- + +Always program the Zedboard via the make target 'program-zedboard' +This requires the installation of Xilinx EDK or SDK. $ make program-zedboard xmd @@ -98,78 +119,104 @@ Connected to "arm" target. id = 64 Starting GDB server for "arm" target (id = 64) at TCP port no 1234 Info: Enabling level shifters and clearing fabric port resets + +Executing programs with grmon +----------------------------- + * The JTAG DSU interface is enabled and accesible via the JTAG port. Start grmon with -xilusb to connect. +* Start grmon with the -u swith to see UART output. The UART connected + to the PS (USB UART) cannot be used. + +* Do not use the CPU RESET button to reset the LEON3 system, as this + will require to initialiaze the PS using xmd again. Use the south + button as reset if neessary. + * Output from GRMON is: - grmon -xilusb - - GRMON2 LEON debug monitor v2.0.30-194-g937ff0a internal version - - Copyright (C) 2012 Aeroflex Gaisler - All rights reserved. - For latest updates, go to http://www.gaisler.com/ - Comments or bug-reports to support@gaisler.com - - -Parsing -xilusb -Xilusb: Cable type/rev : 0x3 - JTAG chain (2): xc7x020 zynq7000_arm_dap - -Commands missing help: - debug - - GRLIB build version: 4120 - Detected frequency: 50 MHz - - Component Vendor - LEON3 SPARC V8 Processor Aeroflex Gaisler - JTAG Debug Link Aeroflex Gaisler - AHB/APB Bridge Aeroflex Gaisler - LEON3 Debug Support Unit Aeroflex Gaisler - Single-port AHB SRAM module Aeroflex Gaisler - Xilinx MIG DDR3 Controller Aeroflex Gaisler - Single-port AHB SRAM module Aeroflex Gaisler - Generic UART Aeroflex Gaisler - Multi-processor Interrupt Ctrl. Aeroflex Gaisler - Modular Timer Unit Aeroflex Gaisler - General Purpose I/O port Aeroflex Gaisler - - Use command 'info sys' to print a detailed report of attached cores - -grmon2> info sys - cpu0 Aeroflex Gaisler LEON3 SPARC V8 Processor - AHB Master 0 - ahbjtag0 Aeroflex Gaisler JTAG Debug Link - AHB Master 1 - apbmst0 Aeroflex Gaisler AHB/APB Bridge - AHB: 80000000 - 80100000 - dsu0 Aeroflex Gaisler LEON3 Debug Support Unit - AHB: 90000000 - A0000000 - AHB trace: 64 lines, 32-bit bus - CPU0: win 8, hwbp 2, V8 mul/div, lddel 2 - stack pointer 0x200003f0 - icache 2 * 4 kB, 16 B/line rnd - dcache 2 * 4 kB, 16 B/line rnd - ahbram0 Aeroflex Gaisler Single-port AHB SRAM module - AHB: 20000000 - 20100000 - 32-bit static ram: 1 kB @ 0x20000000 - adev5 Aeroflex Gaisler Xilinx MIG DDR3 Controller - AHB: 00000000 - 08000000 - ahbram1 Aeroflex Gaisler Single-port AHB SRAM module - AHB: A0000000 - A0100000 - 32-bit static ram: 1 kB @ 0xa0000000 - uart0 Aeroflex Gaisler Generic UART - APB: 80000100 - 80000200 - IRQ: 2 - Baudrate 38343 - irqmp0 Aeroflex Gaisler Multi-processor Interrupt Ctrl. - APB: 80000200 - 80000300 - gptimer0 Aeroflex Gaisler Modular Timer Unit - APB: 80000300 - 80000400 - IRQ: 8 - 8-bit scalar, 2 * 32-bit timers, divisor 50 - gpio0 Aeroflex Gaisler General Purpose I/O port - APB: 80000A00 - 80000B00 - -grmon2> +jiri@antec:~$ grmon -xilusb -u + + Xilinx cable: Cable type/rev : 0x3 + JTAG chain: xc7x020 zynq7000_arm_dap + + GRLIB build version: 4140 + + initialising ........... + detected frequency: 84 MHz + + Component Vendor + LEON3 SPARC V8 Processor Gaisler Research + AHB Debug JTAG TAP Gaisler Research + AHB ROM Gaisler Research + AHB/APB Bridge Gaisler Research + LEON3 Debug Support Unit Gaisler Research + Xilinx MIG DDR2 controller Gaisler Research + Generic APB UART Gaisler Research + Multi-processor Interrupt Ctrl Gaisler Research + Modular Timer Unit Gaisler Research + General purpose I/O port Gaisler Research + AHB status register Gaisler Research + + Use command 'info sys' to print a detailed report of attached cores + +grlib> info sys +00.01:003 Gaisler Research LEON3 SPARC V8 Processor (ver 0x3) + ahb master 0 +01.01:01c Gaisler Research AHB Debug JTAG TAP (ver 0x2) + ahb master 1 +00.01:01b Gaisler Research AHB ROM (ver 0x0) + ahb: 00000000 - 00100000 +01.01:006 Gaisler Research AHB/APB Bridge (ver 0x0) + ahb: 80000000 - 80100000 +02.01:004 Gaisler Research LEON3 Debug Support Unit (ver 0x1) + ahb: 90000000 - a0000000 + AHB trace 128 lines, 32-bit bus, stack pointer 0x4ffffff0 + CPU#0 win 8, hwbp 1, itrace 128, V8 mul/div, srmmu, lddel 1 + icache 2 * 8 kbyte, 32 byte/line lru + dcache 2 * 4 kbyte, 32 byte/line lru +03.01:06b Gaisler Research Xilinx MIG DDR2 controller (ver 0x0) + ahb: 40000000 - 50000000 + apb: 80000000 - 80000100 + DDR2: 256 Mbyte +01.01:00c Gaisler Research Generic APB UART (ver 0x1) + irq 2 + apb: 80000100 - 80000200 + baud rate 38461, DSU mode (FIFO debug) +02.01:00d Gaisler Research Multi-processor Interrupt Ctrl (ver 0x3) + apb: 80000200 - 80000300 +03.01:011 Gaisler Research Modular Timer Unit (ver 0x0) + irq 8 + apb: 80000300 - 80000400 + 8-bit scaler, 2 * 32-bit timers, divisor 84 +08.01:01a Gaisler Research General purpose I/O port (ver 0x2) + apb: 80000800 - 80000900 +0f.01:052 Gaisler Research AHB status register (ver 0x0) + irq 7 + apb: 80000f00 - 80001000 +grlib> lo ~/examples/dhry412 +section: .text at 0x40000000, size 53296 bytes +section: .data at 0x4000d030, size 2764 bytes +total size: 56060 bytes (1.1 Mbit/s) +read 262 symbols +entry point: 0x40000000 +grlib> run +Execution starts, 1000000 runs through Dhrystone +Total execution time: 4.7 s +Microseconds for one run through Dhrystone: 4.7 +Dhrystones per Second: 214284.1 + +Dhrystones MIPS : 122.0 + + +Program exited normally. +grlib> + + +Problems +-------- + +* The grmon verify command does not work correctly due to some problems + with the JTAG debug interface on Zynq. The load command works correctly + abd programs can be loaded and executed as normal. + diff --git a/designs/leon3-digilent-xc7z020/ahb2axi.vhd b/designs/leon3-digilent-xc7z020/ahb2axi.vhd new file mode 100644 index 00000000..d4a9c214 --- /dev/null +++ b/designs/leon3-digilent-xc7z020/ahb2axi.vhd @@ -0,0 +1,276 @@ +------------------------------------------------------------------------------ +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Entity: ahb2axi +-- File: ahb2axi.vhd +-- Author: Jiri Gaisler +-- +-- AHB/AXI bridge for Zynq S_AXI_GP0 AXI3 slave +------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; + +entity ahb2axi is + generic( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#f00#; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + cidsz : integer := 6; + clensz : integer := 4 + ); + port( + rstn : in std_logic; + clk : in std_logic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + m_axi_araddr : out std_logic_vector ( 31 downto 0 ); + m_axi_arburst : out std_logic_vector ( 1 downto 0 ); + m_axi_arcache : out std_logic_vector ( 3 downto 0 ); + m_axi_arid : out std_logic_vector ( cidsz-1 downto 0 ); + m_axi_arlen : out std_logic_vector ( clensz-1 downto 0 ); + m_axi_arlock : out std_logic_vector (1 downto 0); + m_axi_arprot : out std_logic_vector ( 2 downto 0 ); + m_axi_arqos : out std_logic_vector ( 3 downto 0 ); + m_axi_arready : in std_logic; + m_axi_arsize : out std_logic_vector ( 2 downto 0 ); + m_axi_arvalid : out std_logic; + m_axi_awaddr : out std_logic_vector ( 31 downto 0 ); + m_axi_awburst : out std_logic_vector ( 1 downto 0 ); + m_axi_awcache : out std_logic_vector ( 3 downto 0 ); + m_axi_awid : out std_logic_vector ( cidsz-1 downto 0 ); + m_axi_awlen : out std_logic_vector ( clensz-1 downto 0 ); + m_axi_awlock : out std_logic_vector (1 downto 0); + m_axi_awprot : out std_logic_vector ( 2 downto 0 ); + m_axi_awqos : out std_logic_vector ( 3 downto 0 ); + m_axi_awready : in std_logic; + m_axi_awsize : out std_logic_vector ( 2 downto 0 ); + m_axi_awvalid : out std_logic; + m_axi_bid : in std_logic_vector ( cidsz-1 downto 0 ); + m_axi_bready : out std_logic; + m_axi_bresp : in std_logic_vector ( 1 downto 0 ); + m_axi_bvalid : in std_logic; + m_axi_rdata : in std_logic_vector ( 31 downto 0 ); + m_axi_rid : in std_logic_vector ( cidsz-1 downto 0 ); + m_axi_rlast : in std_logic; + m_axi_rready : out std_logic; + m_axi_rresp : in std_logic_vector ( 1 downto 0 ); + m_axi_rvalid : in std_logic; + m_axi_wdata : out std_logic_vector ( 31 downto 0 ); + m_axi_wid : out std_logic_vector ( cidsz-1 downto 0 ); + m_axi_wlast : out std_logic; + m_axi_wready : in std_logic; + m_axi_wstrb : out std_logic_vector ( 3 downto 0 ); + m_axi_wvalid : out std_logic + ); +end ; + +architecture rtl of ahb2axi is + +type bstate_type is (idle, read1, read2, read3, write1, write2, write3); + +constant hconfig : ahb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0), + 4 => ahb_membar(haddr, '1', '1', hmask), +-- 5 => ahb_iobar(ioaddr, iomask), + others => zero32); + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIGDDR2, 0, 0, 0), + 1 => apb_iobar(paddr, pmask)); + +type reg_type is record + bstate : bstate_type; + hready : std_logic; + hsel : std_logic; + hwrite : std_logic; + htrans : std_logic_vector(1 downto 0); + hburst : std_logic_vector(2 downto 0); + hsize : std_logic_vector(2 downto 0); + hwdata : std_logic_vector(31 downto 0); + haddr : std_logic_vector(31 downto 0); + hmaster : std_logic_vector(3 downto 0); + m_axi_arlen : std_logic_vector (clensz-1 downto 0 ); + m_axi_rdata : std_logic_vector (31 downto 0 ); + m_axi_arvalid : std_logic; + m_axi_awvalid : std_logic; + m_axi_rready : std_logic; + m_axi_wstrb : std_logic_vector (3 downto 0 ); + m_axi_bready : std_logic; + m_axi_wvalid : std_logic; + m_axi_wlast : std_logic; + m_axi_bresp : std_logic_vector (1 downto 0 ); + m_axi_awaddr : std_logic_vector (31 downto 0 ); +end record; + +signal r, rin : reg_type; + +begin + + comb: process( rstn, r, ahbsi, m_axi_arready, m_axi_rlast, m_axi_rvalid, + m_axi_awready, m_axi_wready, m_axi_bvalid, m_axi_bresp, m_axi_rdata ) + variable v : reg_type; + variable hwdata : std_logic_vector(31 downto 0); + variable readdata : std_logic_vector(31 downto 0); + variable wstrb : std_logic_vector (3 downto 0 ); + begin + v := r; + if (ahbsi.hready = '1') then + if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then + v.hsel := '1'; v.hburst := ahbsi.hburst; + v.hwrite := ahbsi.hwrite; v.hsize := ahbsi.hsize; + v.hmaster := ahbsi.hmaster; + v.hready := '0'; + v.haddr := ahbsi.haddr; + if ahbsi.htrans = "10" then + if v.hburst = "000" then v.m_axi_arlen := (others => '0'); + else + v.m_axi_arlen := (others => '0'); + v.m_axi_arlen(2 downto 0) := not ahbsi.haddr(4 downto 2); + end if; + end if; + else + v.hsel := '0'; v.hready := '1'; + end if; + v.htrans := ahbsi.htrans; + end if; + + case r.hsize(1 downto 0) is + when "00" => wstrb := decode(not r.haddr(1 downto 0)); + when "01" => + if r.haddr(1) = '1' then wstrb := "0011"; else wstrb := "1100"; end if; + when others => wstrb := "1111"; + end case; + + case r.bstate is + when idle => + if v.hsel = '1' then + if v.hwrite = '1' then v.bstate := write3; v.hready := '1'; + else v.bstate := read1; v.m_axi_arvalid := '1';end if; + end if; + when read1 => + if m_axi_arready = '1' then + v.m_axi_arvalid := '0'; v.bstate := read2; v.m_axi_rready := '1'; + end if; + when read2 => + v.hready := '0'; + if m_axi_rvalid = '1' then + v.m_axi_rdata := m_axi_rdata; v.hready := '1'; + end if; + if (r.hready = '1') and (ahbsi.htrans /= "11") then + v.bstate := read3; + if v.hsel = '1' then v.hready := '0'; end if; + end if; + if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then + v.bstate := idle; v.m_axi_rready := '0'; + end if; + when read3 => + if (m_axi_rlast = '1') and (m_axi_rvalid = '1') then + v.bstate := idle; v.m_axi_rready := '0'; + end if; + when write1 => + if m_axi_awready = '1' then + v.m_axi_awvalid := '0'; v.bstate := write2; v.m_axi_wvalid := '1'; + v.m_axi_wlast := '1'; + end if; + when write2 => + if m_axi_wready = '1' then + v.m_axi_wlast := '0'; v.bstate := idle; + v.m_axi_wvalid := '0'; v.m_axi_wlast := '0'; + end if; + when write3 => + v.m_axi_awvalid := '1'; + v.m_axi_awaddr := "0001" & r.haddr(27 downto 2) & "00"; + v.m_axi_wstrb := wstrb; v.hwdata := ahbsi.hwdata; + v.bstate := write1; + end case; + + if (m_axi_bvalid = '1') and (r.m_axi_bresp = "00") then v.m_axi_bresp := m_axi_bresp; end if; + readdata := (others => '0'); + readdata(1 downto 0) := r.m_axi_bresp; + + if rstn = '0' then + v.bstate := idle; v.hready := '1'; + v.m_axi_arvalid := '0'; v.m_axi_rready := '0'; + v.m_axi_rready := '0'; v.m_axi_wstrb := (others => '0'); + v.m_axi_bready := '0'; v.m_axi_wvalid := '0'; v.m_axi_wlast := '0'; + v.m_axi_bresp := "00"; v.m_axi_awvalid := '0'; + end if; + + rin <= v; + apbo.prdata <= readdata; + + end process; + + m_axi_araddr <= "0001" & r.haddr(27 downto 2) & "00"; + m_axi_arburst <= "01"; + m_axi_arcache <= "0011"; + m_axi_arid <= (others => '0'); + m_axi_arlen <= r.m_axi_arlen; + m_axi_arlock <= (others => '0'); + m_axi_arprot <= "001"; + m_axi_arsize <= "010"; + m_axi_arvalid <= r.m_axi_arvalid; + m_axi_rready <= r.m_axi_rready; + m_axi_arqos <= (others => '0'); + m_axi_awaddr <= r.m_axi_awaddr; + m_axi_awburst <= "01"; + m_axi_awcache <= "0011"; + m_axi_awid <= (others => '0'); + m_axi_awlen <= (others => '0'); + m_axi_awlock <= (others => '0'); + m_axi_awprot <= "001"; + m_axi_awsize <= "010"; + m_axi_awvalid <= r.m_axi_awvalid; + m_axi_awqos <= (others => '0'); + + m_axi_rready <= r.m_axi_rready; + m_axi_wstrb <= r.m_axi_wstrb; + m_axi_bready <= '1'; + m_axi_wvalid <= r.m_axi_wvalid; + m_axi_wlast <= r.m_axi_wlast; + m_axi_wdata <= r.hwdata; + m_axi_wid <= (others => '0'); + + ahbso.hready <= r.hready; + ahbso.hresp <= "00"; --r.hresp; + ahbso.hrdata <= r.m_axi_rdata; + + ahbso.hconfig <= hconfig; + ahbso.hirq <= (others => '0'); + ahbso.hindex <= hindex; + ahbso.hsplit <= (others => '0'); + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.pirq <= (others => '0'); + + regs : process(clk) + begin + if rising_edge(clk) then + r <= rin; + end if; + end process; + +end; diff --git a/designs/leon3-digilent-xc7z020/ahbrom.vhd b/designs/leon3-digilent-xc7z020/ahbrom.vhd index ac26c7b2..ff4991e9 100644 --- a/designs/leon3-digilent-xc7z020/ahbrom.vhd +++ b/designs/leon3-digilent-xc7z020/ahbrom.vhd @@ -1,7 +1,7 @@ ---------------------------------------------------------------------------- -- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2009 Aeroflex Gaisler +-- Copyright (C) 2010 Aeroflex Gaisler ---------------------------------------------------------------------------- -- Entity: ahbrom -- File: ahbrom.vhd @@ -32,8 +32,8 @@ entity ahbrom is end; architecture rtl of ahbrom is -constant abits : integer := 10; -constant bytes : integer := 560; +constant abits : integer := 9; +constant bytes : integer := 496; constant hconfig : ahb_config_type := ( 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), @@ -139,10 +139,10 @@ begin when 16#00039# => romdata <= X"83480000"; when 16#0003A# => romdata <= X"8330600C"; when 16#0003B# => romdata <= X"80886001"; - when 16#0003C# => romdata <= X"02800024"; + when 16#0003C# => romdata <= X"02800018"; when 16#0003D# => romdata <= X"01000000"; when 16#0003E# => romdata <= X"07000000"; - when 16#0003F# => romdata <= X"8610E178"; + when 16#0003F# => romdata <= X"8610E148"; when 16#00040# => romdata <= X"C108C000"; when 16#00041# => romdata <= X"C118C000"; when 16#00042# => romdata <= X"C518C000"; @@ -159,67 +159,51 @@ begin when 16#0004D# => romdata <= X"F118C000"; when 16#0004E# => romdata <= X"F518C000"; when 16#0004F# => romdata <= X"F918C000"; - when 16#00050# => romdata <= X"FD18C000"; - when 16#00051# => romdata <= X"01000000"; - when 16#00052# => romdata <= X"01000000"; - when 16#00053# => romdata <= X"01000000"; - when 16#00054# => romdata <= X"01000000"; - when 16#00055# => romdata <= X"01000000"; - when 16#00056# => romdata <= X"89A00842"; - when 16#00057# => romdata <= X"01000000"; - when 16#00058# => romdata <= X"01000000"; - when 16#00059# => romdata <= X"01000000"; - when 16#0005A# => romdata <= X"01000000"; - when 16#0005B# => romdata <= X"10800005"; - when 16#0005C# => romdata <= X"01000000"; - when 16#0005D# => romdata <= X"01000000"; - when 16#0005E# => romdata <= X"00000000"; - when 16#0005F# => romdata <= X"00000000"; - when 16#00060# => romdata <= X"87444000"; - when 16#00061# => romdata <= X"8730E01C"; - when 16#00062# => romdata <= X"8688E00F"; - when 16#00063# => romdata <= X"12800015"; - when 16#00064# => romdata <= X"03200000"; - when 16#00065# => romdata <= X"05040E00"; - when 16#00066# => romdata <= X"8410A033"; - when 16#00067# => romdata <= X"C4204000"; - when 16#00068# => romdata <= X"0539AE1B"; - when 16#00069# => romdata <= X"8410A260"; - when 16#0006A# => romdata <= X"C4206004"; - when 16#0006B# => romdata <= X"050003FC"; - when 16#0006C# => romdata <= X"C4206008"; - when 16#0006D# => romdata <= X"82103860"; - when 16#0006E# => romdata <= X"C4004000"; - when 16#0006F# => romdata <= X"8530A00C"; - when 16#00070# => romdata <= X"03000004"; - when 16#00071# => romdata <= X"82106009"; - when 16#00072# => romdata <= X"80A04002"; - when 16#00073# => romdata <= X"12800005"; - when 16#00074# => romdata <= X"03200000"; - when 16#00075# => romdata <= X"0539A81B"; - when 16#00076# => romdata <= X"8410A260"; - when 16#00077# => romdata <= X"C4204000"; - when 16#00078# => romdata <= X"05000080"; - when 16#00079# => romdata <= X"82100000"; - when 16#0007A# => romdata <= X"80A0E000"; - when 16#0007B# => romdata <= X"02800005"; - when 16#0007C# => romdata <= X"01000000"; - when 16#0007D# => romdata <= X"82004002"; - when 16#0007E# => romdata <= X"10BFFFFC"; - when 16#0007F# => romdata <= X"8620E001"; - when 16#00080# => romdata <= X"3D1003FF"; - when 16#00081# => romdata <= X"BC17A3E0"; - when 16#00082# => romdata <= X"BC278001"; - when 16#00083# => romdata <= X"9C27A060"; - when 16#00084# => romdata <= X"03100000"; - when 16#00085# => romdata <= X"81C04000"; - when 16#00086# => romdata <= X"01000000"; - when 16#00087# => romdata <= X"01000000"; - when 16#00088# => romdata <= X"00000000"; - when 16#00089# => romdata <= X"00000000"; - when 16#0008A# => romdata <= X"00000000"; - when 16#0008B# => romdata <= X"00000000"; - when 16#0008C# => romdata <= X"00000000"; + when 16#00050# => romdata <= X"10800004"; + when 16#00051# => romdata <= X"FD18C000"; + when 16#00052# => romdata <= X"00000000"; + when 16#00053# => romdata <= X"00000000"; + when 16#00054# => romdata <= X"87444000"; + when 16#00055# => romdata <= X"8730E01C"; + when 16#00056# => romdata <= X"8688E00F"; + when 16#00057# => romdata <= X"1280000B"; + when 16#00058# => romdata <= X"03200000"; + when 16#00059# => romdata <= X"82106300"; + when 16#0005A# => romdata <= X"84102052"; + when 16#0005B# => romdata <= X"C4206004"; + when 16#0005C# => romdata <= X"C4206000"; + when 16#0005D# => romdata <= X"C0206008"; + when 16#0005E# => romdata <= X"84103FFF"; + when 16#0005F# => romdata <= X"C4206014"; + when 16#00060# => romdata <= X"84102007"; + when 16#00061# => romdata <= X"C4206008"; + when 16#00062# => romdata <= X"05000080"; + when 16#00063# => romdata <= X"82100000"; + when 16#00064# => romdata <= X"80A0E000"; + when 16#00065# => romdata <= X"02800005"; + when 16#00066# => romdata <= X"01000000"; + when 16#00067# => romdata <= X"82004002"; + when 16#00068# => romdata <= X"10BFFFFC"; + when 16#00069# => romdata <= X"8620E001"; + when 16#0006A# => romdata <= X"3D1003FF"; + when 16#0006B# => romdata <= X"BC17A3E0"; + when 16#0006C# => romdata <= X"BC278001"; + when 16#0006D# => romdata <= X"9C27A060"; + when 16#0006E# => romdata <= X"03100000"; + when 16#0006F# => romdata <= X"81C04000"; + when 16#00070# => romdata <= X"01000000"; + when 16#00071# => romdata <= X"01000000"; + when 16#00072# => romdata <= X"01000000"; + when 16#00073# => romdata <= X"01000000"; + when 16#00074# => romdata <= X"01000000"; + when 16#00075# => romdata <= X"01000000"; + when 16#00076# => romdata <= X"01000000"; + when 16#00077# => romdata <= X"01000000"; + when 16#00078# => romdata <= X"00000000"; + when 16#00079# => romdata <= X"00000000"; + when 16#0007A# => romdata <= X"00000000"; + when 16#0007B# => romdata <= X"00000000"; + when 16#0007C# => romdata <= X"00000000"; when others => romdata <= (others => '-'); end case; end process; diff --git a/designs/leon3-digilent-xc7z020/config.h b/designs/leon3-digilent-xc7z020/config.h index dd539279..d59bb473 100644 --- a/designs/leon3-digilent-xc7z020/config.h +++ b/designs/leon3-digilent-xc7z020/config.h @@ -96,19 +96,18 @@ */ #define CONFIG_IU_NWINDOWS (8) #define CONFIG_IU_V8MULDIV 1 -#undef CONFIG_IU_MUL_LATENCY_2 +#define CONFIG_IU_MUL_LATENCY_2 1 #undef CONFIG_IU_MUL_LATENCY_4 -#define CONFIG_IU_MUL_LATENCY_5 1 -#undef CONFIG_IU_MUL_MAC +#undef CONFIG_IU_MUL_LATENCY_5 #define CONFIG_IU_MUL_INFERRED 1 #undef CONFIG_IU_MUL_MODGEN #undef CONFIG_IU_MUL_TECHSPEC #undef CONFIG_IU_MUL_DW #define CONFIG_IU_BP 1 #define CONFIG_IU_SVT 1 -#undef CONFIG_NOTAG -#define CONFIG_IU_LDELAY (2) -#define CONFIG_IU_WATCHPOINTS (2) +#define CONFIG_NOTAG 1 +#define CONFIG_IU_LDELAY (1) +#define CONFIG_IU_WATCHPOINTS (1) #define CONFIG_PWD 1 #define CONFIG_IU_RSTADDR 00000 /* @@ -125,21 +124,20 @@ #undef CONFIG_ICACHE_ASSO4 #undef CONFIG_ICACHE_SZ1 #undef CONFIG_ICACHE_SZ2 -#define CONFIG_ICACHE_SZ4 1 -#undef CONFIG_ICACHE_SZ8 +#undef CONFIG_ICACHE_SZ4 +#define CONFIG_ICACHE_SZ8 1 #undef CONFIG_ICACHE_SZ16 #undef CONFIG_ICACHE_SZ32 #undef CONFIG_ICACHE_SZ64 #undef CONFIG_ICACHE_SZ128 #undef CONFIG_ICACHE_SZ256 -#define CONFIG_ICACHE_LZ16 1 -#undef CONFIG_ICACHE_LZ32 -#define CONFIG_ICACHE_ALGORND 1 +#undef CONFIG_ICACHE_LZ16 +#define CONFIG_ICACHE_LZ32 1 +#undef CONFIG_ICACHE_ALGORND #undef CONFIG_ICACHE_ALGODIR #undef CONFIG_ICACHE_ALGOLRR -#undef CONFIG_ICACHE_ALGOLRU +#define CONFIG_ICACHE_ALGOLRU 1 #undef CONFIG_ICACHE_LOCK -#undef CONFIG_ICACHE_LRAM #define CONFIG_DCACHE_ENABLE 1 #undef CONFIG_DCACHE_ASSO1 #define CONFIG_DCACHE_ASSO2 1 @@ -154,35 +152,56 @@ #undef CONFIG_DCACHE_SZ64 #undef CONFIG_DCACHE_SZ128 #undef CONFIG_DCACHE_SZ256 -#define CONFIG_DCACHE_LZ16 1 -#undef CONFIG_DCACHE_LZ32 -#define CONFIG_DCACHE_ALGORND 1 +#undef CONFIG_DCACHE_LZ16 +#define CONFIG_DCACHE_LZ32 1 +#undef CONFIG_DCACHE_ALGORND #undef CONFIG_DCACHE_ALGODIR #undef CONFIG_DCACHE_ALGOLRR -#undef CONFIG_DCACHE_ALGOLRU +#define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 #define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 -#undef CONFIG_DCACHE_LRAM /* * MMU */ -#undef CONFIG_MMU_ENABLE +#define CONFIG_MMU_ENABLE 1 +#undef CONFIG_MMU_COMBINED +#define CONFIG_MMU_SPLIT 1 +#define CONFIG_MMU_REPARRAY 1 +#undef CONFIG_MMU_REPINCREMENT +#undef CONFIG_MMU_I2 +#undef CONFIG_MMU_I4 +#define CONFIG_MMU_I8 1 +#undef CONFIG_MMU_I16 +#undef CONFIG_MMU_I32 +#undef CONFIG_MMU_I64 +#undef CONFIG_MMU_D2 +#undef CONFIG_MMU_D4 +#define CONFIG_MMU_D8 1 +#undef CONFIG_MMU_D16 +#undef CONFIG_MMU_D32 +#undef CONFIG_MMU_D64 +#define CONFIG_MMU_FASTWB 1 +#define CONFIG_MMU_PAGE_4K 1 +#undef CONFIG_MMU_PAGE_8K +#undef CONFIG_MMU_PAGE_16K +#undef CONFIG_MMU_PAGE_32K +#undef CONFIG_MMU_PAGE_PROG /* * Debug Support Unit */ #define CONFIG_DSU_ENABLE 1 #define CONFIG_DSU_ITRACE 1 -#define CONFIG_DSU_ITRACESZ1 1 -#undef CONFIG_DSU_ITRACESZ2 +#undef CONFIG_DSU_ITRACESZ1 +#define CONFIG_DSU_ITRACESZ2 1 #undef CONFIG_DSU_ITRACESZ4 #undef CONFIG_DSU_ITRACESZ8 #undef CONFIG_DSU_ITRACESZ16 #define CONFIG_DSU_ATRACE 1 -#define CONFIG_DSU_ATRACESZ1 1 -#undef CONFIG_DSU_ATRACESZ2 +#undef CONFIG_DSU_ATRACESZ1 +#define CONFIG_DSU_ATRACESZ2 1 #undef CONFIG_DSU_ATRACESZ4 #undef CONFIG_DSU_ATRACESZ8 #undef CONFIG_DSU_ATRACESZ16 @@ -198,7 +217,7 @@ * AMBA configuration */ #define CONFIG_AHB_DEFMST (0) -#undef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 1 #undef CONFIG_AHB_SPLIT #undef CONFIG_AHB_FPNPEN #define CONFIG_AHB_IOADDR FFF @@ -215,27 +234,15 @@ /* * Memory controller */ -#undef CONFIG_AHBSTAT_ENABLE +#define CONFIG_AHBSTAT_ENABLE 1 +#define CONFIG_AHBSTAT_NFTSLV (1) /* * On-chip RAM/ROM */ -#undef CONFIG_AHBROM_ENABLE -#define CONFIG_AHBRAM_ENABLE 1 -#define CONFIG_AHBRAM_SZ1 1 -#undef CONFIG_AHBRAM_SZ2 -#undef CONFIG_AHBRAM_SZ4 -#undef CONFIG_AHBRAM_SZ8 -#undef CONFIG_AHBRAM_SZ16 -#undef CONFIG_AHBRAM_SZ32 -#undef CONFIG_AHBRAM_SZ64 -#undef CONFIG_AHBRAM_SZ128 -#undef CONFIG_AHBRAM_SZ256 -#undef CONFIG_AHBRAM_SZ512 -#undef CONFIG_AHBRAM_SZ1024 -#undef CONFIG_AHBRAM_SZ2048 -#undef CONFIG_AHBRAM_SZ4096 -#define CONFIG_AHBRAM_START A00 -#undef CONFIG_AHBRAM_PIPE +#define CONFIG_AHBROM_ENABLE 1 +#define CONFIG_AHBROM_START 000 +#define CONFIG_AHBROM_PIPE 1 +#undef CONFIG_AHBRAM_ENABLE /* * UARTs, timers and irq control */ @@ -253,7 +260,7 @@ #define CONFIG_GPT_SW (8) #define CONFIG_GPT_TW (32) #define CONFIG_GPT_IRQ (8) -#undef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 1 #undef CONFIG_GPT_WDOGEN #define CONFIG_GRGPIO_ENABLE 1 #define CONFIG_GRGPIO_WIDTH (16) diff --git a/designs/leon3-digilent-xc7z020/config.vhd b/designs/leon3-digilent-xc7z020/config.vhd index 1cf89a42..fda8176d 100644 --- a/designs/leon3-digilent-xc7z020/config.vhd +++ b/designs/leon3-digilent-xc7z020/config.vhd @@ -33,22 +33,22 @@ package config is constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); - constant CFG_V8 : integer := 2 + 4*0; + constant CFG_V8 : integer := 16#32# + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; - constant CFG_LDDEL : integer := (2); - constant CFG_NOTAG : integer := 0; - constant CFG_NWP : integer := (2); + constant CFG_LDDEL : integer := (1); + constant CFG_NOTAG : integer := 1; + constant CFG_NWP : integer := (1); constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; constant CFG_ISETS : integer := 2; - constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 4; - constant CFG_IREPL : integer := 2; + constant CFG_ISETSZ : integer := 8; + constant CFG_ILINE : integer := 8; + constant CFG_IREPL : integer := 0; constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; @@ -56,23 +56,23 @@ package config is constant CFG_DCEN : integer := 1; constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 4; - constant CFG_DREPL : integer := 2; + constant CFG_DLINE : integer := 8; + constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; constant CFG_DSNOOP : integer := 1 + 1 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; constant CFG_DLRAMSZ : integer := 1; - constant CFG_MMUEN : integer := 0; - constant CFG_ITLBNUM : integer := 2; - constant CFG_DTLBNUM : integer := 2; - constant CFG_TLB_TYPE : integer := 1 + 0*2; - constant CFG_TLB_REP : integer := 1; + constant CFG_MMUEN : integer := 1; + constant CFG_ITLBNUM : integer := 8; + constant CFG_DTLBNUM : integer := 8; + constant CFG_TLB_TYPE : integer := 0 + 1*2; + constant CFG_TLB_REP : integer := 0; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 1; - constant CFG_ATBSZ : integer := 1; + constant CFG_ITBSZ : integer := 2; + constant CFG_ATBSZ : integer := 2; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; @@ -84,7 +84,7 @@ package config is constant CFG_PCLOW : integer := 2; -- AMBA settings constant CFG_DEFMST : integer := (0); - constant CFG_RROBIN : integer := 0; + constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; constant CFG_FPNPEN : integer := 0; constant CFG_AHBIO : integer := 16#FFF#; @@ -103,16 +103,16 @@ package config is constant CFG_ETH_ENM : integer := 16#020000#; constant CFG_ETH_ENL : integer := 16#000009#; -- AHB status register - constant CFG_AHBSTAT : integer := 0; - constant CFG_AHBSTATN : integer := 1; + constant CFG_AHBSTAT : integer := 1; + constant CFG_AHBSTATN : integer := (1); -- AHB ROM - constant CFG_AHBROMEN : integer := 0; - constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBROMEN : integer := 1; + constant CFG_AHBROPIP : integer := 1; constant CFG_AHBRODDR : integer := 16#000#; - constant CFG_ROMADDR : integer := 16#000#; - constant CFG_ROMMASK : integer := 16#E00# + 16#000#; + constant CFG_ROMADDR : integer := 16#100#; + constant CFG_ROMMASK : integer := 16#E00# + 16#100#; -- AHB RAM - constant CFG_AHBRAMEN : integer := 1; + constant CFG_AHBRAMEN : integer := 0; constant CFG_AHBRSZ : integer := 1; constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; @@ -128,7 +128,7 @@ package config is constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); - constant CFG_GPT_SEPIRQ : integer := 0; + constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; -- GPIO port diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/__xps/ise/_xmsgs/.gitignore b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/__xps/ise/_xmsgs/.gitignore deleted file mode 100644 index e69de29b..00000000 diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/__xps/ise/xmsgprops.lst b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/__xps/ise/xmsgprops.lst deleted file mode 100644 index d79c9360..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/__xps/ise/xmsgprops.lst +++ /dev/null @@ -1,3 +0,0 @@ -MessageCaptureEnabled: TRUE -MessageFilteringEnabled: FALSE -IncrementalMessagingEnabled: TRUE diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.ncf b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.ncf deleted file mode 100644 index 1d25821e..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.ncf +++ /dev/null @@ -1,8 +0,0 @@ -# -# pin constraints -# - -# -# additional constraints -# - diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.ucf b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.ucf deleted file mode 100644 index 1d25821e..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.ucf +++ /dev/null @@ -1,8 +0,0 @@ -# -# pin constraints -# - -# -# additional constraints -# - diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.xdc b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.xdc deleted file mode 100644 index 1d25821e..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/leon3_zedboard.xdc +++ /dev/null @@ -1,8 +0,0 @@ -# -# pin constraints -# - -# -# additional constraints -# - diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_constraints.ucf b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_constraints.ucf deleted file mode 100644 index 971c138d..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_constraints.ucf +++ /dev/null @@ -1,94 +0,0 @@ -############################################################################ -## -## Xilinx, Inc. 2006 www.xilinx.com -############################################################################ -## File name : data/ps7_constraints.ucf -## -## Details : Constraints file -## FPGA family: zynq -## FPGA: xc7z020clg484-1 -## Device Size: xc7z020 -## Package: clg484 -## Speedgrade: -1 -## -##Note: This is a generated file. Configuration settings should not be edited -## -############################################################################ -############################################################################ -############################################################################ -# I/O STANDARDS and Location Constraints # -############################################################################ - -NET "DDR_WEB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "R4" ; -NET "DDR_VRP" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N7" ; -NET "DDR_VRN" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M7" ; -NET "DDR_RAS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "R5" ; -NET "DDR_ODT" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P5" ; -NET "DDR_DRSTB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F3" ; -NET "DDR_DQS[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "V2" ; -NET "DDR_DQS[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "N2" ; -NET "DDR_DQS[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "H2" ; -NET "DDR_DQS[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C2" ; -NET "DDR_DQS_n[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W2" ; -NET "DDR_DQS_n[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "P2" ; -NET "DDR_DQS_n[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "J2" ; -NET "DDR_DQS_n[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "D2" ; -NET "DDR_DQ[9]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G1" ; -NET "DDR_DQ[8]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G2" ; -NET "DDR_DQ[7]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F1" ; -NET "DDR_DQ[6]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F2" ; -NET "DDR_DQ[5]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E1" ; -NET "DDR_DQ[4]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E3" ; -NET "DDR_DQ[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D3" ; -NET "DDR_DQ[31]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y1" ; -NET "DDR_DQ[30]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W3" ; -NET "DDR_DQ[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B2" ; -NET "DDR_DQ[29]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y3" ; -NET "DDR_DQ[28]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W1" ; -NET "DDR_DQ[27]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U2" ; -NET "DDR_DQ[26]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA1" ; -NET "DDR_DQ[25]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U1" ; -NET "DDR_DQ[24]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA3" ; -NET "DDR_DQ[23]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R1" ; -NET "DDR_DQ[22]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M2" ; -NET "DDR_DQ[21]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T2" ; -NET "DDR_DQ[20]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R3" ; -NET "DDR_DQ[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C3" ; -NET "DDR_DQ[19]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T1" ; -NET "DDR_DQ[18]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N3" ; -NET "DDR_DQ[17]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T3" ; -NET "DDR_DQ[16]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M1" ; -NET "DDR_DQ[15]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K3" ; -NET "DDR_DQ[14]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J1" ; -NET "DDR_DQ[13]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K1" ; -NET "DDR_DQ[12]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L3" ; -NET "DDR_DQ[11]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L2" ; -NET "DDR_DQ[10]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L1" ; -NET "DDR_DQ[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D1" ; -NET "DDR_DM[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA2" ; -NET "DDR_DM[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P1" ; -NET "DDR_DM[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H3" ; -NET "DDR_DM[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B1" ; -NET "DDR_CS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P6" ; -NET "DDR_CKE" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "V3" ; -NET "DDR_Clk" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "N4" ; -NET "DDR_Clk_n" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "N5" ; -NET "DDR_CAS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P3" ; -NET "DDR_BankAddr[2]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M6" ; -NET "DDR_BankAddr[1]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L6" ; -NET "DDR_BankAddr[0]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L7" ; -NET "DDR_Addr[9]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H5" ; -NET "DDR_Addr[8]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J5" ; -NET "DDR_Addr[7]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J6" ; -NET "DDR_Addr[6]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J7" ; -NET "DDR_Addr[5]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K5" ; -NET "DDR_Addr[4]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K6" ; -NET "DDR_Addr[3]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L4" ; -NET "DDR_Addr[2]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K4" ; -NET "DDR_Addr[1]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M5" ; -NET "DDR_Addr[14]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G4" ; -NET "DDR_Addr[13]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F4" ; -NET "DDR_Addr[12]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H4" ; -NET "DDR_Addr[11]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G5" ; -NET "DDR_Addr[10]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J3" ; -NET "DDR_Addr[0]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M4" ; diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_constraints.xdc b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_constraints.xdc deleted file mode 100644 index ea7e65b8..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_constraints.xdc +++ /dev/null @@ -1,240 +0,0 @@ -############################################################################ -## -## Xilinx, Inc. 2006 www.xilinx.com -############################################################################ -## File name : data/ps7_constraints.xdc -## -## Details : Constraints file -## FPGA family: zynq -## FPGA: xc7z020clg484-1 -## Device Size: xc7z020 -## Package: clg484 -## Speedgrade: -1 -## -##Note: This is a generated file. Configuration settings should not be edited -## -############################################################################ -############################################################################ -############################################################################ -# I/O STANDARDS and Location Constraints # -############################################################################ - -set_property iostandard "SSTL15" [get_ports "DDR_WEB"] -set_property PACKAGE_PIN "R4" [get_ports "DDR_WEB"] -set_property slew "FAST" [get_ports "DDR_WEB"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"] -set_property PACKAGE_PIN "N7" [get_ports "DDR_VRP"] -set_property slew "FAST" [get_ports "DDR_VRP"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"] -set_property PACKAGE_PIN "M7" [get_ports "DDR_VRN"] -set_property slew "FAST" [get_ports "DDR_VRN"] -set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"] -set_property PACKAGE_PIN "R5" [get_ports "DDR_RAS_n"] -set_property slew "FAST" [get_ports "DDR_RAS_n"] -set_property iostandard "SSTL15" [get_ports "DDR_ODT"] -set_property PACKAGE_PIN "P5" [get_ports "DDR_ODT"] -set_property slew "FAST" [get_ports "DDR_ODT"] -set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"] -set_property PACKAGE_PIN "F3" [get_ports "DDR_DRSTB"] -set_property slew "FAST" [get_ports "DDR_DRSTB"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"] -set_property PACKAGE_PIN "V2" [get_ports "DDR_DQS[3]"] -set_property slew "FAST" [get_ports "DDR_DQS[3]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"] -set_property PACKAGE_PIN "N2" [get_ports "DDR_DQS[2]"] -set_property slew "FAST" [get_ports "DDR_DQS[2]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"] -set_property PACKAGE_PIN "H2" [get_ports "DDR_DQS[1]"] -set_property slew "FAST" [get_ports "DDR_DQS[1]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"] -set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"] -set_property slew "FAST" [get_ports "DDR_DQS[0]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"] -set_property PACKAGE_PIN "W2" [get_ports "DDR_DQS_n[3]"] -set_property slew "FAST" [get_ports "DDR_DQS_n[3]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"] -set_property PACKAGE_PIN "P2" [get_ports "DDR_DQS_n[2]"] -set_property slew "FAST" [get_ports "DDR_DQS_n[2]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"] -set_property PACKAGE_PIN "J2" [get_ports "DDR_DQS_n[1]"] -set_property slew "FAST" [get_ports "DDR_DQS_n[1]"] -set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"] -set_property PACKAGE_PIN "D2" [get_ports "DDR_DQS_n[0]"] -set_property slew "FAST" [get_ports "DDR_DQS_n[0]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"] -set_property PACKAGE_PIN "G1" [get_ports "DDR_DQ[9]"] -set_property slew "FAST" [get_ports "DDR_DQ[9]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"] -set_property PACKAGE_PIN "G2" [get_ports "DDR_DQ[8]"] -set_property slew "FAST" [get_ports "DDR_DQ[8]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"] -set_property PACKAGE_PIN "F1" [get_ports "DDR_DQ[7]"] -set_property slew "FAST" [get_ports "DDR_DQ[7]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"] -set_property PACKAGE_PIN "F2" [get_ports "DDR_DQ[6]"] -set_property slew "FAST" [get_ports "DDR_DQ[6]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"] -set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[5]"] -set_property slew "FAST" [get_ports "DDR_DQ[5]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"] -set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[4]"] -set_property slew "FAST" [get_ports "DDR_DQ[4]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"] -set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[3]"] -set_property slew "FAST" [get_ports "DDR_DQ[3]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"] -set_property PACKAGE_PIN "Y1" [get_ports "DDR_DQ[31]"] -set_property slew "FAST" [get_ports "DDR_DQ[31]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"] -set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[30]"] -set_property slew "FAST" [get_ports "DDR_DQ[30]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"] -set_property PACKAGE_PIN "B2" [get_ports "DDR_DQ[2]"] -set_property slew "FAST" [get_ports "DDR_DQ[2]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"] -set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[29]"] -set_property slew "FAST" [get_ports "DDR_DQ[29]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"] -set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[28]"] -set_property slew "FAST" [get_ports "DDR_DQ[28]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"] -set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[27]"] -set_property slew "FAST" [get_ports "DDR_DQ[27]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"] -set_property PACKAGE_PIN "AA1" [get_ports "DDR_DQ[26]"] -set_property slew "FAST" [get_ports "DDR_DQ[26]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"] -set_property PACKAGE_PIN "U1" [get_ports "DDR_DQ[25]"] -set_property slew "FAST" [get_ports "DDR_DQ[25]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"] -set_property PACKAGE_PIN "AA3" [get_ports "DDR_DQ[24]"] -set_property slew "FAST" [get_ports "DDR_DQ[24]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"] -set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[23]"] -set_property slew "FAST" [get_ports "DDR_DQ[23]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"] -set_property PACKAGE_PIN "M2" [get_ports "DDR_DQ[22]"] -set_property slew "FAST" [get_ports "DDR_DQ[22]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"] -set_property PACKAGE_PIN "T2" [get_ports "DDR_DQ[21]"] -set_property slew "FAST" [get_ports "DDR_DQ[21]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"] -set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[20]"] -set_property slew "FAST" [get_ports "DDR_DQ[20]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"] -set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[1]"] -set_property slew "FAST" [get_ports "DDR_DQ[1]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"] -set_property PACKAGE_PIN "T1" [get_ports "DDR_DQ[19]"] -set_property slew "FAST" [get_ports "DDR_DQ[19]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"] -set_property PACKAGE_PIN "N3" [get_ports "DDR_DQ[18]"] -set_property slew "FAST" [get_ports "DDR_DQ[18]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"] -set_property PACKAGE_PIN "T3" [get_ports "DDR_DQ[17]"] -set_property slew "FAST" [get_ports "DDR_DQ[17]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"] -set_property PACKAGE_PIN "M1" [get_ports "DDR_DQ[16]"] -set_property slew "FAST" [get_ports "DDR_DQ[16]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"] -set_property PACKAGE_PIN "K3" [get_ports "DDR_DQ[15]"] -set_property slew "FAST" [get_ports "DDR_DQ[15]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"] -set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[14]"] -set_property slew "FAST" [get_ports "DDR_DQ[14]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"] -set_property PACKAGE_PIN "K1" [get_ports "DDR_DQ[13]"] -set_property slew "FAST" [get_ports "DDR_DQ[13]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"] -set_property PACKAGE_PIN "L3" [get_ports "DDR_DQ[12]"] -set_property slew "FAST" [get_ports "DDR_DQ[12]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"] -set_property PACKAGE_PIN "L2" [get_ports "DDR_DQ[11]"] -set_property slew "FAST" [get_ports "DDR_DQ[11]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"] -set_property PACKAGE_PIN "L1" [get_ports "DDR_DQ[10]"] -set_property slew "FAST" [get_ports "DDR_DQ[10]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"] -set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[0]"] -set_property slew "FAST" [get_ports "DDR_DQ[0]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"] -set_property PACKAGE_PIN "AA2" [get_ports "DDR_DM[3]"] -set_property slew "FAST" [get_ports "DDR_DM[3]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"] -set_property PACKAGE_PIN "P1" [get_ports "DDR_DM[2]"] -set_property slew "FAST" [get_ports "DDR_DM[2]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"] -set_property PACKAGE_PIN "H3" [get_ports "DDR_DM[1]"] -set_property slew "FAST" [get_ports "DDR_DM[1]"] -set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"] -set_property PACKAGE_PIN "B1" [get_ports "DDR_DM[0]"] -set_property slew "FAST" [get_ports "DDR_DM[0]"] -set_property iostandard "SSTL15" [get_ports "DDR_CS_n"] -set_property PACKAGE_PIN "P6" [get_ports "DDR_CS_n"] -set_property slew "FAST" [get_ports "DDR_CS_n"] -set_property iostandard "SSTL15" [get_ports "DDR_CKE"] -set_property PACKAGE_PIN "V3" [get_ports "DDR_CKE"] -set_property slew "FAST" [get_ports "DDR_CKE"] -set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"] -set_property PACKAGE_PIN "N4" [get_ports "DDR_Clk"] -set_property slew "FAST" [get_ports "DDR_Clk"] -set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"] -set_property PACKAGE_PIN "N5" [get_ports "DDR_Clk_n"] -set_property slew "FAST" [get_ports "DDR_Clk_n"] -set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"] -set_property PACKAGE_PIN "P3" [get_ports "DDR_CAS_n"] -set_property slew "FAST" [get_ports "DDR_CAS_n"] -set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"] -set_property PACKAGE_PIN "M6" [get_ports "DDR_BankAddr[2]"] -set_property slew "FAST" [get_ports "DDR_BankAddr[2]"] -set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"] -set_property PACKAGE_PIN "L6" [get_ports "DDR_BankAddr[1]"] -set_property slew "FAST" [get_ports "DDR_BankAddr[1]"] -set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"] -set_property PACKAGE_PIN "L7" [get_ports "DDR_BankAddr[0]"] -set_property slew "FAST" [get_ports "DDR_BankAddr[0]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"] -set_property PACKAGE_PIN "H5" [get_ports "DDR_Addr[9]"] -set_property slew "FAST" [get_ports "DDR_Addr[9]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"] -set_property PACKAGE_PIN "J5" [get_ports "DDR_Addr[8]"] -set_property slew "FAST" [get_ports "DDR_Addr[8]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"] -set_property PACKAGE_PIN "J6" [get_ports "DDR_Addr[7]"] -set_property slew "FAST" [get_ports "DDR_Addr[7]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"] -set_property PACKAGE_PIN "J7" [get_ports "DDR_Addr[6]"] -set_property slew "FAST" [get_ports "DDR_Addr[6]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"] -set_property PACKAGE_PIN "K5" [get_ports "DDR_Addr[5]"] -set_property slew "FAST" [get_ports "DDR_Addr[5]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"] -set_property PACKAGE_PIN "K6" [get_ports "DDR_Addr[4]"] -set_property slew "FAST" [get_ports "DDR_Addr[4]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"] -set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[3]"] -set_property slew "FAST" [get_ports "DDR_Addr[3]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"] -set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[2]"] -set_property slew "FAST" [get_ports "DDR_Addr[2]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"] -set_property PACKAGE_PIN "M5" [get_ports "DDR_Addr[1]"] -set_property slew "FAST" [get_ports "DDR_Addr[1]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"] -set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[14]"] -set_property slew "FAST" [get_ports "DDR_Addr[14]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"] -set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[13]"] -set_property slew "FAST" [get_ports "DDR_Addr[13]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"] -set_property PACKAGE_PIN "H4" [get_ports "DDR_Addr[12]"] -set_property slew "FAST" [get_ports "DDR_Addr[12]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"] -set_property PACKAGE_PIN "G5" [get_ports "DDR_Addr[11]"] -set_property slew "FAST" [get_ports "DDR_Addr[11]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"] -set_property PACKAGE_PIN "J3" [get_ports "DDR_Addr[10]"] -set_property slew "FAST" [get_ports "DDR_Addr[10]"] -set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"] -set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[0]"] -set_property slew "FAST" [get_ports "DDR_Addr[0]"] diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_leon3_zedboard_prj.xml b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_leon3_zedboard_prj.xml deleted file mode 100644 index f9332b59..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/data/ps7_leon3_zedboard_prj.xml +++ /dev/null @@ -1,87 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/bitgen.ut b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/bitgen.ut deleted file mode 100644 index 1f1bbbe8..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/bitgen.ut +++ /dev/null @@ -1 +0,0 @@ -##bitgen options for zynq architecture diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/download.cmd b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/download.cmd deleted file mode 100644 index 02228c1a..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/download.cmd +++ /dev/null @@ -1,6 +0,0 @@ -setMode -bscan -setCable -p auto -identify -assignfile -p 2 -file implementation/download.bit -program -p 2 -quit diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/fast_runtime.opt b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/fast_runtime.opt deleted file mode 100644 index 994a6d2f..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/fast_runtime.opt +++ /dev/null @@ -1,84 +0,0 @@ -FLOWTYPE = FPGA; -############################################################### -## Filename: fast_runtime.opt -## -## Option File For Xilinx FPGA Implementation Flow for Fast -## Runtime. -## -## Version: 4.1.1 -############################################################### -# -# Options for Translator -# -# Type "ngdbuild -h" for a detailed list of ngdbuild command line options -# -Program ngdbuild --p ; # Partname to use - picked from xflow commandline --nt timestamp; # NGO File generation. Regenerate only when - # source netlist is newer than existing - # NGO file (default) --bm .bmm # Block RAM memory map file -; # User design - pick from xflow command line --uc .ucf; # ucf constraints -.ngd; # Name of NGD file. Filebase same as design filebase -End Program ngdbuild - -# -# Options for Mapper -# -# Type "map -h " for a detailed list of map command line options -# -Program map --o _map.ncd; # Output Mapped ncd file --w; # Overwrite output files. --pr b; # Pack internal FF/latches into IOBs -#-fp .mfp; # Floorplan file --ol high; --timing; --detail; -.ngd; # Input NGD file -.pcf; # Physical constraints file -END Program map - -# -# Options for Post Map Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_map_trce --e 3; # Produce error report limited to 3 items per constraint -#-o _map.twr; # Output trace report file --xml _map.twx; # Output XML version of the timing report -#-tsi _map.tsi; # Produce Timing Specification Interaction report -_map.ncd; # Input mapped ncd -.pcf; # Physical constraints file -END Program post_map_trce - -# -# Options for Place and Route -# -# Type "par -h" for a detailed list of par command line options -# -Program par --w; # Overwrite existing placed and routed ncd --ol high; # Overall effort level -_map.ncd; # Input mapped NCD file -.ncd; # Output placed and routed NCD -.pcf; # Input physical constraints file -END Program par - -# -# Options for Post Par Trace -# -# Type "trce -h" for a detailed list of trce command line options -# -Program post_par_trce --e 3; # Produce error report limited to 3 items per constraint -#-o .twr; # Output trace report file --xml .twx; # Output XML version of the timing report -#-tsi .tsi; # Produce Timing Specification Interaction report -.ncd; # Input placed and routed ncd -.pcf; # Physical constraints file -END Program post_par_trce - - diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/leon3_zedboard.filters b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/leon3_zedboard.filters deleted file mode 100644 index 63cea3a8..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/leon3_zedboard.filters +++ /dev/null @@ -1,147 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/leon3_zedboard.gui b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/leon3_zedboard.gui deleted file mode 100644 index af84db94..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/etc/leon3_zedboard.gui +++ /dev/null @@ -1,204 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ No newline at end of file diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/leon3_zedboard.mhs b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/leon3_zedboard.mhs deleted file mode 100644 index 0d9f334b..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/leon3_zedboard.mhs +++ /dev/null @@ -1,175 +0,0 @@ - -# ############################################################################## -# Created by Base System Builder Wizard for Xilinx EDK 14.3 Build EDK_P.40xd -# Fri Dec 7 08:24:42 2012 -# Target Board: em.avnet.com ZedBoard Rev C -# Family: zynq -# Device: xc7z020 -# Package: clg484 -# Speed Grade: -1 -# ############################################################################## - PARAMETER VERSION = 2.1.0 - - - PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0] - PORT processing_system7_0_PS_SRSTB = processing_system7_0_PS_SRSTB, DIR = I - PORT processing_system7_0_PS_CLK = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK - PORT processing_system7_0_PS_PORB = processing_system7_0_PS_PORB, DIR = I - PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK - PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK - PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO - PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO - PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO - PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO - PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O - PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0] - PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0] - PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO - PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST - PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0] - PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0] - PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0] - PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0] - PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO - PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO - PORT ahblite_axi_bridge_0_S_AHB_HSEL_pin = ahblite_axi_bridge_0_S_AHB_HSEL, DIR = I - PORT ahblite_axi_bridge_0_S_AHB_HADDR_pin = ahblite_axi_bridge_0_S_AHB_HADDR, DIR = I, VEC = [31:0] - PORT ahblite_axi_bridge_0_S_AHB_HPROT_pin = ahblite_axi_bridge_0_S_AHB_HPROT, DIR = I, VEC = [3:0] - PORT ahblite_axi_bridge_0_S_AHB_HTRANS_pin = ahblite_axi_bridge_0_S_AHB_HTRANS, DIR = I, VEC = [1:0] - PORT ahblite_axi_bridge_0_S_AHB_HSIZE_pin = ahblite_axi_bridge_0_S_AHB_HSIZE, DIR = I, VEC = [2:0] - PORT ahblite_axi_bridge_0_S_AHB_HWRITE_pin = ahblite_axi_bridge_0_S_AHB_HWRITE, DIR = I - PORT ahblite_axi_bridge_0_S_AHB_HBURST_pin = ahblite_axi_bridge_0_S_AHB_HBURST, DIR = I, VEC = [2:0] - PORT ahblite_axi_bridge_0_S_AHB_HWDATA_pin = ahblite_axi_bridge_0_S_AHB_HWDATA, DIR = I, VEC = [31:0] - PORT ahblite_axi_bridge_0_S_AHB_HREADY_OUT_pin = ahblite_axi_bridge_0_S_AHB_HREADY_OUT, DIR = O - PORT ahblite_axi_bridge_0_S_AHB_HREADY_IN_pin = ahblite_axi_bridge_0_S_AHB_HREADY_IN, DIR = I - PORT ahblite_axi_bridge_0_S_AHB_HRDATA_pin = ahblite_axi_bridge_0_S_AHB_HRDATA, DIR = O, VEC = [31:0] - PORT ahblite_axi_bridge_0_S_AHB_HRESP_pin = ahblite_axi_bridge_0_S_AHB_HRESP, DIR = O - PORT processing_system7_0_FCLK_RESET0_N_pin = processing_system7_0_FCLK_RESET0_N, DIR = O, SIGIS = RST - PORT processing_system7_0_FCLK_CLKTRIG0_N_pin = processing_system7_0_FCLK_CLKTRIG0_N, DIR = I - PORT processing_system7_0_FCLK_CLK0_pin = processing_system7_0_FCLK_CLK0, DIR = O, SIGIS = CLK, CLK_FREQ = 50000000 - - -BEGIN processing_system7 - PARAMETER INSTANCE = processing_system7_0 - PARAMETER HW_VER = 4.02.a - PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF - PARAMETER C_USE_M_AXI_GP0 = 0 - PARAMETER C_EN_EMIO_CAN0 = 0 - PARAMETER C_EN_EMIO_CAN1 = 0 - PARAMETER C_EN_EMIO_ENET0 = 0 - PARAMETER C_EN_EMIO_ENET1 = 0 - PARAMETER C_EN_EMIO_I2C0 = 0 - PARAMETER C_EN_EMIO_I2C1 = 0 - PARAMETER C_EN_EMIO_PJTAG = 0 - PARAMETER C_EN_EMIO_SDIO0 = 0 - PARAMETER C_EN_EMIO_CD_SDIO0 = 0 - PARAMETER C_EN_EMIO_WP_SDIO0 = 0 - PARAMETER C_EN_EMIO_SDIO1 = 0 - PARAMETER C_EN_EMIO_CD_SDIO1 = 0 - PARAMETER C_EN_EMIO_WP_SDIO1 = 0 - PARAMETER C_EN_EMIO_SPI0 = 0 - PARAMETER C_EN_EMIO_SPI1 = 0 - PARAMETER C_EN_EMIO_SRAM_INT = 0 - PARAMETER C_EN_EMIO_TRACE = 0 - PARAMETER C_EN_EMIO_TTC0 = 0 - PARAMETER C_EN_EMIO_TTC1 = 0 - PARAMETER C_EN_EMIO_UART0 = 0 - PARAMETER C_EN_EMIO_UART1 = 0 - PARAMETER C_EN_EMIO_MODEM_UART0 = 0 - PARAMETER C_EN_EMIO_MODEM_UART1 = 0 - PARAMETER C_EN_EMIO_WDT = 0 - PARAMETER C_EN_QSPI = 0 - PARAMETER C_EN_SMC = 0 - PARAMETER C_EN_CAN0 = 0 - PARAMETER C_EN_CAN1 = 0 - PARAMETER C_EN_ENET0 = 0 - PARAMETER C_EN_ENET1 = 0 - PARAMETER C_EN_I2C0 = 0 - PARAMETER C_EN_I2C1 = 0 - PARAMETER C_EN_PJTAG = 0 - PARAMETER C_EN_SDIO0 = 0 - PARAMETER C_EN_SDIO1 = 0 - PARAMETER C_EN_SPI0 = 0 - PARAMETER C_EN_SPI1 = 0 - PARAMETER C_EN_TRACE = 0 - PARAMETER C_EN_TTC0 = 0 - PARAMETER C_EN_TTC1 = 0 - PARAMETER C_EN_UART0 = 0 - PARAMETER C_EN_UART1 = 0 - PARAMETER C_EN_MODEM_UART0 = 0 - PARAMETER C_EN_MODEM_UART1 = 0 - PARAMETER C_EN_USB0 = 0 - PARAMETER C_EN_USB1 = 0 - PARAMETER C_EN_WDT = 0 - PARAMETER C_EN_DDR = 1 - PARAMETER C_EN_GPIO = 0 - PARAMETER C_FCLK_CLK0_FREQ = 50000000 - PARAMETER C_FCLK_CLK1_FREQ = 50000000 - PARAMETER C_FCLK_CLK2_FREQ = 50000000 - PARAMETER C_FCLK_CLK3_FREQ = 50000000 - PARAMETER C_USE_FABRIC_INTERRUPT = 0 - PARAMETER C_USE_S_AXI_GP0 = 0 - PARAMETER C_USE_S_AXI_HP0 = 1 - PARAMETER C_S_AXI_HP0_DATA_WIDTH = 32 - PARAMETER C_USE_CR_FABRIC = 1 - PARAMETER C_INTERCONNECT_S_AXI_GP0_MASTERS = ahblite_axi_bridge_0.M_AXI - PARAMETER C_EN_EMIO_GPIO = 0 - PARAMETER C_EMIO_GPIO_WIDTH = 64 - PARAMETER C_INTERCONNECT_S_AXI_HP0_MASTERS = ahblite_axi_bridge_0.M_AXI - BUS_INTERFACE S_AXI_HP0 = axi_interconnect_0 - PORT MIO = processing_system7_0_MIO - PORT PS_SRSTB = processing_system7_0_PS_SRSTB - PORT PS_CLK = processing_system7_0_PS_CLK - PORT PS_PORB = processing_system7_0_PS_PORB - PORT DDR_Clk = processing_system7_0_DDR_Clk - PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n - PORT DDR_CKE = processing_system7_0_DDR_CKE - PORT DDR_CS_n = processing_system7_0_DDR_CS_n - PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n - PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n - PORT DDR_WEB = processing_system7_0_DDR_WEB - PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr - PORT DDR_Addr = processing_system7_0_DDR_Addr - PORT DDR_ODT = processing_system7_0_DDR_ODT - PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB - PORT DDR_DQ = processing_system7_0_DDR_DQ - PORT DDR_DM = processing_system7_0_DDR_DM - PORT DDR_DQS = processing_system7_0_DDR_DQS - PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n - PORT DDR_VRN = processing_system7_0_DDR_VRN - PORT DDR_VRP = processing_system7_0_DDR_VRP - PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0 - PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N - PORT S_AXI_HP0_ACLK = processing_system7_0_FCLK_CLK0 - PORT FCLK_CLKTRIG0_N = processing_system7_0_FCLK_CLKTRIG0_N -END - -BEGIN ahblite_axi_bridge - PARAMETER INSTANCE = ahblite_axi_bridge_0 - PARAMETER HW_VER = 1.00.a - PARAMETER C_AHB_AXI_TIMEOUT = 0 - PARAMETER C_BASEADDR = 0x6c000000 - PARAMETER C_HIGHADDR = 0x6c00ffff - BUS_INTERFACE M_AXI = axi_interconnect_0 - PORT S_AHB_HCLK = processing_system7_0_FCLK_CLK0 - PORT S_AHB_HSEL = ahblite_axi_bridge_0_S_AHB_HSEL - PORT S_AHB_HADDR = ahblite_axi_bridge_0_S_AHB_HADDR - PORT S_AHB_HPROT = ahblite_axi_bridge_0_S_AHB_HPROT - PORT S_AHB_HTRANS = ahblite_axi_bridge_0_S_AHB_HTRANS - PORT S_AHB_HSIZE = ahblite_axi_bridge_0_S_AHB_HSIZE - PORT S_AHB_HWRITE = ahblite_axi_bridge_0_S_AHB_HWRITE - PORT S_AHB_HBURST = ahblite_axi_bridge_0_S_AHB_HBURST - PORT S_AHB_HWDATA = ahblite_axi_bridge_0_S_AHB_HWDATA - PORT S_AHB_HREADY_OUT = ahblite_axi_bridge_0_S_AHB_HREADY_OUT - PORT S_AHB_HREADY_IN = ahblite_axi_bridge_0_S_AHB_HREADY_IN - PORT S_AHB_HRDATA = ahblite_axi_bridge_0_S_AHB_HRDATA - PORT S_AHB_HRESP = ahblite_axi_bridge_0_S_AHB_HRESP -END - -BEGIN axi_interconnect - PARAMETER INSTANCE = axi_interconnect_0 - PARAMETER HW_VER = 1.06.a - PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0 - PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N -END - diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/leon3_zedboard.xmp b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/leon3_zedboard.xmp deleted file mode 100644 index b4fe03fc..00000000 --- a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/leon3_zedboard.xmp +++ /dev/null @@ -1,29 +0,0 @@ -#Please do not modify this file by hand -XmpVersion: 14.3 -VerMgmt: 14.3 -IntStyle: default -Flow: ise -MHS File: leon3_zedboard.mhs -Architecture: zynq -Device: xc7z020 -Package: clg484 -SpeedGrade: -1 -UserCmd1: -UserCmd1Type: 0 -UserCmd2: -UserCmd2Type: 0 -GenSimTB: 0 -SdkExportBmmBit: 1 -SdkExportDir: SDK/SDK_Export -InsertNoPads: 1 -WarnForEAArch: 1 -HdlLang: vhdl -SimModel: BEHAVIORAL -ExternalMemSim: 0 -UcfFile: data/leon3_zedboard.ucf -EnableParTimingError: 1 -ShowLicenseDialog: 1 -BInfo: ZEDBOARD -Processor: processing_system7_0 -ElfImp: -ElfSim: diff --git a/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/pcores/.gitignore b/designs/leon3-digilent-xc7z020/edk_files/leon3_zedboard/pcores/.gitignore deleted file mode 100644 index e69de29b..00000000 diff --git a/designs/leon3-digilent-xc7z020/leon3_zedboard_stub.tcl b/designs/leon3-digilent-xc7z020/leon3_zedboard_stub.tcl new file mode 100644 index 00000000..07f237be --- /dev/null +++ b/designs/leon3-digilent-xc7z020/leon3_zedboard_stub.tcl @@ -0,0 +1,169 @@ + +################################################################ +# This is a generated script based on design: leon3_zedboard_stub +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2013.4 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + puts "ERROR: This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script." + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source leon3_zedboard_stub_script.tcl + +# If you do not already have a project created, +# you can create a project using the following command: +# create_project project_1 myproj -part xc7z020clg484-1 +# set_property BOARD em.avnet.com:zynq:zed:c [current_project] + + +# CHANGE DESIGN NAME HERE +set design_name leon3_zedboard_stub + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# CHECKING IF PROJECT EXISTS +if { [get_projects -quiet] eq "" } { + puts "ERROR: Please open or create a project!" + return 1 +} + + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +if { ${design_name} ne "" && ${cur_design} eq ${design_name} } { + # Checks if design is empty or not + set list_cells [get_bd_cells -quiet] + + if { $list_cells ne "" } { + set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 + } else { + puts "INFO: Constructing design in IPI design <$design_name>..." + } +} else { + + if { [get_files -quiet ${design_name}.bd] eq "" } { + puts "INFO: Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + puts "INFO: Making design <$design_name> as current_bd_design." + current_bd_design $design_name + + } else { + set errMsg "ERROR: Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 3 + } + +} + +puts "INFO: Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + puts $errMsg + return $nRet +} + +################################################################## +# DESIGN PROCs +################################################################## + + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + puts "ERROR: Unable to find parent cell <$parentCell>!" + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + puts "ERROR: Parent <$parentObj> has TYPE = <$parentType>. Expected to be ." + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] + set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] + set S_AXI_GP0 [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_GP0 ] + set_property -dict [ list CONFIG.ADDR_WIDTH {32} CONFIG.ARUSER_WIDTH {0} CONFIG.AWUSER_WIDTH {0} CONFIG.BUSER_WIDTH {0} CONFIG.CLK_DOMAIN {} CONFIG.DATA_WIDTH {32} CONFIG.FREQ_HZ {83333336} CONFIG.ID_WIDTH {6} CONFIG.MAX_BURST_LENGTH {16} CONFIG.NUM_READ_OUTSTANDING {1} CONFIG.NUM_WRITE_OUTSTANDING {1} CONFIG.PHASE {0.000} CONFIG.PROTOCOL {AXI3} CONFIG.READ_WRITE_MODE {READ_WRITE} CONFIG.RUSER_WIDTH {0} CONFIG.SUPPORTS_NARROW_BURST {1} CONFIG.WUSER_WIDTH {0} ] $S_AXI_GP0 + + # Create ports + set FCLK_CLK0 [ create_bd_port -dir O -type clk FCLK_CLK0 ] + set FCLK_CLK1 [ create_bd_port -dir O -type clk FCLK_CLK1 ] + set FCLK_RESET0_N [ create_bd_port -dir O -type rst FCLK_RESET0_N ] + + # Create instance: processing_system7_0, and set properties + set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 processing_system7_0 ] + set_property -dict [ list CONFIG.PCW_EN_CLK1_PORT {1} CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {83.000000} CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.000000} CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0} CONFIG.PCW_USE_M_AXI_GP0 {0} CONFIG.PCW_USE_M_AXI_GP1 {0} CONFIG.PCW_USE_S_AXI_ACP {0} CONFIG.PCW_USE_S_AXI_GP0 {1} CONFIG.PCW_USE_S_AXI_GP1 {0} CONFIG.PCW_USE_S_AXI_HP0 {0} CONFIG.preset {ZedBoard*} ] $processing_system7_0 + + # Create interface connections + connect_bd_intf_net -intf_net S_AXI_GP0_1 [get_bd_intf_ports S_AXI_GP0] [get_bd_intf_pins processing_system7_0/S_AXI_GP0] + connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] + connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] + + # Create port connections + connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_ports FCLK_CLK0] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/S_AXI_GP0_ACLK] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_ports FCLK_CLK1] [get_bd_pins processing_system7_0/FCLK_CLK1] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_ports FCLK_RESET0_N] [get_bd_pins processing_system7_0/FCLK_RESET0_N] + + # Create address segments + create_bd_addr_seg -range 0x20000000 -offset 0x0 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_DDR_LOWOCM] SEG_processing_system7_0_GP0_DDR_LOWOCM + create_bd_addr_seg -range 0x400000 -offset 0xE0000000 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_IOP] SEG_processing_system7_0_GP0_IOP + create_bd_addr_seg -range 0x1000000 -offset 0xFC000000 [get_bd_addr_spaces S_AXI_GP0] [get_bd_addr_segs processing_system7_0/S_AXI_GP0/GP0_QSPI_LINEAR] SEG_processing_system7_0_GP0_QSPI_LINEAR + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + + diff --git a/designs/leon3-digilent-xc7z020/leon3_zedboard_stub_sim.vhd b/designs/leon3-digilent-xc7z020/leon3_zedboard_stub_sim.vhd index 26f00a95..c57969f2 100644 --- a/designs/leon3-digilent-xc7z020/leon3_zedboard_stub_sim.vhd +++ b/designs/leon3-digilent-xc7z020/leon3_zedboard_stub_sim.vhd @@ -7,59 +7,266 @@ use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; +use std.textio.all; + +library grlib; +use grlib.stdlib.all; +use grlib.stdio.all; + entity leon3_zedboard_stub is port ( - processing_system7_0_MIO : inout std_logic_vector(53 downto 0); - processing_system7_0_PS_SRSTB : in std_logic; - processing_system7_0_PS_CLK : in std_logic; - processing_system7_0_PS_PORB : in std_logic; - processing_system7_0_DDR_Clk : inout std_logic; - processing_system7_0_DDR_Clk_n : inout std_logic; - processing_system7_0_DDR_CKE : inout std_logic; - processing_system7_0_DDR_CS_n : inout std_logic; - processing_system7_0_DDR_RAS_n : inout std_logic; - processing_system7_0_DDR_CAS_n : inout std_logic; - processing_system7_0_DDR_WEB_pin : out std_logic; - processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); - processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); - processing_system7_0_DDR_ODT : inout std_logic; - processing_system7_0_DDR_DRSTB : inout std_logic; - processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0); - processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0); - processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0); - processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0); - processing_system7_0_DDR_VRN : inout std_logic; - processing_system7_0_DDR_VRP : inout std_logic; - ahblite_axi_bridge_0_S_AHB_HSEL_pin : in std_logic; - ahblite_axi_bridge_0_S_AHB_HADDR_pin : in std_logic_vector(31 downto 0); - ahblite_axi_bridge_0_S_AHB_HPROT_pin : in std_logic_vector(3 downto 0); - ahblite_axi_bridge_0_S_AHB_HTRANS_pin : in std_logic_vector(1 downto 0); - ahblite_axi_bridge_0_S_AHB_HSIZE_pin : in std_logic_vector(2 downto 0); - ahblite_axi_bridge_0_S_AHB_HWRITE_pin : in std_logic; - ahblite_axi_bridge_0_S_AHB_HBURST_pin : in std_logic_vector(2 downto 0); - ahblite_axi_bridge_0_S_AHB_HWDATA_pin : in std_logic_vector(31 downto 0); - ahblite_axi_bridge_0_S_AHB_HREADY_OUT_pin : out std_logic; - ahblite_axi_bridge_0_S_AHB_HREADY_IN_pin : in std_logic; - ahblite_axi_bridge_0_S_AHB_HRDATA_pin : out std_logic_vector(31 downto 0); - ahblite_axi_bridge_0_S_AHB_HRESP_pin : out std_logic; - processing_system7_0_FCLK_CLK0_pin : out std_logic; - processing_system7_0_FCLK_RESET0_N_pin : out std_logic; - processing_system7_0_FCLK_CLKTRIG0_N_pin : in std_logic + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); -- + S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); -- + S_AXI_GP0_arready : out STD_LOGIC; + S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_arvalid : in STD_LOGIC; + S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); -- + S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); -- + S_AXI_GP0_awready : out STD_LOGIC; + S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_awvalid : in STD_LOGIC; + S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_bready : in STD_LOGIC; + S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_bvalid : out STD_LOGIC; + S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_rlast : out STD_LOGIC; + S_AXI_GP0_rready : in STD_LOGIC; + S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_rvalid : out STD_LOGIC; + S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_wlast : in STD_LOGIC; + S_AXI_GP0_wready : out STD_LOGIC; + S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_wvalid : in STD_LOGIC ); end leon3_zedboard_stub; architecture STRUCTURE of leon3_zedboard_stub is -signal gclk : std_logic := '0'; +signal clk : std_logic := '0'; +signal clk0 : std_logic := '0'; +signal clk1 : std_logic := '0'; signal rst : std_logic := '0'; +type memstatetype is (idle, read1, read2, read3, write1, write2, write3); +type blane is array (0 to 2**18-1) of natural; +type memtype is array (0 to 3) of blane; +constant abits : integer := 20; +subtype BYTE is std_logic_vector(7 downto 0); +type MEM is array(0 to ((2**abits)-1)) of BYTE; +type regtype is record + memstate : memstatetype; + addr : integer; + arlen : integer; + mem : memtype; + rcnt : integer; +end record; +signal S_AXI_GP0_rvalid_i : std_logic; +signal r, rin : regtype; + begin - gclk <= not gclk after 10.0 ns; + clk0 <= not clk0 after 6.0 ns; -- 83.33 MHz + clk1 <= not clk1 after 2.5 ns; -- 200 MHz rst <= '1' after 1 us; + S_AXI_GP0_rvalid <= S_AXI_GP0_rvalid_i; + FCLK_CLK0 <= clk0; + clk <= clk0; + FCLK_CLK1 <= clk1; +-- FCLK_CLK2 <= clk2; +-- FCLK_CLK3 <= clk3; + FCLK_RESET0_N <= rst; + + + mem0 : process(clk) + variable MEMA : MEM; + variable L1 : line; + variable FIRST : boolean := true; + variable ADR : std_logic_vector(19 downto 0); + variable BUF : std_logic_vector(31 downto 0); + variable CH : character; + variable ai : integer := 0; + variable len : integer := 0; + file TCF : text open read_mode is "ram.srec"; + variable rectype : std_logic_vector(3 downto 0); + variable recaddr : std_logic_vector(31 downto 0); + variable reclen : std_logic_vector(7 downto 0); + variable recdata : std_logic_vector(0 to 16*8-1); + + variable memstate : memstatetype; + variable addr : integer; +-- variable len : integer; +-- variable mem : memtype; + variable rcnt : integer; + + begin + if FIRST then + +-- if clear = 1 then MEMA := (others => X"00"); end if; + L1:= new string'(""); --' + while not endfile(TCF) loop + readline(TCF,L1); + if (L1'length /= 0) then --' + while (not (L1'length=0)) and (L1(L1'left) = ' ') loop + std.textio.read(L1,CH); + end loop; + + if L1'length > 0 then --' + read(L1, ch); + if (ch = 'S') or (ch = 's') then + hread(L1, rectype); + hread(L1, reclen); + len := conv_integer(reclen)-1; + recaddr := (others => '0'); + case rectype is + when "0001" => + hread(L1, recaddr(15 downto 0)); + when "0010" => + hread(L1, recaddr(23 downto 0)); + when "0011" => + hread(L1, recaddr); + when others => next; + end case; + hread(L1, recdata); + recaddr(31 downto abits) := (others => '0'); + ai := conv_integer(recaddr); + for i in 0 to 15 loop + MEMA(ai+i) := recdata((i*8) to (i*8+7)); + end loop; + if ai = 0 then + ai := 1; + end if; + end if; + end if; + end if; + end loop; + + FIRST := false; - processing_system7_0_FCLK_CLK0_pin <= gclk; - processing_system7_0_FCLK_RESET0_N_pin <= rst; + elsif rising_edge(clk) then + case memstate is + when idle => + S_AXI_GP0_arready <= '0'; S_AXI_GP0_rvalid_i <= '0'; S_AXI_GP0_rlast <= '0'; + S_AXI_GP0_awready <= '0'; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '0'; + if S_AXI_GP0_arvalid = '1' then + memstate := read1; S_AXI_GP0_arready <= '1'; + elsif S_AXI_GP0_awvalid = '1' then + memstate := write1; S_AXI_GP0_awready <= '1'; + end if; + when read1 => + addr:= conv_integer(S_AXI_GP0_araddr(19 downto 0)); + len := conv_integer(S_AXI_GP0_arlen); + S_AXI_GP0_arready <= '0'; memstate := read2; rcnt := 23; + when read2 => + if rcnt /= 0 then rcnt := rcnt - 1; + else + S_AXI_GP0_rvalid_i <= '1'; + if len = 0 then S_AXI_GP0_rlast <= '1'; end if; + if (S_AXI_GP0_rready and S_AXI_GP0_rvalid_i) = '1' then + if len = 0 then + S_AXI_GP0_rlast <= '0'; S_AXI_GP0_rvalid_i <= '0'; + memstate := idle; + else + addr := addr + 4; len := len - 1; + if len = 0 then S_AXI_GP0_rlast <= '1'; end if; + end if; + end if; + for i in 0 to 3 loop + S_AXI_GP0_rdata(i*8+7 downto i*8) <= MEMA(addr+3-i); + end loop; + end if; + when write1 => + addr:= conv_integer(S_AXI_GP0_awaddr(19 downto 0)); + len := conv_integer(S_AXI_GP0_awlen); + S_AXI_GP0_awready <= '0'; memstate := write2; rcnt := 0; + when write2 => + if rcnt /= 0 then rcnt := rcnt - 1; + else + memstate := write3; + S_AXI_GP0_wready <= '1'; + end if; + when write3 => + if S_AXI_GP0_wvalid = '1' then + for i in 0 to 3 loop + if S_AXI_GP0_wstrb(i) = '1' then + MEMA(addr+3-i) := S_AXI_GP0_wdata(i*8+7 downto i*8); + end if; + end loop; + if (len = 0) or (S_AXI_GP0_wlast = '1') then + memstate := idle; S_AXI_GP0_wready <= '0'; S_AXI_GP0_bvalid <= '1'; + else + addr := addr + 1; len := len - 1; + end if; + end if; + when others => + end case; + end if; + end process; + + S_AXI_GP0_bid <= (others => '0'); + S_AXI_GP0_bresp <= (others => '0'); + S_AXI_GP0_rresp <= (others => '0'); + S_AXI_GP0_rid <= (others => '0'); + DDR_addr <= (others => '0'); + DDR_ba <= (others => '0'); + DDR_cas_n <= '0'; + DDR_ck_n <= '0'; + DDR_ck_p <= '0'; + DDR_cke <= '0'; + DDR_cs_n <= '0'; + DDR_dm <= (others => '0'); + DDR_dq <= (others => '0'); + DDR_dqs_n <= (others => '0'); + DDR_dqs_p <= (others => '0'); + DDR_odt <= '0'; + DDR_ras_n <= '0'; + DDR_reset_n <= '0'; + DDR_we_n <= '0'; + FIXED_IO_ddr_vrn <= '0'; + FIXED_IO_ddr_vrp <= '0'; + FIXED_IO_mio <= (others => '0'); + FIXED_IO_ps_clk <= '0'; + FIXED_IO_ps_porb <= '0'; + FIXED_IO_ps_srstb <= '0'; end architecture STRUCTURE; diff --git a/designs/leon3-digilent-xc7z020/leon3mp.vhd b/designs/leon3-digilent-xc7z020/leon3mp.vhd index 537f81d0..034a3cdb 100644 --- a/designs/leon3-digilent-xc7z020/leon3mp.vhd +++ b/designs/leon3-digilent-xc7z020/leon3mp.vhd @@ -1,6 +1,7 @@ ----------------------------------------------------------------------------- -- LEON3 Zedboard Demonstration design -- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler +-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05 ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research @@ -26,22 +27,15 @@ use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; use grlib.stdlib.all; -use grlib.devices.all; -use grlib.config_types.all; use grlib.config.all; use techmap.gencomp.all; -use techmap.allclkgen.all; library gaisler; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; -use gaisler.i2c.all; -use gaisler.net.all; use gaisler.jtag.all; -- pragma translate_off use gaisler.sim.all; -library unisim; -use unisim.all; -- pragma translate_on use work.config.all; @@ -59,16 +53,16 @@ entity leon3mp is ); port ( processing_system7_0_MIO : inout std_logic_vector(53 downto 0); - processing_system7_0_PS_SRSTB : in std_logic; - processing_system7_0_PS_CLK : in std_logic; - processing_system7_0_PS_PORB : in std_logic; + processing_system7_0_PS_SRSTB : inout std_logic; + processing_system7_0_PS_CLK : inout std_logic; + processing_system7_0_PS_PORB : inout std_logic; processing_system7_0_DDR_Clk : inout std_logic; processing_system7_0_DDR_Clk_n : inout std_logic; processing_system7_0_DDR_CKE : inout std_logic; processing_system7_0_DDR_CS_n : inout std_logic; processing_system7_0_DDR_RAS_n : inout std_logic; processing_system7_0_DDR_CAS_n : inout std_logic; - processing_system7_0_DDR_WEB_pin : out std_logic; + processing_system7_0_DDR_WEB_pin : inout std_logic; processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); processing_system7_0_DDR_ODT : inout std_logic; @@ -87,16 +81,77 @@ end; architecture rtl of leon3mp is -constant use_ps_block : boolean := true; - -constant hconfig : ahb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_MIG_SERIES7, 0, 0, 0), - 4 => ahb_membar(16#000#, '1', '1', 16#F80#), - others => zero32); +component leon3_zedboard_stub + port ( + DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_cas_n : inout STD_LOGIC; + DDR_ck_n : inout STD_LOGIC; + DDR_ck_p : inout STD_LOGIC; + DDR_cke : inout STD_LOGIC; + DDR_cs_n : inout STD_LOGIC; + DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_odt : inout STD_LOGIC; + DDR_ras_n : inout STD_LOGIC; + DDR_reset_n : inout STD_LOGIC; + DDR_we_n : inout STD_LOGIC; + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + FIXED_IO_ddr_vrn : inout STD_LOGIC; + FIXED_IO_ddr_vrp : inout STD_LOGIC; + FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + FIXED_IO_ps_clk : inout STD_LOGIC; + FIXED_IO_ps_porb : inout STD_LOGIC; + FIXED_IO_ps_srstb : inout STD_LOGIC; + S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); -- + S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); -- + S_AXI_GP0_arready : out STD_LOGIC; + S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_arvalid : in STD_LOGIC; + S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); -- + S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); -- + S_AXI_GP0_awready : out STD_LOGIC; + S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_awvalid : in STD_LOGIC; + S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_bready : in STD_LOGIC; + S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_bvalid : out STD_LOGIC; + S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_rlast : out STD_LOGIC; + S_AXI_GP0_rready : in STD_LOGIC; + S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_rvalid : out STD_LOGIC; + S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); -- + S_AXI_GP0_wlast : in STD_LOGIC; + S_AXI_GP0_wready : out STD_LOGIC; + S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_wvalid : in STD_LOGIC + + ); +end component; -constant maxahbm : integer := CFG_NCPU+CFG_AHB_JTAG; -constant maxahbs : integer := 1+CFG_DSU+CFG_AHBROMEN+CFG_AHBRAMEN+1+2; -constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT; +constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG; +constant maxahbs : integer := 8; +constant maxapbs : integer := 16; signal vcc, gnd : std_logic; @@ -105,16 +160,12 @@ signal apbo : apb_slv_out_vector := (others => apb_none); signal ahbsi : ahb_slv_in_type; signal ahbso : ahb_slv_out_vector := (others => ahbs_none); signal ahbmi : ahb_mst_in_type; -signal vahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); -signal vahbmo : ahb_mst_out_type; -signal clkm, rstn, rstraw, sdclkl : std_ulogic; +signal clkm, rstn, rsti, rst : std_ulogic; -signal cgi, cgi2 : clkgen_in_type; -signal cgo, cgo2 : clkgen_out_type; -signal u1i, u2i, dui : uart_in_type; -signal u1o, u2o, duo : uart_out_type; +signal u1i, dui : uart_in_type; +signal u1o, duo : uart_out_type; signal irqi : irq_in_vector(0 to CFG_NCPU-1); signal irqo : irq_out_vector(0 to CFG_NCPU-1); @@ -128,73 +179,60 @@ signal dsuo : dsu_out_type; signal rxd1 : std_logic; signal txd1 : std_logic; -signal ethi : eth_in_type; -signal etho : eth_out_type; -signal egtx_clk :std_ulogic; -signal negtx_clk :std_ulogic; - signal gpti : gptimer_in_type; signal gpto : gptimer_out_type; signal gpioi : gpio_in_type; signal gpioo : gpio_out_type; -signal clklock, elock, ulock : std_ulogic; - -signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic; signal tck, tckn, tms, tdi, tdo : std_ulogic; -signal lcd_datal : std_logic_vector(11 downto 0); -signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic; - -signal i2ci, dvi_i2ci : i2c_in_type; -signal i2co, dvi_i2co : i2c_out_type; - -constant BOARD_FREQ : integer := 50000; -- input frequency in KHz -constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz +constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz +constant CPU_FREQ : integer := BOARD_FREQ; signal stati : ahbstat_in_type; -component leon3_zedboard_stub - port ( - processing_system7_0_MIO : inout std_logic_vector(53 downto 0); - processing_system7_0_PS_SRSTB : in std_logic; - processing_system7_0_PS_CLK : in std_logic; - processing_system7_0_PS_PORB : in std_logic; - processing_system7_0_DDR_Clk : inout std_logic; - processing_system7_0_DDR_Clk_n : inout std_logic; - processing_system7_0_DDR_CKE : inout std_logic; - processing_system7_0_DDR_CS_n : inout std_logic; - processing_system7_0_DDR_RAS_n : inout std_logic; - processing_system7_0_DDR_CAS_n : inout std_logic; - processing_system7_0_DDR_WEB_pin : out std_logic; - processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); - processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); - processing_system7_0_DDR_ODT : inout std_logic; - processing_system7_0_DDR_DRSTB : inout std_logic; - processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0); - processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0); - processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0); - processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0); - processing_system7_0_DDR_VRN : inout std_logic; - processing_system7_0_DDR_VRP : inout std_logic; - ahblite_axi_bridge_0_S_AHB_HSEL_pin : in std_logic; - ahblite_axi_bridge_0_S_AHB_HADDR_pin : in std_logic_vector(31 downto 0); - ahblite_axi_bridge_0_S_AHB_HPROT_pin : in std_logic_vector(3 downto 0); - ahblite_axi_bridge_0_S_AHB_HTRANS_pin : in std_logic_vector(1 downto 0); - ahblite_axi_bridge_0_S_AHB_HSIZE_pin : in std_logic_vector(2 downto 0); - ahblite_axi_bridge_0_S_AHB_HWRITE_pin : in std_logic; - ahblite_axi_bridge_0_S_AHB_HBURST_pin : in std_logic_vector(2 downto 0); - ahblite_axi_bridge_0_S_AHB_HWDATA_pin : in std_logic_vector(31 downto 0); - ahblite_axi_bridge_0_S_AHB_HREADY_OUT_pin : out std_logic; - ahblite_axi_bridge_0_S_AHB_HREADY_IN_pin : in std_logic; - ahblite_axi_bridge_0_S_AHB_HRDATA_pin : out std_logic_vector(31 downto 0); - ahblite_axi_bridge_0_S_AHB_HRESP_pin : out std_logic; - processing_system7_0_FCLK_CLK0_pin : out std_logic; - processing_system7_0_FCLK_RESET0_N_pin : out std_logic; - processing_system7_0_FCLK_CLKTRIG0_N_pin : in std_logic - ); -end component; +constant CIDSZ : integer := 6; +constant CLENSZ : integer := 4; + +signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 ); +signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 ); +signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 ); +signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 ); +signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 ); +signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); -- +signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 ); +signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); -- +signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); -- +signal S_AXI_GP0_arready : STD_LOGIC; +signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 ); +signal S_AXI_GP0_arvalid : STD_LOGIC; +signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 ); +signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 ); +signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 ); +signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 ); +signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 ); +signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); -- +signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 ); +signal S_AXI_GP0_awready : STD_LOGIC; +signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 ); +signal S_AXI_GP0_awvalid : STD_LOGIC; +signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 ); +signal S_AXI_GP0_bready : STD_LOGIC; +signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 ); +signal S_AXI_GP0_bvalid : STD_LOGIC; +signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 ); +signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 ); +signal S_AXI_GP0_rlast : STD_LOGIC; +signal S_AXI_GP0_rready : STD_LOGIC; +signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 ); +signal S_AXI_GP0_rvalid : STD_LOGIC; +signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 ); +signal S_AXI_GP0_wlast : STD_LOGIC; +signal S_AXI_GP0_wready : STD_LOGIC; +signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 ); +signal S_AXI_GP0_wvalid : STD_LOGIC; +signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); -- begin @@ -203,8 +241,10 @@ begin ---------------------------------------------------------------------- vcc <= '1'; gnd <= '0'; + reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) + port map (button(0), rsti); + rstn <= rst and not rsti; - lock <= calib_done ; ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- ---------------------------------------------------------------------- @@ -219,23 +259,8 @@ begin --- LEON3 processor and DSU ----------------------------------------- ---------------------------------------------------------------------- - nosh : if CFG_GRFPUSH = 0 generate + leon3_0 : if CFG_LEON3 = 1 generate cpu : for i in 0 to CFG_NCPU-1 generate - l3ft : if CFG_LEON3FT_EN /= 0 generate - leon3ft0 : leon3ft -- LEON3 processor - generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8, - 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, - CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, - CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, - CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, - CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, - CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ, - CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE) - port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, - irqi(i), irqo(i), dbgi(i), dbgo(i), clkm); - end generate; - - l3s : if CFG_LEON3FT_EN = 0 generate u0 : leon3s -- LEON3 processor generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8, 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, @@ -246,10 +271,10 @@ begin CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP) port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i)); - end generate; end generate; end generate; - + nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate; + led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error); dsugen : if CFG_DSU = 1 generate @@ -258,69 +283,135 @@ begin ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); dsui.enable <= '1'; - dsui_break_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech) port map (button(0), dsui.break); - dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (led(0), ndsuact); - ndsuact <= not dsuo.active; + dsui.break <= gpioi.din(0); end generate; + dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active); nodsu : if CFG_DSU = 0 generate dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none; end generate; ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate - ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => 1) - port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(1), + ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU) + port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU), open, open, open, open, open, open, open, gnd); end generate; - nojtag : if CFG_AHB_JTAG = 0 generate apbo(1) <= apb_none; end generate; - - leon3_zedboard_stub_i : leon3_zedboard_stub + leon3_zedboard_stub_i : leon3_zedboard_stub port map ( - processing_system7_0_MIO => processing_system7_0_MIO, - processing_system7_0_PS_SRSTB => processing_system7_0_PS_SRSTB, - processing_system7_0_PS_CLK => processing_system7_0_PS_CLK, - processing_system7_0_PS_PORB => processing_system7_0_PS_PORB, - processing_system7_0_DDR_Clk => processing_system7_0_DDR_Clk, - processing_system7_0_DDR_Clk_n => processing_system7_0_DDR_Clk_n, - processing_system7_0_DDR_CKE => processing_system7_0_DDR_CKE, - processing_system7_0_DDR_CS_n => processing_system7_0_DDR_CS_n, - processing_system7_0_DDR_RAS_n => processing_system7_0_DDR_RAS_n, - processing_system7_0_DDR_CAS_n => processing_system7_0_DDR_CAS_n, - processing_system7_0_DDR_WEB_pin => processing_system7_0_DDR_WEB_pin, - processing_system7_0_DDR_BankAddr => processing_system7_0_DDR_BankAddr, - processing_system7_0_DDR_Addr => processing_system7_0_DDR_Addr, - processing_system7_0_DDR_ODT => processing_system7_0_DDR_ODT, - processing_system7_0_DDR_DRSTB => processing_system7_0_DDR_DRSTB, - processing_system7_0_DDR_DQ => processing_system7_0_DDR_DQ, - processing_system7_0_DDR_DM => processing_system7_0_DDR_DM, - processing_system7_0_DDR_DQS => processing_system7_0_DDR_DQS, - processing_system7_0_DDR_DQS_n => processing_system7_0_DDR_DQS_n, - processing_system7_0_DDR_VRN => processing_system7_0_DDR_VRN, - processing_system7_0_DDR_VRP => processing_system7_0_DDR_VRP, - ahblite_axi_bridge_0_S_AHB_HSEL_pin => ahbsi.hsel(4), - ahblite_axi_bridge_0_S_AHB_HADDR_pin => ahbsi.haddr, - ahblite_axi_bridge_0_S_AHB_HPROT_pin => ahbsi.hprot, - ahblite_axi_bridge_0_S_AHB_HTRANS_pin => ahbsi.htrans, - ahblite_axi_bridge_0_S_AHB_HSIZE_pin => ahbsi.hsize, - ahblite_axi_bridge_0_S_AHB_HWRITE_pin => ahbsi.hwrite, - ahblite_axi_bridge_0_S_AHB_HBURST_pin => ahbsi.hburst, - ahblite_axi_bridge_0_S_AHB_HWDATA_pin => ahbsi.hwdata, - ahblite_axi_bridge_0_S_AHB_HREADY_OUT_pin => ahbso(4).hready, - ahblite_axi_bridge_0_S_AHB_HREADY_IN_pin => ahbsi.hready, - ahblite_axi_bridge_0_S_AHB_HRDATA_pin => ahbso(4).hrdata, - ahblite_axi_bridge_0_S_AHB_HRESP_pin => ahbso(4).hresp(0), - processing_system7_0_FCLK_CLK0_pin => clkm, - processing_system7_0_FCLK_RESET0_N_pin => rstn, - processing_system7_0_FCLK_CLKTRIG0_N_pin => '0' - ); - - calib_done <= '1'; - ahbso(4).hresp(1) <= '0'; - ahbso(4).hconfig <= hconfig; - ahbso(4).hirq <= (others => '0'); - ahbso(4).hindex <= 4; - ahbso(4).hsplit <= (others => '0'); + DDR_ck_p => processing_system7_0_DDR_Clk, + DDR_ck_n => processing_system7_0_DDR_Clk_n, + DDR_cke => processing_system7_0_DDR_CKE, + DDR_cs_n => processing_system7_0_DDR_CS_n, + DDR_ras_n => processing_system7_0_DDR_RAS_n, + DDR_cas_n => processing_system7_0_DDR_CAS_n, + DDR_we_n => processing_system7_0_DDR_WEB_pin, + DDR_ba => processing_system7_0_DDR_BankAddr, + DDR_addr => processing_system7_0_DDR_Addr, + DDR_odt => processing_system7_0_DDR_ODT, + DDR_reset_n => processing_system7_0_DDR_DRSTB, + DDR_dq => processing_system7_0_DDR_DQ, + DDR_dm => processing_system7_0_DDR_DM, + DDR_dqs_p => processing_system7_0_DDR_DQS, + DDR_dqs_n => processing_system7_0_DDR_DQS_n, + FCLK_CLK0 => clkm, + FCLK_RESET0_N => rst, + FIXED_IO_mio => processing_system7_0_MIO, + FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB, + FIXED_IO_ps_clk => processing_system7_0_PS_CLK, + FIXED_IO_ps_porb => processing_system7_0_PS_PORB, + FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN, + FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP, + S_AXI_GP0_araddr => S_AXI_GP0_araddr, + S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0), + S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0), + S_AXI_GP0_arid => S_AXI_GP0_arid, + S_AXI_GP0_arlen => S_AXI_GP0_arlen, + S_AXI_GP0_arlock => S_AXI_GP0_arlock, + S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0), + S_AXI_GP0_arqos => S_AXI_GP0_arqos, + S_AXI_GP0_awqos => S_AXI_GP0_awqos, + S_AXI_GP0_arready => S_AXI_GP0_arready, + S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0), + S_AXI_GP0_arvalid => S_AXI_GP0_arvalid, + S_AXI_GP0_awaddr => S_AXI_GP0_awaddr, + S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0), + S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0), + S_AXI_GP0_awid => S_AXI_GP0_awid, + S_AXI_GP0_awlen => S_AXI_GP0_awlen, + S_AXI_GP0_awlock => S_AXI_GP0_awlock, + S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0), + S_AXI_GP0_awready => S_AXI_GP0_awready, + S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0), + S_AXI_GP0_awvalid => S_AXI_GP0_awvalid, + S_AXI_GP0_bid => S_AXI_GP0_bid, + S_AXI_GP0_bready => S_AXI_GP0_bready, + S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0), + S_AXI_GP0_bvalid => S_AXI_GP0_bvalid, + S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0), + S_AXI_GP0_rid => S_AXI_GP0_rid, + S_AXI_GP0_rlast => S_AXI_GP0_rlast, + S_AXI_GP0_rready => S_AXI_GP0_rready, + S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0), + S_AXI_GP0_rvalid => S_AXI_GP0_rvalid, + S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0), + S_AXI_GP0_wid => S_AXI_GP0_wid, + S_AXI_GP0_wlast => S_AXI_GP0_wlast, + S_AXI_GP0_wready => S_AXI_GP0_wready, + S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0), + S_AXI_GP0_wvalid => S_AXI_GP0_wvalid + ); + + + ahb2axi0 : entity work.ahb2axi + generic map( + hindex => 3, haddr => 16#400#, hmask => 16#F00#, + pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ) + port map( + rstn => rstn, + clk => clkm, + ahbsi => ahbsi, + ahbso => ahbso(3), + apbi => apbi, + apbo => apbo(0), + M_AXI_araddr => S_AXI_GP0_araddr, + M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0), + M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0), + M_AXI_arid => S_AXI_GP0_arid, + M_AXI_arlen => S_AXI_GP0_arlen, + M_AXI_arlock => S_AXI_GP0_arlock, + M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0), + M_AXI_arqos => S_AXI_GP0_arqos, + M_AXI_arready => S_AXI_GP0_arready, + M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0), + M_AXI_arvalid => S_AXI_GP0_arvalid, + M_AXI_awaddr => S_AXI_GP0_awaddr, + M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0), + M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0), + M_AXI_awid => S_AXI_GP0_awid, + M_AXI_awlen => S_AXI_GP0_awlen, + M_AXI_awlock => S_AXI_GP0_awlock, + M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0), + M_AXI_awqos => S_AXI_GP0_awqos, + M_AXI_awready => S_AXI_GP0_awready, + M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0), + M_AXI_awvalid => S_AXI_GP0_awvalid, + M_AXI_bid => S_AXI_GP0_bid, + M_AXI_bready => S_AXI_GP0_bready, + M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0), + M_AXI_bvalid => S_AXI_GP0_bvalid, + M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0), + M_AXI_rid => S_AXI_GP0_rid, + M_AXI_rlast => S_AXI_GP0_rlast, + M_AXI_rready => S_AXI_GP0_rready, + M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0), + M_AXI_rvalid => S_AXI_GP0_rvalid, + M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0), + M_AXI_wlast => S_AXI_GP0_wlast, + M_AXI_wready => S_AXI_GP0_wready, + M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0), + M_AXI_wvalid => S_AXI_GP0_wvalid + ); ---------------------------------------------------------------------- --- APB Bridge and various periherals ------------------------------- @@ -330,12 +421,14 @@ begin generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); - irqctrl : if CFG_IRQ3_ENABLE /= 0 generate - irqctrl0 : irqmp -- interrupt controller - generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) - port map (rstn, clkm, apbi, apbo(2), irqo, irqi); + irqgen : if CFG_LEON3 = 1 generate + irqctrl : if CFG_IRQ3_ENABLE /= 0 generate + irqctrl0 : irqmp -- interrupt controller + generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + port map (rstn, clkm, apbi, apbo(2), irqo, irqi); + end generate; end generate; - irq3 : if CFG_IRQ3_ENABLE = 0 generate + irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate x : for i in 0 to CFG_NCPU-1 generate irqi(i).irl <= "0000"; end generate; @@ -355,8 +448,8 @@ begin gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit grgpio0: grgpio - generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) - port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10), + generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH) + port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8), gpioi => gpioi, gpioo => gpioo); pio_pads : for i in 0 to 7 generate pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v) @@ -381,13 +474,15 @@ begin u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd; - serrx_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech) - port map (led(2), rxd1); - sertx_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech) - port map (led(3), txd1); + end generate; noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; - + + hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech) + port map (led(2), ahbmi.hready); + rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech) + port map (led(3), rsti); + ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7, nftslv => CFG_AHBSTATN) @@ -400,8 +495,8 @@ begin bpromgen : if CFG_AHBROMEN /= 0 generate brom : entity work.ahbrom - generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) - port map ( rstn, clkm, ahbsi, ahbso(7)); + generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) + port map ( rstn, clkm, ahbsi, ahbso(0)); end generate; ----------------------------------------------------------------------- @@ -413,24 +508,18 @@ begin tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE) port map ( rstn, clkm, ahbsi, ahbso(5)); end generate; - + ----------------------------------------------------------------------- --- Test report module ---------------------------------------------- ----------------------------------------------------------------------- -- pragma translate_off test0_gen : if (testahb = true) generate - test0 : ahbrep generic map (hindex => 3, haddr => 16#200#) - port map (rstn, clkm, ahbsi, ahbso(3)); + test0 : ahbrep generic map (hindex => 6, haddr => 16#200#) + port map (rstn, clkm, ahbsi, ahbso(6)); end generate; -- pragma translate_on - test1_gen : if (testahb = false) generate - ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#, - tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) - port map ( rstn, clkm, ahbsi, ahbso(3)); - end generate; - ----------------------------------------------------------------------- --- Drive unused bus elements --------------------------------------- ----------------------------------------------------------------------- diff --git a/designs/leon3-digilent-xc7z020/leon3mp.xdc b/designs/leon3-digilent-xc7z020/leon3mp.xdc new file mode 100644 index 00000000..d4eaa765 --- /dev/null +++ b/designs/leon3-digilent-xc7z020/leon3mp.xdc @@ -0,0 +1,454 @@ +# ---------------------------------------------------------------------------- +# _____ +# / \ +# /____ \____ +# / \===\ \==/ +# /___\===\___\/ AVNET Design Resource Center +# \======/ www.em.avnet.com/drc +# \====/ +# ---------------------------------------------------------------------------- +# +# Created With Avnet UCF Generator V0.4.0 +# Date: Saturday, June 30, 2012 +# Time: 12:18:55 AM +# +# This design is the property of Avnet. Publication of this +# design is not authorized without written consent from Avnet. +# +# Please direct any questions to: +# Avnet Centralized Technical Support +# Centralized-Support@avnet.com +# 1-800-422-9023 +# +# Disclaimer: +# Avnet, Inc. makes no warranty for the use of this code or design. +# This code is provided "As Is". Avnet, Inc assumes no responsibility for +# any errors, which may appear in this code, nor does it make a commitment +# to update the information contained herein. Avnet, Inc specifically +# disclaims any implied warranties of fitness for a particular purpose. +# Copyright(c) 2012 Avnet, Inc. +# All rights reserved. +# +# ---------------------------------------------------------------------------- +# +# Notes: +# +# 10 August 2012 +# IO standards based upon Bank 34 and Bank 35 Vcco supply options of 1.8V, +# 2.5V, or 3.3V are possible based upon the Vadj jumper (J18) settings. +# By default, Vadj is expected to be set to 1.8V but if a different +# voltage is used for a particular design, then the corresponding IO +# standard within this UCF should also be updated to reflect the actual +# Vadj jumper selection. +# +# 09 September 2012 +# Net names are not allowed to contain hyphen characters '-' since this +# is not a legal VHDL87 or Verilog character within an identifier. +# HDL net names are adjusted to contain no hyphen characters '-' but +# rather use underscore '_' characters. Comment net name with the hyphen +# characters will remain in place since these are intended to match the +# schematic net names in order to better enable schematic search. + +# ---------------------------------------------------------------------------- +#set_property PACKAGE_PIN H20 [get_ports {wbInputData[9]}] RMME +# Bank 13, Vcco = 3.3V +#Set the bank voltage for bank 13. +#set_property IOSTANDARD LVCMOS33 [get_ports -filter { IOBANK == 13 } ] +#In the following the XDC constraint is matched to the origanal UCF constraint, XDC above, UCF below # Commented +#set_property PACKAGE_PIN AB1 [get_ports {AC_ADR0}] +#NET AC_ADR0 LOC = AB1 | IOSTANDARD=LVCMOS33; # "AC-ADR0" +# +#set_property PACKAGE_PIN Y5 [get_ports {AC_ADR1}] +#NET AC_ADR1 LOC = Y5 | IOSTANDARD=LVCMOS33; # "AC-ADR1" +#set_property PACKAGE_PIN Y8 [get_ports {AC_GPIO0}] +#NET AC_GPIO0 LOC = Y8 | IOSTANDARD=LVCMOS33; # "AC-GPIO0" +#set_property PACKAGE_PIN AA7 [get_ports {AC_GPIO1}] +#NET AC_GPIO1 LOC = AA7 | IOSTANDARD=LVCMOS33; # "AC-GPIO1" +#set_property PACKAGE_PIN AA6 [get_ports {AC_GPIO2}] +#NET AC_GPIO2 LOC = AA6 | IOSTANDARD=LVCMOS33; # "AC-GPIO2" +#set_property PACKAGE_PIN Y6 [get_ports {AC_GPIO3}] +#NET AC_GPIO3 LOC = Y6 | IOSTANDARD=LVCMOS33; # "AC-GPIO3" +#set_property PACKAGE_PIN AB2 [get_ports {AC_MCLK}] +#NET AC_MCLK LOC = AB2 | IOSTANDARD=LVCMOS33; # "AC-MCLK" +#set_property PACKAGE_PIN AB4 [get_ports {AC_SCK}] +#NET AC_SCK LOC = AB4 | IOSTANDARD=LVCMOS33; # "AC-SCK" +#set_property PACKAGE_PIN AB5 [get_ports {AC_SDA}] +#NET AC_SDA LOC = AB5 | IOSTANDARD=LVCMOS33; # "AC-SDA" +#set_property PACKAGE_PIN R7 [get_ports {FMC_SCL}] +#NET FMC_SCL LOC = R7 | IOSTANDARD=LVCMOS33; # "FMC-SCL" +#set_property PACKAGE_PIN U7 [get_ports {FMC_SDA}] +#NET FMC_SDA LOC = U7 | IOSTANDARD=LVCMOS33; # "FMC-SDA" +#set_property PACKAGE_PIN Y9 [get_ports {gclk}] +#NET GCLK LOC = Y9 | IOSTANDARD=LVCMOS33; # "GCLK" +#set_property PACKAGE_PIN Y11 [get_ports {JA1}] +#NET JA1 LOC = Y11 | IOSTANDARD=LVCMOS33; # "JA1" +#set_property PACKAGE_PIN AA8 [get_ports {JA10}] +#NET JA10 LOC = AA8 | IOSTANDARD=LVCMOS33; # "JA10" +#set_property PACKAGE_PIN AA11 [get_ports {JA2}] +#NET JA2 LOC = AA11 | IOSTANDARD=LVCMOS33; # "JA2" +#set_property PACKAGE_PIN Y10 [get_ports {JA3}] +#NET JA3 LOC = Y10 | IOSTANDARD=LVCMOS33; # "JA3" +#set_property PACKAGE_PIN AA9 [get_ports {JA4}] +#NET JA4 LOC = AA9 | IOSTANDARD=LVCMOS33; # "JA4" +#set_property PACKAGE_PIN AB11 [get_ports {JA7}] +#NET JA7 LOC = AB11 | IOSTANDARD=LVCMOS33; # "JA7" +#set_property PACKAGE_PIN AB10 [get_ports {JA8}] +#NET JA8 LOC = AB10 | IOSTANDARD=LVCMOS33; # "JA8" +#set_property PACKAGE_PIN AB9 [get_ports {JA9}] +#NET JA9 LOC = AB9 | IOSTANDARD=LVCMOS33; # "JA9" +#set_property PACKAGE_PIN W12 [get_ports {JB1}] +#NET JB1 LOC = W12 | IOSTANDARD=LVCMOS33; # "JB1" +#set_property PACKAGE_PIN V8 [get_ports {JB10}] +#NET JB10 LOC = V8 | IOSTANDARD=LVCMOS33; # "JB10" +#set_property PACKAGE_PIN W11 [get_ports {JB2}] +#NET JB2 LOC = W11 | IOSTANDARD=LVCMOS33; # "JB2" +#set_property PACKAGE_PIN V10 [get_ports {JB3}] +#NET JB3 LOC = V10 | IOSTANDARD=LVCMOS33; # "JB3" +#set_property PACKAGE_PIN W8 [get_ports {JB4}] +#NET JB4 LOC = W8 | IOSTANDARD=LVCMOS33; # "JB4" +#set_property PACKAGE_PIN V12 [get_ports {JB7}] +#NET JB7 LOC = V12 | IOSTANDARD=LVCMOS33; # "JB7" +#set_property PACKAGE_PIN W10 [get_ports {JB8}] +#NET JB8 LOC = W10 | IOSTANDARD=LVCMOS33; # "JB8" +#set_property PACKAGE_PIN V9 [get_ports {JB9}] +#NET JB9 LOC = V9 | IOSTANDARD=LVCMOS33; # "JB9" +#NET JC1_N LOC = AB6 | IOSTANDARD=LVCMOS33; # "JC1_N" +#NET JC1_P LOC = AB7 | IOSTANDARD=LVCMOS33; # "JC1_P" +#NET JC2_N LOC = AA4 | IOSTANDARD=LVCMOS33; # "JC2_N" +#NET JC2_P LOC = Y4 | IOSTANDARD=LVCMOS33; # "JC2_P" +#NET JC3_N LOC = T6 | IOSTANDARD=LVCMOS33; # "JC3_N" +#NET JC3_P LOC = R6 | IOSTANDARD=LVCMOS33; # "JC3_P" +#NET JC4_N LOC = U4 | IOSTANDARD=LVCMOS33; # "JC4_N" +#NET JC4_P LOC = T4 | IOSTANDARD=LVCMOS33; # "JC4_P" +#NET JD1_N LOC = W7 | IOSTANDARD=LVCMOS33; # "JD1_N" +#NET JD1_P LOC = V7 | IOSTANDARD=LVCMOS33; # "JD1_P" +#NET JD2_N LOC = V4 | IOSTANDARD=LVCMOS33; # "JD2_N" +#NET JD2_P LOC = V5 | IOSTANDARD=LVCMOS33; # "JD2_P" +#NET JD3_N LOC = W5 | IOSTANDARD=LVCMOS33; # "JD3_N" +#NET JD3_P LOC = W6 | IOSTANDARD=LVCMOS33; # "JD3_P" +#NET JD4_N LOC = U5 | IOSTANDARD=LVCMOS33; # "JD4_N" +#NET JD4_P LOC = U6 | IOSTANDARD=LVCMOS33; # "JD4_P" +#set_property PACKAGE_PIN U10 [get_ports {OLED_DC}] +#NET OLED_DC LOC = U10 | IOSTANDARD=LVCMOS33; # "OLED-DC" +#set_property PACKAGE_PIN U9 [get_ports {OLED_RES}] +#NET OLED_RES LOC = U9 | IOSTANDARD=LVCMOS33; # "OLED-RES" +#set_property PACKAGE_PIN AB12 [get_ports {OLED_SCLK}] +#NET OLED_SCLK LOC = AB12 | IOSTANDARD=LVCMOS33; # "OLED-SCLK" +#set_property PACKAGE_PIN AA12 [get_ports {OLED_SDIN}] +#NET OLED_SDIN LOC = AA12 | IOSTANDARD=LVCMOS33; # "OLED-SDIN" +#set_property PACKAGE_PIN U11 [get_ports {OLED_VBAT}] +#NET OLED_VBAT LOC = U11 | IOSTANDARD=LVCMOS33; # "OLED-VBAT" +#set_property PACKAGE_PIN U12 [get_ports {OLED_VDD}] +#NET OLED_VDD LOC = U12 | IOSTANDARD=LVCMOS33; # "OLED-VDD" + +# Bank 33, Vcco = 3.3V +#set_property IOSTANDARD LVCMOS33 [get_ports -filter { IOBANK == 33 } ] +#set_property PACKAGE_PIN AB14 [get_ports {FMC_PRSNT}] +#NET FMC_PRSNT LOC = AB14 | IOSTANDARD=LVCMOS33; # "FMC-PRSNT" +#set_property PACKAGE_PIN W18 [get_ports {HD_CLK}] +#NET HD_CLK LOC = W18 | IOSTANDARD=LVCMOS33; # "HD-CLK" +#set_property PACKAGE_PIN Y13 [get_ports {HD_D0}] +#NET HD_D0 LOC = Y13 | IOSTANDARD=LVCMOS33; # "HD-D0" +#set_property PACKAGE_PIN AA13 [get_ports {HD_D1}] +#NET HD_D1 LOC = AA13 | IOSTANDARD=LVCMOS33; # "HD-D1" +#set_property PACKAGE_PIN W13 [get_ports {HD_D10}] +#NET HD_D10 LOC = W13 | IOSTANDARD=LVCMOS33; # "HD-D10" +#set_property PACKAGE_PIN W15 [get_ports {HD_D11}] +#NET HD_D11 LOC = W15 | IOSTANDARD=LVCMOS33; # "HD-D11" +#set_property PACKAGE_PIN V15 [get_ports {HD_D12}] +#NET HD_D12 LOC = V15 | IOSTANDARD=LVCMOS33; # "HD-D12" +#set_property PACKAGE_PIN U17 [get_ports {HD_D13}] +#NET HD_D13 LOC = U17 | IOSTANDARD=LVCMOS33; # "HD-D13" +#set_property PACKAGE_PIN V14 [get_ports {HD_D14}] +#NET HD_D14 LOC = V14 | IOSTANDARD=LVCMOS33; # "HD-D14" +#set_property PACKAGE_PIN V13 [get_ports {HS_D15}] +#NET HD_D15 LOC = V13 | IOSTANDARD=LVCMOS33; # "HD-D15" +#set_property PACKAGE_PIN AA14 [get_ports {HD_D2}] +#NET HD_D2 LOC = AA14 | IOSTANDARD=LVCMOS33; # "HD-D2" +#set_property PACKAGE_PIN Y14 [get_ports {HD_D3}] +#NET HD_D3 LOC = Y14 | IOSTANDARD=LVCMOS33; # "HD-D3" +#set_property PACKAGE_PIN AB15 [get_ports {HD_D4}] +#NET HD_D4 LOC = AB15 | IOSTANDARD=LVCMOS33; # "HD-D4" +#set_property PACKAGE_PIN AB16 [get_ports {HD_D5}] +#NET HD_D5 LOC = AB16 | IOSTANDARD=LVCMOS33; # "HD-D5" +#set_property PACKAGE_PIN AA16 [get_ports {HD_D6}] +#NET HD_D6 LOC = AA16 | IOSTANDARD=LVCMOS33; # "HD-D6" +#set_property PACKAGE_PIN AB17 [get_ports {HD_D7}] +#NET HD_D7 LOC = AB17 | IOSTANDARD=LVCMOS33; # "HD-D7" +#set_property PACKAGE_PIN AA17 [get_ports {HD_D8}] +#NET HD_D8 LOC = AA17 | IOSTANDARD=LVCMOS33; # "HD-D8" +#set_property PACKAGE_PIN Y15 [get_ports {HD_D9}] +#NET HD_D9 LOC = Y15 | IOSTANDARD=LVCMOS33; # "HD-D9" +#set_property PACKAGE_PIN U16 [get_ports {HD_DE}] +#NET HD_DE LOC = U16 | IOSTANDARD=LVCMOS33; # "HD-DE" +#set_property PACKAGE_PIN V17 [get_ports {HD_HSYNC}] +#NET HD_HSYNC LOC = V17 | IOSTANDARD=LVCMOS33; # "HD-HSYNC" +#set_property PACKAGE_PIN W16 [get_ports {HD_INT}] +#NET HD_INT LOC = W16 | IOSTANDARD=LVCMOS33; # "HD-INT" +#set_property PACKAGE_PIN AA18 [get_ports {HD_SCL}] +#NET HD_SCL LOC = AA18 | IOSTANDARD=LVCMOS33; # "HD-SCL" +#set_property PACKAGE_PIN Y16 [get_ports {HD_SDA}] +#NET HD_SDA LOC = Y16 | IOSTANDARD=LVCMOS33; # "HD-SDA" +#set_property PACKAGE_PIN U15 [get_ports {HD_SPDIF}] +#NET HD_SPDIF LOC = U15 | IOSTANDARD=LVCMOS33; # "HD-SPDIF" +#set_property PACKAGE_PIN Y18 [get_ports {HD_SPDIFO}] +#NET HD_SPDIFO LOC = Y18 | IOSTANDARD=LVCMOS33; # "HD-SPDIFO" +#set_property PACKAGE_PIN W17 [get_ports {HD_VSYNC}] +#NET HD_VSYNC LOC = W17 | IOSTANDARD=LVCMOS33; # "HD-VSYNC" +set_property PACKAGE_PIN T22 [get_ports {led[0]}] +#NET LD0 LOC = T22 | IOSTANDARD=LVCMOS33; # "LD0" +set_property PACKAGE_PIN T21 [get_ports {led[1]}] +#NET LD1 LOC = T21 | IOSTANDARD=LVCMOS33; # "LD1" +set_property PACKAGE_PIN U22 [get_ports {led[2]}] +#NET LD2 LOC = U22 | IOSTANDARD=LVCMOS33; # "LD2" +set_property PACKAGE_PIN U21 [get_ports {led[3]}] +#NET LD3 LOC = U21 | IOSTANDARD=LVCMOS33; # "LD3" +set_property PACKAGE_PIN V22 [get_ports {led[4]}] +#NET LD4 LOC = V22 | IOSTANDARD=LVCMOS33; # "LD4" +set_property PACKAGE_PIN W22 [get_ports {led[5]}] +#NET LD5 LOC = W22 | IOSTANDARD=LVCMOS33; # "LD5" +set_property PACKAGE_PIN U19 [get_ports {led[6]}] +#NET LD6 LOC = U19 | IOSTANDARD=LVCMOS33; # "LD6" +set_property PACKAGE_PIN U14 [get_ports {led[7]}] +#NET LD7 LOC = U14 | IOSTANDARD=LVCMOS33; # "LD7" +#set_property PACKAGE_PIN W20 [get_ports {NetIC16_W20}] +#NET NetIC16_W20 LOC = W20 | IOSTANDARD=LVCMOS33; # "NetIC16_W20" +#set_property PACKAGE_PIN W21 [get_ports {NetIC16_W21}] +#NET NetIC16_W21 LOC = W21 | IOSTANDARD=LVCMOS33; # "NetIC16_W21" +#set_property PACKAGE_PIN Y21 [get_ports {VGA_B1}] +#NET VGA_B1 LOC = Y21 | IOSTANDARD=LVCMOS33; # "VGA-B1" +#set_property PACKAGE_PIN Y20 [get_ports {VGA_B2}] +#NET VGA_B2 LOC = Y20 | IOSTANDARD=LVCMOS33; # "VGA-B2" +#set_property PACKAGE_PIN AB20 [get_ports {VGA_B3}] +#NET VGA_B3 LOC = AB20 | IOSTANDARD=LVCMOS33; # "VGA-B3" +#set_property PACKAGE_PIN AB19 [get_ports {VGA_B4}] +#NET VGA_B4 LOC = AB19 | IOSTANDARD=LVCMOS33; # "VGA-B4" +#set_property PACKAGE_PIN AB22 [get_ports {VGA_G1}] +#NET VGA_G1 LOC = AB22 | IOSTANDARD=LVCMOS33; # "VGA-G1" +#set_property PACKAGE_PIN AA22 [get_ports {VGA_G2}] +#NET VGA_G2 LOC = AA22 | IOSTANDARD=LVCMOS33; # "VGA-G2" +#set_property PACKAGE_PIN AB21 [get_ports {VGA_G3}] +#NET VGA_G3 LOC = AB21 | IOSTANDARD=LVCMOS33; # "VGA-G3" +#set_property PACKAGE_PIN AA21 [get_ports {VGA_G4}] +#NET VGA_G4 LOC = AA21 | IOSTANDARD=LVCMOS33; # "VGA-G4" +#set_property PACKAGE_PIN AA19 [get_ports {VGA_HS}] +#NET VGA_HS LOC = AA19 | IOSTANDARD=LVCMOS33; # "VGA-HS" +#set_property PACKAGE_PIN V20 [get_ports {VGA_R1}] +#NET VGA_R1 LOC = V20 | IOSTANDARD=LVCMOS33; # "VGA-R1" +#set_property PACKAGE_PIN U20 [get_ports {VGA_R2}] +#NET VGA_R2 LOC = U20 | IOSTANDARD=LVCMOS33; # "VGA-R2" +#set_property PACKAGE_PIN V19 [get_ports {VGA_R3}] +#NET VGA_R3 LOC = V19 | IOSTANDARD=LVCMOS33; # "VGA-R3" +#set_property PACKAGE_PIN V18 [get_ports {VGA_R4}] +#NET VGA_R4 LOC = V18 | IOSTANDARD=LVCMOS33; # "VGA-R4" +#set_property PACKAGE_PIN Y19 [get_ports {VGA_VS}] +#NET VGA_VS LOC = Y19 | IOSTANDARD=LVCMOS33; # "VGA-VS" + +# Bank 34, Vcco = Vadj +#set_property IOSTANDARD LVCMOS18 [get_ports -filter { IOBANK == 34 } ] +#set_property PACKAGE_PIN P16 [get_ports {BTNC}] +#NET BTNC LOC = P16 | IOSTANDARD=LVCMOS18; # "BTNC" +set_property PACKAGE_PIN R16 [get_ports {button[0]}] +#NET BTND LOC = R16 | IOSTANDARD=LVCMOS18; # "BTND" +set_property PACKAGE_PIN N15 [get_ports {button[1]}] +#NET BTNL LOC = N15 | IOSTANDARD=LVCMOS18; # "BTNL" +set_property PACKAGE_PIN R18 [get_ports {button[2]}] +#NET BTNR LOC = R18 | IOSTANDARD=LVCMOS18; # "BTNR" +set_property PACKAGE_PIN T18 [get_ports {button[3]}] +#NET BTNU LOC = T18 | IOSTANDARD=LVCMOS18; # "BTNU" +#set_property PACKAGE_PIN L19 [get_ports {FMC_CLK0_N}] +#NET FMC_CLK0_N LOC = L19 | IOSTANDARD=LVCMOS18; # "FMC-CLK0_N" +#set_property PACKAGE_PIN L18 [get_ports {FMC_CLK0_P}] +#NET FMC_CLK0_P LOC = L18 | IOSTANDARD=LVCMOS18; # "FMC-CLK0_P" +#set_property PACKAGE_PIN M20 [get_ports {FMC_LA00_CC_N}] +#NET FMC_LA00_CC_N LOC = M20 | IOSTANDARD=LVCMOS18; # "FMC-LA00_CC_N" +#set_property PACKAGE_PIN M19 [get_ports {FMC_LA00_CC_P}] +#NET FMC_LA00_CC_P LOC = M19 | IOSTANDARD=LVCMOS18; # "FMC-LA00_CC_P" +#set_property PACKAGE_PIN N20 [get_ports {FMC_LA01_CC_N}] +#NET FMC_LA01_CC_N LOC = N20 | IOSTANDARD=LVCMOS18; # "FMC-LA01_CC_N" +#set_property PACKAGE_PIN N19 [get_ports {FMC_LA00_CC_P}] +#NET FMC_LA01_CC_P LOC = N19 | IOSTANDARD=LVCMOS18; # "FMC-LA01_CC_P" +#set_property PACKAGE_PIN P18 [get_ports {FMC_LA02_N}] +#NET FMC_LA02_N LOC = P18 | IOSTANDARD=LVCMOS18; # "FMC-LA02_N" +#set_property PACKAGE_PIN P17 [get_ports {FMC_LA02_P}] +#NET FMC_LA02_P LOC = P17 | IOSTANDARD=LVCMOS18; # "FMC-LA02_P" +#set_property PACKAGE_PIN P22 [get_ports {FMC_LA03_N}] +#NET FMC_LA03_N LOC = P22 | IOSTANDARD=LVCMOS18; # "FMC-LA03_N" +#set_property PACKAGE_PIN N22 [get_ports {FMC_LA03_P}] +#NET FMC_LA03_P LOC = N22 | IOSTANDARD=LVCMOS18; # "FMC-LA03_P" +#set_property PACKAGE_PIN M22 [get_ports {FMC_LA04_N}] +#NET FMC_LA04_N LOC = M22 | IOSTANDARD=LVCMOS18; # "FMC-LA04_N" +#set_property PACKAGE_PIN M21 [get_ports {FMC_LA04_P}] +#NET FMC_LA04_P LOC = M21 | IOSTANDARD=LVCMOS18; # "FMC-LA04_P" +#set_property PACKAGE_PIN K18 [get_ports {FMC_LA05_N}] +#NET FMC_LA05_N LOC = K18 | IOSTANDARD=LVCMOS18; # "FMC-LA05_N" +#set_property PACKAGE_PIN J18 [get_ports {FMC_LA05_P}] +#NET FMC_LA05_P LOC = J18 | IOSTANDARD=LVCMOS18; # "FMC-LA05_P" +#set_property PACKAGE_PIN L22 [get_ports {FMC_LA06_N}] +#NET FMC_LA06_N LOC = L22 | IOSTANDARD=LVCMOS18; # "FMC-LA06_N" +#set_property PACKAGE_PIN L21 [get_ports {FMC_LA06_P}] +#NET FMC_LA06_P LOC = L21 | IOSTANDARD=LVCMOS18; # "FMC-LA06_P" +#set_property PACKAGE_PIN T17 [get_ports {FMC_LA07_N}] +#NET FMC_LA07_N LOC = T17 | IOSTANDARD=LVCMOS18; # "FMC-LA07_N" +#set_property PACKAGE_PIN T16 [get_ports {FMC_LA07_P}] +#NET FMC_LA07_P LOC = T16 | IOSTANDARD=LVCMOS18; # "FMC-LA07_P" +#set_property PACKAGE_PIN J22 [get_ports {FMC_LA08_N}] +#NET FMC_LA08_N LOC = J22 | IOSTANDARD=LVCMOS18; # "FMC-LA08_N" +#set_property PACKAGE_PIN J21 [get_ports {FMC_LA08_P}] +#NET FMC_LA08_P LOC = J21 | IOSTANDARD=LVCMOS18; # "FMC-LA08_P" +#set_property PACKAGE_PIN R21 [get_ports {FMC_LA09_N}] +#NET FMC_LA09_N LOC = R21 | IOSTANDARD=LVCMOS18; # "FMC-LA09_N" +#set_property PACKAGE_PIN R20 [get_ports {FMC_LA09_P}] +#NET FMC_LA09_P LOC = R20 | IOSTANDARD=LVCMOS18; # "FMC-LA09_P" +#set_property PACKAGE_PIN T19 [get_ports {FMC_LA10_N}] +#NET FMC_LA10_N LOC = T19 | IOSTANDARD=LVCMOS18; # "FMC-LA10_N" +#set_property PACKAGE_PIN R19 [get_ports {FMC_LA10_P}] +#NET FMC_LA10_P LOC = R19 | IOSTANDARD=LVCMOS18; # "FMC-LA10_P" +#set_property PACKAGE_PIN N18 [get_ports {FMC_LA11_N}] +#NET FMC_LA11_N LOC = N18 | IOSTANDARD=LVCMOS18; # "FMC-LA11_N" +#set_property PACKAGE_PIN N17 [get_ports {FMC_LA11_P}] +#NET FMC_LA11_P LOC = N17 | IOSTANDARD=LVCMOS18; # "FMC-LA11_P" +#set_property PACKAGE_PIN P21 [get_ports {FMC_LA12_N}] +#NET FMC_LA12_N LOC = P21 | IOSTANDARD=LVCMOS18; # "FMC-LA12_N" +#set_property PACKAGE_PIN P20 [get_ports {FMC_LA12_P}] +#NET FMC_LA12_P LOC = P20 | IOSTANDARD=LVCMOS18; # "FMC-LA12_P" +#set_property PACKAGE_PIN M17 [get_ports {FMC_LA13_N}] +#NET FMC_LA13_N LOC = M17 | IOSTANDARD=LVCMOS18; # "FMC-LA13_N" +#set_property PACKAGE_PIN L17 [get_ports {FMC_LA13_P}] +#NET FMC_LA13_P LOC = L17 | IOSTANDARD=LVCMOS18; # "FMC-LA13_P" +#set_property PACKAGE_PIN K20 [get_ports {FMC_LA14_N}] +#NET FMC_LA14_N LOC = K20 | IOSTANDARD=LVCMOS18; # "FMC-LA14_N" +#set_property PACKAGE_PIN K19 [get_ports {FMC_LA14_P}] +#NET FMC_LA14_P LOC = K19 | IOSTANDARD=LVCMOS18; # "FMC-LA14_P" +#set_property PACKAGE_PIN J17 [get_ports {FMC_LA15_N}] +#NET FMC_LA15_N LOC = J17 | IOSTANDARD=LVCMOS18; # "FMC-LA15_N" +#set_property PACKAGE_PIN J16 [get_ports {FMC_LA15_P}] +#NET FMC_LA15_P LOC = J16 | IOSTANDARD=LVCMOS18; # "FMC-LA15_P" +#set_property PACKAGE_PIN K21 [get_ports {FMC_LA16_N}] +#NET FMC_LA16_N LOC = K21 | IOSTANDARD=LVCMOS18; # "FMC-LA16_N" +#set_property PACKAGE_PIN J20 [get_ports {FMC_LA16_P}] +#NET FMC_LA16_P LOC = J20 | IOSTANDARD=LVCMOS18; # "FMC-LA16_P" +#set_property PACKAGE_PIN L16 [get_ports {OTG_VBUSOC}] +#NET OTG_VBUSOC LOC = L16 | IOSTANDARD=LVCMOS18; # "OTG-VBUSOC" +#set_property PACKAGE_PIN K16 [get_ports {PUDC_B}] +#NET PUDC_B LOC = K16 | IOSTANDARD=LVCMOS18; # "PUDC_B" +#set_property PACKAGE_PIN H15 [get_ports {XADC_GIO0}] +#NET XADC_GIO0 LOC = H15; # "XADC-GIO0" +#set_property PACKAGE_PIN R15 [get_ports {XADC_GIO1}] +#NET XADC_GIO1 LOC = R15; # "XADC-GIO1" +#set_property PACKAGE_PIN K15 [get_ports {XADC_GIO2}] +#NET XADC_GIO2 LOC = K15; # "XADC-GIO2" +#set_property PACKAGE_PIN J15 [get_ports {XADC_GIO3}] +#NET XADC_GIO3 LOC = J15; # "XADC-GIO3" + +# Bank 35, Vcco = Vadj +#set_property IOSTANDARD LVCMOS18 [get_ports -filter { IOBANK == 35 } ] +#set_property PACKAGE_PIN C19 [get_ports {FMC_CLK1_N}] +#NET FMC_CLK1_N LOC = C19 | IOSTANDARD=LVCMOS18; # "FMC-CLK1_N" +#set_property PACKAGE_PIN D18 [get_ports {FMC_CLK1_P}] +#NET FMC_CLK1_P LOC = D18 | IOSTANDARD=LVCMOS18; # "FMC-CLK1_P" +#set_property PACKAGE_PIN B20 [get_ports {FMC_LA17_CC_N}] +#NET FMC_LA17_CC_N LOC = B20 | IOSTANDARD=LVCMOS18; # "FMC-LA17_CC_N" +#set_property PACKAGE_PIN B19 [get_ports {FMC_LA17_CC_P}] +#NET FMC_LA17_CC_P LOC = B19 | IOSTANDARD=LVCMOS18; # "FMC-LA17_CC_P" +#set_property PACKAGE_PIN C20 [get_ports {FMC_LA18_CC_N}] +#NET FMC_LA18_CC_N LOC = C20 | IOSTANDARD=LVCMOS18; # "FMC-LA18_CC_N" +#set_property PACKAGE_PIN D20 [get_ports {FMC_LA18_CC_P}] +#NET FMC_LA18_CC_P LOC = D20 | IOSTANDARD=LVCMOS18; # "FMC-LA18_CC_P" +#set_property PACKAGE_PIN G16 [get_ports {FMC_LA19_N}] +#NET FMC_LA19_N LOC = G16 | IOSTANDARD=LVCMOS18; # "FMC-LA19_N" +#set_property PACKAGE_PIN G15 [get_ports {FMC_LA19_P}] +#NET FMC_LA19_P LOC = G15 | IOSTANDARD=LVCMOS18; # "FMC-LA19_P" +#set_property PACKAGE_PIN G21 [get_ports {FMC_LA20_N}] +#NET FMC_LA20_N LOC = G21 | IOSTANDARD=LVCMOS18; # "FMC-LA20_N" +#set_property PACKAGE_PIN G20 [get_ports {FMC_LA20_P}] +#NET FMC_LA20_P LOC = G20 | IOSTANDARD=LVCMOS18; # "FMC-LA20_P" +#set_property PACKAGE_PIN E20 [get_ports {FMC_LA21_N}] +#NET FMC_LA21_N LOC = E20 | IOSTANDARD=LVCMOS18; # "FMC-LA21_N" +#set_property PACKAGE_PIN E19 [get_ports {FMC_LA21_P}] +#NET FMC_LA21_P LOC = E19 | IOSTANDARD=LVCMOS18; # "FMC-LA21_P" +#set_property PACKAGE_PIN F19 [get_ports {FMC_LA22_N}] +#NET FMC_LA22_N LOC = F19 | IOSTANDARD=LVCMOS18; # "FMC-LA22_N" +#set_property PACKAGE_PIN G19 [get_ports {FMC_LA22_P}] +#NET FMC_LA22_P LOC = G19 | IOSTANDARD=LVCMOS18; # "FMC-LA22_P" +#set_property PACKAGE_PIN D15 [get_ports {FMC_LA23_N}] +#NET FMC_LA23_N LOC = D15 | IOSTANDARD=LVCMOS18; # "FMC-LA23_N" +#set_property PACKAGE_PIN E15 [get_ports {FMC_LA23_P}] +#NET FMC_LA23_P LOC = E15 | IOSTANDARD=LVCMOS18; # "FMC-LA23_P" +#set_property PACKAGE_PIN A19 [get_ports {FMC_LA24_N}] +#NET FMC_LA24_N LOC = A19 | IOSTANDARD=LVCMOS18; # "FMC-LA24_N" +#set_property PACKAGE_PIN A18 [get_ports {FMC_LA24_P}] +#NET FMC_LA24_P LOC = A18 | IOSTANDARD=LVCMOS18; # "FMC-LA24_P" +#set_property PACKAGE_PIN C22 [get_ports {FMC_LA25_N}] +#NET FMC_LA25_N LOC = C22 | IOSTANDARD=LVCMOS18; # "FMC-LA25_N" +#set_property PACKAGE_PIN D22 [get_ports {FMC_LA25_P}] +#NET FMC_LA25_P LOC = D22 | IOSTANDARD=LVCMOS18; # "FMC-LA25_P" +#set_property PACKAGE_PIN E18 [get_ports {FMC_LA26_N}] +#NET FMC_LA26_N LOC = E18 | IOSTANDARD=LVCMOS18; # "FMC-LA26_N" +#set_property PACKAGE_PIN F18 [get_ports {FMC_LA26_P}] +#NET FMC_LA26_P LOC = F18 | IOSTANDARD=LVCMOS18; # "FMC-LA26_P" +#set_property PACKAGE_PIN D21 [get_ports {FMC_LA27_N}] +#NET FMC_LA27_N LOC = D21 | IOSTANDARD=LVCMOS18; # "FMC-LA27_N" +#set_property PACKAGE_PIN E21 [get_ports {FMC_LA27_P}] +#NET FMC_LA27_P LOC = E21 | IOSTANDARD=LVCMOS18; # "FMC-LA27_P" +#set_property PACKAGE_PIN A17 [get_ports {FMC_LA28_N}] +#NET FMC_LA28_N LOC = A17 | IOSTANDARD=LVCMOS18; # "FMC-LA28_N" +#set_property PACKAGE_PIN A16 [get_ports {FMC_LA28_P}] +#NET FMC_LA28_P LOC = A16 | IOSTANDARD=LVCMOS18; # "FMC-LA28_P" +#set_property PACKAGE_PIN C18 [get_ports {FMC_LA29_N}] +#NET FMC_LA29_N LOC = C18 | IOSTANDARD=LVCMOS18; # "FMC-LA29_N" +#set_property PACKAGE_PIN C17 [get_ports {FMC_LA29_P}] +#NET FMC_LA29_P LOC = C17 | IOSTANDARD=LVCMOS18; # "FMC-LA29_P" +#set_property PACKAGE_PIN B15 [get_ports {FMC_LA30_N}] +#NET FMC_LA30_N LOC = B15 | IOSTANDARD=LVCMOS18; # "FMC-LA30_N" +#set_property PACKAGE_PIN C15 [get_ports {FMC_LA30_P}] +#NET FMC_LA30_P LOC = C15 | IOSTANDARD=LVCMOS18; # "FMC-LA30_P" +#set_property PACKAGE_PIN B17 [get_ports {FMC_LA31_N}] +#NET FMC_LA31_N LOC = B17 | IOSTANDARD=LVCMOS18; # "FMC-LA31_N" +#set_property PACKAGE_PIN B16 [get_ports {FMC_LA31_P}] +#NET FMC_LA31_P LOC = B16 | IOSTANDARD=LVCMOS18; # "FMC-LA31_P" +#set_property PACKAGE_PIN A22 [get_ports {FMC_LA32_N}] +#NET FMC_LA32_N LOC = A22 | IOSTANDARD=LVCMOS18; # "FMC-LA32_N" +#set_property PACKAGE_PIN A21 [get_ports {FMC_LA32_P}] +#NET FMC_LA32_P LOC = A21 | IOSTANDARD=LVCMOS18; # "FMC-LA32_P" +#set_property PACKAGE_PIN B22 [get_ports {FMC_LA33_N}] +#NET FMC_LA33_N LOC = B22 | IOSTANDARD=LVCMOS18; # "FMC-LA33_N" +#set_property PACKAGE_PIN B21 [get_ports {FMC_LA33_P}] +#NET FMC_LA33_P LOC = B21 | IOSTANDARD=LVCMOS18; # "FMC-LA33_P" +#set_property PACKAGE_PIN G17 [get_ports {OTG_RESETN}] +#NET OTG_RESETN LOC = G17 | IOSTANDARD=LVCMOS18; # "OTG-RESETN" +set_property PACKAGE_PIN F22 [get_ports {switch[0]}] +#NET SW0 LOC = F22 | IOSTANDARD=LVCMOS18; # "SW0" +set_property PACKAGE_PIN G22 [get_ports {switch[1]}] +#NET SW1 LOC = G22 | IOSTANDARD=LVCMOS18; # "SW1" +set_property PACKAGE_PIN H22 [get_ports {switch[2]}] +#NET SW2 LOC = H22 | IOSTANDARD=LVCMOS18; # "SW2" +set_property PACKAGE_PIN F21 [get_ports {switch[3]}] +#NET SW3 LOC = F21 | IOSTANDARD=LVCMOS18; # "SW3" +set_property PACKAGE_PIN H19 [get_ports {switch[4]}] +#NET SW4 LOC = H19 | IOSTANDARD=LVCMOS18; # "SW4" +set_property PACKAGE_PIN H18 [get_ports {switch[5]}] +#NET SW5 LOC = H18 | IOSTANDARD=LVCMOS18; # "SW5" +set_property PACKAGE_PIN H17 [get_ports {switch[6]}] +#NET SW6 LOC = H17 | IOSTANDARD=LVCMOS18; # "SW6" +set_property PACKAGE_PIN M17 [get_ports {switch[7]}] +#NET SW7 LOC = M15 | IOSTANDARD=LVCMOS18; # "SW7" +#set_property PACKAGE_PIN E16 [get_ports {AD0N_R}] +#NET XADC_AD0N_R LOC = E16; # "XADC-AD0N-R" +#set_property PACKAGE_PIN F16 [get_ports {AD0P_R}] +#NET XADC_AD0P_R LOC = F16; # "XADC-AD0P-R" +#set_property PACKAGE_PIN D17 [get_ports {AD8N_N}] +#NET XADC_AD8N_R LOC = D17; # "XADC-AD8N-R" +#set_property PACKAGE_PIN D16 [get_ports {AD8P_R}] +#NET XADC_AD8P_R LOC = D16; # "XADC-AD8P-R" + + +#set_property IOB TRUE [all_outputs] + +#create_clock -name clk100 -period 10.0 [get_ports gclk] +set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks clk_fpga_1] +set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_0] +#set_false_path -from [get_clocks clk_fpga_2] -to [get_clocks clk_fpga_1] +#set_false_path -from [get_clocks clk_fpga_1] -to [get_clocks clk_fpga_2] +#set_false_path -from [get_clocks clk_fpga_2] -to [get_clocks clk_fpga_3] +#set_false_path -from [get_clocks clk_fpga_3] -to [get_clocks clk_fpga_2] \ No newline at end of file diff --git a/designs/leon3-xilinx-sp605/prom.S b/designs/leon3-digilent-xc7z020/prom.S similarity index 73% rename from designs/leon3-xilinx-sp605/prom.S rename to designs/leon3-digilent-xc7z020/prom.S index 220d95f7..f0739d80 100644 --- a/designs/leon3-xilinx-sp605/prom.S +++ b/designs/leon3-digilent-xc7z020/prom.S @@ -6,6 +6,7 @@ #ifndef STACKSIZE #define STACKSIZE 0x00020000 #endif +#define FREQMHZ 83 .seg "text" @@ -108,19 +109,8 @@ start: ldd [%g3], %f24 ldd [%g3], %f26 ldd [%g3], %f28 - ldd [%g3], %f30 - nop - nop - nop - nop - nop - faddd %f0, %f2, %f4 - nop - nop - nop - nop ba 1f - nop + ldd [%g3], %f30 .align 8 @@ -134,38 +124,15 @@ _fsrxx: andcc %g3, 0x0f, %g3 bne 1f - set L2MCTRLIO, %g1 - set MCFG1, %g2 - st %g2, [%g1] - set MCFG2, %g2 - st %g2, [%g1+4] - set MCFG3, %g2 - st %g2, [%g1+8] -! set IRQCTRL, %g1 -! set 0x0ffff, %g2 -! st %g2, [%g1+0x10] - -#ifdef DDR2CTRLIO - set DDR2CTRLIO, %g1 - set DDR2CFG4, %g2 - st %g2, [%g1+12] -#endif - -#ifdef ASDCFG -#ifndef SDCTRLPNP -#define SDCTRLPNP 0xFFFFF860 -#endif - set SDCTRLPNP, %g1 - ld [%g1], %g2 - srl %g2, 12, %g2 - set 0x01009, %g1 - subcc %g1, %g2, %g0 - bne 1f - - set ASDCFG, %g1 - set DSDCFG, %g2 - st %g2, [%g1] -#endif + set GPTIMER, %g1 + set FREQMHZ-1, %g2 + st %g2, [%g1 + 0x04] + st %g2, [%g1 + 0x00] + st %g0, [%g1 + 0x08] + set -1, %g2 + st %g2, [%g1 + 0x14] + set 7, %g2 + st %g2, [%g1 + 0x08] ! %g3 = cpu index 1: set STACKSIZE, %g2 @@ -184,9 +151,6 @@ _fsrxx: set RAMSTART, %g1 -! set 0x88100000, %g2 ! restore data that was zapped by calibration -! set 0x0910006d, %g3 -! std %g2, [%g1] jmp %g1 nop diff --git a/designs/leon3-digilent-xc7z020/prom.h b/designs/leon3-digilent-xc7z020/prom.h new file mode 100644 index 00000000..af29a248 --- /dev/null +++ b/designs/leon3-digilent-xc7z020/prom.h @@ -0,0 +1,11 @@ +#define MCFG1 0x10380033 +#define MCFG2 0xe6B86e60 +#define MCFG3 0x000ff000 +#define ASDCFG 0x80000000 +#define DSDCFG 0xe6A06e60 +#define L2MCTRLIO 0x80000000 +#define GPTIMER 0x80000300 +#define IRQCTRL 0x80000200 +#define RAMSTART 0x40000000 +#define RAMSIZE 0x00100000 + diff --git a/designs/leon3-digilent-xc7z020/prom.srec b/designs/leon3-digilent-xc7z020/prom.srec new file mode 100644 index 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VHDL [current_project] +source {leon3_zedboard_stub.tcl} +generate_target all [get_files vivado/leon3-zedboard-xc7z020/leon3-zedboard-xc7z020.srcs/sources_1/bd/leon3_zedboard_stub/leon3_zedboard_stub.bd] +make_wrapper -files [get_files vivado/leon3-zedboard-xc7z020/leon3-zedboard-xc7z020.srcs/sources_1/bd/leon3_zedboard_stub/leon3_zedboard_stub.bd] -top +add_files -norecurse vivado/leon3-zedboard-xc7z020/leon3-zedboard-xc7z020.srcs/sources_1/bd/leon3_zedboard_stub/hdl/leon3_zedboard_stub_wrapper.vhd +update_compile_order -fileset sources_1 +export_hardware [get_files vivado/leon3-zedboard-xc7z020/leon3-zedboard-xc7z020.srcs/sources_1/bd/leon3_zedboard_stub/leon3_zedboard_stub.bd] diff --git a/designs/leon3-digilent-xc7z020/systest.c b/designs/leon3-digilent-xc7z020/systest.c new file mode 100644 index 00000000..d41808ae --- /dev/null +++ b/designs/leon3-digilent-xc7z020/systest.c @@ -0,0 +1,10 @@ + +main() + +{ + report_start(); + + base_test(); + + report_end(); +} diff --git a/designs/leon3-digilent-xc7z020/testbench.vhd b/designs/leon3-digilent-xc7z020/testbench.vhd index 0ed70cd9..40895c3d 100644 --- a/designs/leon3-digilent-xc7z020/testbench.vhd +++ b/designs/leon3-digilent-xc7z020/testbench.vhd @@ -1,6 +1,7 @@ ----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2012 Fredrik Ringhage, Gaisler Research +-- Modified by Jiri Gaisler, 2014-04-05 ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research @@ -23,19 +24,6 @@ library ieee; use ieee.std_logic_1164.all; -library gaisler; -use gaisler.libdcom.all; -use gaisler.sim.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; -library micron; -use micron.all; -library techmap; -use techmap.gencomp.all; -use work.debug.all; - use work.config.all; entity testbench is @@ -53,15 +41,6 @@ end; architecture behav of testbench is -constant promfile : string := "prom.srec"; -- rom contents -constant sramfile : string := "ram.srec"; -- ram contents -constant sdramfile : string := "ram.srec"; -- sdram contents - -signal GND : std_ulogic := '0'; -signal VCC : std_ulogic := '1'; -signal NC : std_ulogic := 'Z'; -signal gclk : std_logic := '0'; -signal rst : std_logic := '0'; signal button : std_logic_vector(3 downto 0) := (others => '0'); signal switch : std_logic_vector(7 downto 0); -- I/O port signal led : std_logic_vector(7 downto 0); -- I/O port @@ -88,8 +67,6 @@ signal processing_system7_0_DDR_DQS_n : std_logic_vector(3 downto 0); signal processing_system7_0_DDR_VRN : std_logic; signal processing_system7_0_DDR_VRP : std_logic; - - component leon3mp is generic ( fabtech : integer := CFG_FABTECH; @@ -103,16 +80,16 @@ component leon3mp is ); port ( processing_system7_0_MIO : inout std_logic_vector(53 downto 0); - processing_system7_0_PS_SRSTB : in std_logic; - processing_system7_0_PS_CLK : in std_logic; - processing_system7_0_PS_PORB : in std_logic; + processing_system7_0_PS_SRSTB : inout std_logic; + processing_system7_0_PS_CLK : inout std_logic; + processing_system7_0_PS_PORB : inout std_logic; processing_system7_0_DDR_Clk : inout std_logic; processing_system7_0_DDR_Clk_n : inout std_logic; processing_system7_0_DDR_CKE : inout std_logic; processing_system7_0_DDR_CS_n : inout std_logic; processing_system7_0_DDR_RAS_n : inout std_logic; processing_system7_0_DDR_CAS_n : inout std_logic; - processing_system7_0_DDR_WEB_pin : out std_logic; + processing_system7_0_DDR_WEB_pin : inout std_logic; processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0); processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0); processing_system7_0_DDR_ODT : inout std_logic; @@ -132,8 +109,6 @@ end component; begin -- clock, reset and misc - gclk <= not gclk after 5.0 ns; - rst <= '1' after 1 us; button <= (others => '0'); switch <= (others => '0'); @@ -175,5 +150,14 @@ begin led => led ); + iuerr : process + begin + wait for 5000 ns; + wait on led(1); + assert (led(1) = '1') + report "*** IU in error mode, simulation halted ***" + severity failure ; + end process; + end ; diff --git a/designs/leon3-digilent-xc7z020/wave.do b/designs/leon3-digilent-xc7z020/wave.do new file mode 100644 index 00000000..b32303d8 --- /dev/null +++ b/designs/leon3-digilent-xc7z020/wave.do @@ -0,0 +1,50 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /testbench/cpu/clkm +add wave -noupdate /testbench/cpu/rstn +add wave -noupdate -radix hexadecimal /testbench/cpu/apbi +add wave -noupdate -radix hexadecimal /testbench/cpu/apbo +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cpu/ahbsi.hsel -radix hexadecimal} {/testbench/cpu/ahbsi.haddr -radix hexadecimal} {/testbench/cpu/ahbsi.hwrite -radix hexadecimal} {/testbench/cpu/ahbsi.htrans -radix hexadecimal} {/testbench/cpu/ahbsi.hsize -radix hexadecimal} {/testbench/cpu/ahbsi.hburst -radix hexadecimal} {/testbench/cpu/ahbsi.hwdata -radix hexadecimal} {/testbench/cpu/ahbsi.hprot -radix hexadecimal} {/testbench/cpu/ahbsi.hready -radix hexadecimal} {/testbench/cpu/ahbsi.hmaster -radix hexadecimal} {/testbench/cpu/ahbsi.hmastlock -radix hexadecimal} {/testbench/cpu/ahbsi.hmbsel -radix hexadecimal} {/testbench/cpu/ahbsi.hirq -radix hexadecimal} {/testbench/cpu/ahbsi.testen -radix hexadecimal} {/testbench/cpu/ahbsi.testrst -radix hexadecimal} {/testbench/cpu/ahbsi.scanen -radix hexadecimal} {/testbench/cpu/ahbsi.testoen -radix hexadecimal} {/testbench/cpu/ahbsi.testin -radix hexadecimal}} -subitemconfig {/testbench/cpu/ahbsi.hsel {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.haddr {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hwrite {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.htrans {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hsize {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hburst {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hwdata {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hprot {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hready {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hmaster {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hmastlock {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hmbsel {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.hirq {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.testen {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.testrst {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.scanen {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.testoen {-height 16 -radix hexadecimal} /testbench/cpu/ahbsi.testin {-height 16 -radix hexadecimal}} /testbench/cpu/ahbsi +add wave -noupdate -radix hexadecimal /testbench/cpu/ahbso +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cpu/ahbmi.hgrant -radix hexadecimal} {/testbench/cpu/ahbmi.hready -radix hexadecimal} {/testbench/cpu/ahbmi.hresp -radix hexadecimal} {/testbench/cpu/ahbmi.hrdata -radix hexadecimal} {/testbench/cpu/ahbmi.hirq -radix hexadecimal} {/testbench/cpu/ahbmi.testen -radix hexadecimal} {/testbench/cpu/ahbmi.testrst -radix hexadecimal} {/testbench/cpu/ahbmi.scanen -radix hexadecimal} {/testbench/cpu/ahbmi.testoen -radix hexadecimal} {/testbench/cpu/ahbmi.testin -radix hexadecimal}} -subitemconfig {/testbench/cpu/ahbmi.hgrant {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.hready {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.hresp {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.hrdata {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.hirq {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.testen {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.testrst {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.scanen {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.testoen {-height 16 -radix hexadecimal} /testbench/cpu/ahbmi.testin {-height 16 -radix hexadecimal}} /testbench/cpu/ahbmi +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cpu/ahbmo(15) -radix hexadecimal} {/testbench/cpu/ahbmo(14) -radix hexadecimal} {/testbench/cpu/ahbmo(13) -radix hexadecimal} {/testbench/cpu/ahbmo(12) -radix hexadecimal} {/testbench/cpu/ahbmo(11) -radix hexadecimal} {/testbench/cpu/ahbmo(10) -radix hexadecimal} {/testbench/cpu/ahbmo(9) -radix hexadecimal} {/testbench/cpu/ahbmo(8) -radix hexadecimal} {/testbench/cpu/ahbmo(7) -radix hexadecimal} {/testbench/cpu/ahbmo(6) -radix hexadecimal} {/testbench/cpu/ahbmo(5) -radix hexadecimal} {/testbench/cpu/ahbmo(4) -radix hexadecimal} {/testbench/cpu/ahbmo(3) -radix hexadecimal} {/testbench/cpu/ahbmo(2) -radix hexadecimal} {/testbench/cpu/ahbmo(1) -radix hexadecimal} {/testbench/cpu/ahbmo(0) -radix hexadecimal}} -subitemconfig {/testbench/cpu/ahbmo(15) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(14) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(13) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(12) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(11) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(10) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(9) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(8) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(7) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(6) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(5) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(4) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(3) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(2) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(1) {-height 16 -radix hexadecimal} /testbench/cpu/ahbmo(0) {-height 16 -radix hexadecimal}} /testbench/cpu/ahbmo +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_araddr +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_arlen +add wave -noupdate /testbench/cpu/S_AXI_GP0_arvalid +add wave -noupdate /testbench/cpu/S_AXI_GP0_arready +add wave -noupdate /testbench/cpu/S_AXI_GP0_rready +add wave -noupdate /testbench/cpu/S_AXI_GP0_rvalid +add wave -noupdate /testbench/cpu/S_AXI_GP0_rlast +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_rdata +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_rresp +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cpu/S_AXI_GP0_awaddr(31) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(30) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(29) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(28) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(27) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(26) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(25) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(24) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(23) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(22) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(21) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(20) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(19) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(18) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(17) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(16) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(15) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(14) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(13) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(12) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(11) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(10) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(9) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(8) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(7) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(6) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(5) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(4) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(3) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(2) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(1) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_awaddr(0) -radix hexadecimal}} -subitemconfig {/testbench/cpu/S_AXI_GP0_awaddr(31) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(30) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(29) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(28) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(27) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(26) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(25) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(24) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(23) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(22) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(21) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(20) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(19) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(18) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(17) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(16) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(15) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(14) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(13) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(12) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(11) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(10) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(9) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(8) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(7) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(6) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(5) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(4) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(3) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(2) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(1) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_awaddr(0) {-height 16 -radix hexadecimal}} /testbench/cpu/S_AXI_GP0_awaddr +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_awlen +add wave -noupdate /testbench/cpu/S_AXI_GP0_awvalid +add wave -noupdate /testbench/cpu/S_AXI_GP0_awready +add wave -noupdate /testbench/cpu/S_AXI_GP0_wvalid +add wave -noupdate /testbench/cpu/S_AXI_GP0_wlast +add wave -noupdate /testbench/cpu/S_AXI_GP0_wready +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_wdata +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cpu/S_AXI_GP0_wstrb(3) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_wstrb(2) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_wstrb(1) -radix hexadecimal} {/testbench/cpu/S_AXI_GP0_wstrb(0) -radix hexadecimal}} -subitemconfig {/testbench/cpu/S_AXI_GP0_wstrb(3) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_wstrb(2) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_wstrb(1) {-height 16 -radix hexadecimal} /testbench/cpu/S_AXI_GP0_wstrb(0) {-height 16 -radix hexadecimal}} /testbench/cpu/S_AXI_GP0_wstrb +add wave -noupdate /testbench/cpu/S_AXI_GP0_bready +add wave -noupdate -radix hexadecimal /testbench/cpu/S_AXI_GP0_bresp +add wave -noupdate /testbench/cpu/S_AXI_GP0_bvalid +add wave -noupdate -radix hexadecimal -childformat {{/testbench/cpu/ahb2axi0/r.bstate -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hready -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hsel -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hwrite -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.htrans -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hburst -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hsize -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hwdata -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.haddr -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.hmaster -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_arlen -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_rdata -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_arvalid -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_awvalid -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_rready -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_wstrb -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_bready -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_wvalid -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_wlast -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_bresp -radix hexadecimal} {/testbench/cpu/ahb2axi0/r.m_axi_awaddr -radix hexadecimal}} -expand -subitemconfig {/testbench/cpu/ahb2axi0/r.bstate {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hready {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hsel {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hwrite {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.htrans {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hburst {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hsize {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hwdata {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.haddr {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.hmaster {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_arlen {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_rdata {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_arvalid {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_awvalid {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_rready {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_wstrb {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_bready {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_wvalid {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_wlast {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_bresp {-height 16 -radix hexadecimal} /testbench/cpu/ahb2axi0/r.m_axi_awaddr {-height 16 -radix hexadecimal}} /testbench/cpu/ahb2axi0/r +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {1369943 ps} 0} {{Cursor 3} {36483035 ps} 0} +quietly wave cursor active 2 +configure wave -namecolwidth 200 +configure wave -valuecolwidth 115 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ns +update +WaveRestoreZoom {36155503 ps} {36717870 ps} diff --git a/designs/leon3-digilent-xup/.config b/designs/leon3-digilent-xup/.config index b103b922..230c1015 100644 --- a/designs/leon3-digilent-xup/.config +++ b/designs/leon3-digilent-xup/.config @@ -168,7 +168,6 @@ CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -254,7 +253,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000019 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-digilent-xup/Makefile b/designs/leon3-digilent-xup/Makefile index dd276ba6..2719bec9 100644 --- a/designs/leon3-digilent-xup/Makefile +++ b/designs/leon3-digilent-xup/Makefile @@ -24,7 +24,7 @@ LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF usbhc hynix \ DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \ can usb spacewire grusbhc hcan leon4 leon4v0 l2cache \ slink ascs pwm gr1553b iommu -FILESKIP = grcan.vhd i2cmst.vhd +FILESKIP = grcan.vhd i2cmst.vhd sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/leon3-digilent-xup/config.h b/designs/leon3-digilent-xup/config.h index c4992550..59d10ad1 100644 --- a/designs/leon3-digilent-xup/config.h +++ b/designs/leon3-digilent-xup/config.h @@ -163,7 +163,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -243,7 +242,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000019 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-digilent-xup/config.help b/designs/leon3-digilent-xup/config.help index a8f8adf1..6ea29433 100644 --- a/designs/leon3-digilent-xup/config.help +++ b/designs/leon3-digilent-xup/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-digilent-xup/config.vhd b/designs/leon3-digilent-xup/config.vhd index 2c2c3176..630d4006 100644 --- a/designs/leon3-digilent-xup/config.vhd +++ b/designs/leon3-digilent-xup/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-digilent-xup/config.vhd.h b/designs/leon3-digilent-xup/config.vhd.h index 7a14a83c..089a77f6 100644 --- a/designs/leon3-digilent-xup/config.vhd.h +++ b/designs/leon3-digilent-xup/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-digilent-xup/lconfig.tk b/designs/leon3-digilent-xup/lconfig.tk index a321e747..4513e726 100755 --- a/designs/leon3-digilent-xup/lconfig.tk +++ b/designs/leon3-digilent-xup/lconfig.tk @@ -2078,24 +2078,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2167,20 +2166,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2313,9 +2309,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3126,7 +3119,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3176,12 +3169,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3212,12 +3204,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4446,7 +4437,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4592,6 +4582,7 @@ set CONFIG_GRACECTRL 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5048,7 +5039,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5171,10 +5161,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "DDR266 SDRAM controller " global CONFIG_DDRSP @@ -5225,6 +5214,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-digilent-xup/leon3mp.vhd b/designs/leon3-digilent-xup/leon3mp.vhd index 5d6cb292..57258435 100644 --- a/designs/leon3-digilent-xup/leon3mp.vhd +++ b/designs/leon3-digilent-xup/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-digilent-xup/testbench.vhd b/designs/leon3-digilent-xup/testbench.vhd index c1ff1cbc..373a118e 100644 --- a/designs/leon3-digilent-xup/testbench.vhd +++ b/designs/leon3-digilent-xup/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -151,36 +151,43 @@ begin ); ddrmem : for i in 0 to 1 generate - u3 : mt46v16m16 - generic map (index => 3, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); - - u2 : mt46v16m16 - generic map (index => 2, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(3 downto 2)); - u1 : mt46v16m16 - generic map (index => 1, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(5 downto 4)); - - u0 : mt46v16m16 - generic map (index => 0, fname => sdramfile, bbits => 64) - PORT MAP( - Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), - Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(7 downto 6)); + -- u3 : mt46v16m16 + -- generic map (index => 3, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + + -- u2 : mt46v16m16 + -- generic map (index => 2, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(3 downto 2)); + -- u1 : mt46v16m16 + -- generic map (index => 1, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(5 downto 4)); + + -- u0 : mt46v16m16 + -- generic map (index => 0, fname => sdramfile, bbits => 64) + -- PORT MAP( + -- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i), + -- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(7 downto 6)); + ddr0 : ddrram + generic map(width => 64, abits => 14, colbits => 9, rowbits => 14, + implbanks => 1, fname => sdramfile, speedbin => 1, density => 1) + port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i), + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); end generate; prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-digilent-xup/tkconfig.h b/designs/leon3-digilent-xup/tkconfig.h index 2a2845c1..fbebe7bc 100644 --- a/designs/leon3-digilent-xup/tkconfig.h +++ b/designs/leon3-digilent-xup/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-cpci-xc2v6000/.config b/designs/leon3-gr-cpci-xc2v6000/.config index cd72b58a..e399c4ce 100644 --- a/designs/leon3-gr-cpci-xc2v6000/.config +++ b/designs/leon3-gr-cpci-xc2v6000/.config @@ -168,7 +168,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -254,7 +253,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000004 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Memory controllers diff --git a/designs/leon3-gr-cpci-xc2v6000/config.h b/designs/leon3-gr-cpci-xc2v6000/config.h index a5e679ee..a83b7f97 100644 --- a/designs/leon3-gr-cpci-xc2v6000/config.h +++ b/designs/leon3-gr-cpci-xc2v6000/config.h @@ -163,7 +163,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -243,7 +242,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000004 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Memory controllers */ diff --git a/designs/leon3-gr-cpci-xc2v6000/config.help b/designs/leon3-gr-cpci-xc2v6000/config.help index 1beb362b..0836451a 100644 --- a/designs/leon3-gr-cpci-xc2v6000/config.help +++ b/designs/leon3-gr-cpci-xc2v6000/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-gr-cpci-xc2v6000/config.vhd b/designs/leon3-gr-cpci-xc2v6000/config.vhd index 8ce63d93..25b630c7 100644 --- a/designs/leon3-gr-cpci-xc2v6000/config.vhd +++ b/designs/leon3-gr-cpci-xc2v6000/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-gr-cpci-xc2v6000/config.vhd.h b/designs/leon3-gr-cpci-xc2v6000/config.vhd.h index 95a344da..7589856f 100644 --- a/designs/leon3-gr-cpci-xc2v6000/config.vhd.h +++ b/designs/leon3-gr-cpci-xc2v6000/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-gr-cpci-xc2v6000/lconfig.tk b/designs/leon3-gr-cpci-xc2v6000/lconfig.tk index 977d84c0..a83aefaf 100755 --- a/designs/leon3-gr-cpci-xc2v6000/lconfig.tk +++ b/designs/leon3-gr-cpci-xc2v6000/lconfig.tk @@ -2090,24 +2090,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2179,20 +2178,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2325,9 +2321,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3138,7 +3131,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3188,12 +3181,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3224,12 +3216,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5331,7 +5322,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5588,6 +5578,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -6047,7 +6038,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6170,10 +6160,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " global CONFIG_SRCTRL @@ -6276,6 +6265,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_32 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd b/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd index 960ddeb9..30b367e7 100644 --- a/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd +++ b/designs/leon3-gr-cpci-xc2v6000/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-cpci-xc2v6000/testbench.vhd b/designs/leon3-gr-cpci-xc2v6000/testbench.vhd index 408b7c04..76c3c557 100644 --- a/designs/leon3-gr-cpci-xc2v6000/testbench.vhd +++ b/designs/leon3-gr-cpci-xc2v6000/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-cpci-xc2v6000/tkconfig.h b/designs/leon3-gr-cpci-xc2v6000/tkconfig.h index 617db195..d7341f53 100644 --- a/designs/leon3-gr-cpci-xc2v6000/tkconfig.h +++ b/designs/leon3-gr-cpci-xc2v6000/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-cpci-xc4v/.config b/designs/leon3-gr-cpci-xc4v/.config index 6609b272..9b7b026f 100644 --- a/designs/leon3-gr-cpci-xc4v/.config +++ b/designs/leon3-gr-cpci-xc4v/.config @@ -172,7 +172,6 @@ CONFIG_DCACHE_ALGOLRR=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -258,7 +257,6 @@ CONFIG_DSU_IPLSB=0059 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000059 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Memory controllers diff --git a/designs/leon3-gr-cpci-xc4v/config.h b/designs/leon3-gr-cpci-xc4v/config.h index 43edc61f..e0810196 100644 --- a/designs/leon3-gr-cpci-xc4v/config.h +++ b/designs/leon3-gr-cpci-xc4v/config.h @@ -167,7 +167,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -247,7 +246,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000059 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Memory controllers */ diff --git a/designs/leon3-gr-cpci-xc4v/config.help b/designs/leon3-gr-cpci-xc4v/config.help index 61efddc3..f5c55c30 100644 --- a/designs/leon3-gr-cpci-xc4v/config.help +++ b/designs/leon3-gr-cpci-xc4v/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-gr-cpci-xc4v/config.vhd b/designs/leon3-gr-cpci-xc4v/config.vhd index b6b4d87f..4e3e1773 100644 --- a/designs/leon3-gr-cpci-xc4v/config.vhd +++ b/designs/leon3-gr-cpci-xc4v/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 1; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-gr-cpci-xc4v/config.vhd.h b/designs/leon3-gr-cpci-xc4v/config.vhd.h index aa697b1b..707841c6 100644 --- a/designs/leon3-gr-cpci-xc4v/config.vhd.h +++ b/designs/leon3-gr-cpci-xc4v/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-gr-cpci-xc4v/lconfig.tk b/designs/leon3-gr-cpci-xc4v/lconfig.tk index 4c45aea0..3d7d88d7 100755 --- a/designs/leon3-gr-cpci-xc4v/lconfig.tk +++ b/designs/leon3-gr-cpci-xc4v/lconfig.tk @@ -2106,24 +2106,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2195,20 +2194,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2341,9 +2337,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3154,7 +3147,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3204,12 +3197,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3240,12 +3232,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5374,7 +5365,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5639,6 +5629,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -6104,7 +6095,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6227,10 +6217,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -6282,6 +6271,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_31 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-gr-cpci-xc4v/leon3mp.vhd b/designs/leon3-gr-cpci-xc4v/leon3mp.vhd index 767e711d..b6213b74 100644 --- a/designs/leon3-gr-cpci-xc4v/leon3mp.vhd +++ b/designs/leon3-gr-cpci-xc4v/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-cpci-xc4v/testbench.vhd b/designs/leon3-gr-cpci-xc4v/testbench.vhd index d759961d..5e2f8213 100644 --- a/designs/leon3-gr-cpci-xc4v/testbench.vhd +++ b/designs/leon3-gr-cpci-xc4v/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-cpci-xc4v/tkconfig.h b/designs/leon3-gr-cpci-xc4v/tkconfig.h index 772f4978..65480af9 100644 --- a/designs/leon3-gr-cpci-xc4v/tkconfig.h +++ b/designs/leon3-gr-cpci-xc4v/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-pci-xc2v3000/.config b/designs/leon3-gr-pci-xc2v3000/.config index 82c9130e..d78edfab 100644 --- a/designs/leon3-gr-pci-xc2v3000/.config +++ b/designs/leon3-gr-pci-xc2v3000/.config @@ -168,7 +168,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -254,7 +253,6 @@ CONFIG_DSU_IPLSB=0034 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000006 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Memory controllers diff --git a/designs/leon3-gr-pci-xc2v3000/config.h b/designs/leon3-gr-pci-xc2v3000/config.h index 4365b184..ec270401 100644 --- a/designs/leon3-gr-pci-xc2v3000/config.h +++ b/designs/leon3-gr-pci-xc2v3000/config.h @@ -163,7 +163,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -243,7 +242,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000006 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Memory controllers */ diff --git a/designs/leon3-gr-pci-xc2v3000/config.help b/designs/leon3-gr-pci-xc2v3000/config.help index 209c8fcf..9d2abb1c 100644 --- a/designs/leon3-gr-pci-xc2v3000/config.help +++ b/designs/leon3-gr-pci-xc2v3000/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-gr-pci-xc2v3000/config.vhd b/designs/leon3-gr-pci-xc2v3000/config.vhd index b4eec7e1..909663ae 100644 --- a/designs/leon3-gr-pci-xc2v3000/config.vhd +++ b/designs/leon3-gr-pci-xc2v3000/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-gr-pci-xc2v3000/config.vhd.h b/designs/leon3-gr-pci-xc2v3000/config.vhd.h index 02977771..4355f4f8 100644 --- a/designs/leon3-gr-pci-xc2v3000/config.vhd.h +++ b/designs/leon3-gr-pci-xc2v3000/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-gr-pci-xc2v3000/lconfig.tk b/designs/leon3-gr-pci-xc2v3000/lconfig.tk index 3a61e4ca..b6721b32 100755 --- a/designs/leon3-gr-pci-xc2v3000/lconfig.tk +++ b/designs/leon3-gr-pci-xc2v3000/lconfig.tk @@ -2078,24 +2078,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2167,20 +2166,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2313,9 +2309,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3126,7 +3119,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3176,12 +3169,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3212,12 +3204,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4853,7 +4844,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5070,6 +5060,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5527,7 +5518,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5650,10 +5640,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -5707,6 +5696,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd b/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd index 29c9c8d2..b8a050b0 100644 --- a/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd +++ b/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-pci-xc2v3000/testbench.vhd b/designs/leon3-gr-pci-xc2v3000/testbench.vhd index 288b146b..af80cda6 100644 --- a/designs/leon3-gr-pci-xc2v3000/testbench.vhd +++ b/designs/leon3-gr-pci-xc2v3000/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-pci-xc2v3000/tkconfig.h b/designs/leon3-gr-pci-xc2v3000/tkconfig.h index 45cadabe..56b7768f 100644 --- a/designs/leon3-gr-pci-xc2v3000/tkconfig.h +++ b/designs/leon3-gr-pci-xc2v3000/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-pci-xc5v/.config b/designs/leon3-gr-pci-xc5v/.config index ed5bfa72..c379df5b 100644 --- a/designs/leon3-gr-pci-xc5v/.config +++ b/designs/leon3-gr-pci-xc5v/.config @@ -173,7 +173,6 @@ CONFIG_DCACHE_ALGOLRR=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set @@ -239,7 +238,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=0d0007 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Memory controllers diff --git a/designs/leon3-gr-pci-xc5v/config.h b/designs/leon3-gr-pci-xc5v/config.h index d4ab638e..27df15f5 100644 --- a/designs/leon3-gr-pci-xc5v/config.h +++ b/designs/leon3-gr-pci-xc5v/config.h @@ -168,7 +168,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM @@ -228,7 +227,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 0d0007 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Memory controllers */ diff --git a/designs/leon3-gr-pci-xc5v/config.help b/designs/leon3-gr-pci-xc5v/config.help index e6985019..4a5b81e3 100644 --- a/designs/leon3-gr-pci-xc5v/config.help +++ b/designs/leon3-gr-pci-xc5v/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-gr-pci-xc5v/config.vhd b/designs/leon3-gr-pci-xc5v/config.vhd index 4269c6e3..aee02a5a 100644 --- a/designs/leon3-gr-pci-xc5v/config.vhd +++ b/designs/leon3-gr-pci-xc5v/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 1; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-gr-pci-xc5v/config.vhd.h b/designs/leon3-gr-pci-xc5v/config.vhd.h index aa5cf500..803c97b9 100644 --- a/designs/leon3-gr-pci-xc5v/config.vhd.h +++ b/designs/leon3-gr-pci-xc5v/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-gr-pci-xc5v/lconfig.tk b/designs/leon3-gr-pci-xc5v/lconfig.tk index 81b89b7d..e1083eb5 100755 --- a/designs/leon3-gr-pci-xc5v/lconfig.tk +++ b/designs/leon3-gr-pci-xc5v/lconfig.tk @@ -2104,24 +2104,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2193,20 +2192,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2339,9 +2335,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3160,7 +3153,7 @@ proc menu12 {w title} { hex $w.config.f 12 8 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 9 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 10 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 11 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 11 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3212,12 +3205,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x8.l configure -state normal; } else {.menu12.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x8.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x9.l configure -state normal; } else {.menu12.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x9.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x10 normal {n l y}} else {configure_entry .menu12.config.f.x10 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x11 normal {n l y}} else {configure_entry .menu12.config.f.x11 disabled {y n l}} } @@ -3255,12 +3247,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5627,7 +5618,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5938,6 +5928,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -6402,7 +6393,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6532,10 +6522,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -6587,6 +6576,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_32 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-gr-pci-xc5v/leon3mp.vhd b/designs/leon3-gr-pci-xc5v/leon3mp.vhd index 2c1f6c94..162d321b 100644 --- a/designs/leon3-gr-pci-xc5v/leon3mp.vhd +++ b/designs/leon3-gr-pci-xc5v/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-pci-xc5v/testbench.vhd b/designs/leon3-gr-pci-xc5v/testbench.vhd index 2fba5ec7..015957ee 100644 --- a/designs/leon3-gr-pci-xc5v/testbench.vhd +++ b/designs/leon3-gr-pci-xc5v/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-pci-xc5v/tkconfig.h b/designs/leon3-gr-pci-xc5v/tkconfig.h index 769de3d7..42706240 100644 --- a/designs/leon3-gr-pci-xc5v/tkconfig.h +++ b/designs/leon3-gr-pci-xc5v/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-xc3s-1500/.config b/designs/leon3-gr-xc3s-1500/.config index 3856905c..ffdddd01 100644 --- a/designs/leon3-gr-xc3s-1500/.config +++ b/designs/leon3-gr-xc3s-1500/.config @@ -164,7 +164,6 @@ CONFIG_DCACHE_SZ4=y CONFIG_DCACHE_LZ16=y # CONFIG_DCACHE_LZ32 is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -251,7 +250,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000008 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-gr-xc3s-1500/config.h b/designs/leon3-gr-xc3s-1500/config.h index 0e1fb47f..17525edb 100644 --- a/designs/leon3-gr-xc3s-1500/config.h +++ b/designs/leon3-gr-xc3s-1500/config.h @@ -159,7 +159,6 @@ #define CONFIG_DCACHE_LZ16 1 #undef CONFIG_DCACHE_LZ32 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -240,7 +239,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000008 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-gr-xc3s-1500/config.help b/designs/leon3-gr-xc3s-1500/config.help index 9cb18659..852ba9c6 100644 --- a/designs/leon3-gr-xc3s-1500/config.help +++ b/designs/leon3-gr-xc3s-1500/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-gr-xc3s-1500/config.vhd b/designs/leon3-gr-xc3s-1500/config.vhd index cea96b84..300cb46c 100644 --- a/designs/leon3-gr-xc3s-1500/config.vhd +++ b/designs/leon3-gr-xc3s-1500/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-gr-xc3s-1500/config.vhd.h b/designs/leon3-gr-xc3s-1500/config.vhd.h index 629c3143..ed2e28d0 100644 --- a/designs/leon3-gr-xc3s-1500/config.vhd.h +++ b/designs/leon3-gr-xc3s-1500/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-gr-xc3s-1500/lconfig.tk b/designs/leon3-gr-xc3s-1500/lconfig.tk index 2c771c50..9b1a6e3c 100755 --- a/designs/leon3-gr-xc3s-1500/lconfig.tk +++ b/designs/leon3-gr-xc3s-1500/lconfig.tk @@ -2092,24 +2092,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2181,20 +2180,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2327,9 +2323,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3148,7 +3141,7 @@ proc menu12 {w title} { hex $w.config.f 12 8 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 9 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 10 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 11 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 11 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3200,12 +3193,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x8.l configure -state normal; } else {.menu12.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x8.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x9.l configure -state normal; } else {.menu12.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x9.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x10 normal {n l y}} else {configure_entry .menu12.config.f.x10 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x11 normal {n l y}} else {configure_entry .menu12.config.f.x11 disabled {y n l}} } @@ -3243,12 +3235,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5245,7 +5236,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5496,6 +5486,7 @@ set CONFIG_SVGA_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5956,7 +5947,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6086,10 +6076,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6147,6 +6136,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_32 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-gr-xc3s-1500/leon3mp.vhd b/designs/leon3-gr-xc3s-1500/leon3mp.vhd index d75b86cb..13505e29 100644 --- a/designs/leon3-gr-xc3s-1500/leon3mp.vhd +++ b/designs/leon3-gr-xc3s-1500/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-xc3s-1500/testbench.vhd b/designs/leon3-gr-xc3s-1500/testbench.vhd index 51929fee..dd258c92 100644 --- a/designs/leon3-gr-xc3s-1500/testbench.vhd +++ b/designs/leon3-gr-xc3s-1500/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-xc3s-1500/tkconfig.h b/designs/leon3-gr-xc3s-1500/tkconfig.h index 5f2176fe..afadeeeb 100644 --- a/designs/leon3-gr-xc3s-1500/tkconfig.h +++ b/designs/leon3-gr-xc3s-1500/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd b/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd index b1ee2d14..b96a3b45 100644 --- a/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd +++ b/designs/leon3-gr-xc3s-1500/vga_clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-xc6s/.config b/designs/leon3-gr-xc6s/.config index a9d73c02..4a220614 100644 --- a/designs/leon3-gr-xc6s/.config +++ b/designs/leon3-gr-xc6s/.config @@ -169,7 +169,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -255,6 +254,7 @@ CONFIG_DSU_IPMSB=C0A8 CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000000 +# CONFIG_DSU_ETH_PROG is not set # # Peripherals @@ -299,7 +299,12 @@ CONFIG_AHBSTAT_NFTSLV=1 # Ethernet # CONFIG_GRETH_ENABLE=y -CONFIG_GRETH_GIGA=y +# CONFIG_GRETH_GIGA is not set +# CONFIG_GRETH_FIFO4 is not set +CONFIG_GRETH_FIFO8=y +# CONFIG_GRETH_FIFO16 is not set +# CONFIG_GRETH_FIFO32 is not set +# CONFIG_GRETH_FIFO64 is not set # CONFIG_GRETH_FT is not set # @@ -320,12 +325,13 @@ CONFIG_UA1_FIFO4=y CONFIG_IRQ3_ENABLE=y # CONFIG_IRQ3_SEC is not set CONFIG_GPT_ENABLE=y -CONFIG_GPT_NTIM=2 +CONFIG_GPT_NTIM=3 CONFIG_GPT_SW=8 CONFIG_GPT_TW=32 CONFIG_GPT_IRQ=8 CONFIG_GPT_SEPIRQ=y -# CONFIG_GPT_WDOGEN is not set +CONFIG_GPT_WDOGEN=y +CONFIG_GPT_WDOG=FFFF CONFIG_GRGPIO_ENABLE=y CONFIG_GRGPIO_WIDTH=8 CONFIG_GRGPIO_IMASK=0000 diff --git a/designs/leon3-gr-xc6s/Makefile b/designs/leon3-gr-xc6s/Makefile index 66a5ed0c..61d2f073 100644 --- a/designs/leon3-gr-xc6s/Makefile +++ b/designs/leon3-gr-xc6s/Makefile @@ -30,7 +30,6 @@ EFFORT=high ISEMAPOPT=-timing XSTOPT= SYNPOPT="set_option -maxfan 100; set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0" -GRLIB_SIMULATOR=ModelSim-SE VHDLOPTSYNFILES= mig37/mig_37/user_design/rtl/iodrp_controller.vhd \ mig37/mig_37/user_design/rtl/iodrp_mcb_controller.vhd \ mig37/mig_37/user_design/rtl/mcb_raw_wrapper.vhd \ @@ -63,7 +62,7 @@ LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci ambatest ddr \ leon4 leon4v0 l2cache gr1553b iommu ascs slink pwm \ hcan -#FILEADD = MCB.vhd +FILEADD = MCB.vhd FILESKIP = grcan.vhd ddr2.v mobile_ddr.v include $(GRLIB)/bin/Makefile diff --git a/designs/leon3-gr-xc6s/README.txt b/designs/leon3-gr-xc6s/README.txt index 791ca4d8..fcb177b2 100644 --- a/designs/leon3-gr-xc6s/README.txt +++ b/designs/leon3-gr-xc6s/README.txt @@ -24,14 +24,14 @@ library, do as follows: This will ONLY work with correct version of ISE installed, and the XILINX variable properly set in the shell. For ISE13 it is recommened -to use the 'ise' make target and for ISE14 to use the 'planAhead' +to use the 'ise' make target and for ISE14 to use the 'planahead' target. To synthesize the design, do make ise (ISE13) or - make planAhead (ISE14) + make planahead (ISE14) and then @@ -98,31 +98,6 @@ Design specifics voltage of 1.8V and the design of the USB device core it is unlikely that the required timing for the USB interface can be reached. The kit is not suitable for use with the USB IP cores. - -* The pad skew for the Ethernet interface needs to be adjusted in order - to get the Ethernet and edcl interface to work properly. The PAD - skew can be adjusted via register in the Ethernet PHY on the board - - To adjust the Ethernet/RGMII timing on GR-XC6S board via GRMON2: - - wmdio 1 0xB 0x8104 - wmdio 1 0xC 0xF070 - wmdio 1 0xB 0x8105 - wmdio 1 0xC 0x0000 - - A script has been added to adjust the timing. To run the script - from GRMON type: - - batch SetMaxClockDelay - - Ouput from script should look like: - - Writing dev0: PHY addr: 1 Reg addr: 11 Value: 8104 - Writing dev0: PHY addr: 1 Reg addr: 12 Value: f070 - Writing dev0: PHY addr: 1 Reg addr: 11 Value: 8105 - Writing dev0: PHY addr: 1 Reg addr: 12 Value: 0 - Writing dev0: PHY addr: 1 Reg addr: 11 Value: 104 - Reading dev0: PHY addr: 1 Reg addr: 13 Value: f077 * Example output from GRMON is: diff --git a/designs/leon3-gr-xc6s/SetDefaultDelay b/designs/leon3-gr-xc6s/SetDefaultDelay new file mode 100644 index 00000000..1c366f10 --- /dev/null +++ b/designs/leon3-gr-xc6s/SetDefaultDelay @@ -0,0 +1,16 @@ +edcl 192.168.0.170 +# Do not enable (set to 1) register 4h bit [11] for Asymmetric PAUSE support. +wmdio 1 0x4 0x01e1 +wmdio 1 0x1c 0x0080 +# Set Default values +wmdio 1 0xB 0x8104 +wmdio 1 0xC 0x7777 +wmdio 1 0xB 0x8105 +wmdio 1 0xC 0x7777 +after 100 +wmdio 1 0xB 0x0104 +mdio 1 0xD +wmdio 1 0xB 0x0105 +mdio 1 0xD +after 100 +mem 0x80001800 64 diff --git a/designs/leon3-gr-xc6s/SetMaxClockDelay b/designs/leon3-gr-xc6s/SetMaxClockDelay index fe08219a..4a8d3982 100644 --- a/designs/leon3-gr-xc6s/SetMaxClockDelay +++ b/designs/leon3-gr-xc6s/SetMaxClockDelay @@ -1,5 +1,5 @@ wmdio 1 0xB 0x8104 -wmdio 1 0xC 0xF070 +wmdio 1 0xC 0xF020 wmdio 1 0xB 0x8105 wmdio 1 0xC 0x0000 wmdio 1 0xB 0x0104 diff --git a/designs/leon3-gr-xc6s/ahb2mig_grxc6s_2p.vhd b/designs/leon3-gr-xc6s/ahb2mig_grxc6s_2p.vhd index 8b6ef55f..f45b8a2a 100644 --- a/designs/leon3-gr-xc6s/ahb2mig_grxc6s_2p.vhd +++ b/designs/leon3-gr-xc6s/ahb2mig_grxc6s_2p.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-xc6s/config.h b/designs/leon3-gr-xc6s/config.h index 0154e830..8fbe799d 100644 --- a/designs/leon3-gr-xc6s/config.h +++ b/designs/leon3-gr-xc6s/config.h @@ -164,7 +164,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -244,6 +243,7 @@ #define CONFIG_DSU_IPLSB 0033 #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000000 +#undef CONFIG_DSU_ETH_PROG /* * Peripherals */ @@ -281,7 +281,12 @@ * Ethernet */ #define CONFIG_GRETH_ENABLE 1 -#define CONFIG_GRETH_GIGA 1 +#undef CONFIG_GRETH_GIGA +#undef CONFIG_GRETH_FIFO4 +#define CONFIG_GRETH_FIFO8 1 +#undef CONFIG_GRETH_FIFO16 +#undef CONFIG_GRETH_FIFO32 +#undef CONFIG_GRETH_FIFO64 #undef CONFIG_GRETH_FT /* * CAN @@ -300,12 +305,13 @@ #define CONFIG_IRQ3_ENABLE 1 #undef CONFIG_IRQ3_SEC #define CONFIG_GPT_ENABLE 1 -#define CONFIG_GPT_NTIM (2) +#define CONFIG_GPT_NTIM (3) #define CONFIG_GPT_SW (8) #define CONFIG_GPT_TW (32) #define CONFIG_GPT_IRQ (8) #define CONFIG_GPT_SEPIRQ 1 -#undef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 1 +#define CONFIG_GPT_WDOG FFFF #define CONFIG_GRGPIO_ENABLE 1 #define CONFIG_GRGPIO_WIDTH (8) #define CONFIG_GRGPIO_IMASK 0000 diff --git a/designs/leon3-gr-xc6s/config.help b/designs/leon3-gr-xc6s/config.help index 54c88a19..ecf195ed 100644 --- a/designs/leon3-gr-xc6s/config.help +++ b/designs/leon3-gr-xc6s/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-gr-xc6s/config.vhd b/designs/leon3-gr-xc6s/config.vhd index b3c3f550..5418169d 100644 --- a/designs/leon3-gr-xc6s/config.vhd +++ b/designs/leon3-gr-xc6s/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -156,7 +156,7 @@ package config is constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core constant CFG_GRETH : integer := 1; - constant CFG_GRETH1G : integer := 1; + constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 8; constant CFG_GRETH_FT : integer := 0; @@ -185,13 +185,13 @@ package config is -- Modular timer constant CFG_GPT_ENABLE : integer := 1; - constant CFG_GPT_NTIM : integer := (2); + constant CFG_GPT_NTIM : integer := (3); constant CFG_GPT_SW : integer := (8); constant CFG_GPT_TW : integer := (32); constant CFG_GPT_IRQ : integer := (8); constant CFG_GPT_SEPIRQ : integer := 1; - constant CFG_GPT_WDOGEN : integer := 0; - constant CFG_GPT_WDOG : integer := 16#0#; + constant CFG_GPT_WDOGEN : integer := 1; + constant CFG_GPT_WDOG : integer := 16#FFFF#; -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; diff --git a/designs/leon3-gr-xc6s/config.vhd.h b/designs/leon3-gr-xc6s/config.vhd.h index 2378f6cf..149dfa07 100644 --- a/designs/leon3-gr-xc6s/config.vhd.h +++ b/designs/leon3-gr-xc6s/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-gr-xc6s/lconfig.tk b/designs/leon3-gr-xc6s/lconfig.tk index d75ed811..5c58114e 100755 --- a/designs/leon3-gr-xc6s/lconfig.tk +++ b/designs/leon3-gr-xc6s/lconfig.tk @@ -2094,24 +2094,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2183,20 +2182,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2329,9 +2325,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3212,7 +3205,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3262,12 +3255,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3298,12 +3290,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5788,7 +5779,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -6065,6 +6055,7 @@ set CONFIG_LEON3FT_PRESENT 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_MODULES 4 proc writeconfig {file1 file2} { set cfg [open $file1 w] @@ -6509,7 +6500,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6653,10 +6643,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6772,6 +6761,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-gr-xc6s/leon3mp.ucf b/designs/leon3-gr-xc6s/leon3mp.ucf index ad6c9f3f..dc40d75d 100644 --- a/designs/leon3-gr-xc6s/leon3mp.ucf +++ b/designs/leon3-gr-xc6s/leon3mp.ucf @@ -28,7 +28,7 @@ NET "mig_gen.ddrc/MCB_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_ter # --- MIG39 --- INST "mig_gen.ddrc/MCB_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG; - + ############################################################################ # Main clocks ############################################################################ @@ -44,13 +44,36 @@ TIMESPEC "TS_clk2" = PERIOD "clk2" 5.000 ns HIGH 50.00%; # ------------------------------- # RGMII interface +# Allow non dedicated clock routing (Onlu needed if clock mux is used) +PIN "rgmii0/useclkmux0.tecclkmux.clkmux1000/tec.xil.buf/buf.O" CLOCK_DEDICATED_ROUTE = FALSE; + # -- GTX clock inout -NET "clk125" TNM_NET = "clk125"; -TIMESPEC "TS_clk125" = PERIOD "clk125" 8.000 ns HIGH 50.00%; +# Only used when external GTX clock is used +#NET "clk125" TNM_NET = "clk125"; +#TIMESPEC "TS_clk125" = PERIOD "clk125" 8.000 ns HIGH 50.00%; + +# To be used for internal GTX clock generation when 10/100 mode is used +PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE; +PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE; +PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE; NET "erx_clk" TNM_NET = "erx_clk"; TIMESPEC "TS_erx_clk" = PERIOD "erx_clk" 8.000 ns HIGH 50.00%; +NET "mig_gen.ddrc/MCB_inst/memc3_infrastructure_inst/clk0" TNM_NET = clkm; + +# All mode +NET "rgmii0/gmiii_gtx_clk" TNM_NET = "clk125_mux"; +TIMESPEC TS_clk125_mux = PERIOD "clk125_mux" 8 ns HIGH 50.00%; +TIMESPEC "TS_clkm_gtx_clk" = FROM "clkm" TO "clk125_mux" TIG; +TIMESPEC "TS_gtx_clk_clkm" = FROM "clk125_mux" TO "clkm" TIG; + +# Giga mode only +NET "clk_125_bufg" TNM_NET = "clk125_bufg"; +TIMESPEC TS_clk125_bufg = PERIOD "clk125_bufg" 8 ns HIGH 50.00%; +TIMESPEC "TS_clkm_gtx_clk_2" = FROM "clkm" TO "clk125_bufg" TIG; +TIMESPEC "TS_gtx_clk_clkm_2" = FROM "clk125_bufg" TO "clkm" TIG; + INST "etx_clk" SLEW = FAST; INST "etxd* " SLEW = FAST; INST "etx_en " SLEW = FAST; @@ -62,14 +85,26 @@ INST "erx_dv" TNM = IN_RGMII; # http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ug612.pdf # Use when IODELAY is inserted -TIMEGRP "IN_RGMII" OFFSET = IN 1.1 ns VALID 2.2 ns BEFORE "erx_clk" RISING; -TIMEGRP "IN_RGMII" OFFSET = IN 1.1 ns VALID 2.2 ns BEFORE "erx_clk" FALLING; +#TIMEGRP "IN_RGMII" OFFSET = IN 5.1 ns VALID 2.2 ns BEFORE "erx_clk" RISING; +#TIMEGRP "IN_RGMII" OFFSET = IN 5.1 ns VALID 2.2 ns BEFORE "erx_clk" FALLING; # No IODELAY # Please, note that these will fail but will be fixed by setup script in GRMON2 #TIMEGRP "IN_RGMII" OFFSET = IN 1.5 ns VALID 2.25 ns BEFORE "erx_clk" RISING; #TIMEGRP "IN_RGMII" OFFSET = IN 1.5 ns VALID 2.25 ns BEFORE "erx_clk" FALLING; +# Use when IODELAY is inserted +NET "etxd[0]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" RISING; +NET "etxd[0]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" FALLING; +NET "etxd[1]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" RISING; +NET "etxd[1]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" FALLING; +NET "etxd[2]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" RISING; +NET "etxd[2]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" FALLING; +NET "etxd[3]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" RISING; +NET "etxd[4]" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" FALLING; +NET "etx_en" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" RISING; +NET "etx_en" OFFSET = OUT 2.25 ns AFTER "clk125" REFERENCE_PIN "etx_clk" FALLING; + ############################################################################ # I/O STANDARDS AND LOCATIONS ############################################################################ diff --git a/designs/leon3-gr-xc6s/leon3mp.vhd b/designs/leon3-gr-xc6s/leon3mp.vhd index e4ceb602..1ea0c20f 100644 --- a/designs/leon3-gr-xc6s/leon3mp.vhd +++ b/designs/leon3-gr-xc6s/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -46,7 +46,6 @@ library unisim; use unisim.all; -- pragma translate_on - library esa; use esa.memoryctrl.all; @@ -92,10 +91,6 @@ entity leon3mp is ddr_rzq : inout std_ulogic; ddr_zio : inout std_ulogic; - -- dsuen : in std_ulogic; -- dip swtich 7 --- dsubre : in std_ulogic; -- switch 9 --- dsuact : out std_ulogic; -- led (0) - txd1 : out std_ulogic; -- UART1 tx data rxd1 : in std_ulogic; -- UART1 rx data ctsn1 : in std_ulogic; -- UART1 ctsn @@ -132,8 +127,6 @@ entity leon3mp is dvi_iic_scl : inout std_logic; dvi_iic_sda : inout std_logic; - - tft_lcd_data : out std_logic_vector(11 downto 0); tft_lcd_clk_p : out std_ulogic; tft_lcd_clk_n : out std_ulogic; @@ -142,7 +135,6 @@ entity leon3mp is tft_lcd_de : out std_ulogic; tft_lcd_reset_b : out std_ulogic; - spw_clk : in std_ulogic; spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1); spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1); @@ -158,14 +150,6 @@ entity leon3mp is spi_clk : out std_ulogic; spi_mosi : out std_ulogic - -- SD Card interface (SD SPI interface) --- sdata : inout std_ulogic_vector(3 downto 0); --- sd_clk : out std_ulogic; --- spi_cmd : out std_ulogic; - --- sd_prot : in std_logic; --- sd_detect : in std_logic - ); end; @@ -210,6 +194,9 @@ attribute syn_netlist_hierarchy of rtl : architecture is false; constant use_eth_input_delay : integer := 1; constant use_eth_output_delay : integer := 1; +constant use_eth_data_output_delay : integer := 0; +constant use_eth_input_delay_clk : integer := 0; +constant use_gtx_clk : integer := 0; constant blength : integer := 12; constant fifodepth : integer := 8; @@ -252,7 +239,7 @@ signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); signal dsui : dsu_in_type; signal dsuo : dsu_out_type; -signal gmiii, rgmiii, rgmiii_buf : eth_in_type; +signal gmiii, rgmiii, rgmiii_buf, rgmii_pad : eth_in_type; signal gmiio, rgmiio : eth_out_type; signal gpti : gptimer_in_type; @@ -336,7 +323,7 @@ constant SPW_LOOP_BACK : integer := 0; signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen. signal clk_sel : std_logic_vector(1 downto 0); signal clkvga, clkvga_p, clkvga_n : std_ulogic; -signal clk_125 : std_ulogic; +signal clk_125, clk_125_pll, clk_125_bufg : std_ulogic; signal nerror : std_ulogic; attribute keep : boolean; @@ -831,7 +818,7 @@ begin hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 14, paddr => 14, pirq => 6, memtech => memtech, mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO, - nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1, + nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G) @@ -849,15 +836,46 @@ begin noethoutdelay0 : if (use_eth_output_delay = 0) generate rgmiio_tx_clk <= rgmiio.tx_clk; - rgmiio_tx_en <= rgmiio.tx_en; + end generate; + + noethdataoutdelay0 : if (use_eth_data_output_delay = 0) generate + rgmiio_tx_en <= rgmiio.tx_en; rgmiio_txd <= rgmiio.txd(3 downto 0); end generate; ethindelay0 : if (use_eth_input_delay /= 0) generate + + erx_clk0 : if (use_eth_input_delay_clk /= 0) generate + delay_rgmii_rx_clk : IODELAY2 generic map( + DELAY_SRC => "IDATAIN", + IDELAY_TYPE => "FIXED", + DATA_RATE => "DDR", + IDELAY_VALUE => 0 -- (See table 39 in Xilinx ds162.pdf) + ) + port map( + IDATAIN => rgmiii_buf.rx_clk, + T => '1', + ODATAIN => '0', + CAL => '0', + IOCLK0 => '0', + IOCLK1 => '0', + CLK => '0', + INC => '0', + CE => '0', + RST => '0', + BUSY => OPEN, + DATAOUT => rgmiii.rx_clk, + DATAOUT2 => OPEN, + TOUT => OPEN, + DOUT => OPEN + ); + end generate; + delay_rgmii_rx_ctl0 : IODELAY2 generic map( DELAY_SRC => "IDATAIN", IDELAY_TYPE => "FIXED", - IDELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf) + DATA_RATE => "DDR", + IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf) ) port map( IDATAIN => rgmiii_buf.rx_dv, @@ -881,7 +899,8 @@ begin delay_rgmii_rxd0 : IODELAY2 generic map( DELAY_SRC => "IDATAIN", IDELAY_TYPE => "FIXED", - IDELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf) + DATA_RATE => "DDR", + IDELAY_VALUE => 80 -- (See table 39 in Xilinx ds162.pdf) ) port map( IDATAIN => rgmiii_buf.rxd(i), @@ -907,7 +926,8 @@ begin delay_rgmii_tx_clk0 : IODELAY2 generic map( DELAY_SRC => "ODATAIN", IDELAY_TYPE => "FIXED", - ODELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf) + DATA_RATE => "DDR", + ODELAY_VALUE => 10 -- (See table 39 in Xilinx ds162.pdf) ) port map( IDATAIN => '0', @@ -926,10 +946,13 @@ begin TOUT => OPEN, DOUT => rgmiio_tx_clk ); - + end generate; + + ethoutdatadelay0 : if (use_eth_data_output_delay /= 0) generate delay_rgmii_tx_en0 : IODELAY2 generic map( DELAY_SRC => "ODATAIN", IDELAY_TYPE => "FIXED", + DATA_RATE => "DDR", ODELAY_VALUE => 0 ) port map( @@ -954,6 +977,7 @@ begin delay_rgmii_txd0 : IODELAY2 generic map( DELAY_SRC => "ODATAIN", IDELAY_TYPE => "FIXED", + DATA_RATE => "DDR", ODELAY_VALUE => 0 ) port map( @@ -976,14 +1000,26 @@ begin end generate; end generate; - rgmii0 : rgmii generic map (15, 16#010# , 16#ff0#, fabtech, CFG_GRETH1G, 1, 0, 1) - port map (rstn, rgmiii.gtx_clk, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15)); + rgmii0 : rgmii generic map (pindex => 15, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech, + gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 0, + pirq => 15, use90degtxclk => 0) + port map (rstn, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15)); + ethpads : if (CFG_GRETH = 1) generate -- eth pads etxc_pad : outpad generic map (tech => padtech) port map (etx_clk, rgmiio_tx_clk); - erxc_pad : clkpad generic map (tech => padtech, arch => 2) - port map (erx_clk, rgmiii.rx_clk); + + erx_clk1 : if (use_eth_input_delay_clk = 0) generate + erxc_pad : clkpad generic map (tech => padtech, arch => 2) + port map (erx_clk, rgmiii.rx_clk); + end generate; + + erx_clk2 : if (use_eth_input_delay_clk /= 0) generate + erxc_pad : inpad generic map (tech => padtech) + port map (erx_clk, rgmii_pad.rx_clk); + erxc_bufg0 : BUFG port map (O => rgmiii_buf.rx_clk, I => rgmii_pad.rx_clk); + end generate; erxd_pad : inpadv generic map (tech => padtech, width => 4) port map (erxd, rgmiii_buf.rxd(3 downto 0)); @@ -1003,13 +1039,35 @@ begin emdint_pad : inpad generic map (tech => padtech) port map (emdint, rgmiii.mdint); - -- Incoming 125Mhz ref clock - clk125_pad : clkpad generic map (tech => padtech, arch => 2) - port map (clk125, rgmiii.gtx_clk); + gtx_clk0 : if (use_gtx_clk = 0) generate + -- Use MIG PLL + -- Add to UCF (only if there is no BUFG left): + -- PIN "ethpads.gtx_clk0.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE; + clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125); + rgmiii.gtx_clk <= clk_125_bufg; + end generate; + + gtx_clk1 : if (use_gtx_clk = 1) generate + -- Incoming 125Mhz ref clock + clk125_pad : clkpad generic map (tech => padtech, arch => 3) + port map (clk125, rgmiii.gtx_clk); + end generate; + + gtx_clk2 : if (use_gtx_clk = 2) generate + -- Use Separate PLL + -- Add to UCF (only if there is no BUFG left): + -- PIN "ethpads.gtx_clk2.clkgen0/xc3s.v/bufg0.O" CLOCK_DEDICATED_ROUTE =FALSE; + -- PIN "ethpads.gtx_clk2.clk_125_bufg0.O" CLOCK_DEDICATED_ROUTE = FALSE; + cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; + clkgen0 : clkgen -- clock generator + generic map (clktech, 5, 2, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ) + port map (clkm, clkm, clk_125_pll, open, open, open, open, cgi2, cgo2, open, open, open); + clk_125_bufg0 : BUFG port map (O => clk_125_bufg, I => clk_125_pll); + rgmiii.gtx_clk <= clk_125_bufg; + end generate; end generate; - ----------------------------------------------------------------------- --- AHB RAM ---------------------------------------------------------- ----------------------------------------------------------------------- diff --git a/designs/leon3-gr-xc6s/ram.srec b/designs/leon3-gr-xc6s/ram.srec index cb6b90ef..17e16fa8 100755 --- a/designs/leon3-gr-xc6s/ram.srec +++ b/designs/leon3-gr-xc6s/ram.srec @@ -1,14 +1,14 @@ -S00D0000736472616D2E7372656300 -S31540000000881000000910006B81C1238401000000A4 -S31540000010A1480000A75000001080203EAC102001EF +S00B000072616D2E73726563D9 +S31540000000881000000910007481C121F4010000002D +S31540000010A1480000A75000001080403EAC102001CF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006B81C522D8010000009C -S31540000050A14800002910006981C522540100000012 -S31540000060A14800002910006981C522C00100000096 +S31540000040A14800002910007481C521480100000024 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Public License as published by diff --git a/designs/leon3-gr-xc6s/systest.c b/designs/leon3-gr-xc6s/systest.c index 3b94b290..511f448d 100644 --- a/designs/leon3-gr-xc6s/systest.c +++ b/designs/leon3-gr-xc6s/systest.c @@ -1,11 +1,29 @@ +#include "gptimer.h" main() { + int addr=0x80000300; + struct gptimer *lr = (struct gptimer *) addr; + report_start(); +//gptimer_test(0x80000300, 8); + +leon3_test(1, 0x80000200, 0); + +//LEON3_BYPASS_STORE_PA(0x80000338, 0); +//LEON3_BYPASS_STORE_PA(0x80000334, 0xf); +//LEON3_BYPASS_STORE_PA(0x80000338, 0x4); +//LEON3_BYPASS_STORE_PA(0x80000338, 0x9); +lr->timer[2].control = 0; +lr->timer[2].reload = 0xf; +lr->timer[2].control = 0x4; +lr->timer[2].control = 0x9; +irqtest(0x80000200); +apbuart_test(0x80000100); - base_test(); +// base_test(); // svgactrl_test(0x80000600, 1, 0, 0x40200000, -1, 0, 0); // greth_test(0x80000e00); diff --git a/designs/leon3-gr-xc6s/testbench.vhd b/designs/leon3-gr-xc6s/testbench.vhd index aad99211..39e0dfaf 100644 --- a/designs/leon3-gr-xc6s/testbench.vhd +++ b/designs/leon3-gr-xc6s/testbench.vhd @@ -1,10 +1,10 @@ ------------------------------------------------------------------------------ +---------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -29,8 +29,6 @@ use gaisler.sim.all; library techmap; use techmap.gencomp.all; use work.debug.all; -library hynix; -use hynix.components.all; library grlib; use grlib.stdlib.all; @@ -75,7 +73,7 @@ signal writen : std_ulogic; signal GND : std_ulogic := '0'; signal VCC : std_ulogic := '1'; signal NC : std_ulogic := 'Z'; -signal wdogn : std_logic; +signal wdogn,wdogn_local : std_logic; signal txd1, rxd1 : std_logic; signal txd2, rxd2 : std_logic; @@ -156,6 +154,8 @@ signal led : std_logic_vector(3 downto 0); -- I/O port signal erx_crs : std_logic := '1'; signal etx_er : std_logic := '0'; + + constant lresp : boolean := false; begin @@ -163,15 +163,16 @@ begin -- clock and reset clk <= not clk after ct * 1 ns; - clk125 <= not clk125 after 4 ns; + clk125 <= not clk125 after 10 ns; --erx_clk <= not erx_clk after 4 ns; clk2 <= '0'; --not clk2 after 5 ns; - rst <= dsurst and wdogn; + rst <= dsurst and wdogn_local; rxd1 <= 'H'; ctsn1 <= '0'; rxd2 <= 'H'; ctsn2 <= '0'; ps2clk <= "HH"; ps2data <= "HH"; pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H'); wdogn <= 'H'; + wdogn_local <= 'H'; switch(7) <= '1'; switch(8) <= '0'; emdio <= 'H'; @@ -203,18 +204,15 @@ begin writen, oen); ddr2mem : if (CFG_MIG_DDR2 = 1) generate - ddr2mem0 : for i in 0 to 0 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => false, PUSCheckFlag => false, - index => i, bbits => 16, fname => sdramfile, fdelay => 340) - port map (DQ => ddr_dq(i*16+15 downto i*16), - LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2), - UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1), - LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas, - RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0), - ADDR => ddr_ad(12 downto 0), CKE => ddr_cke, - CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1)); - end generate; + u1: ddr2ram + generic map (width => 16, abits => 13, babits => 3, + colbits => 10, rowbits => 13, implbanks => 1, + fname => sdramfile, lddelay => (340 us), + speedbin => 1) + port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, + odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, + dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn); end generate; ps2devs: for i in 0 to 1 generate @@ -227,7 +225,24 @@ begin phy0 : if (CFG_GRETH = 1) generate emdio <= 'H'; p0: phy - generic map(address => 1) + generic map( + address => 1, + extended_regs => 1, + aneg => 1, + base100_t4 => 1, + base100_x_fd => 1, + base100_x_hd => 1, + fd_10 => 1, + hd_10 => 1, + base100_t2_fd => 1, + base100_t2_hd => 1, + base1000_x_fd => 1, + base1000_x_hd => 1, + base1000_t_fd => 1, + base1000_t_hd => 1, + rmii => 0, + rgmii => 1 + ) port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d, erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125); end generate; @@ -238,6 +253,20 @@ begin erx_dv <= erx_dv_d; end process; + wdognp : process + begin + + wdogn_local <= 'H'; + + if wdogn = '0' then + wdogn_local <= '0'; + wait for 1 ms; + end if; + + wait for 20 ns; + + end process; + data <= buskeep(data) after 5 ns; diff --git a/designs/leon3-gr-xc6s/tkconfig.h b/designs/leon3-gr-xc6s/tkconfig.h index a76f5d52..94fc2ddf 100644 --- a/designs/leon3-gr-xc6s/tkconfig.h +++ b/designs/leon3-gr-xc6s/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-gr-xc6s/vga_clkgen.vhd b/designs/leon3-gr-xc6s/vga_clkgen.vhd index b1ee2d14..b96a3b45 100644 --- a/designs/leon3-gr-xc6s/vga_clkgen.vhd +++ b/designs/leon3-gr-xc6s/vga_clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-gr-xc6s/wave.do b/designs/leon3-gr-xc6s/wave.do index d179177e..f0b9f8d2 100644 --- a/designs/leon3-gr-xc6s/wave.do +++ b/designs/leon3-gr-xc6s/wave.do @@ -1,119 +1,59 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /testbench/cpu/resetn -add wave -noupdate -format Logic /testbench/cpu/clk -add wave -noupdate -format Logic /testbench/cpu/clk2 -add wave -noupdate -format Logic /testbench/cpu/wdogn -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/address -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/data -add wave -noupdate -format Logic /testbench/cpu/oen -add wave -noupdate -format Logic /testbench/cpu/writen -add wave -noupdate -format Logic /testbench/cpu/romsn -add wave -noupdate -format Logic /testbench/cpu/ddr_clk -add wave -noupdate -format Logic /testbench/cpu/ddr_clkb -add wave -noupdate -format Logic /testbench/cpu/ddr_cke -add wave -noupdate -format Logic /testbench/cpu/ddr_odt -add wave -noupdate -format Logic /testbench/cpu/ddr_we -add wave -noupdate -format Logic /testbench/cpu/ddr_ras -add wave -noupdate -format Logic /testbench/cpu/ddr_cas -add wave -noupdate -format Literal /testbench/cpu/ddr_dm -add wave -noupdate -format Literal /testbench/cpu/ddr_dqs -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ddr_ad -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ddr_ba -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ddr_dq -add wave -noupdate -format Logic /testbench/cpu/ddr_rzq -add wave -noupdate -format Logic /testbench/cpu/ddr_zio -add wave -noupdate -format Logic /testbench/cpu/txd1 -add wave -noupdate -format Logic /testbench/cpu/rxd1 -add wave -noupdate -format Logic /testbench/cpu/ctsn1 -add wave -noupdate -format Logic /testbench/cpu/rtsn1 -add wave -noupdate -format Logic /testbench/cpu/txd2 -add wave -noupdate -format Logic /testbench/cpu/rxd2 -add wave -noupdate -format Logic /testbench/cpu/ctsn2 -add wave -noupdate -format Logic /testbench/cpu/rtsn2 -add wave -noupdate -format Logic /testbench/cpu/erx_clk -add wave -noupdate -format Logic /testbench/cpu/emdio -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/erxd -add wave -noupdate -format Logic /testbench/cpu/erx_dv -add wave -noupdate -format Logic /testbench/cpu/emdint -add wave -noupdate -format Logic /testbench/cpu/etx_clk -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/etxd -add wave -noupdate -format Logic /testbench/cpu/etx_en -add wave -noupdate -format Logic /testbench/cpu/emdc -add wave -noupdate -format Literal /testbench/cpu/pio -add wave -noupdate -format Literal /testbench/cpu/genio -add wave -noupdate -format Literal /testbench/cpu/switch -add wave -noupdate -format Literal /testbench/cpu/led -add wave -noupdate -format Literal /testbench/cpu/ps2clk -add wave -noupdate -format Literal /testbench/cpu/ps2data -add wave -noupdate -format Logic /testbench/cpu/iic_scl -add wave -noupdate -format Logic /testbench/cpu/iic_sda -add wave -noupdate -format Logic /testbench/cpu/ddc_scl -add wave -noupdate -format Logic /testbench/cpu/ddc_sda -add wave -noupdate -format Logic /testbench/cpu/dvi_iic_scl -add wave -noupdate -format Logic /testbench/cpu/dvi_iic_sda -add wave -noupdate -format Literal /testbench/cpu/tft_lcd_data -add wave -noupdate -format Logic /testbench/cpu/tft_lcd_clk_p -add wave -noupdate -format Logic /testbench/cpu/tft_lcd_clk_n -add wave -noupdate -format Logic /testbench/cpu/tft_lcd_hsync -add wave -noupdate -format Logic /testbench/cpu/tft_lcd_vsync -add wave -noupdate -format Logic /testbench/cpu/tft_lcd_de -add wave -noupdate -format Logic /testbench/cpu/tft_lcd_reset_b -add wave -noupdate -format Logic /testbench/cpu/spw_clk -add wave -noupdate -format Literal /testbench/cpu/spw_rxdp -add wave -noupdate -format Literal /testbench/cpu/spw_rxdn -add wave -noupdate -format Literal /testbench/cpu/spw_rxsp -add wave -noupdate -format Literal /testbench/cpu/spw_rxsn -add wave -noupdate -format Literal /testbench/cpu/spw_txdp -add wave -noupdate -format Literal /testbench/cpu/spw_txdn -add wave -noupdate -format Literal /testbench/cpu/spw_txsp -add wave -noupdate -format Literal /testbench/cpu/spw_txsn -add wave -noupdate -format Logic /testbench/cpu/usb_clk -add wave -noupdate -format Literal /testbench/cpu/usb_d -add wave -noupdate -format Logic /testbench/cpu/usb_nxt -add wave -noupdate -format Logic /testbench/cpu/usb_stp -add wave -noupdate -format Logic /testbench/cpu/usb_dir -add wave -noupdate -format Logic /testbench/cpu/usb_resetn -add wave -noupdate -format Logic /testbench/cpu/spi_sel_n -add wave -noupdate -format Logic /testbench/cpu/spi_clk -add wave -noupdate -format Logic /testbench/cpu/spi_mosi -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/apbi -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/apbo -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbsi -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbso -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbmi -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/ahbmo -add wave -noupdate -format Logic /testbench/cpu/clkm -add wave -noupdate -format Logic /testbench/cpu/rstn -add wave -noupdate -format Logic /testbench/cpu/rstraw -add wave -noupdate -format Logic /testbench/cpu/mig_gen/ddrc/mcb_inst/c3_sys_clk -add wave -noupdate -format Logic /testbench/cpu/mig_gen/ddrc/mcb_inst/c3_sys_rst_n -add wave -noupdate -format Logic /testbench/cpu/mig_gen/ddrc/mcb_inst/c3_calib_done -add wave -noupdate -format Logic /testbench/cpu/vgadvi/dvi0/clk -add wave -noupdate -format Literal /testbench/cpu/vgadvi/dvi0/vgao -add wave -noupdate -format Logic /testbench/cpu/vgadvi/dvi0/vgaclk -add wave -noupdate -format Logic /testbench/cpu/vgadvi/dvi0/dclk_p -add wave -noupdate -format Logic /testbench/cpu/vgadvi/dvi0/dclk_n -add wave -noupdate -format Logic /testbench/cpu/svga/svga0/vgaclk -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/svga/svga0/vgao -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/svga/svga0/clk_sel -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/svga/svga0/t -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/svga/svga0/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/svga/svga0/dmai -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/svga/svga0/dmao -add wave -noupdate -format Logic /testbench/cpu/mig_gen/ddrc/calib_done -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/mig_gen/ddrc/r -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/mig_gen/ddrc/i -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/mig_gen/ddrc/ahbmi -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/mig_gen/ddrc/ahbmo -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/mig_gen/ddrc/r2 -add wave -noupdate -format Literal -radix hexadecimal /testbench/cpu/mig_gen/ddrc/p2 +add wave -noupdate /testbench/wdogn +add wave -noupdate /testbench/wdogn_local +add wave -noupdate -divider {WDOG PAD} +add wave -noupdate /testbench/cpu/wdogn +add wave -noupdate -divider MIG +add wave -noupdate /testbench/cpu/mig_gen/ddrc/ahbso +add wave -noupdate /testbench/cpu/mig_gen/ddrc/ahbsi +add wave -noupdate /testbench/cpu/mig_gen/ddrc/ahbmi +add wave -noupdate /testbench/cpu/mig_gen/ddrc/ahbmo +add wave -noupdate /testbench/cpu/mig_gen/ddrc/apbi +add wave -noupdate /testbench/cpu/mig_gen/ddrc/apbo +add wave -noupdate /testbench/cpu/mig_gen/ddrc/calib_done +add wave -noupdate /testbench/cpu/mig_gen/ddrc/test_error +add wave -noupdate /testbench/cpu/mig_gen/ddrc/rst_n_syn +add wave -noupdate /testbench/cpu/mig_gen/ddrc/rst_n_async +add wave -noupdate /testbench/cpu/mig_gen/ddrc/clk_amba +add wave -noupdate /testbench/cpu/mig_gen/ddrc/clk_mem_n +add wave -noupdate /testbench/cpu/mig_gen/ddrc/clk_mem_p +add wave -noupdate /testbench/cpu/mig_gen/ddrc/clk_125 +add wave -noupdate /testbench/cpu/mig_gen/ddrc/clk_100 +add wave -noupdate -divider WDOG +add wave -noupdate /testbench/cpu/resetn +add wave -noupdate /testbench/cpu/rst +add wave -noupdate -divider GPTIMER +add wave -noupdate /testbench/cpu/gpt/timer0/pindex +add wave -noupdate /testbench/cpu/gpt/timer0/paddr +add wave -noupdate /testbench/cpu/gpt/timer0/pmask +add wave -noupdate /testbench/cpu/gpt/timer0/pirq +add wave -noupdate /testbench/cpu/gpt/timer0/sepirq +add wave -noupdate /testbench/cpu/gpt/timer0/sbits +add wave -noupdate /testbench/cpu/gpt/timer0/ntimers +add wave -noupdate /testbench/cpu/gpt/timer0/nbits +add wave -noupdate /testbench/cpu/gpt/timer0/wdog +add wave -noupdate /testbench/cpu/gpt/timer0/ewdogen +add wave -noupdate /testbench/cpu/gpt/timer0/rst +add wave -noupdate /testbench/cpu/gpt/timer0/clk +add wave -noupdate /testbench/cpu/gpt/timer0/apbi +add wave -noupdate /testbench/cpu/gpt/timer0/apbo +add wave -noupdate /testbench/cpu/gpt/timer0/gpti +add wave -noupdate /testbench/cpu/gpt/timer0/gpto +add wave -noupdate /testbench/cpu/gpt/timer0/r +add wave -noupdate /testbench/cpu/gpt/timer0/rin +add wave -noupdate /testbench/cpu/gpt/timer0/REVISION +add wave -noupdate /testbench/cpu/gpt/timer0/pconfig +add wave -noupdate /testbench/cpu/gpt/timer0/TBITS +add wave -noupdate /testbench/cpu/gpt/timer0/NMI +add wave -noupdate /testbench/cpu/gpt/timer0/RESET_ALL +add wave -noupdate /testbench/cpu/gpt/timer0/RESVAL TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {6662738 ps} 0} {{Cursor 3} {341676502 ps} 0} -configure wave -namecolwidth 212 +WaveRestoreCursors {{Cursor 1} {578161251 ps} 0} +configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left -configure wave -signalnamewidth 0 +configure wave -signalnamewidth 2 configure wave -snapdistance 10 configure wave -datasetprefix 0 configure wave -rowmargin 4 @@ -121,7 +61,7 @@ configure wave -childrowmargin 2 configure wave -gridoffset 0 configure wave -gridperiod 1 configure wave -griddelta 40 -configure wave -timeline 0 +configure wave -timeline 1 configure wave -timelineunits ns update -WaveRestoreZoom {337706096 ps} {349485406 ps} +WaveRestoreZoom {575334046 ps} {606486148 ps} diff --git a/designs/leon3-jopdesign-ep1c12/.config b/designs/leon3-jopdesign-ep1c12/.config index 12ecbfae..4de325b0 100644 --- a/designs/leon3-jopdesign-ep1c12/.config +++ b/designs/leon3-jopdesign-ep1c12/.config @@ -165,7 +165,6 @@ CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set diff --git a/designs/leon3-jopdesign-ep1c12/config.h b/designs/leon3-jopdesign-ep1c12/config.h index a6ae10b5..e60c1ab3 100644 --- a/designs/leon3-jopdesign-ep1c12/config.h +++ b/designs/leon3-jopdesign-ep1c12/config.h @@ -160,7 +160,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM diff --git a/designs/leon3-jopdesign-ep1c12/config.help b/designs/leon3-jopdesign-ep1c12/config.help index 088f5249..acc4dd0f 100644 --- a/designs/leon3-jopdesign-ep1c12/config.help +++ b/designs/leon3-jopdesign-ep1c12/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-jopdesign-ep1c12/config.vhd b/designs/leon3-jopdesign-ep1c12/config.vhd index 1fcaaaf7..8cdba67d 100644 --- a/designs/leon3-jopdesign-ep1c12/config.vhd +++ b/designs/leon3-jopdesign-ep1c12/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-jopdesign-ep1c12/config.vhd.h b/designs/leon3-jopdesign-ep1c12/config.vhd.h index 21647e25..527910bf 100644 --- a/designs/leon3-jopdesign-ep1c12/config.vhd.h +++ b/designs/leon3-jopdesign-ep1c12/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-jopdesign-ep1c12/lconfig.tk b/designs/leon3-jopdesign-ep1c12/lconfig.tk index 1e5e4ad7..76878003 100755 --- a/designs/leon3-jopdesign-ep1c12/lconfig.tk +++ b/designs/leon3-jopdesign-ep1c12/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5324,7 +5315,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5580,6 +5570,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -6037,7 +6028,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6160,10 +6150,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " @@ -6266,6 +6255,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_32 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-jopdesign-ep1c12/leon3mp.vhd b/designs/leon3-jopdesign-ep1c12/leon3mp.vhd index e1670995..7cbb4cf5 100644 --- a/designs/leon3-jopdesign-ep1c12/leon3mp.vhd +++ b/designs/leon3-jopdesign-ep1c12/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-jopdesign-ep1c12/testbench.vhd b/designs/leon3-jopdesign-ep1c12/testbench.vhd index ec596c85..d19f9ff7 100644 --- a/designs/leon3-jopdesign-ep1c12/testbench.vhd +++ b/designs/leon3-jopdesign-ep1c12/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-jopdesign-ep1c12/tkconfig.h b/designs/leon3-jopdesign-ep1c12/tkconfig.h index a800c20b..2f1ffa8f 100644 --- a/designs/leon3-jopdesign-ep1c12/tkconfig.h +++ b/designs/leon3-jopdesign-ep1c12/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-minimal/leon3mp.vhd b/designs/leon3-minimal/leon3mp.vhd index 0f092444..f978704e 100644 --- a/designs/leon3-minimal/leon3mp.vhd +++ b/designs/leon3-minimal/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -279,7 +279,7 @@ begin -- pragma translate_off x : report_design generic map ( - msg1 => "LEON3 Demonstration design for Digilent NEXYS 3 board", + msg1 => "LEON3 Demonstration design", fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); diff --git a/designs/leon3-minimal/testbench.vhd b/designs/leon3-minimal/testbench.vhd index 06e4890f..2f89cf91 100644 --- a/designs/leon3-minimal/testbench.vhd +++ b/designs/leon3-minimal/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,15 +30,10 @@ library techmap; use techmap.gencomp.all; library micron; use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -library hynix; -use hynix.components.all; - entity testbench is generic ( fabtech : integer := CFG_FABTECH; diff --git a/designs/leon3-nuhorizons-3s1500/.config b/designs/leon3-nuhorizons-3s1500/.config index fad02b85..5986a018 100644 --- a/designs/leon3-nuhorizons-3s1500/.config +++ b/designs/leon3-nuhorizons-3s1500/.config @@ -160,7 +160,6 @@ CONFIG_DCACHE_SZ8=y # CONFIG_DCACHE_LZ16 is not set CONFIG_DCACHE_LZ32=y CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=00f3 @@ -246,7 +245,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=00002B # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-nuhorizons-3s1500/config.h b/designs/leon3-nuhorizons-3s1500/config.h index 3aa52905..b65c11e1 100644 --- a/designs/leon3-nuhorizons-3s1500/config.h +++ b/designs/leon3-nuhorizons-3s1500/config.h @@ -155,7 +155,6 @@ #undef CONFIG_DCACHE_LZ16 #define CONFIG_DCACHE_LZ32 1 #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 00f3 /* @@ -235,7 +234,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 00002B #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-nuhorizons-3s1500/config.help b/designs/leon3-nuhorizons-3s1500/config.help index fea6bcd8..e1e907f7 100644 --- a/designs/leon3-nuhorizons-3s1500/config.help +++ b/designs/leon3-nuhorizons-3s1500/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-nuhorizons-3s1500/config.vhd b/designs/leon3-nuhorizons-3s1500/config.vhd index 3eef4463..1d18d85f 100644 --- a/designs/leon3-nuhorizons-3s1500/config.vhd +++ b/designs/leon3-nuhorizons-3s1500/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#00f3#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-nuhorizons-3s1500/config.vhd.h b/designs/leon3-nuhorizons-3s1500/config.vhd.h index 90c30143..4ed8ca80 100644 --- a/designs/leon3-nuhorizons-3s1500/config.vhd.h +++ b/designs/leon3-nuhorizons-3s1500/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-nuhorizons-3s1500/lconfig.tk b/designs/leon3-nuhorizons-3s1500/lconfig.tk index d81da0a9..6fd91d75 100755 --- a/designs/leon3-nuhorizons-3s1500/lconfig.tk +++ b/designs/leon3-nuhorizons-3s1500/lconfig.tk @@ -2077,24 +2077,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2166,20 +2165,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2312,9 +2308,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3125,7 +3118,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3175,12 +3168,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3211,12 +3203,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4439,7 +4430,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4603,6 +4593,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_MCTRL_RMW 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5063,7 +5054,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5186,10 +5176,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -5242,6 +5231,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-nuhorizons-3s1500/leon3mp.vhd b/designs/leon3-nuhorizons-3s1500/leon3mp.vhd index 1b5f7c12..81a96499 100644 --- a/designs/leon3-nuhorizons-3s1500/leon3mp.vhd +++ b/designs/leon3-nuhorizons-3s1500/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-nuhorizons-3s1500/testbench.vhd b/designs/leon3-nuhorizons-3s1500/testbench.vhd index a3b09e88..1fefaab2 100644 --- a/designs/leon3-nuhorizons-3s1500/testbench.vhd +++ b/designs/leon3-nuhorizons-3s1500/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-nuhorizons-3s1500/tkconfig.h b/designs/leon3-nuhorizons-3s1500/tkconfig.h index 0d36eec2..91171148 100644 --- a/designs/leon3-nuhorizons-3s1500/tkconfig.h +++ b/designs/leon3-nuhorizons-3s1500/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-terasic-de0-nano/clkgen_de0.vhd b/designs/leon3-terasic-de0-nano/clkgen_de0.vhd index 7dab9963..39e0c51c 100644 --- a/designs/leon3-terasic-de0-nano/clkgen_de0.vhd +++ b/designs/leon3-terasic-de0-nano/clkgen_de0.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-terasic-de0-nano/config.help b/designs/leon3-terasic-de0-nano/config.help index 0794d859..bc10358a 100644 --- a/designs/leon3-terasic-de0-nano/config.help +++ b/designs/leon3-terasic-de0-nano/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-terasic-de0-nano/config.vhd b/designs/leon3-terasic-de0-nano/config.vhd index b9179ce0..ba21058e 100644 --- a/designs/leon3-terasic-de0-nano/config.vhd +++ b/designs/leon3-terasic-de0-nano/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-terasic-de0-nano/config.vhd.h b/designs/leon3-terasic-de0-nano/config.vhd.h index 882dea63..76c679d0 100644 --- a/designs/leon3-terasic-de0-nano/config.vhd.h +++ b/designs/leon3-terasic-de0-nano/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-terasic-de0-nano/lconfig.tk b/designs/leon3-terasic-de0-nano/lconfig.tk index 9c46cd29..81126662 100755 --- a/designs/leon3-terasic-de0-nano/lconfig.tk +++ b/designs/leon3-terasic-de0-nano/lconfig.tk @@ -2087,24 +2087,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2176,20 +2175,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2322,9 +2318,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4595,7 +4588,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4748,6 +4740,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -5204,7 +5197,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-terasic-de0-nano/leon3mp.vhd b/designs/leon3-terasic-de0-nano/leon3mp.vhd index 25b61b85..bac33785 100644 --- a/designs/leon3-terasic-de0-nano/leon3mp.vhd +++ b/designs/leon3-terasic-de0-nano/leon3mp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-terasic-de0-nano/sdctrl16.vhd b/designs/leon3-terasic-de0-nano/sdctrl16.vhd index ba718144..f0253087 100644 --- a/designs/leon3-terasic-de0-nano/sdctrl16.vhd +++ b/designs/leon3-terasic-de0-nano/sdctrl16.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-terasic-de0-nano/testbench.vhd b/designs/leon3-terasic-de0-nano/testbench.vhd index f0a2628a..c788e0a9 100644 --- a/designs/leon3-terasic-de0-nano/testbench.vhd +++ b/designs/leon3-terasic-de0-nano/testbench.vhd @@ -5,7 +5,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-terasic-de0-nano/tkconfig.h b/designs/leon3-terasic-de0-nano/tkconfig.h index 9a191105..21c72fa5 100644 --- a/designs/leon3-terasic-de0-nano/tkconfig.h +++ b/designs/leon3-terasic-de0-nano/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-terasic-de2-115/.config b/designs/leon3-terasic-de2-115/.config index aad1e6bb..989e18ec 100644 --- a/designs/leon3-terasic-de2-115/.config +++ b/designs/leon3-terasic-de2-115/.config @@ -166,7 +166,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -252,7 +251,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=0d0007 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Memory controllers diff --git a/designs/leon3-terasic-de2-115/config.h b/designs/leon3-terasic-de2-115/config.h index 16bbbd76..81e943ae 100644 --- a/designs/leon3-terasic-de2-115/config.h +++ b/designs/leon3-terasic-de2-115/config.h @@ -161,7 +161,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -241,7 +240,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 0d0007 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Memory controllers */ diff --git a/designs/leon3-terasic-de2-115/config.help b/designs/leon3-terasic-de2-115/config.help index c3fdbe3b..88f8775f 100644 --- a/designs/leon3-terasic-de2-115/config.help +++ b/designs/leon3-terasic-de2-115/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-terasic-de2-115/config.vhd b/designs/leon3-terasic-de2-115/config.vhd index 2a64bb57..01ad107c 100644 --- a/designs/leon3-terasic-de2-115/config.vhd +++ b/designs/leon3-terasic-de2-115/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-terasic-de2-115/config.vhd.h b/designs/leon3-terasic-de2-115/config.vhd.h index 48e687ff..164a18ef 100644 --- a/designs/leon3-terasic-de2-115/config.vhd.h +++ b/designs/leon3-terasic-de2-115/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-terasic-de2-115/lconfig.tk b/designs/leon3-terasic-de2-115/lconfig.tk index 76999e15..cfa4d52e 100755 --- a/designs/leon3-terasic-de2-115/lconfig.tk +++ b/designs/leon3-terasic-de2-115/lconfig.tk @@ -2089,24 +2089,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2178,20 +2177,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2324,9 +2320,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3137,7 +3130,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3187,12 +3180,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3223,12 +3215,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4934,7 +4925,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5114,6 +5104,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -5572,7 +5563,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5695,10 +5685,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -5750,6 +5739,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-terasic-de2-115/leon3mp.vhd b/designs/leon3-terasic-de2-115/leon3mp.vhd index 279a81f2..3684eb5d 100644 --- a/designs/leon3-terasic-de2-115/leon3mp.vhd +++ b/designs/leon3-terasic-de2-115/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-terasic-de2-115/testbench.vhd b/designs/leon3-terasic-de2-115/testbench.vhd index 335a6bdf..d77d9754 100644 --- a/designs/leon3-terasic-de2-115/testbench.vhd +++ b/designs/leon3-terasic-de2-115/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-terasic-de2-115/tkconfig.h b/designs/leon3-terasic-de2-115/tkconfig.h index 5b0f8df6..6a60bde6 100644 --- a/designs/leon3-terasic-de2-115/tkconfig.h +++ b/designs/leon3-terasic-de2-115/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-terasic-de4/.config b/designs/leon3-terasic-de4/.config index 4125d647..3bd3d0dc 100644 --- a/designs/leon3-terasic-de4/.config +++ b/designs/leon3-terasic-de4/.config @@ -89,7 +89,7 @@ CONFIG_CLK_DIV=5 # Processor # CONFIG_LEON3=y -CONFIG_PROC_NUM=1 +CONFIG_PROC_NUM=4 # CONFIG_LEON3_MIN is not set # CONFIG_LEON3_GP is not set # CONFIG_LEON3_HP is not set @@ -166,7 +166,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -224,13 +223,42 @@ CONFIG_DSU_ATRACESZ2=y # CONFIG_IU_DISAS is not set # CONFIG_DEBUG_PC32 is not set +# +# L2 Cache +# +# CONFIG_L2_ENABLE is not set +# CONFIG_L2_ASSO1 is not set +# CONFIG_L2_ASSO2 is not set +# CONFIG_L2_ASSO3 is not set +CONFIG_L2_ASSO4=y +# CONFIG_L2_SZ1 is not set +# CONFIG_L2_SZ2 is not set +# CONFIG_L2_SZ4 is not set +# CONFIG_L2_SZ8 is not set +# CONFIG_L2_SZ16 is not set +CONFIG_L2_SZ32=y +# CONFIG_L2_SZ64 is not set +# CONFIG_L2_SZ128 is not set +# CONFIG_L2_SZ256 is not set +# CONFIG_L2_SZ512 is not set +# CONFIG_L2_LINE32 is not set +CONFIG_L2_LINE64=y +# CONFIG_L2_HPROT is not set +# CONFIG_L2_PEN is not set +# CONFIG_L2_WT is not set +# CONFIG_L2_RAN is not set +# CONFIG_L2_SHARE is not set +CONFIG_L2_MAP=00F0 +CONFIG_L2_MTRR=8 +# CONFIG_L2_EDAC is not set + # # AMBA configuration # CONFIG_AHB_DEFMST=0 CONFIG_AHB_RROBIN=y # CONFIG_AHB_SPLIT is not set -# CONFIG_AHB_FPNPEN is not set +CONFIG_AHB_FPNPEN=y CONFIG_AHB_IOADDR=FFF CONFIG_APB_HADDR=800 # CONFIG_AHB_MON is not set @@ -319,4 +347,4 @@ CONFIG_GRGPIO_IMASK=fe # # VHDL Debugging # -# CONFIG_DEBUG_UART is not set +CONFIG_DEBUG_UART=y diff --git a/designs/leon3-terasic-de4/Makefile b/designs/leon3-terasic-de4/Makefile index e22d7081..fa42cd27 100644 --- a/designs/leon3-terasic-de4/Makefile +++ b/designs/leon3-terasic-de4/Makefile @@ -1,5 +1,6 @@ include .config GRLIB=../.. +GRLIB_CONFIG=grlib_config.vhd TOP=leon3mp BOARD=terasic-de4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc @@ -11,7 +12,7 @@ QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf EFFORT=high XSTOPT= ISEMAPOPT=-timing -VHDLSYNFILES=ddr2if.vhd pll_125.vhd config.vhd leon3mp.vhd +VHDLSYNFILES=ddr2if.vhd config.vhd leon3mp.vhd VHDLSIMFILES=ddr2sim.vhd testbench.vhd SIMTOP=testbench SDCFILE=default.sdc @@ -28,10 +29,10 @@ TECHLIBS = altera altera_mf stratixiii LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ tmtc openchip hynix cypress ihp fmf spansion gsi DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan \ - slink ascs leon3ft leon4 leon4v0 l2cache \ - spacewire usb pwm gr1553b iommu pci leon3ft hcan + slink ascs leon3ft leon4 leon4v0 \ + spacewire usb pwm gr1553b iommu pci hcan -FILESKIP = grcan.vhd ata_device.v i2c_slave_model.v +FILESKIP = grcan.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile @@ -45,14 +46,14 @@ qwiz: else \ echo "ddr2ctrl core already compiled"; \ fi ; -ifeq ($(CONFIG_GRETH_ENABLE),y) - @cp $(GRLIB)/boards/$(BOARD)/sgmii2gmii.vhd . - @if [ ! -d ./sgmii2gmii/ ]; then \ - qmegawiz -silent sgmii2gmii.vhd ; \ - else \ - echo "sgmii2gmii core already compiled"; \ - fi ; -endif +#ifeq ($(CONFIG_GRETH_ENABLE),y) +# @cp $(GRLIB)/boards/$(BOARD)/sgmii2gmii.vhd . +# @if [ ! -d ./sgmii2gmii/ ]; then \ +# qmegawiz -silent sgmii2gmii.vhd ; \ +# else \ +# echo "sgmii2gmii core already compiled"; \ +# fi ; +#endif localclean: @rm -rf sgmii2gmii.vhd sgmii2gmii sgmii2gmii_sim sgmii2gmii_testbench sgmii2gmii.[bcpqs]* sgmii2gmii_sim.f diff --git a/designs/leon3-terasic-de4/README.txt b/designs/leon3-terasic-de4/README.txt index fc4b7cb2..a5776293 100644 --- a/designs/leon3-terasic-de4/README.txt +++ b/designs/leon3-terasic-de4/README.txt @@ -5,7 +5,7 @@ LEON3 Template design for TerASIC Altera DE4 board 0verview -------- The design contains: - * LEON3 running at 50 MHz + * LEON3 running at 100 MHz * 1 GiB DDR2 running at 400 MHz using Quartus soft memory controller IP * JTAG debug link connected to on-board USB blaster II * One debug UART (AHBUART) and one standard UART (APBUART), @@ -14,6 +14,8 @@ The design contains: * Memory controller to access the on-board flash via GRMON * Two GRETH Gigabit Ethernet cores with EDCL, connected to the PHY through Altera's SGMII to GMII bridge IP. + * Currently, only gigabit operation is supported for the Ethernet + core and the 10/100 Mbit GRETH cannot be used. Important notes --------------- @@ -22,6 +24,8 @@ Important notes the FPGA designs. * The Ethernet gigabit cores are disabled by default and are not available in the GPL release of GRLIB. +* The Level-2 cache can be enabled in the design. This requires a + GRLIB release that includes the Level-2 cache. Design details -------------- @@ -39,10 +43,10 @@ Design details LED assignments: LED7 - unused LED6 - unused - LED5 - Ethernet 1 link up - LED4 - Ethernet 1 carrier sense - LED3 - Ethernet 0 link up - LED2 - Ethernet 0 carrier sense + LED5 - unused + LED4 - unused + LED3 - unused + LED2 - unused LED1 - DSU active LED0 - DBG error @@ -56,10 +60,12 @@ Push button assignments: Slide switches: SLIDE_SW3 - unused SLIDE_SW2 - unused - SLIDE_SW1 - unused + SLIDE_SW1 - Disable EDCL: + ON (down, 0) - EDCL is ON for all links at reset + OFF (up, 1) - EDCL is OFF for all links at reset SLIDE_SW0 - Select serial port (J30) UART mapping: - ON (left, 0) - is AHB debug UART - OFF (right,1) - is system's APB UART + ON (down, 0) - is AHB debug UART + OFF (up,1) - is system's APB UART Simulation and synthesis @@ -72,7 +78,7 @@ Simulation and synthesis make vsim [or make riviera] -* Synthesis will work with Quartus 13.1 or newwer. To synthesize the +* Synthesis will work with Quartus 13.1 or newer. To synthesize the design run: make qwiz @@ -87,3 +93,40 @@ Simulation and synthesis then program the board with: make quartus-prog-fpga + +5.1 How to program the flash prom with a FPGA programming file +-------------------------------------------------------------- +To program the board's flash permanently, you first have to generate +an srec file with the firmware and then write it to the flash via +Grmon. You will need a Quartus installation, and the SREC tools from: +http://srecord.sourceforge.net/ + +Launch a Nios II Command Shell, which is part of your Quartus +installation. On Windows it's in the Start menu, under Nios II. On +Linux you can find it in $QUARTUS_INST_DIR/nios2eds/nios2_command_shell.sh + +In the shell execute the following commands: + + sof2flash --input=leon3mp_quartus.sof --output=leon3mp_quartus.flash --offset=0x00020000 --pfl --optionbit=0x18000 --programmingmode=FPP + +At the end of this step you will have generated two files: + - leon3mp_quartus.flash + - leon3mp_quartus.map.flash + +Execute the following: + echo "S21501808003FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6" >> leon3mp_quartus.map.flash + +Finally merge the two files with: + srec_cat leon3mp_quartus.flash -byteswap leon3mp_quartus.map.flash -byteswap -output leon3mp.srec + +Now you have to write the firmware to the flash. To do so, connect to +your board with Grmon and execute the following. + + flash unlock all + + flash erase 0x18000 0xC00000 + + flash load leon3mp.srec + +At this point your board is programmed permanently. You can push the +RE_CONFIGn button to test it. diff --git a/designs/leon3-terasic-de4/config.h b/designs/leon3-terasic-de4/config.h index fdab6549..9d5e863a 100644 --- a/designs/leon3-terasic-de4/config.h +++ b/designs/leon3-terasic-de4/config.h @@ -87,7 +87,7 @@ * Processor */ #define CONFIG_LEON3 1 -#define CONFIG_PROC_NUM (1) +#define CONFIG_PROC_NUM (4) #undef CONFIG_LEON3_MIN #undef CONFIG_LEON3_GP #undef CONFIG_LEON3_HP @@ -161,7 +161,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -214,13 +213,41 @@ */ #undef CONFIG_IU_DISAS #undef CONFIG_DEBUG_PC32 +/* + * L2 Cache + */ +#undef CONFIG_L2_ENABLE +#undef CONFIG_L2_ASSO1 +#undef CONFIG_L2_ASSO2 +#undef CONFIG_L2_ASSO3 +#define CONFIG_L2_ASSO4 1 +#undef CONFIG_L2_SZ1 +#undef CONFIG_L2_SZ2 +#undef CONFIG_L2_SZ4 +#undef CONFIG_L2_SZ8 +#undef CONFIG_L2_SZ16 +#define CONFIG_L2_SZ32 1 +#undef CONFIG_L2_SZ64 +#undef CONFIG_L2_SZ128 +#undef CONFIG_L2_SZ256 +#undef CONFIG_L2_SZ512 +#undef CONFIG_L2_LINE32 +#define CONFIG_L2_LINE64 1 +#undef CONFIG_L2_HPROT +#undef CONFIG_L2_PEN +#undef CONFIG_L2_WT +#undef CONFIG_L2_RAN +#undef CONFIG_L2_SHARE +#define CONFIG_L2_MAP 00F0 +#define CONFIG_L2_MTRR (8) +#undef CONFIG_L2_EDAC /* * AMBA configuration */ #define CONFIG_AHB_DEFMST (0) #define CONFIG_AHB_RROBIN 1 #undef CONFIG_AHB_SPLIT -#undef CONFIG_AHB_FPNPEN +#define CONFIG_AHB_FPNPEN 1 #define CONFIG_AHB_IOADDR FFF #define CONFIG_APB_HADDR 800 #undef CONFIG_AHB_MON @@ -299,4 +326,4 @@ /* * VHDL Debugging */ -#undef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 1 diff --git a/designs/leon3-terasic-de4/config.help b/designs/leon3-terasic-de4/config.help index 105131f0..df4bfe59 100644 --- a/designs/leon3-terasic-de4/config.help +++ b/designs/leon3-terasic-de4/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED @@ -631,6 +634,64 @@ CONFIG_DEBUG_PC32 be implemented with full 32 bits, making debugging of the VHDL model much easier. Turn of this option for synthesis or you will be wasting area. +L2 Associativity +CONFIG_L2_ASSO1 + Select how many cache ways the L2 cache should have. + +L2 Way size +CONFIG_L2_SZ1 + Select the szie of each way in kbytes. The total L2 cache + size will be way size * number of ways. + +L2 cache line size +CONFIG_L2_LINE16 + The L2 cache can have either 16 or 32 bytes per line. It is + recommened to use 32 bytes for best performance. + +HPROT cachebility decoding +CONFIG_L2_HPROT + Say yes here to enable the AHB HPROT signals to define if an + L2 access should be cached. Should be disabled for now until + all I/O units in grlib generate these signals correctly. + +L2 power-on enable +CONFIG_L2_PEN + Say yes here to enable the L2 cache directly after reset. + This will allow to use the cache without first enable it + in software. The cache will automatically be flushed before + enabled. + +Random replacement +CONFIG_L2_RAN + Say Y here to enable random replacement policy rather then + the default LRU. + +Write-through operation +CONFIG_L2_WT + The L2 cache operates by default in copy-back mode. Say yes + here to enable write-through operation at power-on. + +Cachebility mapping +CONFIG_L2_MAP + This 16-bit hexadecimal vaule defines which address areas + are to be cacheable by the L2 cache. Each bit set indicates + a cacheable 256 Mbyte block. The left-most bit (LSB) indicates + address 0 - 256M and so on. + +RAM sharing +CONFIG_L2_SHARE + Say yes here to implement one shared data RAM for all cache ways. + This will reduce the number of RAM blocks for multi-way caches. + +MTRR registers +CONFIG_L2_MTRR + Specify the number of MTRR registers. Each MTRR can define one + memory area to be uncached, write-through, or copy-back. + +EDAC protection +CONFIG_L2_EDAC + Say yes here to enable EDAC protection. + CONFIG_AHB_DEFMST Sets the default AHB master (see AMBA 2.0 specification for definition). Should not be set to a value larger than the number of AHB masters - 1. diff --git a/designs/leon3-terasic-de4/config.in b/designs/leon3-terasic-de4/config.in index 820f3887..bcbb4255 100644 --- a/designs/leon3-terasic-de4/config.in +++ b/designs/leon3-terasic-de4/config.in @@ -23,6 +23,7 @@ mainmenu_option next_comment endmenu source lib/gaisler/leon3/leon3.in +source lib/gaisler/l2cache/l2c.in source lib/grlib/amba/amba.in mainmenu_option next_comment diff --git a/designs/leon3-terasic-de4/config.vhd b/designs/leon3-terasic-de4/config.vhd index 288df99f..41bfca72 100644 --- a/designs/leon3-terasic-de4/config.vhd +++ b/designs/leon3-terasic-de4/config.vhd @@ -1,9 +1,16 @@ + + + + ----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench configuration -- Copyright (C) 2009 Aeroflex Gaisler ------------------------------------------------------------------------------ + + library techmap; use techmap.gencomp.all; + package config is -- Technology and synthesis options constant CFG_FABTECH : integer := stratix4; @@ -23,7 +30,7 @@ package config is constant CFG_CLK_NOFB : integer := 0; -- LEON3 processor core constant CFG_LEON3 : integer := 1; - constant CFG_NCPU : integer := (1); + constant CFG_NCPU : integer := (4); constant CFG_NWIN : integer := (8); constant CFG_V8 : integer := 16#32# + 4*0; constant CFG_MAC : integer := 0; @@ -51,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -74,11 +81,24 @@ package config is constant CFG_LEON3_NETLIST: integer := 0; constant CFG_DISAS : integer := 0 + 0; constant CFG_PCLOW : integer := 2; +-- L2 Cache + constant CFG_L2_EN : integer := 0; + constant CFG_L2_SIZE : integer := 32; + constant CFG_L2_WAYS : integer := 4; + constant CFG_L2_HPROT : integer := 0; + constant CFG_L2_PEN : integer := 0; + constant CFG_L2_WT : integer := 0; + constant CFG_L2_RAN : integer := 0; + constant CFG_L2_SHARE : integer := 0; + constant CFG_L2_LSZ : integer := 64; + constant CFG_L2_MAP : integer := 16#00F0#; + constant CFG_L2_MTRR : integer := (8); + constant CFG_L2_EDAC : integer := 0; -- AMBA settings constant CFG_DEFMST : integer := (0); constant CFG_RROBIN : integer := 1; constant CFG_SPLIT : integer := 0; - constant CFG_FPNPEN : integer := 0; + constant CFG_FPNPEN : integer := 1; constant CFG_AHBIO : integer := 16#FFF#; constant CFG_APBADDR : integer := 16#800#; constant CFG_AHB_MON : integer := 0; @@ -118,10 +138,13 @@ package config is constant CFG_GRETH : integer := 0; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 8; + + -- Gaisler Ethernet core constant CFG_GRETH2 : integer := 0; constant CFG_GRETH21G : integer := 0; constant CFG_ETH2_FIFO : integer := 8; + -- SPI controller constant CFG_SPICTRL_ENABLE : integer := 1; constant CFG_SPICTRL_NUM : integer := (1); @@ -135,12 +158,15 @@ package config is constant CFG_SPICTRL_MAXWLEN : integer := (0); constant CFG_SPICTRL_SYNCRAM : integer := 1; constant CFG_SPICTRL_FT : integer := 0; + -- UART 1 constant CFG_UART1_ENABLE : integer := 1; constant CFG_UART1_FIFO : integer := 4; + -- LEON3 interrupt controller constant CFG_IRQ3_ENABLE : integer := 1; constant CFG_IRQ3_NSEC : integer := 0; + -- Modular timer constant CFG_GPT_ENABLE : integer := 1; constant CFG_GPT_NTIM : integer := (2); @@ -150,10 +176,12 @@ package config is constant CFG_GPT_SEPIRQ : integer := 1; constant CFG_GPT_WDOGEN : integer := 0; constant CFG_GPT_WDOG : integer := 16#0#; + -- GPIO port constant CFG_GRGPIO_ENABLE : integer := 1; constant CFG_GRGPIO_IMASK : integer := 16#fe#; constant CFG_GRGPIO_WIDTH : integer := (32); + -- GRLIB debugging - constant CFG_DUART : integer := 0; + constant CFG_DUART : integer := 1; end; diff --git a/designs/leon3-terasic-de4/config.vhd.h b/designs/leon3-terasic-de4/config.vhd.h index 5846484d..55ee33c4 100644 --- a/designs/leon3-terasic-de4/config.vhd.h +++ b/designs/leon3-terasic-de4/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; @@ -70,6 +70,20 @@ constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; constant CFG_PCLOW : integer := CFG_DEBUG_PC32; +-- L2 Cache + constant CFG_L2_EN : integer := CONFIG_L2_ENABLE; + constant CFG_L2_SIZE : integer := CFG_L2_SZ; + constant CFG_L2_WAYS : integer := CFG_L2_ASSO; + constant CFG_L2_HPROT : integer := CONFIG_L2_HPROT; + constant CFG_L2_PEN : integer := CONFIG_L2_PEN; + constant CFG_L2_WT : integer := CONFIG_L2_WT; + constant CFG_L2_RAN : integer := CONFIG_L2_RAN; + constant CFG_L2_SHARE : integer := CONFIG_L2_SHARE; + constant CFG_L2_LSZ : integer := CFG_L2_LINE; + constant CFG_L2_MAP : integer := 16#CONFIG_L2_MAP#; + constant CFG_L2_MTRR : integer := CONFIG_L2_MTRR; + constant CFG_L2_EDAC : integer := CONFIG_L2_EDAC; + -- AMBA settings constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; diff --git a/designs/leon3-terasic-de4/ddr2if.vhd b/designs/leon3-terasic-de4/ddr2if.vhd index b7697f26..763c6811 100644 --- a/designs/leon3-terasic-de4/ddr2if.vhd +++ b/designs/leon3-terasic-de4/ddr2if.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,6 +30,7 @@ entity ddr2if is hindex: integer; haddr: integer := 16#400#; hmask: integer := 16#000#; + ahbbits: integer := ahbdw; burstlen: integer := 8 ); port ( @@ -92,7 +93,7 @@ architecture rtl of ddr2if is avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable avl_read_req : in std_logic := '0'; -- .read avl_write_req : in std_logic := '0'; -- .write - avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount + avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount local_init_done : out std_logic; -- status.local_init_done local_cal_success : out std_logic; -- .local_cal_success local_cal_fail : out std_logic; -- .local_cal_fail @@ -162,7 +163,7 @@ begin avl_be => be, avl_read_req => avlsi.read_req, avl_write_req => avlsi.write_req, - avl_size => avlsi.size(2 downto 0), + avl_size => avlsi.size, local_init_done => local_init_done, local_cal_success => local_cal_success, local_cal_fail => local_cal_fail, @@ -179,6 +180,7 @@ begin hmask => hmask, burstlen => burstlen, nosync => 0, + ahbbits => ahbbits, avldbits => 256, avlabits => 25 ) diff --git a/designs/leon3-terasic-de4/ddr2sim.vhd b/designs/leon3-terasic-de4/ddr2sim.vhd index cfde4202..f98251e1 100644 --- a/designs/leon3-terasic-de4/ddr2sim.vhd +++ b/designs/leon3-terasic-de4/ddr2sim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -56,7 +56,7 @@ entity ddr2ctrl is avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable avl_read_req : in std_logic := '0'; -- .read avl_write_req : in std_logic := '0'; -- .write - avl_size : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount + avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount local_init_done : out std_logic; -- status.local_init_done local_cal_success : out std_logic; -- .local_cal_success local_cal_fail : out std_logic; -- .local_cal_fail @@ -222,4 +222,4 @@ begin end if; end loop; end process; -end; \ No newline at end of file +end; diff --git a/designs/leon3-terasic-de4/default.sdc b/designs/leon3-terasic-de4/default.sdc index 380e6f62..bb742be7 100644 --- a/designs/leon3-terasic-de4/default.sdc +++ b/designs/leon3-terasic-de4/default.sdc @@ -55,6 +55,9 @@ create_clock -name CLK_M2 -period "50 MHZ" [get_ports OSC_50_Bank4] # False Path # +set_false_path -from [get_clocks {clkgen0|\stra3:v|sdclk_pll|\nosd:altpll0|auto_generated|pll1|clk[0]}] -to [get_clocks {\eth1:pll0|altpll_component|auto_generated|pll1|clk[0]}] +set_false_path -from [get_clocks {\eth1:bridge1|lvds_rx|ALTLVDS_RX_component|auto_generated|rx_0|clk0}] -to [get_clocks {clkgen0|\stra3:v|sdclk_pll|\nosd:altpll0|auto_generated|pll1|clk[0]}] + # # Path Delay # diff --git a/designs/leon3-terasic-de4/grlib_config.vhd b/designs/leon3-terasic-de4/grlib_config.vhd new file mode 100644 index 00000000..c1b53c69 --- /dev/null +++ b/designs/leon3-terasic-de4/grlib_config.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Package: config +-- File: config.vhd +-- Description: GRLIB Global configuration package. Can be overriden +-- by local config packages in template designs. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.config_types.all; + +package config is + +-- AHBDW - AHB data with +-- +-- Valid values are 32, 64, 128 and 256 +-- +-- The value here sets the width of the AMBA AHB data vectors for all +-- cores in the library. +-- +constant CFG_AHBDW : integer := 32; + + +-- CFG_AHB_ACDM - Enable AMBA Compliant Data Muxing in cores +-- +-- Valid values are 0 and 1 +-- +-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package +-- will read their data from the low part of the AHB data vector. +-- +-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package +-- will select valid data, as defined in the AMBA AHB standard, from the +-- AHB data vectors based on the address input. If a core uses a function +-- that does not have the address input, a failure will be asserted. +-- +-- The value of CFG_AHB_ACDM is assigned to the constant CORE_ACDM in the +-- grlib.amba package. Note that this setting is separate from the ACDM setting +-- of the AHBCTRL core (which is set directly via a AHBCTRL VHDL generic). +-- +constant CFG_AHB_ACDM : integer := 0; + +-- GRLIB_CONFIG_ARRAY - Array of configuration values +-- +-- The length of this array and the meaning of different positions is defined +-- in the grlib.config_types package. +constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := ( + grlib_debug_level => 0, + grlib_debug_mask => 0, + grlib_techmap_strict_ram => 0, + grlib_techmap_testin_extra => 0, + grlib_sync_reset_enable_all => 0, + grlib_async_reset_enable => 0, + others => 0); + +end; diff --git a/designs/leon3-terasic-de4/lconfig.tk b/designs/leon3-terasic-de4/lconfig.tk index 2e333adb..f6844110 100755 --- a/designs/leon3-terasic-de4/lconfig.tk +++ b/designs/leon3-terasic-de4/lconfig.tk @@ -643,8 +643,8 @@ frame .f0.right set active_menus [list] set processed_top_level 0 set ARCH sparc -set menus_per_column 4 -set total_menus 21 +set menus_per_column 5 +set total_menus 22 proc toplevel_menu {num} { if {$num == 4} then {return 3} @@ -654,12 +654,12 @@ proc toplevel_menu {num} { if {$num == 8} then {return 3} if {$num == 9} then {return 3} if {$num == 10} then {return 3} - if {$num == 14} then {return 13} - if {$num == 16} then {return 15} - if {$num == 17} then {return 15} - if {$num == 18} then {return 15} - if {$num == 19} then {return 18} - if {$num == 20} then {return 15} + if {$num == 15} then {return 14} + if {$num == 17} then {return 16} + if {$num == 18} then {return 16} + if {$num == 19} then {return 16} + if {$num == 20} then {return 19} + if {$num == 21} then {return 16} return $num } @@ -2087,24 +2087,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2176,20 +2175,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2322,9 +2318,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -2947,7 +2940,7 @@ proc update_define_menu10 {} { } -menu_option menu11 11 "AMBA configuration" +menu_option menu11 11 "L2 Cache" proc menu11 {w title} { set oldFocus [focus] catch {destroy $w; unregister_active 11} @@ -2956,9 +2949,9 @@ proc menu11 {w title} { global active_menus set active_menus [lsort -integer [linsert $active_menus end 11]] message $w.m -width 400 -aspect 300 -text \ - "AMBA configuration" -relief raised + "L2 Cache" -relief raised pack $w.m -pady 10 -side top -padx 10 - wm title $w "AMBA configuration" + wm title $w "L2 Cache" bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; break" set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\"" @@ -2998,16 +2991,43 @@ proc menu11 {w title} { pack $w.config.canvas -side right -fill y - int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST - bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN - bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT - bool $w.config.f 11 3 "Enable full plug&play decoding " CONFIG_AHB_FPNPEN - hex $w.config.f 11 4 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR - hex $w.config.f 11 5 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR - bool $w.config.f 11 6 "Enable AMBA AHB monitor " CONFIG_AHB_MON - bool $w.config.f 11 7 "Report AHB errors " CONFIG_AHB_MONERR - bool $w.config.f 11 8 "Report AHB warings " CONFIG_AHB_MONWAR - bool $w.config.f 11 9 "Write trace to simulation console " CONFIG_AHB_DTRACE + bool $w.config.f 11 0 "Enable L2 Cache " CONFIG_L2_ENABLE + global tmpvar_28 + minimenu $w.config.f 11 1 "Associativity (ways) " tmpvar_28 CONFIG_L2_ASSO1 + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (ways) \"" + $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_28 -value "3" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 4 + global tmpvar_29 + minimenu $w.config.f 11 2 "Way size (kbytes/way)" tmpvar_29 CONFIG_L2_SZ1 + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Way size (kbytes/way)\"" + $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_29 -value "1" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_29 -value "2" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_29 -value "128" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_29 -value "256" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "512" -variable tmpvar_29 -value "512" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 10 + global tmpvar_30 + minimenu $w.config.f 11 3 "Line size (bytes) " tmpvar_30 CONFIG_L2_LINE32 + menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes) \"" + $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_30 -value "32" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "64" -variable tmpvar_30 -value "64" -command "update_active" + menusplit $w $w.config.f.x3.x.menu 2 + bool $w.config.f 11 4 "Use HPROT information " CONFIG_L2_HPROT + bool $w.config.f 11 5 "Enable L2 cache at power-on " CONFIG_L2_PEN + bool $w.config.f 11 6 "Enable write-through at power-on " CONFIG_L2_WT + bool $w.config.f 11 7 "Random replacement (LRU default) " CONFIG_L2_RAN + bool $w.config.f 11 8 "Shared RAM for multi-way caches " CONFIG_L2_SHARE + hex $w.config.f 11 9 "Cacheability map " CONFIG_L2_MAP + int $w.config.f 11 10 "Number of MTRR registers " CONFIG_L2_MTRR + bool $w.config.f 11 11 "Enable EDAC " CONFIG_L2_EDAC @@ -3044,17 +3064,165 @@ proc menu11 {w title} { } proc update_menu11 {} { + global CONFIG_L2_ASSO1 + global CONFIG_L2_SHARE + if {($CONFIG_L2_ASSO1 != "1")} then { + configure_entry .menu11.config.f.x8 normal {n l y}} else {configure_entry .menu11.config.f.x8 disabled {y n l}} +} + + +proc update_define_menu11 {} { + update_define_mainmenu + global CONFIG_MODULES + global tmpvar_28 + global CONFIG_L2_ASSO1 + if {$tmpvar_28 == "1"} then {set CONFIG_L2_ASSO1 1} else {set CONFIG_L2_ASSO1 0} + global CONFIG_L2_ASSO2 + if {$tmpvar_28 == "2"} then {set CONFIG_L2_ASSO2 1} else {set CONFIG_L2_ASSO2 0} + global CONFIG_L2_ASSO3 + if {$tmpvar_28 == "3"} then {set CONFIG_L2_ASSO3 1} else {set CONFIG_L2_ASSO3 0} + global CONFIG_L2_ASSO4 + if {$tmpvar_28 == "4"} then {set CONFIG_L2_ASSO4 1} else {set CONFIG_L2_ASSO4 0} + global tmpvar_29 + global CONFIG_L2_SZ1 + if {$tmpvar_29 == "1"} then {set CONFIG_L2_SZ1 1} else {set CONFIG_L2_SZ1 0} + global CONFIG_L2_SZ2 + if {$tmpvar_29 == "2"} then {set CONFIG_L2_SZ2 1} else {set CONFIG_L2_SZ2 0} + global CONFIG_L2_SZ4 + if {$tmpvar_29 == "4"} then {set CONFIG_L2_SZ4 1} else {set CONFIG_L2_SZ4 0} + global CONFIG_L2_SZ8 + if {$tmpvar_29 == "8"} then {set CONFIG_L2_SZ8 1} else {set CONFIG_L2_SZ8 0} + global CONFIG_L2_SZ16 + if {$tmpvar_29 == "16"} then {set CONFIG_L2_SZ16 1} else {set CONFIG_L2_SZ16 0} + global CONFIG_L2_SZ32 + if {$tmpvar_29 == "32"} then {set CONFIG_L2_SZ32 1} else {set CONFIG_L2_SZ32 0} + global CONFIG_L2_SZ64 + if {$tmpvar_29 == "64"} then {set CONFIG_L2_SZ64 1} else {set CONFIG_L2_SZ64 0} + global CONFIG_L2_SZ128 + if {$tmpvar_29 == "128"} then {set CONFIG_L2_SZ128 1} else {set CONFIG_L2_SZ128 0} + global CONFIG_L2_SZ256 + if {$tmpvar_29 == "256"} then {set CONFIG_L2_SZ256 1} else {set CONFIG_L2_SZ256 0} + global CONFIG_L2_SZ512 + if {$tmpvar_29 == "512"} then {set CONFIG_L2_SZ512 1} else {set CONFIG_L2_SZ512 0} + global tmpvar_30 + global CONFIG_L2_LINE32 + if {$tmpvar_30 == "32"} then {set CONFIG_L2_LINE32 1} else {set CONFIG_L2_LINE32 0} + global CONFIG_L2_LINE64 + if {$tmpvar_30 == "64"} then {set CONFIG_L2_LINE64 1} else {set CONFIG_L2_LINE64 0} + global CONFIG_L2_SHARE + if {($CONFIG_L2_ASSO1 != "1")} then { + set CONFIG_L2_SHARE [expr $CONFIG_L2_SHARE&15]} else {set CONFIG_L2_SHARE [expr $CONFIG_L2_SHARE|16]} +} + + +menu_option menu12 12 "AMBA configuration" +proc menu12 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 12} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 12]] + message $w.m -width 400 -aspect 300 -text \ + "AMBA configuration" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "AMBA configuration" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + int $w.config.f 12 0 "Default AHB master" CONFIG_AHB_DEFMST + bool $w.config.f 12 1 "Round-robin arbiter " CONFIG_AHB_RROBIN + bool $w.config.f 12 2 "AHB split-transaction support " CONFIG_AHB_SPLIT + bool $w.config.f 12 3 "Enable full plug&play decoding " CONFIG_AHB_FPNPEN + hex $w.config.f 12 4 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR + hex $w.config.f 12 5 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR + bool $w.config.f 12 6 "Enable AMBA AHB monitor " CONFIG_AHB_MON + bool $w.config.f 12 7 "Report AHB errors " CONFIG_AHB_MONERR + bool $w.config.f 12 8 "Report AHB warings " CONFIG_AHB_MONWAR + bool $w.config.f 12 9 "Write trace to simulation console " CONFIG_AHB_DTRACE + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu12 {} { global CONFIG_AHB_MON global CONFIG_AHB_MONERR if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}} + configure_entry .menu12.config.f.x7 normal {n l y}} else {configure_entry .menu12.config.f.x7 disabled {y n l}} global CONFIG_AHB_MONWAR if {($CONFIG_AHB_MON == 1)} then { - configure_entry .menu11.config.f.x8 normal {n l y}} else {configure_entry .menu11.config.f.x8 disabled {y n l}} + configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} } -proc update_define_menu11 {} { +proc update_define_menu12 {} { update_define_mainmenu global CONFIG_MODULES global CONFIG_AHB_MON @@ -3067,30 +3235,30 @@ proc update_define_menu11 {} { } -menu_option menu12 12 "Debug Link " -proc menu12 {w title} { +menu_option menu13 13 "Debug Link " +proc menu13 {w title} { set oldFocus [focus] - catch {destroy $w; unregister_active 12} + catch {destroy $w; unregister_active 13} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 12]] + set active_menus [lsort -integer [linsert $active_menus end 13]] message $w.m -width 400 -aspect 300 -text \ "Debug Link " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "Debug Link " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu14 .menu14 \"$title\"" frame $w.f button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3118,24 +3286,24 @@ proc menu12 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART - bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG - bool $w.config.f 12 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH - global tmpvar_28 - minimenu $w.config.f 12 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_28 CONFIG_DSU_ETHSZ1 + bool $w.config.f 13 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART + bool $w.config.f 13 1 "JTAG Debug Link" CONFIG_DSU_JTAG + bool $w.config.f 13 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH + global tmpvar_31 + minimenu $w.config.f 13 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_31 CONFIG_DSU_ETHSZ1 menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\"" - $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active" - $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_31 -value "1" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_31 -value "2" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_31 -value "4" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_31 -value "8" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_31 -value "16" -command "update_active" menusplit $w $w.config.f.x3.x.menu 5 - hex $w.config.f 12 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB - hex $w.config.f 12 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB - hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB - hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB - bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + hex $w.config.f 13 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB + hex $w.config.f 13 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB + hex $w.config.f 13 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB + hex $w.config.f 13 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB + bool $w.config.f 13 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG + bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3171,48 +3339,47 @@ proc menu12 {w title} { } } -proc update_menu12 {} { +proc update_menu13 {} { global CONFIG_GRETH_ENABLE global CONFIG_DSU_ETH if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu12.config.f.x2 normal {n l y}} else {configure_entry .menu12.config.f.x2 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}} + configure_entry .menu13.config.f.x2 normal {n l y}} else {configure_entry .menu13.config.f.x2 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu13.config.f.x3 normal {x l}} else {configure_entry .menu13.config.f.x3 disabled {x l}} global CONFIG_DSU_IPMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x4.l configure -state normal; } else {.menu12.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x4.l configure -state disabled} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x4.l configure -state normal; } else {.menu13.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x4.l configure -state disabled} global CONFIG_DSU_IPLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x5.l configure -state normal; } else {.menu13.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x5.l configure -state disabled} global CONFIG_DSU_ETHMSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x6.l configure -state normal; } else {.menu13.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x7.l configure -state normal; } else {.menu13.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x7.l configure -state disabled} global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { + configure_entry .menu13.config.f.x8 normal {n l y}} else {configure_entry .menu13.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { + configure_entry .menu13.config.f.x9 normal {n l y}} else {configure_entry .menu13.config.f.x9 disabled {y n l}} } -proc update_define_menu12 {} { +proc update_define_menu13 {} { update_define_mainmenu global CONFIG_MODULES global CONFIG_GRETH_ENABLE global CONFIG_DSU_ETH if {($CONFIG_GRETH_ENABLE == 1)} then { set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]} - global tmpvar_28 + global tmpvar_31 global CONFIG_DSU_ETHSZ1 - if {$tmpvar_28 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0} + if {$tmpvar_31 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0} global CONFIG_DSU_ETHSZ2 - if {$tmpvar_28 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0} + if {$tmpvar_31 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0} global CONFIG_DSU_ETHSZ4 - if {$tmpvar_28 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0} + if {$tmpvar_31 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0} global CONFIG_DSU_ETHSZ8 - if {$tmpvar_28 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0} + if {$tmpvar_31 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0} global CONFIG_DSU_ETHSZ16 - if {$tmpvar_28 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0} + if {$tmpvar_31 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0} global CONFIG_DSU_IPMSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8} global CONFIG_DSU_IPLSB @@ -3221,40 +3388,39 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } -menu_option menu13 13 "Memory controllers " -proc menu13 {w title} { +menu_option menu14 14 "Memory controllers " +proc menu14 {w title} { set oldFocus [focus] - catch {destroy $w; unregister_active 13} + catch {destroy $w; unregister_active 14} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 13]] + set active_menus [lsort -integer [linsert $active_menus end 14]] message $w.m -width 400 -aspect 300 -text \ "Memory controllers " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "Memory controllers " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; break" - set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; break" + set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\"" frame $w.f button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3282,9 +3448,9 @@ proc menu13 {w title} { pack $w.config.canvas -side right -fill y - submenu $w.config.f 13 0 "Leon2 memory controller " 14 - bool $w.config.f 13 1 "Enable AHB Status Register " CONFIG_AHBSTAT_ENABLE - int $w.config.f 13 2 "Number of correctable-error slaves " CONFIG_AHBSTAT_NFTSLV + submenu $w.config.f 14 0 "Leon2 memory controller " 15 + bool $w.config.f 14 1 "Enable AHB Status Register " CONFIG_AHBSTAT_ENABLE + int $w.config.f 14 2 "Number of correctable-error slaves " CONFIG_AHBSTAT_NFTSLV @@ -3320,14 +3486,14 @@ proc menu13 {w title} { } } -proc update_menu13 {} { +proc update_menu14 {} { global CONFIG_AHBSTAT_ENABLE global CONFIG_AHBSTAT_NFTSLV - if {($CONFIG_AHBSTAT_ENABLE == 1)} then {.menu13.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x2.l configure -state normal; } else {.menu13.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x2.l configure -state disabled} + if {($CONFIG_AHBSTAT_ENABLE == 1)} then {.menu14.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu14.config.f.x2.l configure -state normal; } else {.menu14.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu14.config.f.x2.l configure -state disabled} } -proc update_define_menu13 {} { +proc update_define_menu14 {} { update_define_mainmenu global CONFIG_MODULES global CONFIG_AHBSTAT_ENABLE @@ -3336,30 +3502,30 @@ proc update_define_menu13 {} { } -proc menu14 {w title} { +proc menu15 {w title} { set oldFocus [focus] - catch {focus .menu13} - catch {destroy $w; unregister_active 14} + catch {focus .menu14} + catch {destroy $w; unregister_active 15} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 14]] + set active_menus [lsort -integer [linsert $active_menus end 15]] message $w.m -width 400 -aspect 300 -text \ "Leon2 memory controller " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "Leon2 memory controller " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 14; catch {destroy .menu13}; unregister_active 13; menu15 .menu15 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; catch {destroy .menu14}; unregister_active 14; menu16 .menu16 \"$title\"" frame $w.f button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3387,24 +3553,24 @@ proc menu14 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 14 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2 - bool $w.config.f 14 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT - bool $w.config.f 14 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT - bool $w.config.f 14 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS - bool $w.config.f 14 4 "SDRAM controller " CONFIG_MCTRL_SDRAM - bool $w.config.f 14 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS - bool $w.config.f 14 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64 - bool $w.config.f 14 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK - bool $w.config.f 14 8 "Enable page burst operation " CONFIG_MCTRL_PAGE - bool $w.config.f 14 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE + bool $w.config.f 15 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2 + bool $w.config.f 15 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT + bool $w.config.f 15 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT + bool $w.config.f 15 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS + bool $w.config.f 15 4 "SDRAM controller " CONFIG_MCTRL_SDRAM + bool $w.config.f 15 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS + bool $w.config.f 15 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64 + bool $w.config.f 15 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK + bool $w.config.f 15 8 "Enable page burst operation " CONFIG_MCTRL_PAGE + bool $w.config.f 15 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE focus $w update_active global winx; global winy - if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Memory controllers "} - set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controllers "} + set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} update idletasks if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f @@ -3433,39 +3599,39 @@ proc menu14 {w title} { } } -proc update_menu14 {} { +proc update_menu15 {} { global CONFIG_MCTRL_LEON2 global CONFIG_MCTRL_8BIT if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu14.config.f.x1 normal {n l y}} else {configure_entry .menu14.config.f.x1 disabled {y n l}} + configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}} global CONFIG_MCTRL_16BIT if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu14.config.f.x2 normal {n l y}} else {configure_entry .menu14.config.f.x2 disabled {y n l}} + configure_entry .menu15.config.f.x2 normal {n l y}} else {configure_entry .menu15.config.f.x2 disabled {y n l}} global CONFIG_MCTRL_5CS if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu14.config.f.x3 normal {n l y}} else {configure_entry .menu14.config.f.x3 disabled {y n l}} + configure_entry .menu15.config.f.x3 normal {n l y}} else {configure_entry .menu15.config.f.x3 disabled {y n l}} global CONFIG_MCTRL_SDRAM if {($CONFIG_MCTRL_LEON2 == 1)} then { - configure_entry .menu14.config.f.x4 normal {n l y}} else {configure_entry .menu14.config.f.x4 disabled {y n l}} + configure_entry .menu15.config.f.x4 normal {n l y}} else {configure_entry .menu15.config.f.x4 disabled {y n l}} global CONFIG_MCTRL_SDRAM_SEPBUS if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu14.config.f.x5 normal {n l y}} else {configure_entry .menu14.config.f.x5 disabled {y n l}} + configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}} global CONFIG_MCTRL_SDRAM_BUS64 if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu14.config.f.x6 normal {n l y}} else {configure_entry .menu14.config.f.x6 disabled {y n l}} + configure_entry .menu15.config.f.x6 normal {n l y}} else {configure_entry .menu15.config.f.x6 disabled {y n l}} global CONFIG_MCTRL_SDRAM_INVCLK if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { - configure_entry .menu14.config.f.x7 normal {n l y}} else {configure_entry .menu14.config.f.x7 disabled {y n l}} + configure_entry .menu15.config.f.x7 normal {n l y}} else {configure_entry .menu15.config.f.x7 disabled {y n l}} global CONFIG_MCTRL_PAGE if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { - configure_entry .menu14.config.f.x8 normal {n l y}} else {configure_entry .menu14.config.f.x8 disabled {y n l}} + configure_entry .menu15.config.f.x8 normal {n l y}} else {configure_entry .menu15.config.f.x8 disabled {y n l}} global CONFIG_MCTRL_PROGPAGE if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { - configure_entry .menu14.config.f.x9 normal {n l y}} else {configure_entry .menu14.config.f.x9 disabled {y n l}} + configure_entry .menu15.config.f.x9 normal {n l y}} else {configure_entry .menu15.config.f.x9 disabled {y n l}} } -proc update_define_menu14 {} { +proc update_define_menu15 {} { update_define_mainmenu global CONFIG_MODULES global CONFIG_MCTRL_LEON2 @@ -3499,30 +3665,30 @@ proc update_define_menu14 {} { } -menu_option menu15 15 "Peripherals " -proc menu15 {w title} { +menu_option menu16 16 "Peripherals " +proc menu16 {w title} { set oldFocus [focus] - catch {destroy $w; unregister_active 15} + catch {destroy $w; unregister_active 16} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 15]] + set active_menus [lsort -integer [linsert $active_menus end 16]] message $w.m -width 400 -aspect 300 -text \ "Peripherals " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "Peripherals " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; break" - set nextscript "catch {focus $oldFocus}; menu16 .menu16 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; break" + set nextscript "catch {focus $oldFocus}; menu17 .menu17 \"$title\"" frame $w.f button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3550,10 +3716,10 @@ proc menu15 {w title} { pack $w.config.canvas -side right -fill y - submenu $w.config.f 15 0 "On-chip RAM/ROM " 16 - submenu $w.config.f 15 1 "Ethernet " 17 - submenu $w.config.f 15 2 "SPI " 18 - submenu $w.config.f 15 3 "UARTs, timers and I/O port " 20 + submenu $w.config.f 16 0 "On-chip RAM/ROM " 17 + submenu $w.config.f 16 1 "Ethernet " 18 + submenu $w.config.f 16 2 "SPI " 19 + submenu $w.config.f 16 3 "UARTs, timers and I/O port " 21 @@ -3589,40 +3755,40 @@ proc menu15 {w title} { } } -proc update_menu15 {} { +proc update_menu16 {} { } -proc update_define_menu15 {} { +proc update_define_menu16 {} { update_define_mainmenu global CONFIG_MODULES } -proc menu16 {w title} { +proc menu17 {w title} { set oldFocus [focus] - catch {focus .menu15} - catch {destroy $w; unregister_active 16} + catch {focus .menu16} + catch {destroy $w; unregister_active 17} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 16]] + set active_menus [lsort -integer [linsert $active_menus end 17]] message $w.m -width 400 -aspect 300 -text \ "On-chip RAM/ROM " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "On-chip RAM/ROM " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu18 .menu18 \"$title\"" frame $w.f button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3650,34 +3816,34 @@ proc menu16 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 16 0 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE - global tmpvar_29 - minimenu $w.config.f 16 1 "AHB RAM size (Kbyte)" tmpvar_29 CONFIG_AHBRAM_SZ1 + bool $w.config.f 17 0 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE + global tmpvar_32 + minimenu $w.config.f 17 1 "AHB RAM size (Kbyte)" tmpvar_32 CONFIG_AHBRAM_SZ1 menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_29 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_29 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "128" -variable tmpvar_29 -value "128" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "256" -variable tmpvar_29 -value "256" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "512" -variable tmpvar_29 -value "512" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "1024" -variable tmpvar_29 -value "1024" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2048" -variable tmpvar_29 -value "2048" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4096" -variable tmpvar_29 -value "4096" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_32 -value "1" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_32 -value "2" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_32 -value "4" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_32 -value "8" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_32 -value "16" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_32 -value "32" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "64" -variable tmpvar_32 -value "64" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "128" -variable tmpvar_32 -value "128" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "256" -variable tmpvar_32 -value "256" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "512" -variable tmpvar_32 -value "512" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "1024" -variable tmpvar_32 -value "1024" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "2048" -variable tmpvar_32 -value "2048" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "4096" -variable tmpvar_32 -value "4096" -command "update_active" menusplit $w $w.config.f.x1.x.menu 13 - hex $w.config.f 16 2 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START - bool $w.config.f 16 3 "Extra pipeline stage " CONFIG_AHBRAM_PIPE + hex $w.config.f 17 2 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START + bool $w.config.f 17 3 "Extra pipeline stage " CONFIG_AHBRAM_PIPE focus $w update_active global winx; global winy - if {[winfo exists .menu15] == 0} then {menu15 .menu15 "Peripherals "} - set winx [expr [winfo x .menu15]+30]; set winy [expr [winfo y .menu15]+30] + if {[winfo exists .menu16] == 0} then {menu16 .menu16 "Peripherals "} + set winx [expr [winfo x .menu16]+30]; set winy [expr [winfo y .menu16]+30] if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} update idletasks if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f @@ -3706,47 +3872,47 @@ proc menu16 {w title} { } } -proc update_menu16 {} { +proc update_menu17 {} { global CONFIG_AHBRAM_ENABLE - if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu16.config.f.x1 normal {x l}} else {configure_entry .menu16.config.f.x1 disabled {x l}} + if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu17.config.f.x1 normal {x l}} else {configure_entry .menu17.config.f.x1 disabled {x l}} global CONFIG_AHBRAM_START - if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu16.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x2.l configure -state normal; } else {.menu16.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x2.l configure -state disabled} + if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu17.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu17.config.f.x2.l configure -state normal; } else {.menu17.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu17.config.f.x2.l configure -state disabled} global CONFIG_AHBRAM_PIPE if {($CONFIG_AHBRAM_ENABLE == 1)} then { - configure_entry .menu16.config.f.x3 normal {n l y}} else {configure_entry .menu16.config.f.x3 disabled {y n l}} + configure_entry .menu17.config.f.x3 normal {n l y}} else {configure_entry .menu17.config.f.x3 disabled {y n l}} } -proc update_define_menu16 {} { +proc update_define_menu17 {} { update_define_mainmenu global CONFIG_MODULES - global tmpvar_29 + global tmpvar_32 global CONFIG_AHBRAM_SZ1 - if {$tmpvar_29 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0} + if {$tmpvar_32 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0} global CONFIG_AHBRAM_SZ2 - if {$tmpvar_29 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0} + if {$tmpvar_32 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0} global CONFIG_AHBRAM_SZ4 - if {$tmpvar_29 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0} + if {$tmpvar_32 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0} global CONFIG_AHBRAM_SZ8 - if {$tmpvar_29 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0} + if {$tmpvar_32 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0} global CONFIG_AHBRAM_SZ16 - if {$tmpvar_29 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0} + if {$tmpvar_32 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0} global CONFIG_AHBRAM_SZ32 - if {$tmpvar_29 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0} + if {$tmpvar_32 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0} global CONFIG_AHBRAM_SZ64 - if {$tmpvar_29 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0} + if {$tmpvar_32 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0} global CONFIG_AHBRAM_SZ128 - if {$tmpvar_29 == "128"} then {set CONFIG_AHBRAM_SZ128 1} else {set CONFIG_AHBRAM_SZ128 0} + if {$tmpvar_32 == "128"} then {set CONFIG_AHBRAM_SZ128 1} else {set CONFIG_AHBRAM_SZ128 0} global CONFIG_AHBRAM_SZ256 - if {$tmpvar_29 == "256"} then {set CONFIG_AHBRAM_SZ256 1} else {set CONFIG_AHBRAM_SZ256 0} + if {$tmpvar_32 == "256"} then {set CONFIG_AHBRAM_SZ256 1} else {set CONFIG_AHBRAM_SZ256 0} global CONFIG_AHBRAM_SZ512 - if {$tmpvar_29 == "512"} then {set CONFIG_AHBRAM_SZ512 1} else {set CONFIG_AHBRAM_SZ512 0} + if {$tmpvar_32 == "512"} then {set CONFIG_AHBRAM_SZ512 1} else {set CONFIG_AHBRAM_SZ512 0} global CONFIG_AHBRAM_SZ1024 - if {$tmpvar_29 == "1024"} then {set CONFIG_AHBRAM_SZ1024 1} else {set CONFIG_AHBRAM_SZ1024 0} + if {$tmpvar_32 == "1024"} then {set CONFIG_AHBRAM_SZ1024 1} else {set CONFIG_AHBRAM_SZ1024 0} global CONFIG_AHBRAM_SZ2048 - if {$tmpvar_29 == "2048"} then {set CONFIG_AHBRAM_SZ2048 1} else {set CONFIG_AHBRAM_SZ2048 0} + if {$tmpvar_32 == "2048"} then {set CONFIG_AHBRAM_SZ2048 1} else {set CONFIG_AHBRAM_SZ2048 0} global CONFIG_AHBRAM_SZ4096 - if {$tmpvar_29 == "4096"} then {set CONFIG_AHBRAM_SZ4096 1} else {set CONFIG_AHBRAM_SZ4096 0} + if {$tmpvar_32 == "4096"} then {set CONFIG_AHBRAM_SZ4096 1} else {set CONFIG_AHBRAM_SZ4096 0} global CONFIG_AHBRAM_ENABLE global CONFIG_AHBRAM_START if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00} @@ -3756,30 +3922,30 @@ proc update_define_menu16 {} { } -proc menu17 {w title} { +proc menu18 {w title} { set oldFocus [focus] - catch {focus .menu15} - catch {destroy $w; unregister_active 17} + catch {focus .menu16} + catch {destroy $w; unregister_active 18} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 17]] + set active_menus [lsort -integer [linsert $active_menus end 18]] message $w.m -width 400 -aspect 300 -text \ "Ethernet " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "Ethernet " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu18 .menu18 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu19 .menu19 \"$title\"" frame $w.f button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3807,27 +3973,27 @@ proc menu17 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 17 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE - bool $w.config.f 17 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA - global tmpvar_30 - minimenu $w.config.f 17 2 "AHB FIFO size (words) " tmpvar_30 CONFIG_GRETH_FIFO4 + bool $w.config.f 18 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE + bool $w.config.f 18 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA + global tmpvar_33 + minimenu $w.config.f 18 2 "AHB FIFO size (words) " tmpvar_33 CONFIG_GRETH_FIFO4 menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \"" - $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_30 -value "4" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_30 -value "8" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_30 -value "16" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_30 -value "32" -command "update_active" - $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_30 -value "64" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_33 -value "4" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_33 -value "8" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_33 -value "16" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_33 -value "32" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_33 -value "64" -command "update_active" menusplit $w $w.config.f.x2.x.menu 5 - bool $w.config.f 17 3 "Enable second Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH2_ENABLE - bool $w.config.f 17 4 "Enable 1000 Mbit support " CONFIG_GRETH2_GIGA - global tmpvar_31 - minimenu $w.config.f 17 5 "AHB FIFO size (words) " tmpvar_31 CONFIG_GRETH2_FIFO4 + bool $w.config.f 18 3 "Enable second Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH2_ENABLE + bool $w.config.f 18 4 "Enable 1000 Mbit support " CONFIG_GRETH2_GIGA + global tmpvar_34 + minimenu $w.config.f 18 5 "AHB FIFO size (words) " tmpvar_34 CONFIG_GRETH2_FIFO4 menu $w.config.f.x5.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \"" - $w.config.f.x5.x.menu add radiobutton -label "4" -variable tmpvar_31 -value "4" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "8" -variable tmpvar_31 -value "8" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "16" -variable tmpvar_31 -value "16" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "32" -variable tmpvar_31 -value "32" -command "update_active" - $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_31 -value "64" -command "update_active" + $w.config.f.x5.x.menu add radiobutton -label "4" -variable tmpvar_34 -value "4" -command "update_active" + $w.config.f.x5.x.menu add radiobutton -label "8" -variable tmpvar_34 -value "8" -command "update_active" + $w.config.f.x5.x.menu add radiobutton -label "16" -variable tmpvar_34 -value "16" -command "update_active" + $w.config.f.x5.x.menu add radiobutton -label "32" -variable tmpvar_34 -value "32" -command "update_active" + $w.config.f.x5.x.menu add radiobutton -label "64" -variable tmpvar_34 -value "64" -command "update_active" menusplit $w $w.config.f.x5.x.menu 5 @@ -3835,8 +4001,8 @@ proc menu17 {w title} { focus $w update_active global winx; global winy - if {[winfo exists .menu15] == 0} then {menu15 .menu15 "Peripherals "} - set winx [expr [winfo x .menu15]+30]; set winy [expr [winfo y .menu15]+30] + if {[winfo exists .menu16] == 0} then {menu16 .menu16 "Peripherals "} + set winx [expr [winfo x .menu16]+30]; set winy [expr [winfo y .menu16]+30] if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} update idletasks if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f @@ -3865,84 +4031,84 @@ proc menu17 {w title} { } } -proc update_menu17 {} { +proc update_menu18 {} { global CONFIG_GRETH_ENABLE global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu17.config.f.x1 normal {n l y}} else {configure_entry .menu17.config.f.x1 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu17.config.f.x2 normal {x l}} else {configure_entry .menu17.config.f.x2 disabled {x l}} + configure_entry .menu18.config.f.x1 normal {n l y}} else {configure_entry .menu18.config.f.x1 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu18.config.f.x2 normal {x l}} else {configure_entry .menu18.config.f.x2 disabled {x l}} global CONFIG_GRETH2_ENABLE if {($CONFIG_GRETH_ENABLE == 1)} then { - configure_entry .menu17.config.f.x3 normal {n l y}} else {configure_entry .menu17.config.f.x3 disabled {y n l}} + configure_entry .menu18.config.f.x3 normal {n l y}} else {configure_entry .menu18.config.f.x3 disabled {y n l}} global CONFIG_GRETH2_GIGA if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH2_ENABLE == 1)} then { - configure_entry .menu17.config.f.x4 normal {n l y}} else {configure_entry .menu17.config.f.x4 disabled {y n l}} - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH2_ENABLE == 1) && ($CONFIG_GRETH2_GIGA == 0)} then {configure_entry .menu17.config.f.x5 normal {x l}} else {configure_entry .menu17.config.f.x5 disabled {x l}} + configure_entry .menu18.config.f.x4 normal {n l y}} else {configure_entry .menu18.config.f.x4 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH2_ENABLE == 1) && ($CONFIG_GRETH2_GIGA == 0)} then {configure_entry .menu18.config.f.x5 normal {x l}} else {configure_entry .menu18.config.f.x5 disabled {x l}} } -proc update_define_menu17 {} { +proc update_define_menu18 {} { update_define_mainmenu global CONFIG_MODULES global CONFIG_GRETH_ENABLE global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then { set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]} - global tmpvar_30 + global tmpvar_33 global CONFIG_GRETH_FIFO4 - if {$tmpvar_30 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0} + if {$tmpvar_33 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0} global CONFIG_GRETH_FIFO8 - if {$tmpvar_30 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0} + if {$tmpvar_33 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0} global CONFIG_GRETH_FIFO16 - if {$tmpvar_30 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0} + if {$tmpvar_33 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0} global CONFIG_GRETH_FIFO32 - if {$tmpvar_30 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0} + if {$tmpvar_33 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0} global CONFIG_GRETH_FIFO64 - if {$tmpvar_30 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0} + if {$tmpvar_33 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0} global CONFIG_GRETH2_ENABLE if {($CONFIG_GRETH_ENABLE == 1)} then { set CONFIG_GRETH2_ENABLE [expr $CONFIG_GRETH2_ENABLE&15]} else {set CONFIG_GRETH2_ENABLE [expr $CONFIG_GRETH2_ENABLE|16]} global CONFIG_GRETH2_GIGA if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH2_ENABLE == 1)} then { set CONFIG_GRETH2_GIGA [expr $CONFIG_GRETH2_GIGA&15]} else {set CONFIG_GRETH2_GIGA [expr $CONFIG_GRETH2_GIGA|16]} - global tmpvar_31 + global tmpvar_34 global CONFIG_GRETH2_FIFO4 - if {$tmpvar_31 == "4"} then {set CONFIG_GRETH2_FIFO4 1} else {set CONFIG_GRETH2_FIFO4 0} + if {$tmpvar_34 == "4"} then {set CONFIG_GRETH2_FIFO4 1} else {set CONFIG_GRETH2_FIFO4 0} global CONFIG_GRETH2_FIFO8 - if {$tmpvar_31 == "8"} then {set CONFIG_GRETH2_FIFO8 1} else {set CONFIG_GRETH2_FIFO8 0} + if {$tmpvar_34 == "8"} then {set CONFIG_GRETH2_FIFO8 1} else {set CONFIG_GRETH2_FIFO8 0} global CONFIG_GRETH2_FIFO16 - if {$tmpvar_31 == "16"} then {set CONFIG_GRETH2_FIFO16 1} else {set CONFIG_GRETH2_FIFO16 0} + if {$tmpvar_34 == "16"} then {set CONFIG_GRETH2_FIFO16 1} else {set CONFIG_GRETH2_FIFO16 0} global CONFIG_GRETH2_FIFO32 - if {$tmpvar_31 == "32"} then {set CONFIG_GRETH2_FIFO32 1} else {set CONFIG_GRETH2_FIFO32 0} + if {$tmpvar_34 == "32"} then {set CONFIG_GRETH2_FIFO32 1} else {set CONFIG_GRETH2_FIFO32 0} global CONFIG_GRETH2_FIFO64 - if {$tmpvar_31 == "64"} then {set CONFIG_GRETH2_FIFO64 1} else {set CONFIG_GRETH2_FIFO64 0} + if {$tmpvar_34 == "64"} then {set CONFIG_GRETH2_FIFO64 1} else {set CONFIG_GRETH2_FIFO64 0} } -proc menu18 {w title} { +proc menu19 {w title} { set oldFocus [focus] - catch {focus .menu15} - catch {destroy $w; unregister_active 18} + catch {focus .menu16} + catch {destroy $w; unregister_active 19} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 18]] + set active_menus [lsort -integer [linsert $active_menus end 19]] message $w.m -width 400 -aspect 300 -text \ "SPI " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "SPI " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; break" - set nextscript "catch {focus $oldFocus}; menu19 .menu19 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; break" + set nextscript "catch {focus $oldFocus}; menu20 .menu20 \"$title\"" frame $w.f button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -3970,15 +4136,15 @@ proc menu18 {w title} { pack $w.config.canvas -side right -fill y - submenu $w.config.f 18 0 "SPI controller(s) " 19 + submenu $w.config.f 19 0 "SPI controller(s) " 20 focus $w update_active global winx; global winy - if {[winfo exists .menu15] == 0} then {menu15 .menu15 "Peripherals "} - set winx [expr [winfo x .menu15]+30]; set winy [expr [winfo y .menu15]+30] + if {[winfo exists .menu16] == 0} then {menu16 .menu16 "Peripherals "} + set winx [expr [winfo x .menu16]+30]; set winy [expr [winfo y .menu16]+30] if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} update idletasks if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f @@ -4007,40 +4173,40 @@ proc menu18 {w title} { } } -proc update_menu18 {} { +proc update_menu19 {} { } -proc update_define_menu18 {} { +proc update_define_menu19 {} { update_define_mainmenu global CONFIG_MODULES } -proc menu19 {w title} { +proc menu20 {w title} { set oldFocus [focus] - catch {focus .menu18} - catch {destroy $w; unregister_active 19} + catch {focus .menu19} + catch {destroy $w; unregister_active 20} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 19]] + set active_menus [lsort -integer [linsert $active_menus end 20]] message $w.m -width 400 -aspect 300 -text \ "SPI controller(s) " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "SPI controller(s) " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; catch {destroy .menu18}; unregister_active 18; menu20 .menu20 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; catch {destroy .menu19}; unregister_active 19; menu21 .menu21 \"$title\"" frame $w.f button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -4068,23 +4234,23 @@ proc menu19 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 19 0 "Enable SPI controller(s) " CONFIG_SPICTRL_ENABLE - int $w.config.f 19 1 "Number of SPI controllers " CONFIG_SPICTRL_NUM - int $w.config.f 19 2 "Slave select lines " CONFIG_SPICTRL_SLVS - int $w.config.f 19 3 "FIFO depth (2^N) " CONFIG_SPICTRL_FIFO - bool $w.config.f 19 4 "Enable slave select registers" CONFIG_SPICTRL_SLVREG - bool $w.config.f 19 5 "Enable automatic slave select" CONFIG_SPICTRL_ASEL - bool $w.config.f 19 6 "Support automated transfers " CONFIG_SPICTRL_AM - bool $w.config.f 19 7 "Support open drain mode " CONFIG_SPICTRL_ODMODE - bool $w.config.f 19 8 "Support three-wire mode " CONFIG_SPICTRL_TWEN - int $w.config.f 19 9 "Maximum supported word length (see help!) " CONFIG_SPICTRL_MAXWLEN - bool $w.config.f 19 10 "Use SYNCRAM for rx and tx queues " CONFIG_SPICTRL_SYNCRAM - global tmpvar_32 - minimenu $w.config.f 19 11 "Fault-tolerance" tmpvar_32 CONFIG_SPICTRL_NOFT + bool $w.config.f 20 0 "Enable SPI controller(s) " CONFIG_SPICTRL_ENABLE + int $w.config.f 20 1 "Number of SPI controllers " CONFIG_SPICTRL_NUM + int $w.config.f 20 2 "Slave select lines " CONFIG_SPICTRL_SLVS + int $w.config.f 20 3 "FIFO depth (2^N) " CONFIG_SPICTRL_FIFO + bool $w.config.f 20 4 "Enable slave select registers" CONFIG_SPICTRL_SLVREG + bool $w.config.f 20 5 "Enable automatic slave select" CONFIG_SPICTRL_ASEL + bool $w.config.f 20 6 "Support automated transfers " CONFIG_SPICTRL_AM + bool $w.config.f 20 7 "Support open drain mode " CONFIG_SPICTRL_ODMODE + bool $w.config.f 20 8 "Support three-wire mode " CONFIG_SPICTRL_TWEN + int $w.config.f 20 9 "Maximum supported word length (see help!) " CONFIG_SPICTRL_MAXWLEN + bool $w.config.f 20 10 "Use SYNCRAM for rx and tx queues " CONFIG_SPICTRL_SYNCRAM + global tmpvar_35 + minimenu $w.config.f 20 11 "Fault-tolerance" tmpvar_35 CONFIG_SPICTRL_NOFT menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Fault-tolerance\"" - $w.config.f.x11.x.menu add radiobutton -label "None" -variable tmpvar_32 -value "None" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "Parity-DMR" -variable tmpvar_32 -value "Parity-DMR" -command "update_active" - $w.config.f.x11.x.menu add radiobutton -label "TMR" -variable tmpvar_32 -value "TMR" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "None" -variable tmpvar_35 -value "None" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "Parity-DMR" -variable tmpvar_35 -value "Parity-DMR" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "TMR" -variable tmpvar_35 -value "TMR" -command "update_active" menusplit $w $w.config.f.x11.x.menu 3 @@ -4092,8 +4258,8 @@ proc menu19 {w title} { focus $w update_active global winx; global winy - if {[winfo exists .menu18] == 0} then {menu18 .menu18 "SPI "} - set winx [expr [winfo x .menu18]+30]; set winy [expr [winfo y .menu18]+30] + if {[winfo exists .menu19] == 0} then {menu19 .menu19 "SPI "} + set winx [expr [winfo x .menu19]+30]; set winy [expr [winfo y .menu19]+30] if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} update idletasks if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f @@ -4122,39 +4288,39 @@ proc menu19 {w title} { } } -proc update_menu19 {} { +proc update_menu20 {} { global CONFIG_SPICTRL_ENABLE global CONFIG_SPICTRL_NUM - if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu19.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x1.l configure -state normal; } else {.menu19.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x1.l configure -state disabled} + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu20.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x1.l configure -state normal; } else {.menu20.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x1.l configure -state disabled} global CONFIG_SPICTRL_SLVS - if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu19.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x2.l configure -state normal; } else {.menu19.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x2.l configure -state disabled} + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu20.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x2.l configure -state normal; } else {.menu20.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x2.l configure -state disabled} global CONFIG_SPICTRL_FIFO - if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu19.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x3.l configure -state normal; } else {.menu19.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x3.l configure -state disabled} + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu20.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x3.l configure -state normal; } else {.menu20.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x3.l configure -state disabled} global CONFIG_SPICTRL_SLVREG if {($CONFIG_SPICTRL_ENABLE == 1)} then { - configure_entry .menu19.config.f.x4 normal {n l y}} else {configure_entry .menu19.config.f.x4 disabled {y n l}} + configure_entry .menu20.config.f.x4 normal {n l y}} else {configure_entry .menu20.config.f.x4 disabled {y n l}} global CONFIG_SPICTRL_ASEL if {($CONFIG_SPICTRL_ENABLE == 1)} then { - configure_entry .menu19.config.f.x5 normal {n l y}} else {configure_entry .menu19.config.f.x5 disabled {y n l}} + configure_entry .menu20.config.f.x5 normal {n l y}} else {configure_entry .menu20.config.f.x5 disabled {y n l}} global CONFIG_SPICTRL_AM if {($CONFIG_SPICTRL_ENABLE == 1)} then { - configure_entry .menu19.config.f.x6 normal {n l y}} else {configure_entry .menu19.config.f.x6 disabled {y n l}} + configure_entry .menu20.config.f.x6 normal {n l y}} else {configure_entry .menu20.config.f.x6 disabled {y n l}} global CONFIG_SPICTRL_ODMODE if {($CONFIG_SPICTRL_ENABLE == 1)} then { - configure_entry .menu19.config.f.x7 normal {n l y}} else {configure_entry .menu19.config.f.x7 disabled {y n l}} + configure_entry .menu20.config.f.x7 normal {n l y}} else {configure_entry .menu20.config.f.x7 disabled {y n l}} global CONFIG_SPICTRL_TWEN if {($CONFIG_SPICTRL_ENABLE == 1)} then { - configure_entry .menu19.config.f.x8 normal {n l y}} else {configure_entry .menu19.config.f.x8 disabled {y n l}} + configure_entry .menu20.config.f.x8 normal {n l y}} else {configure_entry .menu20.config.f.x8 disabled {y n l}} global CONFIG_SPICTRL_MAXWLEN - if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu19.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu19.config.f.x9.l configure -state normal; } else {.menu19.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu19.config.f.x9.l configure -state disabled} + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu20.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x9.l configure -state normal; } else {.menu20.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x9.l configure -state disabled} global CONFIG_SPICTRL_SYNCRAM if {($CONFIG_SPICTRL_ENABLE == 1)} then { - configure_entry .menu19.config.f.x10 normal {n l y}} else {configure_entry .menu19.config.f.x10 disabled {y n l}} - if {($CONFIG_SPICTRL_ENABLE == 1) && ($CONFIG_SPICTRL_SYNCRAM == 1)} then {configure_entry .menu19.config.f.x11 normal {x l}} else {configure_entry .menu19.config.f.x11 disabled {x l}} + configure_entry .menu20.config.f.x10 normal {n l y}} else {configure_entry .menu20.config.f.x10 disabled {y n l}} + if {($CONFIG_SPICTRL_ENABLE == 1) && ($CONFIG_SPICTRL_SYNCRAM == 1)} then {configure_entry .menu20.config.f.x11 normal {x l}} else {configure_entry .menu20.config.f.x11 disabled {x l}} } -proc update_define_menu19 {} { +proc update_define_menu20 {} { update_define_mainmenu global CONFIG_MODULES global CONFIG_SPICTRL_ENABLE @@ -4184,40 +4350,40 @@ proc update_define_menu19 {} { global CONFIG_SPICTRL_SYNCRAM if {($CONFIG_SPICTRL_ENABLE == 1)} then { set CONFIG_SPICTRL_SYNCRAM [expr $CONFIG_SPICTRL_SYNCRAM&15]} else {set CONFIG_SPICTRL_SYNCRAM [expr $CONFIG_SPICTRL_SYNCRAM|16]} - global tmpvar_32 + global tmpvar_35 global CONFIG_SPICTRL_NOFT - if {$tmpvar_32 == "None"} then {set CONFIG_SPICTRL_NOFT 1} else {set CONFIG_SPICTRL_NOFT 0} + if {$tmpvar_35 == "None"} then {set CONFIG_SPICTRL_NOFT 1} else {set CONFIG_SPICTRL_NOFT 0} global CONFIG_SPICTRL_DMRFT - if {$tmpvar_32 == "Parity-DMR"} then {set CONFIG_SPICTRL_DMRFT 1} else {set CONFIG_SPICTRL_DMRFT 0} + if {$tmpvar_35 == "Parity-DMR"} then {set CONFIG_SPICTRL_DMRFT 1} else {set CONFIG_SPICTRL_DMRFT 0} global CONFIG_SPICTRL_TMRFT - if {$tmpvar_32 == "TMR"} then {set CONFIG_SPICTRL_TMRFT 1} else {set CONFIG_SPICTRL_TMRFT 0} + if {$tmpvar_35 == "TMR"} then {set CONFIG_SPICTRL_TMRFT 1} else {set CONFIG_SPICTRL_TMRFT 0} } -proc menu20 {w title} { +proc menu21 {w title} { set oldFocus [focus] - catch {focus .menu15} - catch {destroy $w; unregister_active 20} + catch {focus .menu16} + catch {destroy $w; unregister_active 21} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 20]] + set active_menus [lsort -integer [linsert $active_menus end 21]] message $w.m -width 400 -aspect 300 -text \ "UARTs, timers and I/O port " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "UARTs, timers and I/O port " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; break" - set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; catch {destroy .menu15}; unregister_active 15; menu21 .menu21 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; catch {destroy .menu16}; unregister_active 16; menu22 .menu22 \"$title\"" frame $w.f button $w.f.back -text "OK" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript bind all $nextscript button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -4245,39 +4411,39 @@ proc menu20 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 20 0 "Enable console UART " CONFIG_UART1_ENABLE - global tmpvar_33 - minimenu $w.config.f 20 1 "UART1 FIFO depth" tmpvar_33 CONFIG_UA1_FIFO1 + bool $w.config.f 21 0 "Enable console UART " CONFIG_UART1_ENABLE + global tmpvar_36 + minimenu $w.config.f 21 1 "UART1 FIFO depth" tmpvar_36 CONFIG_UA1_FIFO1 menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\"" - $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_33 -value "1" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_33 -value "2" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_33 -value "4" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_33 -value "8" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_33 -value "16" -command "update_active" - $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_33 -value "32" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_36 -value "1" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_36 -value "2" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_36 -value "4" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_36 -value "8" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_36 -value "16" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_36 -value "32" -command "update_active" menusplit $w $w.config.f.x1.x.menu 6 - bool $w.config.f 20 2 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE - bool $w.config.f 20 3 "Enable secondary interrupts " CONFIG_IRQ3_SEC - int $w.config.f 20 4 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC - bool $w.config.f 20 5 "Enable Timer Unit " CONFIG_GPT_ENABLE - int $w.config.f 20 6 "Number of timers (1 - 7) " CONFIG_GPT_NTIM - int $w.config.f 20 7 "Scaler width (2 - 16) " CONFIG_GPT_SW - int $w.config.f 20 8 "Timer width (2 - 32) " CONFIG_GPT_TW - int $w.config.f 20 9 "Timer unit interrupt " CONFIG_GPT_IRQ - bool $w.config.f 20 10 "Separate interrupts " CONFIG_GPT_SEPIRQ - bool $w.config.f 20 11 "Watchdog enable " CONFIG_GPT_WDOGEN - hex $w.config.f 20 12 "Initial watchdog time-out value " CONFIG_GPT_WDOG - bool $w.config.f 20 13 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE - int $w.config.f 20 14 "GPIO width " CONFIG_GRGPIO_WIDTH - hex $w.config.f 20 15 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK + bool $w.config.f 21 2 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE + bool $w.config.f 21 3 "Enable secondary interrupts " CONFIG_IRQ3_SEC + int $w.config.f 21 4 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC + bool $w.config.f 21 5 "Enable Timer Unit " CONFIG_GPT_ENABLE + int $w.config.f 21 6 "Number of timers (1 - 7) " CONFIG_GPT_NTIM + int $w.config.f 21 7 "Scaler width (2 - 16) " CONFIG_GPT_SW + int $w.config.f 21 8 "Timer width (2 - 32) " CONFIG_GPT_TW + int $w.config.f 21 9 "Timer unit interrupt " CONFIG_GPT_IRQ + bool $w.config.f 21 10 "Separate interrupts " CONFIG_GPT_SEPIRQ + bool $w.config.f 21 11 "Watchdog enable " CONFIG_GPT_WDOGEN + hex $w.config.f 21 12 "Initial watchdog time-out value " CONFIG_GPT_WDOG + bool $w.config.f 21 13 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE + int $w.config.f 21 14 "GPIO width " CONFIG_GRGPIO_WIDTH + hex $w.config.f 21 15 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK focus $w update_active global winx; global winy - if {[winfo exists .menu15] == 0} then {menu15 .menu15 "Peripherals "} - set winx [expr [winfo x .menu15]+30]; set winy [expr [winfo y .menu15]+30] + if {[winfo exists .menu16] == 0} then {menu16 .menu16 "Peripherals "} + set winx [expr [winfo x .menu16]+30]; set winy [expr [winfo y .menu16]+30] if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} update idletasks if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f @@ -4306,56 +4472,56 @@ proc menu20 {w title} { } } -proc update_menu20 {} { +proc update_menu21 {} { global CONFIG_UART1_ENABLE - if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu20.config.f.x1 normal {x l}} else {configure_entry .menu20.config.f.x1 disabled {x l}} + if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu21.config.f.x1 normal {x l}} else {configure_entry .menu21.config.f.x1 disabled {x l}} global CONFIG_IRQ3_ENABLE global CONFIG_IRQ3_SEC if {($CONFIG_IRQ3_ENABLE == 1)} then { - configure_entry .menu20.config.f.x3 normal {n l y}} else {configure_entry .menu20.config.f.x3 disabled {y n l}} + configure_entry .menu21.config.f.x3 normal {n l y}} else {configure_entry .menu21.config.f.x3 disabled {y n l}} global CONFIG_IRQ3_NSEC - if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu20.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x4.l configure -state normal; } else {.menu20.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x4.l configure -state disabled} + if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu21.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x4.l configure -state normal; } else {.menu21.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x4.l configure -state disabled} global CONFIG_GPT_ENABLE global CONFIG_GPT_NTIM - if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x6.l configure -state normal; } else {.menu20.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x6.l configure -state disabled} + if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x6.l configure -state normal; } else {.menu21.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x6.l configure -state disabled} global CONFIG_GPT_SW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x7.l configure -state normal; } else {.menu20.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x7.l configure -state disabled} + if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x7.l configure -state normal; } else {.menu21.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x7.l configure -state disabled} global CONFIG_GPT_TW - if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x8.l configure -state normal; } else {.menu20.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x8.l configure -state disabled} + if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x8.l configure -state normal; } else {.menu21.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x8.l configure -state disabled} global CONFIG_GPT_IRQ - if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x9.l configure -state normal; } else {.menu20.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x9.l configure -state disabled} + if {($CONFIG_GPT_ENABLE == 1)} then {.menu21.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x9.l configure -state normal; } else {.menu21.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x9.l configure -state disabled} global CONFIG_GPT_SEPIRQ if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu20.config.f.x10 normal {n l y}} else {configure_entry .menu20.config.f.x10 disabled {y n l}} + configure_entry .menu21.config.f.x10 normal {n l y}} else {configure_entry .menu21.config.f.x10 disabled {y n l}} global CONFIG_GPT_WDOGEN if {($CONFIG_GPT_ENABLE == 1)} then { - configure_entry .menu20.config.f.x11 normal {n l y}} else {configure_entry .menu20.config.f.x11 disabled {y n l}} + configure_entry .menu21.config.f.x11 normal {n l y}} else {configure_entry .menu21.config.f.x11 disabled {y n l}} global CONFIG_GPT_WDOG - if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu20.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x12.l configure -state normal; } else {.menu20.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x12.l configure -state disabled} + if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu21.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x12.l configure -state normal; } else {.menu21.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x12.l configure -state disabled} global CONFIG_GRGPIO_ENABLE global CONFIG_GRGPIO_WIDTH - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu20.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x14.l configure -state normal; } else {.menu20.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x14.l configure -state disabled} + if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu21.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x14.l configure -state normal; } else {.menu21.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x14.l configure -state disabled} global CONFIG_GRGPIO_IMASK - if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu20.config.f.x15.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x15.l configure -state normal; } else {.menu20.config.f.x15.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x15.l configure -state disabled} + if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu21.config.f.x15.x configure -state normal -foreground [ cget .ref -foreground ]; .menu21.config.f.x15.l configure -state normal; } else {.menu21.config.f.x15.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu21.config.f.x15.l configure -state disabled} } -proc update_define_menu20 {} { +proc update_define_menu21 {} { update_define_mainmenu global CONFIG_MODULES - global tmpvar_33 + global tmpvar_36 global CONFIG_UA1_FIFO1 - if {$tmpvar_33 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0} + if {$tmpvar_36 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0} global CONFIG_UA1_FIFO2 - if {$tmpvar_33 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0} + if {$tmpvar_36 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0} global CONFIG_UA1_FIFO4 - if {$tmpvar_33 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0} + if {$tmpvar_36 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0} global CONFIG_UA1_FIFO8 - if {$tmpvar_33 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0} + if {$tmpvar_36 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0} global CONFIG_UA1_FIFO16 - if {$tmpvar_33 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0} + if {$tmpvar_36 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0} global CONFIG_UA1_FIFO32 - if {$tmpvar_33 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0} + if {$tmpvar_36 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0} global CONFIG_IRQ3_ENABLE global CONFIG_IRQ3_SEC if {($CONFIG_IRQ3_ENABLE == 1)} then { @@ -4387,31 +4553,31 @@ proc update_define_menu20 {} { } -menu_option menu21 21 "VHDL Debugging " -proc menu21 {w title} { +menu_option menu22 22 "VHDL Debugging " +proc menu22 {w title} { set oldFocus [focus] - catch {destroy $w; unregister_active 21} + catch {destroy $w; unregister_active 22} toplevel $w -class Dialog wm withdraw $w global active_menus - set active_menus [lsort -integer [linsert $active_menus end 21]] + set active_menus [lsort -integer [linsert $active_menus end 22]] message $w.m -width 400 -aspect 300 -text \ "VHDL Debugging " -relief raised pack $w.m -pady 10 -side top -padx 10 wm title $w "VHDL Debugging " - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; break" - set nextscript "catch {focus $oldFocus}; menu22 .menu22 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; break" + set nextscript "catch {focus $oldFocus}; menu23 .menu23 \"$title\"" frame $w.f button $w.f.back -text "Main Menu" \ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22" button $w.f.next -text "Next" -underline 0\ -width 15 -command $nextscript $w.f.next configure -state disabled bind all "puts \"no more menus\" " button $w.f.prev -text "Prev" -underline 0\ - -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\"" - bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break" + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break" pack $w.f.back $w.f.next $w.f.prev -side left -expand on pack $w.f -pady 10 -side bottom -anchor w -fill x frame $w.topline -relief ridge -borderwidth 2 -height 2 @@ -4439,7 +4605,7 @@ proc menu21 {w title} { pack $w.config.canvas -side right -fill y - bool $w.config.f 21 0 "Accelerated UART tracing " CONFIG_DEBUG_UART + bool $w.config.f 22 0 "Accelerated UART tracing " CONFIG_DEBUG_UART @@ -4475,11 +4641,11 @@ proc menu21 {w title} { } } -proc update_menu21 {} { +proc update_menu22 {} { } -proc update_define_menu21 {} { +proc update_define_menu22 {} { update_define_mainmenu global CONFIG_MODULES } @@ -4685,7 +4851,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4746,6 +4911,34 @@ set CONFIG_DSU_ATRACESZ16 0 set CONFIG_IU_DISAS 0 set CONFIG_IU_DISAS_NET 0 set CONFIG_DEBUG_PC32 0 +set CONFIG_L2_ENABLE 0 +set tmpvar_28 "(not set)" +set CONFIG_L2_ASSO1 0 +set CONFIG_L2_ASSO2 0 +set CONFIG_L2_ASSO3 0 +set CONFIG_L2_ASSO4 0 +set tmpvar_29 "(not set)" +set CONFIG_L2_SZ1 0 +set CONFIG_L2_SZ2 0 +set CONFIG_L2_SZ4 0 +set CONFIG_L2_SZ8 0 +set CONFIG_L2_SZ16 0 +set CONFIG_L2_SZ32 0 +set CONFIG_L2_SZ64 0 +set CONFIG_L2_SZ128 0 +set CONFIG_L2_SZ256 0 +set CONFIG_L2_SZ512 0 +set tmpvar_30 "(not set)" +set CONFIG_L2_LINE32 0 +set CONFIG_L2_LINE64 0 +set CONFIG_L2_HPROT 0 +set CONFIG_L2_PEN 0 +set CONFIG_L2_WT 0 +set CONFIG_L2_RAN 0 +set CONFIG_L2_SHARE 0 +set CONFIG_L2_MAP 00F0 +set CONFIG_L2_MTRR 0 +set CONFIG_L2_EDAC 0 set CONFIG_AHB_DEFMST 0 set CONFIG_AHB_RROBIN 0 set CONFIG_AHB_SPLIT 0 @@ -4759,7 +4952,7 @@ set CONFIG_AHB_DTRACE 0 set CONFIG_DSU_UART 0 set CONFIG_DSU_JTAG 0 set CONFIG_DSU_ETH 0 -set tmpvar_28 "(not set)" +set tmpvar_31 "(not set)" set CONFIG_DSU_ETHSZ1 0 set CONFIG_DSU_ETHSZ2 0 set CONFIG_DSU_ETHSZ4 0 @@ -4784,7 +4977,7 @@ set CONFIG_MCTRL_PROGPAGE 0 set CONFIG_AHBSTAT_ENABLE 0 set CONFIG_AHBSTAT_NFTSLV 1 set CONFIG_AHBRAM_ENABLE 0 -set tmpvar_29 "(not set)" +set tmpvar_32 "(not set)" set CONFIG_AHBRAM_SZ1 0 set CONFIG_AHBRAM_SZ2 0 set CONFIG_AHBRAM_SZ4 0 @@ -4802,7 +4995,7 @@ set CONFIG_AHBRAM_START A00 set CONFIG_AHBRAM_PIPE 0 set CONFIG_GRETH_ENABLE 0 set CONFIG_GRETH_GIGA 0 -set tmpvar_30 "(not set)" +set tmpvar_33 "(not set)" set CONFIG_GRETH_FIFO4 0 set CONFIG_GRETH_FIFO8 0 set CONFIG_GRETH_FIFO16 0 @@ -4810,7 +5003,7 @@ set CONFIG_GRETH_FIFO32 0 set CONFIG_GRETH_FIFO64 0 set CONFIG_GRETH2_ENABLE 0 set CONFIG_GRETH2_GIGA 0 -set tmpvar_31 "(not set)" +set tmpvar_34 "(not set)" set CONFIG_GRETH2_FIFO4 0 set CONFIG_GRETH2_FIFO8 0 set CONFIG_GRETH2_FIFO16 0 @@ -4827,12 +5020,12 @@ set CONFIG_SPICTRL_ODMODE 0 set CONFIG_SPICTRL_TWEN 0 set CONFIG_SPICTRL_MAXWLEN 0 set CONFIG_SPICTRL_SYNCRAM 0 -set tmpvar_32 "(not set)" +set tmpvar_35 "(not set)" set CONFIG_SPICTRL_NOFT 0 set CONFIG_SPICTRL_DMRFT 0 set CONFIG_SPICTRL_TMRFT 0 set CONFIG_UART1_ENABLE 0 -set tmpvar_33 "(not set)" +set tmpvar_36 "(not set)" set CONFIG_UA1_FIFO1 0 set CONFIG_UA1_FIFO2 0 set CONFIG_UA1_FIFO4 0 @@ -4857,6 +5050,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_LEON3FT_EN 4 set CONFIG_IUFT_NONE 4 @@ -5315,7 +5509,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5393,6 +5586,48 @@ proc writeconfig {file1 file2} { if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 } global CONFIG_DEBUG_PC32 if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 } + write_comment $cfg $autocfg "L2 Cache" + global CONFIG_L2_ENABLE + write_tristate $cfg $autocfg CONFIG_L2_ENABLE $CONFIG_L2_ENABLE [list $notmod] 2 + global tmpvar_28 + + if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_L2_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_ASSO1 0 [list $notmod] 2 } + if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_L2_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_ASSO2 0 [list $notmod] 2 } + if { $tmpvar_28 == "3" } then { write_tristate $cfg $autocfg CONFIG_L2_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_ASSO3 0 [list $notmod] 2 } + if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_L2_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_ASSO4 0 [list $notmod] 2 } + global tmpvar_29 + + if { $tmpvar_29 == "1" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ1 0 [list $notmod] 2 } + if { $tmpvar_29 == "2" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ2 0 [list $notmod] 2 } + if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ4 0 [list $notmod] 2 } + if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ8 0 [list $notmod] 2 } + if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ16 0 [list $notmod] 2 } + if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ32 0 [list $notmod] 2 } + if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ64 0 [list $notmod] 2 } + if { $tmpvar_29 == "128" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ128 0 [list $notmod] 2 } + if { $tmpvar_29 == "256" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ256 0 [list $notmod] 2 } + if { $tmpvar_29 == "512" } then { write_tristate $cfg $autocfg CONFIG_L2_SZ512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_SZ512 0 [list $notmod] 2 } + global tmpvar_30 + + if { $tmpvar_30 == "32" } then { write_tristate $cfg $autocfg CONFIG_L2_LINE32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_LINE32 0 [list $notmod] 2 } + if { $tmpvar_30 == "64" } then { write_tristate $cfg $autocfg CONFIG_L2_LINE64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_L2_LINE64 0 [list $notmod] 2 } + global CONFIG_L2_HPROT + write_tristate $cfg $autocfg CONFIG_L2_HPROT $CONFIG_L2_HPROT [list $notmod] 2 + global CONFIG_L2_PEN + write_tristate $cfg $autocfg CONFIG_L2_PEN $CONFIG_L2_PEN [list $notmod] 2 + global CONFIG_L2_WT + write_tristate $cfg $autocfg CONFIG_L2_WT $CONFIG_L2_WT [list $notmod] 2 + global CONFIG_L2_RAN + write_tristate $cfg $autocfg CONFIG_L2_RAN $CONFIG_L2_RAN [list $notmod] 2 + global CONFIG_L2_SHARE + global CONFIG_L2_ASSO1 + if {($CONFIG_L2_ASSO1 != "1")} then {write_tristate $cfg $autocfg CONFIG_L2_SHARE $CONFIG_L2_SHARE [list $notmod] 2 } + global CONFIG_L2_MAP + write_hex $cfg $autocfg CONFIG_L2_MAP $CONFIG_L2_MAP $notmod + global CONFIG_L2_MTRR + write_int $cfg $autocfg CONFIG_L2_MTRR $CONFIG_L2_MTRR $notmod + global CONFIG_L2_EDAC + write_tristate $cfg $autocfg CONFIG_L2_EDAC $CONFIG_L2_EDAC [list $notmod] 2 write_comment $cfg $autocfg "AMBA configuration" global CONFIG_AHB_DEFMST write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod @@ -5422,13 +5657,13 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETH global CONFIG_GRETH_ENABLE if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 } - global tmpvar_28 + global tmpvar_31 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { - if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 } - if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 } - if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 } - if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 } - if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }} + if { $tmpvar_31 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 } + if { $tmpvar_31 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 } + if { $tmpvar_31 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 } + if { $tmpvar_31 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 } + if { $tmpvar_31 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }} global CONFIG_DSU_IPMSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod } global CONFIG_DSU_IPLSB @@ -5438,10 +5673,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " global CONFIG_MCTRL_LEON2 @@ -5472,46 +5706,47 @@ proc writeconfig {file1 file2} { write_comment $cfg $autocfg "On-chip RAM/ROM " global CONFIG_AHBRAM_ENABLE write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2 - global tmpvar_29 + global tmpvar_32 if {($CONFIG_AHBRAM_ENABLE == 1)} then { - if { $tmpvar_29 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 } - if { $tmpvar_29 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 } - if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 } - if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 } - if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 } - if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 } - if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 } - if { $tmpvar_29 == "128" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ128 0 [list $notmod] 2 } - if { $tmpvar_29 == "256" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ256 0 [list $notmod] 2 } - if { $tmpvar_29 == "512" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ512 0 [list $notmod] 2 } - if { $tmpvar_29 == "1024" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1024 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1024 0 [list $notmod] 2 } - if { $tmpvar_29 == "2048" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2048 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2048 0 [list $notmod] 2 } - if { $tmpvar_29 == "4096" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4096 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4096 0 [list $notmod] 2 }} + if { $tmpvar_32 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 } + if { $tmpvar_32 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 } + if { $tmpvar_32 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 } + if { $tmpvar_32 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 } + if { $tmpvar_32 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 } + if { $tmpvar_32 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 } + if { $tmpvar_32 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 } + if { $tmpvar_32 == "128" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ128 0 [list $notmod] 2 } + if { $tmpvar_32 == "256" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ256 0 [list $notmod] 2 } + if { $tmpvar_32 == "512" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ512 0 [list $notmod] 2 } + if { $tmpvar_32 == "1024" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1024 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1024 0 [list $notmod] 2 } + if { $tmpvar_32 == "2048" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2048 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2048 0 [list $notmod] 2 } + if { $tmpvar_32 == "4096" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4096 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4096 0 [list $notmod] 2 }} global CONFIG_AHBRAM_START if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod } global CONFIG_AHBRAM_PIPE if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } - global tmpvar_30 + global tmpvar_33 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { - if { $tmpvar_30 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_30 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_30 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_30 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_30 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }} + if { $tmpvar_33 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 } + if { $tmpvar_33 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 } + if { $tmpvar_33 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 } + if { $tmpvar_33 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 } + if { $tmpvar_33 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }} global CONFIG_GRETH2_ENABLE if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH2_ENABLE $CONFIG_GRETH2_ENABLE [list $notmod] 2 } global CONFIG_GRETH2_GIGA if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH2_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH2_GIGA $CONFIG_GRETH2_GIGA [list $notmod] 2 } - global tmpvar_31 + global tmpvar_34 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH2_ENABLE == 1) && ($CONFIG_GRETH2_GIGA == 0)} then { - if { $tmpvar_31 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_31 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_31 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_31 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO32 0 [list $notmod] 2 } - if { $tmpvar_31 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO64 0 [list $notmod] 2 }} + if { $tmpvar_34 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO4 0 [list $notmod] 2 } + if { $tmpvar_34 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO8 0 [list $notmod] 2 } + if { $tmpvar_34 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO16 0 [list $notmod] 2 } + if { $tmpvar_34 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO32 0 [list $notmod] 2 } + if { $tmpvar_34 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH2_FIFO64 0 [list $notmod] 2 }} write_comment $cfg $autocfg "SPI " write_comment $cfg $autocfg "SPI controller(s) " global CONFIG_SPICTRL_ENABLE @@ -5536,22 +5771,22 @@ proc writeconfig {file1 file2} { if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_MAXWLEN $CONFIG_SPICTRL_MAXWLEN $notmod } global CONFIG_SPICTRL_SYNCRAM if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_SYNCRAM $CONFIG_SPICTRL_SYNCRAM [list $notmod] 2 } - global tmpvar_32 + global tmpvar_35 if {($CONFIG_SPICTRL_ENABLE == 1) && ($CONFIG_SPICTRL_SYNCRAM == 1)} then { - if { $tmpvar_32 == "None" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_NOFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_NOFT 0 [list $notmod] 2 } - if { $tmpvar_32 == "Parity-DMR" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_DMRFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_DMRFT 0 [list $notmod] 2 } - if { $tmpvar_32 == "TMR" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_TMRFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_TMRFT 0 [list $notmod] 2 }} + if { $tmpvar_35 == "None" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_NOFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_NOFT 0 [list $notmod] 2 } + if { $tmpvar_35 == "Parity-DMR" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_DMRFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_DMRFT 0 [list $notmod] 2 } + if { $tmpvar_35 == "TMR" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_TMRFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_TMRFT 0 [list $notmod] 2 }} write_comment $cfg $autocfg "UARTs, timers and I/O port " global CONFIG_UART1_ENABLE write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2 - global tmpvar_33 + global tmpvar_36 if {($CONFIG_UART1_ENABLE == 1)} then { - if { $tmpvar_33 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 } - if { $tmpvar_33 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 } - if { $tmpvar_33 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 } - if { $tmpvar_33 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 } - if { $tmpvar_33 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 } - if { $tmpvar_33 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }} + if { $tmpvar_36 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 } + if { $tmpvar_36 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 } + if { $tmpvar_36 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 } + if { $tmpvar_36 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 } + if { $tmpvar_36 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 } + if { $tmpvar_36 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }} global CONFIG_IRQ3_ENABLE write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2 global CONFIG_IRQ3_SEC @@ -5774,6 +6009,22 @@ proc clear_choices { } { global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0 global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0 global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0 + global CONFIG_L2_ASSO1; set CONFIG_L2_ASSO1 0 + global CONFIG_L2_ASSO2; set CONFIG_L2_ASSO2 0 + global CONFIG_L2_ASSO3; set CONFIG_L2_ASSO3 0 + global CONFIG_L2_ASSO4; set CONFIG_L2_ASSO4 0 + global CONFIG_L2_SZ1; set CONFIG_L2_SZ1 0 + global CONFIG_L2_SZ2; set CONFIG_L2_SZ2 0 + global CONFIG_L2_SZ4; set CONFIG_L2_SZ4 0 + global CONFIG_L2_SZ8; set CONFIG_L2_SZ8 0 + global CONFIG_L2_SZ16; set CONFIG_L2_SZ16 0 + global CONFIG_L2_SZ32; set CONFIG_L2_SZ32 0 + global CONFIG_L2_SZ64; set CONFIG_L2_SZ64 0 + global CONFIG_L2_SZ128; set CONFIG_L2_SZ128 0 + global CONFIG_L2_SZ256; set CONFIG_L2_SZ256 0 + global CONFIG_L2_SZ512; set CONFIG_L2_SZ512 0 + global CONFIG_L2_LINE32; set CONFIG_L2_LINE32 0 + global CONFIG_L2_LINE64; set CONFIG_L2_LINE64 0 global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0 global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0 global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0 @@ -6238,91 +6489,129 @@ proc update_choices { } { global CONFIG_DSU_ATRACESZ16 if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_25 "16" } global tmpvar_28 - set tmpvar_28 "2" + set tmpvar_28 "1" + global CONFIG_L2_ASSO1 + if { $CONFIG_L2_ASSO1 == 1 } then { set tmpvar_28 "1" } + global CONFIG_L2_ASSO2 + if { $CONFIG_L2_ASSO2 == 1 } then { set tmpvar_28 "2" } + global CONFIG_L2_ASSO3 + if { $CONFIG_L2_ASSO3 == 1 } then { set tmpvar_28 "3" } + global CONFIG_L2_ASSO4 + if { $CONFIG_L2_ASSO4 == 1 } then { set tmpvar_28 "4" } + global tmpvar_29 + set tmpvar_29 "64" + global CONFIG_L2_SZ1 + if { $CONFIG_L2_SZ1 == 1 } then { set tmpvar_29 "1" } + global CONFIG_L2_SZ2 + if { $CONFIG_L2_SZ2 == 1 } then { set tmpvar_29 "2" } + global CONFIG_L2_SZ4 + if { $CONFIG_L2_SZ4 == 1 } then { set tmpvar_29 "4" } + global CONFIG_L2_SZ8 + if { $CONFIG_L2_SZ8 == 1 } then { set tmpvar_29 "8" } + global CONFIG_L2_SZ16 + if { $CONFIG_L2_SZ16 == 1 } then { set tmpvar_29 "16" } + global CONFIG_L2_SZ32 + if { $CONFIG_L2_SZ32 == 1 } then { set tmpvar_29 "32" } + global CONFIG_L2_SZ64 + if { $CONFIG_L2_SZ64 == 1 } then { set tmpvar_29 "64" } + global CONFIG_L2_SZ128 + if { $CONFIG_L2_SZ128 == 1 } then { set tmpvar_29 "128" } + global CONFIG_L2_SZ256 + if { $CONFIG_L2_SZ256 == 1 } then { set tmpvar_29 "256" } + global CONFIG_L2_SZ512 + if { $CONFIG_L2_SZ512 == 1 } then { set tmpvar_29 "512" } + global tmpvar_30 + set tmpvar_30 "32" + global CONFIG_L2_LINE32 + if { $CONFIG_L2_LINE32 == 1 } then { set tmpvar_30 "32" } + global CONFIG_L2_LINE64 + if { $CONFIG_L2_LINE64 == 1 } then { set tmpvar_30 "64" } + global tmpvar_31 + set tmpvar_31 "2" global CONFIG_DSU_ETHSZ1 - if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_28 "1" } + if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_31 "1" } global CONFIG_DSU_ETHSZ2 - if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_28 "2" } + if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_31 "2" } global CONFIG_DSU_ETHSZ4 - if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_28 "4" } + if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_31 "4" } global CONFIG_DSU_ETHSZ8 - if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_28 "8" } + if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_31 "8" } global CONFIG_DSU_ETHSZ16 - if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_28 "16" } - global tmpvar_29 - set tmpvar_29 "4" + if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_31 "16" } + global tmpvar_32 + set tmpvar_32 "4" global CONFIG_AHBRAM_SZ1 - if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_29 "1" } + if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_32 "1" } global CONFIG_AHBRAM_SZ2 - if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_29 "2" } + if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_32 "2" } global CONFIG_AHBRAM_SZ4 - if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_29 "4" } + if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_32 "4" } global CONFIG_AHBRAM_SZ8 - if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_29 "8" } + if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_32 "8" } global CONFIG_AHBRAM_SZ16 - if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_29 "16" } + if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_32 "16" } global CONFIG_AHBRAM_SZ32 - if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_29 "32" } + if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_32 "32" } global CONFIG_AHBRAM_SZ64 - if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_29 "64" } + if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_32 "64" } global CONFIG_AHBRAM_SZ128 - if { $CONFIG_AHBRAM_SZ128 == 1 } then { set tmpvar_29 "128" } + if { $CONFIG_AHBRAM_SZ128 == 1 } then { set tmpvar_32 "128" } global CONFIG_AHBRAM_SZ256 - if { $CONFIG_AHBRAM_SZ256 == 1 } then { set tmpvar_29 "256" } + if { $CONFIG_AHBRAM_SZ256 == 1 } then { set tmpvar_32 "256" } global CONFIG_AHBRAM_SZ512 - if { $CONFIG_AHBRAM_SZ512 == 1 } then { set tmpvar_29 "512" } + if { $CONFIG_AHBRAM_SZ512 == 1 } then { set tmpvar_32 "512" } global CONFIG_AHBRAM_SZ1024 - if { $CONFIG_AHBRAM_SZ1024 == 1 } then { set tmpvar_29 "1024" } + if { $CONFIG_AHBRAM_SZ1024 == 1 } then { set tmpvar_32 "1024" } global CONFIG_AHBRAM_SZ2048 - if { $CONFIG_AHBRAM_SZ2048 == 1 } then { set tmpvar_29 "2048" } + if { $CONFIG_AHBRAM_SZ2048 == 1 } then { set tmpvar_32 "2048" } global CONFIG_AHBRAM_SZ4096 - if { $CONFIG_AHBRAM_SZ4096 == 1 } then { set tmpvar_29 "4096" } - global tmpvar_30 - set tmpvar_30 "8" + if { $CONFIG_AHBRAM_SZ4096 == 1 } then { set tmpvar_32 "4096" } + global tmpvar_33 + set tmpvar_33 "8" global CONFIG_GRETH_FIFO4 - if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_30 "4" } + if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_33 "4" } global CONFIG_GRETH_FIFO8 - if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_30 "8" } + if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_33 "8" } global CONFIG_GRETH_FIFO16 - if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_30 "16" } + if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_33 "16" } global CONFIG_GRETH_FIFO32 - if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_30 "32" } + if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_33 "32" } global CONFIG_GRETH_FIFO64 - if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_30 "64" } - global tmpvar_31 - set tmpvar_31 "8" + if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_33 "64" } + global tmpvar_34 + set tmpvar_34 "8" global CONFIG_GRETH2_FIFO4 - if { $CONFIG_GRETH2_FIFO4 == 1 } then { set tmpvar_31 "4" } + if { $CONFIG_GRETH2_FIFO4 == 1 } then { set tmpvar_34 "4" } global CONFIG_GRETH2_FIFO8 - if { $CONFIG_GRETH2_FIFO8 == 1 } then { set tmpvar_31 "8" } + if { $CONFIG_GRETH2_FIFO8 == 1 } then { set tmpvar_34 "8" } global CONFIG_GRETH2_FIFO16 - if { $CONFIG_GRETH2_FIFO16 == 1 } then { set tmpvar_31 "16" } + if { $CONFIG_GRETH2_FIFO16 == 1 } then { set tmpvar_34 "16" } global CONFIG_GRETH2_FIFO32 - if { $CONFIG_GRETH2_FIFO32 == 1 } then { set tmpvar_31 "32" } + if { $CONFIG_GRETH2_FIFO32 == 1 } then { set tmpvar_34 "32" } global CONFIG_GRETH2_FIFO64 - if { $CONFIG_GRETH2_FIFO64 == 1 } then { set tmpvar_31 "64" } - global tmpvar_32 - set tmpvar_32 "None" + if { $CONFIG_GRETH2_FIFO64 == 1 } then { set tmpvar_34 "64" } + global tmpvar_35 + set tmpvar_35 "None" global CONFIG_SPICTRL_NOFT - if { $CONFIG_SPICTRL_NOFT == 1 } then { set tmpvar_32 "None" } + if { $CONFIG_SPICTRL_NOFT == 1 } then { set tmpvar_35 "None" } global CONFIG_SPICTRL_DMRFT - if { $CONFIG_SPICTRL_DMRFT == 1 } then { set tmpvar_32 "Parity-DMR" } + if { $CONFIG_SPICTRL_DMRFT == 1 } then { set tmpvar_35 "Parity-DMR" } global CONFIG_SPICTRL_TMRFT - if { $CONFIG_SPICTRL_TMRFT == 1 } then { set tmpvar_32 "TMR" } - global tmpvar_33 - set tmpvar_33 "1" + if { $CONFIG_SPICTRL_TMRFT == 1 } then { set tmpvar_35 "TMR" } + global tmpvar_36 + set tmpvar_36 "1" global CONFIG_UA1_FIFO1 - if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_33 "1" } + if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_36 "1" } global CONFIG_UA1_FIFO2 - if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_33 "2" } + if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_36 "2" } global CONFIG_UA1_FIFO4 - if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_33 "4" } + if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_36 "4" } global CONFIG_UA1_FIFO8 - if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_33 "8" } + if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_36 "8" } global CONFIG_UA1_FIFO16 - if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_33 "16" } + if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_36 "16" } global CONFIG_UA1_FIFO32 - if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_33 "32" } + if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_36 "32" } } diff --git a/designs/leon3-terasic-de4/leon3mp.vhd b/designs/leon3-terasic-de4/leon3mp.vhd index 40a8fd99..6138d370 100644 --- a/designs/leon3-terasic-de4/leon3mp.vhd +++ b/designs/leon3-terasic-de4/leon3mp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -17,7 +17,7 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- LEON3 Demonstration design --- Copyright (C) 2013 Aeroflex Gaisler +-- Copyright (C) 2014 Aeroflex Gaisler ------------------------------------------------------------------------------ @@ -25,6 +25,7 @@ library ieee; use ieee.std_logic_1164.all; library grlib, techmap; use grlib.amba.all; +use grlib.devices.all; use grlib.stdlib.all; use techmap.gencomp.all; library gaisler; @@ -37,6 +38,7 @@ use gaisler.can.all; use gaisler.net.all; use gaisler.jtag.all; use gaisler.ddrpkg.all; +use gaisler.l2cache.all; -- pragma translate_off use gaisler.sim.all; -- pragma translate_on @@ -67,16 +69,16 @@ entity leon3mp is SMA_CLKIN_p : in std_logic; -- SMA_GXBCLK_p : in std_logic; GCLKIN : in std_logic; - GCLKOUT_FPGA : out std_logic; - SMA_CLKOUT_p : out std_logic; +-- GCLKOUT_FPGA : out std_logic; +-- SMA_CLKOUT_p : out std_logic; -- cpu reset CPU_RESET_n : in std_ulogic; -- max i/o - MAX_CONF_D : inout std_logic_vector(3 downto 0); - MAX_I2C_SCLK : out std_logic; - MAX_I2C_SDAT : inout std_logic; +-- MAX_CONF_D : inout std_logic_vector(3 downto 0); +-- MAX_I2C_SCLK : out std_logic; +-- MAX_I2C_SDAT : inout std_logic; -- LEDs LED : out std_logic_vector(7 downto 0); @@ -91,9 +93,9 @@ entity leon3mp is SLIDE_SW : in std_logic_vector(3 downto 0); -- temperature - TEMP_SMCLK : out std_logic; - TEMP_SMDAT : inout std_logic; - TEMP_INT_n : in std_logic; +-- TEMP_SMCLK : out std_logic; +-- TEMP_SMDAT : inout std_logic; +-- TEMP_INT_n : in std_logic; -- current CSENSE_ADC_FO : out std_logic; @@ -110,10 +112,10 @@ entity leon3mp is EEP_SDA : inout std_logic; -- sdcard - SD_CLK : out std_logic; - SD_CMD : inout std_logic; - SD_DAT : inout std_logic_vector(3 downto 0); - SD_WP_n : in std_logic; + -- SD_CLK : out std_logic; + -- SD_CMD : inout std_logic; + -- SD_DAT : inout std_logic_vector(3 downto 0); + -- SD_WP_n : in std_logic; -- Ethernet interfaces ETH_INT_n : in std_logic_vector(3 downto 0); @@ -220,7 +222,7 @@ entity leon3mp is -- GPIO GPIO0_D : inout std_logic_vector(35 downto 0); - GPIO1_D : inout std_logic_vector(35 downto 0); +-- GPIO1_D : inout std_logic_vector(35 downto 0); -- Ext I/O -- EXT_IO : inout std_logic; @@ -231,8 +233,8 @@ entity leon3mp is -- HSMA_CLKIN_p1 : in std_logic; -- HSMA_CLKIN_p2 : in std_logic; -- HSMA_CLKIN0 : in std_logic; --- HSMA_CLKOUT_n2 : out std_logic; --- HSMA_CLKOUT_p2 : out std_logic; + HSMA_CLKOUT_n2 : out std_logic; + HSMA_CLKOUT_p2 : out std_logic; -- HSMA_D : inout std_logic_vector(3 downto 0); -- HSMA_GXB_RX_p : in std_logic_vector(3 downto 0); -- HSMA_GXB_TX_p : out std_logic_vector(3 downto 0); @@ -285,64 +287,11 @@ end; architecture rtl of leon3mp is - component sgmii2gmii is - port ( - ref_clk : in std_logic := '0'; -- pcs_ref_clk_clock_connection.clk - clk : in std_logic := '0'; -- control_port_clock_connection.clk - reset : in std_logic := '0'; -- reset_connection.reset - address : in std_logic_vector(4 downto 0) := (others => '0'); -- control_port.address - readdata : out std_logic_vector(15 downto 0); -- .readdata - read : in std_logic := '0'; -- .read - writedata : in std_logic_vector(15 downto 0) := (others => '0'); -- .writedata - write : in std_logic := '0'; -- .write - waitrequest : out std_logic; -- .waitrequest - tx_clk : out std_logic; -- pcs_transmit_clock_connection.clk - rx_clk : out std_logic; -- pcs_receive_clock_connection.clk - reset_tx_clk : in std_logic := '0'; -- pcs_transmit_reset_connection.reset - reset_rx_clk : in std_logic := '0'; -- pcs_receive_reset_connection.reset - gmii_rx_dv : out std_logic; -- gmii_connection.gmii_rx_dv - gmii_rx_d : out std_logic_vector(7 downto 0); -- .gmii_rx_d - gmii_rx_err : out std_logic; -- .gmii_rx_err - gmii_tx_en : in std_logic := '0'; -- .gmii_tx_en - gmii_tx_d : in std_logic_vector(7 downto 0) := (others => '0'); -- .gmii_tx_d - gmii_tx_err : in std_logic := '0'; -- .gmii_tx_err - tx_clkena : out std_logic; -- clock_enable_connection.tx_clkena - rx_clkena : out std_logic; -- .rx_clkena - mii_rx_dv : out std_logic; -- mii_connection.mii_rx_dv - mii_rx_d : out std_logic_vector(3 downto 0); -- .mii_rx_d - mii_rx_err : out std_logic; -- .mii_rx_err - mii_tx_en : in std_logic := '0'; -- .mii_tx_en - mii_tx_d : in std_logic_vector(3 downto 0) := (others => '0'); -- .mii_tx_d - mii_tx_err : in std_logic := '0'; -- .mii_tx_err - mii_col : out std_logic; -- .mii_col - mii_crs : out std_logic; -- .mii_crs - set_10 : out std_logic; -- sgmii_status_connection.set_10 - set_1000 : out std_logic; -- .set_1000 - set_100 : out std_logic; -- .set_100 - hd_ena : out std_logic; -- .hd_ena - led_crs : out std_logic; -- status_led_connection.crs - led_link : out std_logic; -- .link - led_col : out std_logic; -- .col - led_an : out std_logic; -- .an - led_char_err : out std_logic; -- .char_err - led_disp_err : out std_logic; -- .disp_err - rx_recovclkout : out std_logic; -- serdes_control_connection.export - txp : out std_logic; -- serial_connection.txp - rxp : in std_logic := '0' -- .rxp - ); - end component sgmii2gmii; - - component pll_125 is - port( - inclk0 : in std_logic := '0'; - c0 : out std_logic - ); - end component; - constant blength : integer := 12; constant fifodepth : integer := 8; - - signal vcc, gnd : std_logic_vector(4 downto 0); + constant burstlen : integer := 16; -- burst length in 32-bit words + + signal vcc, gnd : std_logic_vector(7 downto 0); signal memi : memory_in_type; signal memo : memory_out_type; @@ -358,9 +307,17 @@ architecture rtl of leon3mp is signal ahbmi : ahb_mst_in_type; signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); + signal edcl_ahbmi : ahb_mst_in_type; + signal edcl_ahbmo : ahb_mst_out_vector_type(1 downto 0); + + signal mem_ahbsi : ahb_slv_in_type; + signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none); + signal mem_ahbmi : ahb_mst_in_type; + signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none); + signal clkm, rstn, rstraw : std_logic; - signal cgi : clkgen_in_type; - signal cgo : clkgen_out_type; + signal cgi, cgi_125 : clkgen_in_type; + signal cgo, cgo_125 : clkgen_out_type; signal u1i, dui : uart_in_type; signal u1o, duo : uart_out_type; @@ -392,24 +349,27 @@ architecture rtl of leon3mp is signal fpi : grfpu_in_vector_type; signal fpo : grfpu_out_vector_type; - signal gmiii1, gmiii2 : eth_in_type; - signal gmiio1, gmiio2 : eth_out_type; - - signal sgmiii1, sgmiii2 : eth_sgmii_in_type; - signal sgmiio1, sgmiio2 : eth_sgmii_out_type; + signal nolock : ahb2ahb_ctrl_type; + signal noifctrl : ahb2ahb_ifctrl_type; + + signal gmiii0, gmiii1, gmiii2, gmiii3 : eth_in_type; + signal gmiio0, gmiio1, gmiio2, gmiio3 : eth_out_type; signal eth_tx_pad, eth_rx_pad : std_logic_vector(3 downto 0) ; - signal reset1_tx_clk, reset1_rx_clk, reset2_tx_clk, reset2_rx_clk, ref_clk, ctrl_rst: std_logic; + signal reset1_tx_clk, reset1_rx_clk, reset2_tx_clk, reset2_rx_clk, ref_clk, ctrl_rst, ref_rstn, ref_rst: std_logic; signal led_crs1, led_link1, led_col1, led_an1, led_char_err1, led_disp_err1 : std_logic; signal led_crs2, led_link2, led_col2, led_an2, led_char_err2, led_disp_err2 : std_logic; + signal led1_int, led2_int, led3_int, led4_int, led5_int, led6_int, led7_int : std_logic; constant BOARD_FREQ : integer := 100000; -- Board frequency in KHz constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz constant IOAEN : integer := 0; constant OEPOL : integer := padoen_polarity(padtech); - + constant DEBUG_BUS : integer := CFG_L2_EN; + constant EDCL_SEP_AHB : integer := CFG_L2_EN; + attribute syn_keep : boolean; attribute syn_preserve : boolean; attribute keep : boolean; @@ -421,8 +381,19 @@ architecture rtl of leon3mp is signal ddr_clk_fb : std_ulogic; signal clkm125 : std_logic; signal clklock, lock, clkml : std_logic; + + signal mdio_o, mdio_i, mdio_oe : std_logic; + signal mdio_o_sgmii, mdio_i_sgmii, mdio_oe_sgmii : std_logic; + signal gprego : std_logic_vector(15 downto 0); + + signal counter1 : std_logic_vector(26 downto 0); + signal counter2 : std_logic_vector(3 downto 0); + signal bitslip_int : std_logic; begin + nolock <= ahb2ahb_ctrl_none; + noifctrl <= ahb2ahb_ifctrl_none; + ---------------------------------------------------------------------- --- Reset and Clock generation ------------------------------------- ---------------------------------------------------------------------- @@ -452,14 +423,15 @@ begin ---------------------------------------------------------------------- ahb0 : ahbctrl -- AHB arbiter/multiplexer - generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, fpnpen => CFG_FPNPEN, rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN, - nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH, + nahbm => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+ + DEBUG_BUS+CFG_GRETH+CFG_GRETH2, nahbs => 8) port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); ---------------------------------------------------------------------- ---- LEON3 processor and DSU ----------------------------------------- +--- LEON3 processor ----------------------------------------- ---------------------------------------------------------------------- cpu : for i in 0 to CFG_NCPU-1 generate @@ -497,37 +469,180 @@ begin end generate; errorn_pad : odpad generic map (tech => padtech) port map (LED(0), dbgo(0).error); + +---------------------------------------------------------------------- +--- Debug ----------------------------------------- +---------------------------------------------------------------------- + -- Debug DSU and debug links can be connected to the system on two + -- ways: + -- + -- a) Directly to the main AHB bus + -- b) Connected via a dedicated debug AHB bus that is connected to + -- the main AHB bus via a AHB/AHB bridge. + - dsugen : if CFG_DSU = 1 generate - dsu0 : dsu3 -- LEON3 Debug Support Unit - generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, - ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) - port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); - dsui.enable <= '1'; - dsubre_pad : inpad generic map (tech => padtech) port map (BUTTON(0), dsubren); - dsui.break <= not dsubren; - dsuact_pad : outpad generic map (tech => padtech) port map (LED(1), dsuo.active); - end generate; - nodsu : if CFG_DSU = 0 generate - ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; - end generate; + dsui.enable <= '1'; + dsubre_pad : inpad generic map (tech => padtech) port map (BUTTON(0), dsubren); + dsui.break <= not dsubren; + dsuact_pad : outpad generic map (tech => padtech) port map (LED(1), dsuo.active); + + dui.rxd <= uart_rxd when slide_sw(0) = '0' else '1'; - dcomgen : if CFG_AHB_UART = 1 generate - dcom0: ahbuart -- Debug UART - generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) - port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); - dui.rxd <= uart_rxd when slide_sw(0) = '0' else '1'; - end generate; + nodbgbus : if DEBUG_BUS /= 1 generate + -- DSU and debug links directly connected to main bus + + edcl_ahbmi <= ahbmi; + -- EDCL ahbmo interfaces are not used in this configuration + + dsugen : if CFG_DSU = 1 generate + dsu0 : dsu3 -- LEON3 Debug Support Unit + generic map (hindex => 2, haddr => 16#E00#, hmask => 16#FC0#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + end generate; + nodsu : if CFG_DSU = 0 generate + ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + end generate; + + dcomgen : if CFG_AHB_UART = 1 generate + dcom0: ahbuart -- Debug UART + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + end generate; -- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; - ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate - ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) - port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), - open, open, open, open, open, open, open, gnd(0)); + ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate + ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART) + port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART), + open, open, open, open, open, open, open, gnd(0)); + end generate; + end generate; + + dbgbus : if DEBUG_BUS = 1 generate + -- DSU and debug links connected via AHB/AHB bridge to process + dbgsubsys : block + constant DBG_AHBIO : integer := 16#EFF#; + + signal dbg_ahbsi : ahb_slv_in_type; + signal dbg_ahbso : ahb_slv_out_vector := (others => ahbs_none); + signal dbg_ahbmi : ahb_mst_in_type; + signal dbg_ahbmo : ahb_mst_out_vector := (others => ahbm_none); + begin + + edcl_ahbmi <= dbg_ahbmi; + dbg_ahbmo(CFG_AHB_UART+CFG_AHB_JTAG) <= edcl_ahbmo(0); + dbg_ahbmo(CFG_AHB_UART+CFG_AHB_JTAG+1) <= edcl_ahbmo(1); + + dsugen : if CFG_DSU = 1 generate + dsu0 : dsu3_mb -- LEON3 Debug Support Unit + generic map (hindex => 0, haddr => 16#E00#, hmask => 16#FC0#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + port map (rstn, clkm, ahbmi, dbg_ahbsi, dbg_ahbso(0), ahbsi, dbgo, dbgi, dsui, dsuo); + end generate; + nodsu : if CFG_DSU = 0 generate + dbg_ahbso(0) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; + end generate; + + membustrc : if true generate + ahbtrace0: ahbtrace_mb + generic map ( + hindex => 2, + ioaddr => 16#000#, + iomask => 16#E00#, + tech => memtech, + irq => 0, + kbytes => 8, + ahbfilt => 2) + port map( + rst => rstn, + clk => clkm, + ahbsi => dbg_ahbsi, + ahbso => dbg_ahbso(2), + tahbmi => mem_ahbmi, + tahbsi => mem_ahbsi); + end generate; + + dcomgen : if CFG_AHB_UART = 1 generate + dcom0: ahbuart -- Debug UART + generic map (hindex => 0, pindex => 7, paddr => 7) + port map (rstn, clkm, dui, duo, apbi, apbo(7), dbg_ahbmi, dbg_ahbmo(0)); + end generate; +-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; + + ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate + ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_AHB_UART) + port map(rstn, clkm, tck, tms, tdi, tdo, dbg_ahbmi, dbg_ahbmo(CFG_AHB_UART), + open, open, open, open, open, open, open, gnd(0)); + end generate; + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => 0, fpnpen => CFG_FPNPEN, + rrobin => CFG_RROBIN, ioaddr => DBG_AHBIO, + ioen => 1, + nahbm => CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRETH2, + nahbs => 3) + port map (rstn, clkm, dbg_ahbmi, dbg_ahbmo, dbg_ahbsi, dbg_ahbso); + + -- Bridge connecting debug bus -> processor bus + -- Configuration: + -- Prefetching with a maximum burst length of 8 words + -- No interrupt synchronisation + -- Debug cores cannot make locked accesses => lckdac = 0 + -- Slave maximum access size: 32 + -- Master maximum access size: 128 + -- Read and write combining + -- No special handling for instruction bursts + debug_bridge: ahb2ahb + generic map ( + memtech => 0, + hsindex => 1, + hmindex => CFG_NCPU+CFG_GRETH+CFG_GRETH2, + slv => 0, + dir => 1, + ffact => 1, + pfen => 1, + wburst => burstlen, + iburst => 8, + rburst => burstlen, + irqsync => 0, + bar0 => ahb2ahb_membar(16#000#, '1', '1', 16#800#), + bar1 => ahb2ahb_membar(16#800#, '0', '0', 16#C00#), + bar2 => ahb2ahb_membar(16#C00#, '0', '0', 16#E00#), + bar3 => ahb2ahb_membar(16#F00#, '0', '0', 16#F00#), + sbus => 2, + mbus => 0, + ioarea => 16#FFF#, + ibrsten => 0, + lckdac => 0, + slvmaccsz => 32, + mstmaccsz => 32, + rdcomb => 0, + wrcomb => 0, + combmask => 0, + allbrst => 0, + ifctrlen => 0, + fcfs => 0, + fcfsmtech => 0, + scantest => 0, + split => 0, + pipe => 0) + port map ( + rstn => rstn, + hclkm => clkm, + hclks => clkm, + ahbsi => dbg_ahbsi, + ahbso => dbg_ahbso(1), + ahbmi => ahbmi, + ahbmo => ahbmo(CFG_NCPU+CFG_GRETH+CFG_GRETH2), + ahbso2 => ahbso, + lcki => nolock, + lcko => open, + ifctrl => noifctrl); + end block dbgsubsys; end generate; ---------------------------------------------------------------------- ---- Memory controllers ---------------------------------------------- +--- Memory subsystem ---------------------------------------------- ---------------------------------------------------------------------- data_pad : iopadvv generic map (tech => padtech, width => 16, oepol => OEPOL) port map (FSM_D, memo.data(31 downto 16), memo.vbdrive(31 downto 16), memi.data(31 downto 16)); @@ -569,37 +684,100 @@ begin memo <= memory_out_none; end generate; - ddr2if0: entity work.ddr2if - generic map( - hindex => 3, - haddr => 16#400#, - hmask => 16#C00#, - burstlen => 32 - ) - port map ( - pll_ref_clk => OSC_50_BANK4, - global_reset_n => CPU_RESET_n, - mem_a => M1_DDR2_addr(13 downto 0), - mem_ba => M1_DDR2_ba, - mem_ck => M1_DDR2_clk, - mem_ck_n => M1_DDR2_clk_n, - mem_cke => M1_DDR2_cke(0), - mem_cs_n => M1_DDR2_cs_n(0), - mem_dm => M1_DDR2_dm, - mem_ras_n => M1_DDR2_ras_n, - mem_cas_n => M1_DDR2_cas_n, - mem_we_n => M1_DDR2_we_n, - mem_dq => M1_DDR2_dq, - mem_dqs => M1_DDR2_dqs, - mem_dqs_n => M1_DDR2_dqsn, - mem_odt => M1_DDR2_odt(0), - ahb_clk => clkm, - ahb_rst => rstn, - ahbsi => ahbsi, - ahbso => ahbso(3), - oct_rdn => M1_DDR2_oct_rdn, - oct_rup => M1_DDR2_oct_rup - ); + ----------------------------------------------------------------------------- + -- DDR2 SDRAM memory controller + ----------------------------------------------------------------------------- + l2cdis : if CFG_L2_EN = 0 generate + ddr2if0: entity work.ddr2if + generic map( + hindex => 3, + haddr => 16#400#, + hmask => 16#C00#, + burstlen => burstlen + ) + port map ( + pll_ref_clk => OSC_50_BANK4, + global_reset_n => CPU_RESET_n, + mem_a => M1_DDR2_addr(13 downto 0), + mem_ba => M1_DDR2_ba, + mem_ck => M1_DDR2_clk, + mem_ck_n => M1_DDR2_clk_n, + mem_cke => M1_DDR2_cke(0), + mem_cs_n => M1_DDR2_cs_n(0), + mem_dm => M1_DDR2_dm, + mem_ras_n => M1_DDR2_ras_n, + mem_cas_n => M1_DDR2_cas_n, + mem_we_n => M1_DDR2_we_n, + mem_dq => M1_DDR2_dq, + mem_dqs => M1_DDR2_dqs, + mem_dqs_n => M1_DDR2_dqsn, + mem_odt => M1_DDR2_odt(0), + ahb_clk => clkm, + ahb_rst => rstn, + ahbsi => ahbsi, + ahbso => ahbso(3), + oct_rdn => M1_DDR2_oct_rdn, + oct_rup => M1_DDR2_oct_rup + ); + end generate; + ----------------------------------------------------------------------------- + -- L2 cache covering DDR2 SDRAM memory controller + ----------------------------------------------------------------------------- + l2cen : if CFG_L2_EN /= 0 generate + memorysubsys : block + constant MEM_AHBIO : integer := 16#FFE#; + begin + l2c0 : l2c + generic map(hslvidx => 3, hmstidx => 0, cen => CFG_L2_PEN, + haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#, + cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS, + linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE, + memtech => memtech, bbuswidth => AHBDW, + bioaddr => MEM_AHBIO, biomask => 16#fff#, + sbus => 0, mbus => 1, arch => CFG_L2_SHARE, + ft => CFG_L2_EDAC) + port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(3), + ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso); + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => MEM_AHBIO, + ioen => IOAEN, nahbm => 1, nahbs => 1) + port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso); + + ddr2if0: entity work.ddr2if + generic map( + hindex => 0, + haddr => 16#400#, + hmask => 16#C00#, + burstlen => burstlen + ) + port map ( + pll_ref_clk => OSC_50_BANK4, + global_reset_n => CPU_RESET_n, + mem_a => M1_DDR2_addr(13 downto 0), + mem_ba => M1_DDR2_ba, + mem_ck => M1_DDR2_clk, + mem_ck_n => M1_DDR2_clk_n, + mem_cke => M1_DDR2_cke(0), + mem_cs_n => M1_DDR2_cs_n(0), + mem_dm => M1_DDR2_dm, + mem_ras_n => M1_DDR2_ras_n, + mem_cas_n => M1_DDR2_cas_n, + mem_we_n => M1_DDR2_we_n, + mem_dq => M1_DDR2_dq, + mem_dqs => M1_DDR2_dqs, + mem_dqs_n => M1_DDR2_dqsn, + mem_odt => M1_DDR2_odt(0), + ahb_clk => clkm, + ahb_rst => rstn, + ahbsi => mem_ahbsi, + ahbso => mem_ahbso(0), + oct_rdn => M1_DDR2_oct_rdn, + oct_rup => M1_DDR2_oct_rup + ); + end block memorysubsys; + end generate; lock <= '1'; ---------------------------------------------------------------------- @@ -655,6 +833,9 @@ begin port map (GPIO0_D(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); end generate; end generate; + unused_pio_pads : for i in (CFG_GRGPIO_WIDTH*CFG_GRGPIO_ENABLE) to 35 generate + GPIO0_D(i) <= '0'; + end generate; spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller spi1 : spictrl @@ -685,255 +866,255 @@ begin end generate; nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate; + fan_pad : outpad generic map (tech => padtech) port map (FAN_CTRL, vcc(0)); + ----------------------------------------------------------------------- --- ETHERNET --------------------------------------------------------- ----------------------------------------------------------------------- - eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC - - pll0: entity work.pll_125 - port map (OSC_50_BANK3, ref_clk); + eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC - rst1 : rstgen -- reset generator - generic map (acthigh => 1) - port map (CPU_RESET_n, clkm, '1', ctrl_rst, open); + -- 125 MHz Gigabit ethernet clock generator from 50 MHz input + sgmii_pll0 : clkgen + generic map ( + tech => CFG_CLKTECH, + clk_mul => 5, + clk_div => 2, + sdramen => 0, + freq => 50000 + ) + port map ( + clkin => OSC_50_BANK3, + pciclkin => gnd(0), + clk => ref_clk, + clkn => open, + clk2x => open, + sdclk => open, + pciclk => open, + cgi => cgi_125, + cgo => cgo_125 + ); - rst10 : rstgen -- reset generator - generic map (acthigh => 1) - port map (CPU_RESET_n, gmiii1.tx_clk, '1', reset1_tx_clk, open); + -- 125 MHz clock reset synchronizer + rst2 : rstgen + generic map (acthigh => 0) + port map (gmiio0.reset, ref_clk, cgo_125.clklock, ref_rstn, open); - rst11 : rstgen -- reset generator - generic map (acthigh => 1) - port map (CPU_RESET_n, gmiii1.rx_clk, '1', reset1_rx_clk, open); + -- TODO: reset of LVDS transceiver must be asserted at least 10 ns + ref_rst <= not ref_rstn; - bridge1: sgmii2gmii + bridge0: sgmii + generic map ( + fabtech => fabtech + ) port map( - ref_clk => ref_clk, -- in pcs_ref_clk_clock_connection.clk - clk => clkm, -- in control_port_clock_connection.clk - reset => ctrl_rst, -- in reset_connection.reset - address => zero32(4 downto 0), -- in control_port.address - readdata => open, -- out .readdata - read => '0', -- in .read - writedata => zero32(15 downto 0), -- in .writedata - write => '0', -- in .write - waitrequest => open, -- out .waitrequest - tx_clk => gmiii1.tx_clk, -- out pcs_transmit_clock_connection.clk - rx_clk => gmiii1.rx_clk, -- out pcs_receive_clock_connection.clk - reset_tx_clk => reset1_tx_clk, -- in pcs_transmit_reset_connection.reset - reset_rx_clk => reset1_rx_clk, -- in pcs_receive_reset_connection.reset - gmii_rx_dv => gmiii1.rx_dv, -- out gmii_connection.gmii_rx_dv - gmii_rx_d => gmiii1.rxd, -- out .gmii_rx_d - gmii_rx_err => gmiii1.rx_er, -- out .gmii_rx_err - gmii_tx_en => gmiio1.tx_en, -- in .gmii_tx_en - gmii_tx_d => gmiio1.txd, -- in .gmii_tx_d - gmii_tx_err => gmiio1.tx_er, -- in .gmii_tx_err - tx_clkena => open, -- out clock_enable_connection.tx_clkena - rx_clkena => open, -- out .rx_clkena - mii_rx_dv => open, -- out mii_connection.mii_rx_dv - mii_rx_d => open, -- out .mii_rx_d - mii_rx_err => open, -- out .mii_rx_err - mii_tx_en => '0', -- in .mii_tx_en - mii_tx_d => zero32(3 downto 0), -- in .mii_tx_d - mii_tx_err => '0', -- in .mii_tx_err - mii_col => open, -- out .mii_col - mii_crs => open, -- out .mii_crs - set_10 => open, -- out sgmii_status_connection.set_10 - set_1000 => open, -- out .set_1000 - set_100 => open, -- out .set_100 - hd_ena => open, -- out .hd_ena - led_crs => led_crs1, -- out status_led_connection.crs - led_link => led_link1, -- out .link - led_col => open, -- out .col - led_an => open, -- out .an - led_char_err => open, -- out .char_err - led_disp_err => open, -- out .disp_err - rx_recovclkout => open, -- out serdes_control_connection.export - txp => ETH_TX_p(0), -- out serial_connection.txp - rxp => ETH_RX_p(0) -- in .rxp + clk_125 => ref_clk, + rst_125 => ref_rst, + + ser_rx_p => ETH_RX_p(0), + ser_tx_p => ETH_TX_p(0), + + txd => gmiio0.txd, + tx_en => gmiio0.tx_en, + tx_er => gmiio0.tx_er, + tx_clk => gmiii0.gtx_clk, + + rxd => gmiii0.rxd, + rx_dv => gmiii0.rx_dv, + rx_er => gmiii0.rx_er, + rx_col => gmiii0.rx_col, + rx_crs => gmiii0.rx_crs, + rx_clk => gmiii0.rx_clk, + + -- optional MDIO interface to PCS + mdc => gmiio0.mdc, + mdio_o => mdio_o_sgmii, + mdio_oe => mdio_oe_sgmii, + mdio_i => mdio_i_sgmii ); - led2_pad : outpad generic map (tech => padtech) port map (LED(2), led_crs1); - led3_pad : outpad generic map (tech => padtech) port map (LED(3), led_link1); - --led4_pad : outpad generic map (tech => padtech) port map (LED(4), led_col); - --led5_pad : outpad generic map (tech => padtech) port map (LED(5), led_an); - --led6_pad : outpad generic map (tech => padtech) port map (LED(6), led_char_err); - --led7_pad : outpad generic map (tech => padtech) port map (LED(7), led_disp_err); - - e1 : grethm - generic map( - hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, + e0 : greth_gbit_mb -- Gaisler (gigabit) Ethernet MAC 0 + generic map ( + hindex => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS), + ehindex => CFG_AHB_UART+CFG_AHB_JTAG, pindex => 11, paddr => 11, - pirq => 6, - memtech => stratix3, + pirq => 6, + memtech => memtech, mdcscaler => CPU_FREQ/1000, - enable_mdio => 1, - fifosize => CFG_ETH_FIFO, nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, + burstlength => burstlen, macaddrh => CFG_ETH_ENM, - macaddrl => CFG_ETH_ENL, + macaddrl => CFG_ETH_ENL, phyrstadr => 0, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, - giga => CFG_GRETH1G + edclsepahb => EDCL_SEP_AHB + ) + port map ( + rst => rstn, + clk => clkm, + ahbmi => ahbmi, + ahbmo => ahbmo(CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)), + ahbmi2 => edcl_ahbmi, + ahbmo2 => edcl_ahbmo(0), + apbi => apbi, + apbo => apbo(11), + ethi => gmiii0, + etho => gmiio0 + ); + + gmiii0.tx_clk <= gmiii0.gtx_clk; + gmiii0.phyrstaddr <= "00000"; + gmiii0.edcladdr <= ( others => '0' ); + gmiii0.edclsepahb <= '1'; + gmiii0.edcldisable <= SLIDE_SW(1); + + -- SGMII MDIO DEBUG BYPASS + mdio_oe_sgmii <= gmiio0.mdio_oe when gprego(0) = '1' else + '1'; + + mdio_o_sgmii <= gmiio0.mdio_o when gprego(0) = '1' else + '0'; + + mdio_oe <= '1' when gprego(0) = '1' else + gmiio0.mdio_oe; + + mdio_o <= '0' when gprego(0) = '1' else + gmiio0.mdio_o; + + gmiii0.mdio_i <= mdio_i_sgmii when gprego(0) = '1' else + mdio_i; + + grgpreg0 : grgpreg + generic map ( + pindex => 8, + paddr => 4, + rstval => 0 ) - port map( - rst => rstn, - clk => clkm, - ahbmi => ahbmi, - ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), - apbi => apbi, - apbo => apbo(11), - ethi => gmiii1, - etho => gmiio1 + port map ( + rst => rstn, + clk => clkm, + apbi => apbi, + apbo => apbo(8), + gprego => gprego ); - -- MDIO interface setup - emdio_pad1 : iopad generic map (tech => padtech) - port map (ETH_MDIO(0), gmiio1.mdio_o, gmiio1.mdio_oe, gmiii1.mdio_i); + -- + led2_pad : outpad generic map (tech => padtech) port map (LED(2), vcc(0)); + led3_pad : outpad generic map (tech => padtech) port map (LED(3), vcc(0)); + led4_pad : outpad generic map (tech => padtech) port map (LED(4), vcc(0)); + led5_pad : outpad generic map (tech => padtech) port map (LED(5), vcc(0)); + led6_pad : outpad generic map (tech => padtech) port map (LED(6), vcc(0)); + led7_pad : outpad generic map (tech => padtech) port map (LED(7), vcc(0)); - emdc_pad1 : outpad generic map (tech => padtech) - port map (ETH_MDC(0), gmiio1.mdc); + ethrst_pad : outpad generic map (tech => padtech) + port map (ETH_RST_n, gmiio0.reset); - eint_pad1 : inpad generic map (tech => padtech) - port map (ETH_INT_n(0), gmiii1.mdint); - - erst_pad1 : outpad generic map (tech => padtech) - port map (ETH_RST_n, gmiio1.reset); + -- MDIO interface setup + emdio0_pad : iopad generic map (tech => padtech) + port map (ETH_MDIO(0), mdio_o, mdio_oe, mdio_i); - gmiii1.edclsepahb <= '0'; - gmiii1.edcldisable <= '0'; - gmiii1.phyrstaddr <= (others => '0'); - gmiii1.edcladdr <= (others => '0'); + emdc0_pad : outpad generic map (tech => padtech) + port map (ETH_MDC(0), gmiio0.mdc); - gmiii1.gtx_clk <= ref_clk; - gmiii1.rmii_clk <= '0'; - gmiii1.rx_col <= '0'; - gmiii1.rx_crs <= '0'; + eint0_pad : inpad generic map (tech => padtech) + port map (ETH_INT_n(0), gmiii0.mdint); end generate; - noeth1 : if CFG_GRETH = 0 generate - gmiio1 <= eth_out_none; + noeth0 : if CFG_GRETH = 0 generate + gmiio0 <= eth_out_none; + edcl_ahbmo(0) <= ahbm_none; end generate; - eth2: if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC - - rst20 : rstgen -- reset generator - generic map (acthigh => 1) - port map (CPU_RESET_n, gmiii2.tx_clk, '1', reset2_tx_clk, open); - - rst21 : rstgen -- reset generator - generic map (acthigh => 1) - port map (CPU_RESET_n, gmiii2.rx_clk, '1', reset2_rx_clk, open); + eth1: if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC + + -- 125 MHz clock reset synchronizer - bridge2: sgmii2gmii + bridge1: sgmii + generic map ( + fabtech => fabtech + ) port map( - ref_clk => ref_clk, -- in pcs_ref_clk_clock_connection.clk - clk => clkm, -- in control_port_clock_connection.clk - reset => ctrl_rst, -- in reset_connection.reset - address => zero32(4 downto 0), -- in control_port.address - readdata => open, -- out .readdata - read => '0', -- in .read - writedata => zero32(15 downto 0), -- in .writedata - write => '0', -- in .write - waitrequest => open, -- out .waitrequest - tx_clk => gmiii2.tx_clk, -- out pcs_transmit_clock_connection.clk - rx_clk => gmiii2.rx_clk, -- out pcs_receive_clock_connection.clk - reset_tx_clk => reset2_tx_clk, -- in pcs_transmit_reset_connection.reset - reset_rx_clk => reset2_rx_clk, -- in pcs_receive_reset_connection.reset - gmii_rx_dv => gmiii2.rx_dv, -- out gmii_connection.gmii_rx_dv - gmii_rx_d => gmiii2.rxd, -- out .gmii_rx_d - gmii_rx_err => gmiii2.rx_er, -- out .gmii_rx_err - gmii_tx_en => gmiio2.tx_en, -- in .gmii_tx_en - gmii_tx_d => gmiio2.txd, -- in .gmii_tx_d - gmii_tx_err => gmiio2.tx_er, -- in .gmii_tx_err - tx_clkena => open, -- out clock_enable_connection.tx_clkena - rx_clkena => open, -- out .rx_clkena - mii_rx_dv => open, -- out mii_connection.mii_rx_dv - mii_rx_d => open, -- out .mii_rx_d - mii_rx_err => open, -- out .mii_rx_err - mii_tx_en => '0', -- in .mii_tx_en - mii_tx_d => zero32(3 downto 0), -- in .mii_tx_d - mii_tx_err => '0', -- in .mii_tx_err - mii_col => open, -- out .mii_col - mii_crs => open, -- out .mii_crs - set_10 => open, -- out sgmii_status_connection.set_10 - set_1000 => open, -- out .set_1000 - set_100 => open, -- out .set_100 - hd_ena => open, -- out .hd_ena - led_crs => led_crs2, -- out status_led_connection.crs - led_link => led_link2, -- out .link - led_col => open, -- out .col - led_an => open, -- out .an - led_char_err => open, -- out .char_err - led_disp_err => open, -- out .disp_err - rx_recovclkout => open, -- out serdes_control_connection.export - txp => ETH_TX_p(1), -- out serial_connection.txp - rxp => ETH_RX_p(1) -- in .rxp + clk_125 => ref_clk, + rst_125 => ref_rst, + + ser_rx_p => ETH_RX_p(1), + ser_tx_p => ETH_TX_p(1), + + txd => gmiio1.txd, + tx_en => gmiio1.tx_en, + tx_er => gmiio1.tx_er, + tx_clk => gmiii1.gtx_clk, + + rxd => gmiii1.rxd, + rx_dv => gmiii1.rx_dv, + rx_er => gmiii1.rx_er, + rx_col => gmiii1.rx_col, + rx_crs => gmiii1.rx_crs, + rx_clk => gmiii1.rx_clk, + + -- optional MDIO interface to PCS + mdc => gmiio1.mdc ); - led4_pad : outpad generic map (tech => padtech) port map (LED(4), led_crs2); - led5_pad : outpad generic map (tech => padtech) port map (LED(5), led_link2); - - e2 : grethm - generic map( - hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH, + e1 : greth_gbit_mb -- Gaisler (gigabit) Ethernet MAC 1 + generic map ( + hindex => CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+CFG_GRETH, + ehindex => CFG_AHB_UART+CFG_AHB_JTAG+1, pindex => 12, paddr => 12, - pirq => 7, - memtech => stratix3, + pirq => 7, + memtech => memtech, mdcscaler => CPU_FREQ/1000, - enable_mdio => 1, - fifosize => CFG_ETH2_FIFO, nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, + burstlength => burstlen, macaddrh => CFG_ETH_ENM, - macaddrl => CFG_ETH_ENL, - phyrstadr => 0, + macaddrl => CFG_ETH_ENL, + phyrstadr => 1, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, - giga => CFG_GRETH21G - ) - port map( - rst => rstn, - clk => clkm, - ahbmi => ahbmi, - ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH), - apbi => apbi, - apbo => apbo(12), - ethi => gmiii2, - etho => gmiio2 - ); - - -- MDIO interface setup - emdio_pad2 : iopad generic map (tech => padtech) - port map (ETH_MDIO(1), gmiio2.mdio_o, gmiio2.mdio_oe, gmiii2.mdio_i); - - emdc_pad2 : outpad generic map (tech => padtech) - port map (ETH_MDC(1), gmiio2.mdc); + edclsepahb => EDCL_SEP_AHB + ) + port map ( + rst => rstn, + clk => clkm, + ahbmi => ahbmi, + ahbmo => ahbmo(CFG_NCPU+(CFG_AHB_UART+CFG_AHB_JTAG)*(1-DEBUG_BUS)+CFG_GRETH), + ahbmi2 => edcl_ahbmi, + ahbmo2 => edcl_ahbmo(1), + apbi => apbi, + apbo => apbo(12), + ethi => gmiii1, + etho => gmiio1 + ); + + gmiii1.tx_clk <= gmiii1.gtx_clk; + gmiii1.phyrstaddr <= "00001"; + gmiii1.edcladdr <= ( others => '0' ); + gmiii1.edclsepahb <= '1'; + gmiii1.edcldisable <= SLIDE_SW(1); - eint_pad2 : inpad generic map (tech => padtech) - port map (ETH_INT_n(1), gmiii2.mdint); + -- MDIO interface setup + emdio1_pad : iopad generic map (tech => padtech) + port map (ETH_MDIO(1), gmiio1.mdio_o, gmiio1.mdio_oe, gmiii1.mdio_i); - --gmiio2.reset <= ; -- not connected, using gmiio1.reset - gmiii2.edclsepahb <= '0'; - gmiii2.edcldisable <= '0'; - gmiii2.phyrstaddr <= "00001"; - gmiii2.edcladdr <= (others => '0'); + emdc1_pad : outpad generic map (tech => padtech) + port map (ETH_MDC(1), gmiio1.mdc); - gmiii2.gtx_clk <= ref_clk; - gmiii2.rmii_clk <= '0'; - gmiii2.rx_col <= '0'; - gmiii2.rx_crs <= '0'; + eint1_pad : inpad generic map (tech => padtech) + port map (ETH_INT_n(1), gmiii1.mdint); - end generate; + end generate; noeth2 : if CFG_GRETH2 = 0 generate gmiio2 <= eth_out_none; + edcl_ahbmo(1) <= ahbm_none; end generate; ----------------------------------------------------------------------- @@ -981,7 +1162,7 @@ ahbso(ahbso'high downto 5) <= (others => ahbs_none); -- pragma translate_off x : report_design generic map ( - msg1 => "LEON3 TerASIC DE4 Demonstration design", + msg1 => system_table(ALTERA_DE4), fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1 ); diff --git a/designs/leon3-terasic-de4/leon3mp_quartus.sdc b/designs/leon3-terasic-de4/leon3mp_quartus.sdc index 57ccea23..297b03d2 100644 --- a/designs/leon3-terasic-de4/leon3mp_quartus.sdc +++ b/designs/leon3-terasic-de4/leon3mp_quartus.sdc @@ -41,9 +41,8 @@ create_clock -period 10.0 PLL_CLKIN_p derive_pll_clocks set ahbclks [ get_clocks { clkgen0* } ] +set eth0clks [ get_clocks { \eth0:bridge0|* } ] +#set eth1clks [ get_clocks { \eth1:bridge1|* } ] -set sgmii_rx_clk [ get_clocks { eth1:bridge0|sgmii2gmii_inst|i_tse_pcs_0|the_altera_tse_pma_lvds_rx|ALTLVDS_RX_component|auto_generated|rx[0]|clk0 } ] - -set_false_path -from [get_clocks {\eth1:bridge0|sgmii2gmii_inst|i_tse_pcs_0|the_altera_tse_pma_lvds_rx|ALTLVDS_RX_component|auto_generated|rx[0]|clk0}] -to [get_clocks {clkgen0|\stra3:v|sdclk_pll|\nosd:altpll0|auto_generated|pll1|clk[0]}] - -set_false_path -from [get_clocks {\eth1:bridge1|sgmii2gmii_inst|i_tse_pcs_0|the_altera_tse_pma_lvds_rx|ALTLVDS_RX_component|auto_generated|rx[0]|clk0}] -to [get_clocks {clkgen0|\stra3:v|sdclk_pll|\nosd:altpll0|auto_generated|pll1|clk[0]}] \ No newline at end of file +constrain_cdc $ahbclks 10.0 $eth0clks 8.0 +#constrain_cdc $ahbclks 10.0 $eth1clks 8.0 diff --git a/designs/leon3-terasic-de4/ram.srec b/designs/leon3-terasic-de4/ram.srec index c6717fab..97723eeb 100755 --- a/designs/leon3-terasic-de4/ram.srec +++ b/designs/leon3-terasic-de4/ram.srec @@ -1,11 +1,11 @@ S00B000072616D2E73726563D9 -S31540000000881000000910006C81C12398010000008F +S31540000000881000000910007181C1215801000000CC S31540000010A1480000A75000001080203EAC102001EF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006C81C522EC0100000087 -S31540000050A14800002910006981C523500100000015 -S31540000060A14800002910006981C523BC0100000099 +S31540000040A14800002910007181C520AC01000000C4 +S31540000050A14800002910006E81C523D4010000008C +S31540000060A14800002910006F81C520400100000012 S3154000007091D02000010000000100000001000000B6 S3154000008091D02000010000000100000001000000A6 S31540000090A1480000A75000001080201EAC10200987 @@ -16,21 +16,21 @@ S315400000D091D0200001000000010000000100000056 S315400000E091D0200001000000010000000100000046 S315400000F091D0200001000000010000000100000036 S3154000010091D0200001000000010000000100000025 -S31540000110AE102001A148000010806A55A75000008B -S31540000120AE102002A148000010806A51A75000007E -S31540000130AE102003A148000010806A4DA750000071 -S31540000140AE102004A148000010806A49A750000064 -S31540000150AE102005A148000010806A45A750000057 -S31540000160AE102006A148000010806A41A75000004A -S31540000170AE102007A148000010806A3DA75000003D -S31540000180AE102008A148000010806A39A750000030 -S31540000190AE102009A148000010806A35A750000023 -S315400001A0AE10200AA148000010806A31A750000016 -S315400001B0AE10200BA148000010806A2DA750000009 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+S31540048B80000000000000000000000000000000009B +S31540048B90000000000000000000000000000000008B S31540048BA0000000000000000000000000000000007B S31540048BB0000000000000000000000000000000006B S31540048BC0000000000000000000000000000000005B @@ -18625,7 +18625,8 @@ S31540048BE0000000000000000000000000000000003B S31540048BF0000000000000000000000000000000002B S31540048C00000000000000000000000000000000001A S31540048C10000000000000000000000000000000000A -S31540048C200000000000000000800003100000000067 +S31540048C2000000000000000000000000000000000FA S31540048C30000000008000010000000008000000075A S31540048C40000000060000000300000000FFFF8AD079 +S30940048C508000031043 S70540000000BA diff --git a/designs/leon3-terasic-de4/systest.c b/designs/leon3-terasic-de4/systest.c index afd597f5..efde26e3 100644 --- a/designs/leon3-terasic-de4/systest.c +++ b/designs/leon3-terasic-de4/systest.c @@ -1,12 +1,13 @@ -main() - +int main(void) { report_start(); - - base_test(); - //greth_test(0x80000b00); + base_test(); + + greth_test(0x80000b00); + + greth_test(0x80000c00); - report_end(); + report_end(); } diff --git a/designs/leon3-terasic-de4/testbench.vhd b/designs/leon3-terasic-de4/testbench.vhd index 2ff8e202..252a42fa 100644 --- a/designs/leon3-terasic-de4/testbench.vhd +++ b/designs/leon3-terasic-de4/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -26,6 +26,7 @@ use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; +use gaisler.net.all; use work.debug.all; library techmap; use techmap.gencomp.all; @@ -33,6 +34,7 @@ library micron; use micron.components.all; library grlib; use grlib.stdlib.all; +use grlib.amba.all; use work.config.all; -- configuration @@ -73,14 +75,15 @@ architecture behav of testbench is signal SMA_CLKIN_p : std_logic := '0'; --signal SMA_GXBCLK_p : std_logic; signal GCLKIN : std_logic := '0'; - signal GCLKOUT_FPGA : std_logic := '0'; - signal SMA_CLKOUT_p : std_logic := '0'; +-- signal GCLKOUT_FPGA : std_logic := '0'; +-- signal SMA_CLKOUT_p : std_logic := '0'; + signal clk_125 : std_logic := '0'; -- cpu reset signal CPU_RESET_n : std_ulogic := '0'; -- max i/o - signal MAX_CONF_D : std_logic_vector(3 downto 0); - signal MAX_I2C_SCLK : std_logic; - signal MAX_I2C_SDAT : std_logic; +-- signal MAX_CONF_D : std_logic_vector(3 downto 0); +-- signal MAX_I2C_SCLK : std_logic; +-- signal MAX_I2C_SDAT : std_logic; -- LEDs signal LED : std_logic_vector(7 downto 0); -- buttons @@ -90,9 +93,9 @@ architecture behav of testbench is -- slide switches signal SLIDE_SW : std_logic_vector(3 downto 0); -- temperature - signal TEMP_SMCLK : std_logic; - signal TEMP_SMDAT : std_logic; - signal TEMP_INT_n : std_logic; +-- signal TEMP_SMCLK : std_logic; +-- signal TEMP_SMDAT : std_logic; +-- signal TEMP_INT_n : std_logic; -- current signal CSENSE_ADC_FO : std_logic; signal CSENSE_SCK : std_logic; @@ -105,10 +108,10 @@ architecture behav of testbench is signal EEP_SCL : std_logic; signal EEP_SDA : std_logic; -- sdcard - signal SD_CLK : std_logic; - signal SD_CMD : std_logic; - signal SD_DAT : std_logic_vector(3 downto 0); - signal SD_WP_n : std_logic; +-- signal SD_CLK : std_logic; +-- signal SD_CMD : std_logic; +-- signal SD_DAT : std_logic_vector(3 downto 0); +-- signal SD_WP_n : std_logic; -- Ethernet interfaces signal ETH_INT_n : std_logic_vector(3 downto 0); signal ETH_MDC : std_logic_vector(3 downto 0); @@ -204,7 +207,7 @@ signal M1_DDR2_oct_rup : std_logic; --signal M2_DDR2_we_n : std_logic; -- GPIO signal GPIO0_D : std_logic_vector(35 downto 0); - signal GPIO1_D : std_logic_vector(35 downto 0); +-- signal GPIO1_D : std_logic_vector(35 downto 0); -- Ext I/O signal EXT_IO : std_logic; -- HSMC A @@ -213,8 +216,8 @@ signal M1_DDR2_oct_rup : std_logic; -- signal HSMA_CLKIN_p1 : std_logic; -- signal HSMA_CLKIN_p2 : std_logic; -- signal HSMA_CLKIN0 : std_logic; --- signal HSMA_CLKOUT_n2 : std_logic; --- signal HSMA_CLKOUT_p2 : std_logic; + signal HSMA_CLKOUT_n2 : std_logic; + signal HSMA_CLKOUT_p2 : std_logic; -- signal HSMA_D : std_logic_vector(3 downto 0); -- HSMA_GXB_RX_p : std_logic_vector(3 downto 0); -- HSMA_GXB_TX_p : std_logic_vector(3 downto 0); @@ -261,8 +264,60 @@ signal M1_DDR2_oct_rup : std_logic; signal dsuen, dsubren, dsuact : std_ulogic; signal dsurst : std_ulogic; + signal sgmii_rstn : std_logic; + + signal dummy_ethi : eth_in_type; + signal dummy_etho : eth_out_type; + + signal sgmii0_rxd : std_logic_vector(7 downto 0); + signal sgmii0_rx_dv : std_logic; + signal sgmii0_rx_er : std_logic; + signal sgmii0_rx_col : std_logic; + signal sgmii0_rx_crs : std_logic; + signal sgmii0_rx_clk : std_logic; + signal phy0_rxd : std_logic_vector(7 downto 0); + signal phy0_rx_dv : std_logic; + signal phy0_rx_er : std_logic; + signal phy0_rx_col : std_logic; + signal phy0_rx_crs : std_logic; + signal phy0_rx_clk : std_logic; + signal sgmii0_txd : std_logic_vector(7 downto 0); + signal sgmii0_tx_en : std_logic; + signal sgmii0_tx_er : std_logic; + signal sgmii0_gtx_clk : std_logic; + signal phy0_txd : std_logic_vector(7 downto 0); + signal phy0_tx_en : std_logic; + signal phy0_tx_er : std_logic; + signal phy0_gtx_clk : std_logic; + + signal sgmii1_rxd : std_logic_vector(7 downto 0); + signal sgmii1_rx_dv : std_logic; + signal sgmii1_rx_er : std_logic; + signal sgmii1_rx_col : std_logic; + signal sgmii1_rx_crs : std_logic; + signal sgmii1_rx_clk : std_logic; + signal phy1_rxd : std_logic_vector(7 downto 0); + signal phy1_rx_dv : std_logic; + signal phy1_rx_er : std_logic; + signal phy1_rx_col : std_logic; + signal phy1_rx_crs : std_logic; + signal phy1_rx_clk : std_logic; + signal sgmii1_txd : std_logic_vector(7 downto 0); + signal sgmii1_tx_en : std_logic; + signal sgmii1_tx_er : std_logic; + signal sgmii1_gtx_clk : std_logic; + signal phy1_txd : std_logic_vector(7 downto 0); + signal phy1_tx_en : std_logic; + signal phy1_tx_er : std_logic; + signal phy1_gtx_clk : std_logic; + + signal rst_125 : std_logic; + constant lresp : boolean := false; + constant slips : integer := 11; + + signal ETH_RX_p_d : std_logic; begin -- clock and reset @@ -277,25 +332,26 @@ begin PLL_CLKIN_p <= not PLL_CLKIN_p after 5 ns; SMA_CLKIN_p <= not SMA_CLKIN_p after 10 ns; GCLKIN <= not GCLKIN after 10 ns; + clk_125 <= not clk_125 after 4 ns; CPU_RESET_n <= '0', '1' after 200 ns; - + sgmii_rstn <= '0', '1' after 1000 ns; -- various interfaces - MAX_CONF_D <= (others => 'H'); - MAX_I2C_SDAT <= 'H'; +-- MAX_CONF_D <= (others => 'H'); +-- MAX_I2C_SDAT <= 'H'; BUTTON <= "HHHH"; SW <= (others => 'H'); SLIDE_SW <= (others => 'L'); - TEMP_SMDAT <= 'H'; - TEMP_INT_n <= 'H'; +-- TEMP_SMDAT <= 'H'; +-- TEMP_INT_n <= 'H'; CSENSE_SCK <= 'H'; CSENSE_SDO <= 'H'; EEP_SDA <= 'H'; - SD_CMD <= 'H'; - SD_DAT <= (others => 'H'); - SD_WP_n <= 'H'; +-- SD_CMD <= 'H'; +-- SD_DAT <= (others => 'H'); +-- SD_WP_n <= 'H'; GPIO0_D <= (others => 'H'); - GPIO1_D <= (others => 'H'); +-- GPIO1_D <= (others => 'H'); EXT_IO <= 'H'; LED(0) <= 'H'; @@ -312,11 +368,12 @@ begin OSC_50_BANK2, OSC_50_BANK3, OSC_50_BANK4, OSC_50_BANK5, OSC_50_BANK6, OSC_50_BANK7, PLL_CLKIN_p, SMA_CLKIN_p, -- SMA_GXBCLK_p - GCLKIN, GCLKOUT_FPGA, SMA_CLKOUT_p, + GCLKIN, +-- GCLKOUT_FPGA, SMA_CLKOUT_p, -- cpu reset CPU_RESET_n, -- max i/o - MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT, +-- MAX_CONF_D, MAX_I2C_SCLK, MAX_I2C_SDAT, -- LEDs LED, -- buttons @@ -326,7 +383,7 @@ begin -- slide switches SLIDE_SW, -- temperature - TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n, +-- TEMP_SMCLK, TEMP_SMDAT, TEMP_INT_n, -- current CSENSE_ADC_FO, CSENSE_SCK, CSENSE_SDI, CSENSE_SDO, CSENSE_CS_n, -- fan @@ -334,7 +391,7 @@ begin -- eeprom EEP_SCL, EEP_SDA, -- sdcard - SD_CLK, SD_CMD, SD_DAT, SD_WP_n, +-- SD_CLK, SD_CMD, SD_DAT, SD_WP_n, -- Ethernet interfaces ETH_INT_n, ETH_MDC, ETH_MDIO, ETH_RST_n, ETH_RX_p, ETH_TX_p, -- PCIe interfaces @@ -366,12 +423,14 @@ begin -- M2_DDR2_cs_n, M2_DDR2_dm, M2_DDR2_dq, M2_DDR2_dqs, M2_DDR2_dqsn, M2_DDR2_odt, -- M2_DDR2_ras_n, M2_DDR2_SA, M2_DDR2_SCL, M2_DDR2_SDA M2_DDR2_we_n -- GPIO - GPIO0_D, GPIO1_D, + GPIO0_D, +-- GPIO1_D, -- Ext I/O -- EXT_IO, -- HSMC A -- HSMA_CLKIN_n1, HSMA_CLKIN_n2, HSMA_CLKIN_p1, HSMA_CLKIN_p2, HSMA_CLKIN0, --- HSMA_CLKOUT_n2, HSMA_CLKOUT_p2, HSMA_D, + HSMA_CLKOUT_n2, HSMA_CLKOUT_p2, +-- HSMA_D, -- HSMA_GXB_RX_p, HSMA_GXB_TX_p, -- HSMA_OUT_n1, HSMA_OUT_p1, HSMA_OUT0, -- HSMA_REFCLK_p, @@ -392,6 +451,133 @@ begin ); + ethsim0 : if CFG_GRETH /= 0 generate + + rst_125 <= not CPU_RESET_n; + + -- delaying rx line + ETH_RX_p(0) <= transport ETH_RX_p_d after 0.8 ns * slips; + + -- connecting PHY through SGMII to MAC + p0: phy + generic map( + address => 0 + ) + port map( + rstn => CPU_RESET_n, + mdio => ETH_MDIO(0), + tx_clk => open, + rx_clk => open, + rxd => phy0_rxd, + rx_dv => phy0_rx_dv, + rx_er => phy0_rx_er, + rx_col => phy0_rx_col, + rx_crs => phy0_rx_crs, + txd => phy0_txd, + tx_en => phy0_tx_en, + tx_er => phy0_tx_er, + mdc => ETH_MDC(0), + gtx_clk => phy0_gtx_clk + ); + + phy0_txd <= sgmii0_rxd; + phy0_tx_en <= sgmii0_rx_dv; + phy0_tx_er <= sgmii0_rx_er; + phy0_gtx_clk <= sgmii0_gtx_clk; + + sgmii0_txd <= phy0_rxd; + sgmii0_tx_en <= phy0_rx_dv; + sgmii0_tx_er <= phy0_rx_er; + + sgmii0: sgmii + generic map ( + fabtech => fabtech + ) + port map( + clk_125 => clk_125, + rst_125 => rst_125, + + ser_rx_p => ETH_TX_p(0), + ser_tx_p => ETH_RX_p_d, + + txd => sgmii0_txd, + tx_en => sgmii0_tx_en, + tx_er => sgmii0_tx_er, + tx_clk => sgmii0_gtx_clk, + + rxd => sgmii0_rxd, + rx_dv => sgmii0_rx_dv, + rx_er => sgmii0_rx_er, + rx_col => sgmii0_rx_col, + rx_crs => sgmii0_rx_crs, + rx_clk => sgmii0_rx_clk, + + mdc => ETH_MDC(0) + ); + + end generate; + + ethsim1 : if CFG_GRETH2 /= 0 generate + + -- connecting PHY through SGMII to MAC + p1: phy + generic map( + address => 1 + ) + port map( + rstn => CPU_RESET_n, + mdio => ETH_MDIO(1), + tx_clk => open, + rx_clk => open, + rxd => phy1_rxd, + rx_dv => phy1_rx_dv, + rx_er => phy1_rx_er, + rx_col => phy1_rx_col, + rx_crs => phy1_rx_crs, + txd => phy1_txd, + tx_en => phy1_tx_en, + tx_er => phy1_tx_er, + mdc => ETH_MDC(1), + gtx_clk => phy1_gtx_clk + ); + + phy1_txd <= sgmii1_rxd; + phy1_tx_en <= sgmii1_rx_dv; + phy1_tx_er <= sgmii1_rx_er; + phy1_gtx_clk <= sgmii1_gtx_clk; + + sgmii1_txd <= phy1_rxd; + sgmii1_tx_en <= phy1_rx_dv; + sgmii1_tx_er <= phy1_rx_er; + + sgmii1: sgmii + generic map ( + fabtech => fabtech + ) + port map( + clk_125 => clk_125, + rst_125 => rst_125, + + ser_rx_p => ETH_TX_p(1), + ser_tx_p => ETH_RX_p(1), + + txd => sgmii1_txd, + tx_en => sgmii1_tx_en, + tx_er => sgmii1_tx_er, + tx_clk => sgmii1_gtx_clk, + + rxd => sgmii1_rxd, + rx_dv => sgmii1_rx_dv, + rx_er => sgmii1_rx_er, + rx_col => sgmii1_rx_col, + rx_crs => sgmii1_rx_crs, + rx_clk => sgmii1_rx_clk, + + mdc => ETH_MDC(1) + ); + + end generate; + prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) port map (FSM_A(romdepth downto 1), FSM_D, FLASH_CE_n, FLASH_CE_n, FLASH_CE_n, FLASH_WE_n, FLASH_OE_n); diff --git a/designs/leon3-terasic-de4/tkconfig.h b/designs/leon3-terasic-de4/tkconfig.h index 292f8082..4835228c 100644 --- a/designs/leon3-terasic-de4/tkconfig.h +++ b/designs/leon3-terasic-de4/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif @@ -691,6 +687,82 @@ #endif +#ifndef CONFIG_L2_ENABLE +#define CONFIG_L2_ENABLE 0 +#endif + +#if defined CONFIG_L2_ASSO1 +#define CFG_L2_ASSO 1 +#elif defined CONFIG_L2_ASSO2 +#define CFG_L2_ASSO 2 +#elif defined CONFIG_L2_ASSO3 +#define CFG_L2_ASSO 3 +#elif defined CONFIG_L2_ASSO4 +#define CFG_L2_ASSO 4 +#else +#define CFG_L2_ASSO 1 +#endif + +#if defined CONFIG_L2_SZ1 +#define CFG_L2_SZ 1 +#elif defined CONFIG_L2_SZ2 +#define CFG_L2_SZ 2 +#elif defined CONFIG_L2_SZ4 +#define CFG_L2_SZ 4 +#elif defined CONFIG_L2_SZ8 +#define CFG_L2_SZ 8 +#elif defined CONFIG_L2_SZ16 +#define CFG_L2_SZ 16 +#elif defined CONFIG_L2_SZ32 +#define CFG_L2_SZ 32 +#elif defined CONFIG_L2_SZ64 +#define CFG_L2_SZ 64 +#elif defined CONFIG_L2_SZ128 +#define CFG_L2_SZ 128 +#elif defined CONFIG_L2_SZ256 +#define CFG_L2_SZ 256 +#elif defined CONFIG_L2_SZ512 +#define CFG_L2_SZ 512 +#else +#define CFG_L2_SZ 1 +#endif + +#if defined CONFIG_L2_LINE64 +#define CFG_L2_LINE 64 +#else +#define CFG_L2_LINE 32 +#endif + +#ifndef CONFIG_L2_HPROT +#define CONFIG_L2_HPROT 0 +#endif + +#ifndef CONFIG_L2_PEN +#define CONFIG_L2_PEN 0 +#endif + +#ifndef CONFIG_L2_WT +#define CONFIG_L2_WT 0 +#endif + +#ifndef CONFIG_L2_RAN +#define CONFIG_L2_RAN 0 +#endif +#ifndef CONFIG_L2_MAP +#define CONFIG_L2_MAP 00F0 +#endif + +#ifndef CONFIG_L2_SHARE +#define CONFIG_L2_SHARE 0 +#endif + +#ifndef CONFIG_L2_MTRR +#define CONFIG_L2_MTRR 0 +#endif + +#ifndef CONFIG_L2_EDAC +#define CONFIG_L2_EDAC 0 +#endif #ifndef CONFIG_AHB_SPLIT #define CONFIG_AHB_SPLIT 0 #endif @@ -903,7 +975,6 @@ #ifndef CONFIG_GRETH_EDCLFT #define CONFIG_GRETH_EDCLFT 0 #endif - #ifndef CONFIG_GRETH2_ENABLE #define CONFIG_GRETH2_ENABLE 0 #endif diff --git a/designs/leon3-xilinx-ac701/.config b/designs/leon3-xilinx-ac701/.config new file mode 100644 index 00000000..2e7ebeb1 --- /dev/null +++ b/designs/leon3-xilinx-ac701/.config @@ -0,0 +1,282 @@ +# +# Automatically generated make config: don't edit +# +CONFIG_LEON3FT_PRESENT=y +CONFIG_HAS_SHARED_GRFPU=y + +# +# Synthesis +# +# CONFIG_SYN_INFERRED is not set +# CONFIG_SYN_STRATIX is not set +# CONFIG_SYN_STRATIXII is not set +# CONFIG_SYN_STRATIXIII is not set +# CONFIG_SYN_STRATIXIV is not set +# CONFIG_SYN_CYCLONEIII is not set +# CONFIG_SYN_ALTERA is not set +# CONFIG_SYN_AXCEL is not set +# CONFIG_SYN_AXDSP is not set +# CONFIG_SYN_PROASIC is not set +# CONFIG_SYN_PROASICPLUS is not set +# CONFIG_SYN_PROASIC3 is not set +# CONFIG_SYN_PROASIC3E is not set +# CONFIG_SYN_PROASIC3L is not set +# CONFIG_SYN_IGLOO is not set +# CONFIG_SYN_FUSION is not set +# CONFIG_SYN_UT025CRH is not set +# CONFIG_SYN_UT130HBD is not set +# CONFIG_SYN_UT90NHBD is not set +# CONFIG_SYN_ATC18 is not set +# CONFIG_SYN_ATC18RHA is not set +# CONFIG_SYN_CMOS9SF is not set +# CONFIG_SYN_CUSTOM1 is not set +# CONFIG_SYN_EASIC90 is not set +# CONFIG_SYN_EASIC45 is not set +# CONFIG_SYN_IHP25 is not set +# CONFIG_SYN_IHP25RH is not set +# CONFIG_SYN_LATTICE is not set +# CONFIG_SYN_ECLIPSE is not set +# CONFIG_SYN_PEREGRINE is not set +# CONFIG_SYN_RH_LIB18T is not set +# CONFIG_SYN_RHUMC is not set +# CONFIG_SYN_SAED32 is not set +# CONFIG_SYN_DARE is not set +# CONFIG_SYN_SMIC13 is not set +# CONFIG_SYN_TM65GPLUS is not set +# CONFIG_SYN_TSMC90 is not set +# CONFIG_SYN_UMC is not set +CONFIG_SYN_ARTIX7=y +# CONFIG_SYN_KINTEX7 is not set +# CONFIG_SYN_SPARTAN3 is not set +# CONFIG_SYN_SPARTAN3E is not set +# CONFIG_SYN_SPARTAN6 is not set +# CONFIG_SYN_VIRTEXE is not set +# CONFIG_SYN_VIRTEX2 is not set +# CONFIG_SYN_VIRTEX4 is not set +# CONFIG_SYN_VIRTEX5 is not set +# CONFIG_SYN_VIRTEX6 is not set +# CONFIG_SYN_VIRTEX7 is not set +# CONFIG_SYN_ZYNQ7000 is not set +# CONFIG_SYN_INFER_RAM is not set +# CONFIG_SYN_INFER_PADS is not set +# CONFIG_SYN_NO_ASYNC is not set +# CONFIG_SYN_SCAN is not set + +# +# Clock generation +# +# CONFIG_CLK_INFERRED is not set +# CONFIG_CLK_HCLKBUF is not set +# CONFIG_CLK_UT130HBD is not set +# CONFIG_CLK_ALTDLL is not set +# CONFIG_CLK_LATDLL is not set +# CONFIG_CLK_PRO3PLL is not set +# CONFIG_CLK_PRO3EPLL is not set +# CONFIG_CLK_PRO3LPLL is not set +# CONFIG_CLK_FUSPLL is not set +# CONFIG_CLK_LIB18T is not set +# CONFIG_CLK_RHUMC is not set +# CONFIG_CLK_DARE is not set +# CONFIG_CLK_SAED32 is not set +# CONFIG_CLK_EASIC45 is not set +# CONFIG_CLK_CLKPLLE2 is not set +# CONFIG_CLK_CLKDLL is not set +CONFIG_CLK_DCM=y +CONFIG_CLK_MUL=4 +CONFIG_CLK_DIV=8 +# CONFIG_PCI_CLKDLL is not set +# CONFIG_CLK_NOFB is not set +# CONFIG_PCI_SYSCLK is not set + +# +# Processor +# +CONFIG_LEON3=y +CONFIG_PROC_NUM=1 +# CONFIG_LEON3_MIN is not set +CONFIG_LEON3_GP=y +# CONFIG_LEON3_HP is not set +# CONFIG_LEON3_CUSTOM is not set +CONFIG_IU_NWINDOWS=8 +CONFIG_IU_V8MULDIV=y +CONFIG_IU_MUL_LATENCY_5=y +# CONFIG_IU_MUL_MAC is not set +CONFIG_IU_BP=y +CONFIG_IU_SVT=y +# CONFIG_NOTAG is not set +CONFIG_IU_LDELAY=1 +CONFIG_IU_WATCHPOINTS=2 +CONFIG_PWD=y +CONFIG_IU_RSTADDR=00000 +# CONFIG_FPU_ENABLE is not set +CONFIG_ICACHE_ENABLE=y +CONFIG_ICACHE_ASSO2=y +CONFIG_ICACHE_SZ4=y +CONFIG_ICACHE_LZ16=y +CONFIG_ICACHE_ALGORND=y +# CONFIG_ICACHE_LOCK is not set +# CONFIG_ICACHE_LRAM is not set +CONFIG_DCACHE_ENABLE=y +CONFIG_DCACHE_ASSO2=y +CONFIG_DCACHE_SZ4=y +CONFIG_DCACHE_LZ16=y +CONFIG_DCACHE_ALGORND=y +# CONFIG_DCACHE_LOCK is not set +CONFIG_DCACHE_SNOOP=y +CONFIG_DCACHE_SNOOP_FAST=y +CONFIG_DCACHE_SNOOP_SEPTAG=y +CONFIG_CACHE_FIXED=0 +# CONFIG_DCACHE_LRAM is not set +CONFIG_MMU_ENABLE=y +CONFIG_MMU_SPLIT=y +CONFIG_MMU_REPARRAY=y +CONFIG_MMU_I8=y +CONFIG_MMU_D8=y +CONFIG_MMU_FASTWB=y +CONFIG_MMU_PAGE_4K=y +CONFIG_DSU_ENABLE=y +CONFIG_DSU_ITRACE=y +CONFIG_DSU_ITRACESZ4=y +CONFIG_DSU_ATRACESZ4=y + +# +# Fault-tolerance +# +# CONFIG_LEON3FT_EN is not set + +# +# VHDL debug settings +# +# CONFIG_IU_DISAS is not set +# CONFIG_DEBUG_PC32 is not set + +# +# AMBA configuration +# +CONFIG_AHB_DEFMST=0 +CONFIG_AHB_RROBIN=y +# CONFIG_AHB_SPLIT is not set +CONFIG_AHB_FPNPEN=y +CONFIG_AHB_IOADDR=FFF +CONFIG_APB_HADDR=800 +# CONFIG_AHB_MON is not set +# CONFIG_AHB_DTRACE is not set + +# +# Debug Link +# +CONFIG_DSU_UART=y +CONFIG_DSU_JTAG=y + +# +# Peripherals +# + +# +# Memory controller +# + +# +# Leon2 memory controller +# +CONFIG_MCTRL_LEON2=y +CONFIG_MCTRL_8BIT=y +CONFIG_MCTRL_16BIT=y +# CONFIG_MCTRL_5CS is not set +# CONFIG_MCTRL_SDRAM is not set + +# +# MIG memory controller +# +# CONFIG_MIG_DDR2 is not set + +# +# MIG Series 7 memory controller +# +CONFIG_MIG_SERIES7=y +# CONFIG_MIG_SERIES_7_MODEL is not set +# CONFIG_AHBSTAT_ENABLE is not set + +# +# On-chip RAM/ROM +# +# CONFIG_AHBROM_ENABLE is not set +CONFIG_AHBRAM_ENABLE=y +# CONFIG_AHBRAM_SZ1 is not set +# CONFIG_AHBRAM_SZ2 is not set +CONFIG_AHBRAM_SZ4=y +# CONFIG_AHBRAM_SZ8 is not set +# CONFIG_AHBRAM_SZ16 is not set +# CONFIG_AHBRAM_SZ32 is not set +# CONFIG_AHBRAM_SZ64 is not set +# CONFIG_AHBRAM_SZ128 is not set +# CONFIG_AHBRAM_SZ256 is not set +# CONFIG_AHBRAM_SZ512 is not set +# CONFIG_AHBRAM_SZ1024 is not set +# CONFIG_AHBRAM_SZ2048 is not set +# CONFIG_AHBRAM_SZ4096 is not set +CONFIG_AHBRAM_START=A00 +# CONFIG_AHBRAM_PIPE is not set + +# +# Ethernet +# +# CONFIG_GRETH_ENABLE is not set + +# +# UARTs, timers and irq control +# +CONFIG_UART1_ENABLE=y +# CONFIG_UA1_FIFO1 is not set +# CONFIG_UA1_FIFO2 is not set +# CONFIG_UA1_FIFO4 is not set +# CONFIG_UA1_FIFO8 is not set +# CONFIG_UA1_FIFO16 is not set +CONFIG_UA1_FIFO32=y +CONFIG_IRQ3_ENABLE=y +# CONFIG_IRQ3_SEC is not set +CONFIG_GPT_ENABLE=y +CONFIG_GPT_NTIM=2 +CONFIG_GPT_SW=8 +CONFIG_GPT_TW=32 +CONFIG_GPT_IRQ=8 +CONFIG_GPT_SEPIRQ=y +# CONFIG_GPT_WDOGEN is not set +CONFIG_GRGPIO_ENABLE=y +CONFIG_GRGPIO_WIDTH=7 +CONFIG_GRGPIO_IMASK=0000 +CONFIG_I2C_ENABLE=y + +# +# Keybord and VGA interface +# +# CONFIG_KBD_ENABLE is not set +# CONFIG_VGA_ENABLE is not set +# CONFIG_SVGA_ENABLE is not set + +# +# SPI +# + +# +# SPI memory controller +# +CONFIG_SPIMCTRL=y +# CONFIG_SPIMCTRL_SDCARD is not set +CONFIG_SPIMCTRL_READCMD=0B +# CONFIG_SPIMCTRL_DUMMYBYTE is not set +# CONFIG_SPIMCTRL_DUALOUTPUT is not set +CONFIG_SPIMCTRL_OFFSET=0 +CONFIG_SPIMCTRL_SCALER=1 +CONFIG_SPIMCTRL_ASCALER=8 +CONFIG_SPIMCTRL_PWRUPCNT=0 + +# +# SPI controller(s) +# +# CONFIG_SPICTRL_ENABLE is not set + +# +# VHDL Debugging +# +# CONFIG_DEBUG_UART is not set diff --git a/designs/leon3-xilinx-ac701/Makefile b/designs/leon3-xilinx-ac701/Makefile new file mode 100644 index 00000000..eaa34d97 --- /dev/null +++ b/designs/leon3-xilinx-ac701/Makefile @@ -0,0 +1,107 @@ + +### GRLIB general setup and extra target to clean software +include .config +GRLIB=../.. +CLEAN=soft-clean + +### Xilinx Vivado device and board setup +BOARD=xilinx-ac701-xc7a200t +DESIGN=leon3-xilinx-ac701 +include $(GRLIB)/boards/$(BOARD)/Makefile.inc +DEVICE=$(PART)$(PACKAGE)-$(SPEED) +XDC=$(GRLIB)/boards/$(BOARD)/$(BOARD).xdc + +### Simulation Options ### +# Design Top Level +TOP=leon3mp + +# Simulation top level +SIMTOP=testbench + +# Uncomment for Modelsim or change to specify your simulator +#GRLIB_SIMULATOR=ModelSim + +# Options used during compilation +VCOMOPT=-explicit -O0 + +# GRLIB Options +VSIMOPT= -gdisas=1 + +# GRETH options +ifeq ($(CONFIG_GRETH_ENABLE),y) +VSIMOPT+= -L secureip_ver -L xilinxcorelib_ver -L unisims_ver +endif + +# - MIG - +ifeq ($(CONFIG_MIG_SERIES7),y) +VSIMOPT+= -t fs -novopt +VSIMOPT+= -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl +ifndef CONFIG_MIG_SERIES_7_MODEL +VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false +else +VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=true -t ps +endif +endif + +# Simulator switches +ifeq ("$(GRLIB_SIMULATOR)","ALDEC") +VSIMOPT+= +access +w -voptargs="+acc" +notimingchecks +else +VSIMOPT+=-novopt +notimingchecks +endif + +# Run simulation in batch mode +VSIMOPT+= -c + +# Simulation scripts +VSIMOPT+= -do "run -all" + +# Toplevel +VSIMOPT+= $(SIMTOP) + +### End of Simulation Options ### + +### Testbench, design and libraries to compile and not to compile + +VHDLSYNFILES= config.vhd ahbrom.vhd leon3mp.vhd ddr_dummy.vhd +VHDLSIMFILES=testbench.vhd + +TECHLIBS = secureip unisim + +LIBSKIP = pci pci/pcif core1553bbc core1553brm core1553brt gr1553 corePCIF \ + tmtc openchip ihp spw gsi cypress hynix \ + spansion leon4 leon4v0 secureip +DIRSKIP = b1553 pci pci/pcif leon2 leon2ft crypto satcan pci ambatest \ + spacewire ascs slink \ + leon4 leon4v0 l2cache pwm gr1553b iommu ac97 secureip +FILESKIP = grcan.vhd ddr2.v mobile_ddr.v + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile + +################## project specific targets ########################## + +all: help-local + +help-local: help + @echo + @echo " design specific targets:" + @echo " (Only needed to generate and compile IPs for Xilinx Series7)" + @echo + @echo " make compile_xilinx_verilog_lib : compile xilinx verilog library" + @echo " make clean_xilinx_verilog_lib : remove xilinx verilog library" + @echo " make mig_series7 : create xilinx memory controller using coregen." + @echo + @echo " ================================================================" + @echo " Quick start guide for simulation of systest.c" + @echo + @echo " 1. Setup search paths for Xilinx, GCC and Modelsim " + @echo " 2. make vsim" + @echo " 3. make mig_series7" + @echo " 4. make vsim-launch" + @echo + @echo " Please note that this quick start guide will compile and simulate" + @echo " a preconfigured version of the leon3 processor system." + @echo " For customizing the leon3 susbsystem run make 'xconfig'" + @echo " ================================================================" + @echo diff --git a/designs/leon3-xilinx-ac701/README.txt b/designs/leon3-xilinx-ac701/README.txt new file mode 100644 index 00000000..34b21cca --- /dev/null +++ b/designs/leon3-xilinx-ac701/README.txt @@ -0,0 +1,213 @@ +This leon3 design is tailored to the Xilinx Artix-7 AC701 board +--------------------------------------------------------------- + +NOTE: The SGMII Ethernet interface does currently NOT work on this +design. + +http://www.xilinx.com/ac701 + +Note: This design requires that the GRLIB_SIMULATOR variable is +correctly set. Please refer to the documentation in doc/grlib.pdf for +additional information. + +Note: The Vivado flow and parts of this design are still +experimental. Currently the design configuration should be left as-is. + +Note: You must have both Vivado 2013.3 and Xilinx ISE 14.6 in your +path for the make targets to work. + +Simulation and synthesis +------------------------ + +The design uses the Xilinx MIG memory interface with an AHB-2.0 +interface. The MIG source code cannot be distributed due to the +prohibitive Xilinx license, so the MIG must be re-generated with +coregen before simulation and synthesis can be done. + +Xilinx MIG interface will automatically be generated when +Vivado is launched + +To simulate using XSIM and run systest.c on the Leon design using the memory +controller from Xilinx use the make targets: + + make vivado-launch + +To simulate using Modelsim and run systest.c on the Leon design using +the memory controller from Xilinx use the make targets: + + make vsim (only required if Modelsim/Aldec is used as simulator) + make mig_series7 + make vsim-launch + +To simulate using Aldec Riviera use the following make targets: + + make riviera + make mig_series7 + make riviera-launch + +To synthesize the design, do + + make vivado + +and then use iMPACT programming tool: + + make ise-prog-fpga + +to program the FPGA. + +After successfully programmed the FPGA using the target 'ise-prog-fpga' user might +have to press the 'EAST' button in order to successfully complete the calibration +process in the MIG. Led 1 and led 2 should be constant green if the Calibration +process has been successful. + +If user tries to connect to the board and the MIG has not been calibrated successfully +'grmon' will output: + +$ grmon -xilusb -u -nb + + GRMON2 LEON debug monitor v2.0.43-2-g95d293c internal version + + Copyright (C) 2013 Aeroflex Gaisler - All rights reserved. + For latest updates, go to http://www.gaisler.com/ + Comments or bug-reports to support@gaisler.com + +Parsing -xilusb +Parsing -u +Parsing -nb + +Commands missing help: + datacache + +Xilusb: Cable type/rev : 0x3 + JTAG chain (1): +xc7k325t + +AMBA plug&play not found! +Failed to initialize target! +Exiting GRMON + +The MIG and SGMII IP can be disabled either by deselecting the memory +controller and Gaisler Ethernet interface in 'xconfig' or manually +editing the config.vhd file. When no MIG and no SGMII block is +present in the system normal GRLIB flow can be used and no extra +compile steps are needed. Also when when no MIG is present it is +possible to control and set the system frequency via xconfig. Note +that the system frequency can be modified via Vivado when the MIG is +present by modifying within specified limits for the MIG IP. + +Compiling and launching modelsim when no memory controller and no +ethernet interface is present using Modelsim/Aldec simulator: + + make vsim + make vsim-launch + +Simulation options +------------------ + +All options are set either by editing the testbench or specify/modify the generic +default value when launching the simulator. For Modelsim use the option "-g" i.e. +to enable processor disassembly to console launch modelsim with the option: "-gdisas=1" + +USE_MIG_INTERFACE_MODEL - Use MIG simulation model for faster simulation run time +(Option can now be controlled via 'make xconfig') + +disas - Enable processor disassembly to console + +Design specifics +---------------- + +* The DDR3 controller is implemented with Xilinx MIG Series7 2.0 and + runs of the 200 MHz clock. The DDR3 memory runs at 400 MHz + (DDR3-800). grmon-2.0.30-74 or later is needed to detect the + DDR3 memory. + +* The AHB clock is generated by the MMCM module in the DDR3 + controller, and can be controlled via Coregen. When the + MIG DDR3 controller isn't present the AHB clock is generated + from CLKGEN, and can be controlled via xconfig + +* System reset is mapped to the EAST button + (This is since the CPU RESET button pin is used for DDR VTP) + +* DSU break is mapped to GPIO east button + +* LED 0 indicates processor in debug mode + +* LED 1 indicates processor in error mode, execution halted + +* LED 2 indicates DDR3 PHY initialization done (Only valid when MIG is present) + +* LED 3 indicates internal PLL has locked (Only valid when MIG isn't present) + +* 16-bit flash prom can be read at address 0. It can be programmed + with GRMON version 2.0.30-74 or later. + +* The system can be simulated with xilinxs memory interface in normal or fast mode. + For normal mode i.e. with the MIG IP and Memory models from MICRON all simulaion libraries + needs to be installed and compiled with the following command: Please, note the MIG Series7 + only have to be generated if it is going to be used in the system. + + make vsim + make mig_series7 + + Then rebuild the software and launch the simulator simulation: + + make soft + make vsim-launch + + Modelsim v10.1 or newer is required and simulate Xilinx memory + controller for Series 7. + + The normal leon3 test bench can be executed as the DDR3 model + is pre-loading with the systest. A model of the DDR3 interface + exist and can be used for faster simulations and software debug + +* The application UART1 is connected to the USB/RS232 connector + +* The JTAG DSU interface is enabled and accesible via the JTAG port. + Start grmon with -xilusb to connect. + +* Output from GRMON is: + + grmon -xilusb -u -nb + + GRMON2 LEON debug monitor v2.0.46-12-g452afa7 internal version + + Copyright (C) 2013 Aeroflex Gaisler - All rights reserved. + For latest updates, go to http://www.gaisler.com/ + Comments or bug-reports to support@gaisler.com + + This internal version will expire on 28/01/2015 + +Parsing -xilusb +Parsing -u +Parsing -nb + +Commands missing help: + datacache + +Xilusb: Cable type/rev : 0x3 + JTAG chain (1): xc7a200t + GRLIB build version: 4141 + Detected frequency: 100 MHz + + Component Vendor + LEON3 SPARC V8 Processor Aeroflex Gaisler + AHB Debug UART Aeroflex Gaisler + JTAG Debug Link Aeroflex Gaisler + GR Ethernet MAC Aeroflex Gaisler + AHB/APB Bridge Aeroflex Gaisler + LEON3 Debug Support Unit Aeroflex Gaisler + Single-port AHB SRAM module Aeroflex Gaisler + Xilinx MIG DDR3 Controller Aeroflex Gaisler + Single-port AHB SRAM module Aeroflex Gaisler + Generic UART Aeroflex Gaisler + Multi-processor Interrupt Ctrl. Aeroflex Gaisler + Modular Timer Unit Aeroflex Gaisler + AMBA Wrapper for OC I2C-master Aeroflex Gaisler + General Purpose I/O port Aeroflex Gaisler + Gaisler RGMII Interface Aeroflex Gaisler + + Use command 'info sys' to print a detailed report of attached cores + +grmon2> diff --git a/designs/leon3-xilinx-ac701/ahbrom.vhd b/designs/leon3-xilinx-ac701/ahbrom.vhd new file mode 100644 index 00000000..ac26c7b2 --- /dev/null +++ b/designs/leon3-xilinx-ac701/ahbrom.vhd @@ -0,0 +1,231 @@ + +---------------------------------------------------------------------------- +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2009 Aeroflex Gaisler +---------------------------------------------------------------------------- +-- Entity: ahbrom +-- File: ahbrom.vhd +-- Author: Jiri Gaisler - Gaisler Research +-- Description: AHB rom. 0/1-waitstate read +---------------------------------------------------------------------------- +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; + +entity ahbrom is + generic ( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#fff#; + pipe : integer := 0; + tech : integer := 0; + kbytes : integer := 1); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type + ); +end; + +architecture rtl of ahbrom is +constant abits : integer := 10; +constant bytes : integer := 560; + +constant hconfig : ahb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0), + 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32); + +signal romdata : std_logic_vector(31 downto 0); +signal addr : std_logic_vector(abits-1 downto 2); +signal hsel, hready : std_ulogic; + +begin + + ahbso.hresp <= "00"; + ahbso.hsplit <= (others => '0'); + ahbso.hirq <= (others => '0'); + ahbso.hconfig <= hconfig; + ahbso.hindex <= hindex; + + reg : process (clk) + begin + if rising_edge(clk) then + addr <= ahbsi.haddr(abits-1 downto 2); + end if; + end process; + + p0 : if pipe = 0 generate + ahbso.hrdata <= ahbdrivedata(romdata); + ahbso.hready <= '1'; + end generate; + + p1 : if pipe = 1 generate + reg2 : process (clk) + begin + if rising_edge(clk) then + hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1); + hready <= ahbsi.hready; + ahbso.hready <= (not rst) or (hsel and hready) or + (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready); + ahbso.hrdata <= ahbdrivedata(romdata); + end if; + end process; + end generate; + + comb : process (addr) + begin + case conv_integer(addr) is + when 16#00000# => romdata <= X"81D82000"; + when 16#00001# => romdata <= X"03000004"; + when 16#00002# => romdata <= X"821060E0"; + when 16#00003# => romdata <= X"81884000"; + when 16#00004# => romdata <= X"81900000"; + when 16#00005# => romdata <= X"81980000"; + when 16#00006# => romdata <= X"81800000"; + when 16#00007# => romdata <= X"A1800000"; + when 16#00008# => romdata <= X"01000000"; + when 16#00009# => romdata <= X"03002040"; + when 16#0000A# => romdata <= X"8210600F"; + when 16#0000B# => romdata <= X"C2A00040"; + when 16#0000C# => romdata <= X"84100000"; + when 16#0000D# => romdata <= X"01000000"; + when 16#0000E# => romdata <= X"01000000"; + when 16#0000F# => romdata <= X"01000000"; + when 16#00010# => romdata <= X"01000000"; + when 16#00011# => romdata <= X"01000000"; + when 16#00012# => romdata <= X"80108002"; + when 16#00013# => romdata <= X"01000000"; + when 16#00014# => romdata <= X"01000000"; + when 16#00015# => romdata <= X"01000000"; + when 16#00016# => romdata <= X"01000000"; + when 16#00017# => romdata <= X"01000000"; + when 16#00018# => romdata <= X"87444000"; + when 16#00019# => romdata <= X"8608E01F"; + when 16#0001A# => romdata <= X"88100000"; + when 16#0001B# => romdata <= X"8A100000"; + when 16#0001C# => romdata <= X"8C100000"; + when 16#0001D# => romdata <= X"8E100000"; + when 16#0001E# => romdata <= X"A0100000"; + when 16#0001F# => romdata <= X"A2100000"; + when 16#00020# => romdata <= X"A4100000"; + when 16#00021# => romdata <= X"A6100000"; + when 16#00022# => romdata <= X"A8100000"; + when 16#00023# => romdata <= X"AA100000"; + when 16#00024# => romdata <= X"AC100000"; + when 16#00025# => romdata <= X"AE100000"; + when 16#00026# => romdata <= X"90100000"; + when 16#00027# => romdata <= X"92100000"; + when 16#00028# => romdata <= X"94100000"; + when 16#00029# => romdata <= X"96100000"; + when 16#0002A# => romdata <= X"98100000"; + when 16#0002B# => romdata <= X"9A100000"; + when 16#0002C# => romdata <= X"9C100000"; + when 16#0002D# => romdata <= X"9E100000"; + when 16#0002E# => romdata <= X"86A0E001"; + when 16#0002F# => romdata <= X"16BFFFEF"; + when 16#00030# => romdata <= X"81E00000"; + when 16#00031# => romdata <= X"82102002"; + when 16#00032# => romdata <= X"81904000"; + when 16#00033# => romdata <= X"03000004"; + when 16#00034# => romdata <= X"821060E0"; + when 16#00035# => romdata <= X"81884000"; + when 16#00036# => romdata <= X"01000000"; + when 16#00037# => romdata <= X"01000000"; + when 16#00038# => romdata <= X"01000000"; + when 16#00039# => romdata <= X"83480000"; + when 16#0003A# => romdata <= X"8330600C"; + when 16#0003B# => romdata <= X"80886001"; + when 16#0003C# => romdata <= X"02800024"; + when 16#0003D# => romdata <= X"01000000"; + when 16#0003E# => romdata <= X"07000000"; + when 16#0003F# => romdata <= X"8610E178"; + when 16#00040# => romdata <= X"C108C000"; + when 16#00041# => romdata <= X"C118C000"; + when 16#00042# => romdata <= X"C518C000"; + when 16#00043# => romdata <= X"C918C000"; + when 16#00044# => romdata <= X"CD18C000"; + when 16#00045# => romdata <= X"D118C000"; + when 16#00046# => romdata <= X"D518C000"; + when 16#00047# => romdata <= X"D918C000"; + when 16#00048# => romdata <= X"DD18C000"; + when 16#00049# => romdata <= X"E118C000"; + when 16#0004A# => romdata <= X"E518C000"; + when 16#0004B# => romdata <= X"E918C000"; + when 16#0004C# => romdata <= X"ED18C000"; + when 16#0004D# => romdata <= X"F118C000"; + when 16#0004E# => romdata <= X"F518C000"; + when 16#0004F# => romdata <= X"F918C000"; + when 16#00050# => romdata <= X"FD18C000"; + when 16#00051# => romdata <= X"01000000"; + when 16#00052# => romdata <= X"01000000"; + when 16#00053# => romdata <= X"01000000"; + when 16#00054# => romdata <= X"01000000"; + when 16#00055# => romdata <= X"01000000"; + when 16#00056# => romdata <= X"89A00842"; + when 16#00057# => romdata <= X"01000000"; + when 16#00058# => romdata <= X"01000000"; + when 16#00059# => romdata <= X"01000000"; + when 16#0005A# => romdata <= X"01000000"; + when 16#0005B# => romdata <= X"10800005"; + when 16#0005C# => romdata <= X"01000000"; + when 16#0005D# => romdata <= X"01000000"; + when 16#0005E# => romdata <= X"00000000"; + when 16#0005F# => romdata <= X"00000000"; + when 16#00060# => romdata <= X"87444000"; + when 16#00061# => romdata <= X"8730E01C"; + when 16#00062# => romdata <= X"8688E00F"; + when 16#00063# => romdata <= X"12800015"; + when 16#00064# => romdata <= X"03200000"; + when 16#00065# => romdata <= X"05040E00"; + when 16#00066# => romdata <= X"8410A033"; + when 16#00067# => romdata <= X"C4204000"; + when 16#00068# => romdata <= X"0539AE1B"; + when 16#00069# => romdata <= X"8410A260"; + when 16#0006A# => romdata <= X"C4206004"; + when 16#0006B# => romdata <= X"050003FC"; + when 16#0006C# => romdata <= X"C4206008"; + when 16#0006D# => romdata <= X"82103860"; + when 16#0006E# => romdata <= X"C4004000"; + when 16#0006F# => romdata <= X"8530A00C"; + when 16#00070# => romdata <= X"03000004"; + when 16#00071# => romdata <= X"82106009"; + when 16#00072# => romdata <= X"80A04002"; + when 16#00073# => romdata <= X"12800005"; + when 16#00074# => romdata <= X"03200000"; + when 16#00075# => romdata <= X"0539A81B"; + when 16#00076# => romdata <= X"8410A260"; + when 16#00077# => romdata <= X"C4204000"; + when 16#00078# => romdata <= X"05000080"; + when 16#00079# => romdata <= X"82100000"; + when 16#0007A# => romdata <= X"80A0E000"; + when 16#0007B# => romdata <= X"02800005"; + when 16#0007C# => romdata <= X"01000000"; + when 16#0007D# => romdata <= X"82004002"; + when 16#0007E# => romdata <= X"10BFFFFC"; + when 16#0007F# => romdata <= X"8620E001"; + when 16#00080# => romdata <= X"3D1003FF"; + when 16#00081# => romdata <= X"BC17A3E0"; + when 16#00082# => romdata <= X"BC278001"; + when 16#00083# => romdata <= X"9C27A060"; + when 16#00084# => romdata <= X"03100000"; + when 16#00085# => romdata <= X"81C04000"; + when 16#00086# => romdata <= X"01000000"; + when 16#00087# => romdata <= X"01000000"; + when 16#00088# => romdata <= X"00000000"; + when 16#00089# => romdata <= X"00000000"; + when 16#0008A# => romdata <= X"00000000"; + when 16#0008B# => romdata <= X"00000000"; + when 16#0008C# => romdata <= X"00000000"; + when others => romdata <= (others => '-'); + end case; + end process; + -- pragma translate_off + bootmsg : report_version + generic map ("ahbrom" & tost(hindex) & + ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" ); + -- pragma translate_on + end; diff --git a/designs/leon3-xilinx-ac701/config.h b/designs/leon3-xilinx-ac701/config.h new file mode 100644 index 00000000..978646a5 --- /dev/null +++ b/designs/leon3-xilinx-ac701/config.h @@ -0,0 +1,263 @@ +/* + * Automatically generated C config: don't edit + */ +#define AUTOCONF_INCLUDED +#define CONFIG_LEON3FT_PRESENT 1 +#define CONFIG_HAS_SHARED_GRFPU 1 +/* + * Synthesis + */ +#undef CONFIG_SYN_INFERRED +#undef CONFIG_SYN_STRATIX +#undef CONFIG_SYN_STRATIXII +#undef CONFIG_SYN_STRATIXIII +#undef CONFIG_SYN_STRATIXIV +#undef CONFIG_SYN_CYCLONEIII +#undef CONFIG_SYN_ALTERA +#undef CONFIG_SYN_AXCEL +#undef CONFIG_SYN_AXDSP +#undef CONFIG_SYN_PROASIC +#undef CONFIG_SYN_PROASICPLUS +#undef CONFIG_SYN_PROASIC3 +#undef CONFIG_SYN_PROASIC3E +#undef CONFIG_SYN_PROASIC3L +#undef CONFIG_SYN_IGLOO +#undef CONFIG_SYN_FUSION +#undef CONFIG_SYN_UT025CRH +#undef CONFIG_SYN_UT130HBD +#undef CONFIG_SYN_UT90NHBD +#undef CONFIG_SYN_ATC18 +#undef CONFIG_SYN_ATC18RHA +#undef CONFIG_SYN_CMOS9SF +#undef CONFIG_SYN_CUSTOM1 +#undef CONFIG_SYN_EASIC90 +#undef CONFIG_SYN_EASIC45 +#undef CONFIG_SYN_IHP25 +#undef CONFIG_SYN_IHP25RH +#undef CONFIG_SYN_LATTICE +#undef CONFIG_SYN_ECLIPSE +#undef CONFIG_SYN_PEREGRINE +#undef CONFIG_SYN_RH_LIB18T +#undef CONFIG_SYN_RHUMC +#undef CONFIG_SYN_SAED32 +#undef CONFIG_SYN_DARE +#undef CONFIG_SYN_SMIC13 +#undef CONFIG_SYN_TM65GPLUS +#undef CONFIG_SYN_TSMC90 +#undef CONFIG_SYN_UMC +#define CONFIG_SYN_ARTIX7 1 +#undef CONFIG_SYN_KINTEX7 +#undef CONFIG_SYN_SPARTAN3 +#undef CONFIG_SYN_SPARTAN3E +#undef CONFIG_SYN_SPARTAN6 +#undef CONFIG_SYN_VIRTEXE +#undef CONFIG_SYN_VIRTEX2 +#undef CONFIG_SYN_VIRTEX4 +#undef CONFIG_SYN_VIRTEX5 +#undef CONFIG_SYN_VIRTEX6 +#undef CONFIG_SYN_VIRTEX7 +#undef CONFIG_SYN_ZYNQ7000 +#undef CONFIG_SYN_INFER_RAM +#undef CONFIG_SYN_INFER_PADS +#undef CONFIG_SYN_NO_ASYNC +#undef CONFIG_SYN_SCAN +/* + * Clock generation + */ +#undef CONFIG_CLK_INFERRED +#undef CONFIG_CLK_HCLKBUF +#undef CONFIG_CLK_UT130HBD +#undef CONFIG_CLK_ALTDLL +#undef CONFIG_CLK_LATDLL +#undef CONFIG_CLK_PRO3PLL +#undef CONFIG_CLK_PRO3EPLL +#undef CONFIG_CLK_PRO3LPLL +#undef CONFIG_CLK_FUSPLL +#undef CONFIG_CLK_LIB18T +#undef CONFIG_CLK_RHUMC +#undef CONFIG_CLK_DARE +#undef CONFIG_CLK_SAED32 +#undef CONFIG_CLK_EASIC45 +#undef CONFIG_CLK_CLKPLLE2 +#undef CONFIG_CLK_CLKDLL +#define CONFIG_CLK_DCM 1 +#define CONFIG_CLK_MUL (4) +#define CONFIG_CLK_DIV (8) +#undef CONFIG_PCI_CLKDLL +#undef CONFIG_CLK_NOFB +#undef CONFIG_PCI_SYSCLK +/* + * Processor + */ +#define CONFIG_LEON3 1 +#define CONFIG_PROC_NUM (1) +#undef CONFIG_LEON3_MIN +#define CONFIG_LEON3_GP 1 +#undef CONFIG_LEON3_HP +#undef CONFIG_LEON3_CUSTOM +#define CONFIG_IU_NWINDOWS (8) +#define CONFIG_IU_V8MULDIV 1 +#define CONFIG_IU_MUL_LATENCY_5 1 +#undef CONFIG_IU_MUL_MAC +#define CONFIG_IU_BP 1 +#define CONFIG_IU_SVT 1 +#undef CONFIG_NOTAG +#define CONFIG_IU_LDELAY (1) +#define CONFIG_IU_WATCHPOINTS (2) +#define CONFIG_PWD 1 +#define CONFIG_IU_RSTADDR 00000 +#undef CONFIG_FPU_ENABLE +#define CONFIG_ICACHE_ENABLE 1 +#define CONFIG_ICACHE_ASSO2 1 +#define CONFIG_ICACHE_SZ4 1 +#define CONFIG_ICACHE_LZ16 1 +#define CONFIG_ICACHE_ALGORND 1 +#undef CONFIG_ICACHE_LOCK +#undef CONFIG_ICACHE_LRAM +#define CONFIG_DCACHE_ENABLE 1 +#define CONFIG_DCACHE_ASSO2 1 +#define CONFIG_DCACHE_SZ4 1 +#define CONFIG_DCACHE_LZ16 1 +#define CONFIG_DCACHE_ALGORND 1 +#undef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_SNOOP 1 +#define CONFIG_DCACHE_SNOOP_FAST 1 +#define CONFIG_DCACHE_SNOOP_SEPTAG 1 +#define CONFIG_CACHE_FIXED 0 +#undef CONFIG_DCACHE_LRAM +#define CONFIG_MMU_ENABLE 1 +#define CONFIG_MMU_SPLIT 1 +#define CONFIG_MMU_REPARRAY 1 +#define CONFIG_MMU_I8 1 +#define CONFIG_MMU_D8 1 +#define CONFIG_MMU_FASTWB 1 +#define CONFIG_MMU_PAGE_4K 1 +#define CONFIG_DSU_ENABLE 1 +#define CONFIG_DSU_ITRACE 1 +#define CONFIG_DSU_ITRACESZ4 1 +#define CONFIG_DSU_ATRACESZ4 1 +/* + * Fault-tolerance + */ +#undef CONFIG_LEON3FT_EN +/* + * VHDL debug settings + */ +#undef CONFIG_IU_DISAS +#undef CONFIG_DEBUG_PC32 +/* + * AMBA configuration + */ +#define CONFIG_AHB_DEFMST (0) +#define CONFIG_AHB_RROBIN 1 +#undef CONFIG_AHB_SPLIT +#define CONFIG_AHB_FPNPEN 1 +#define CONFIG_AHB_IOADDR FFF +#define CONFIG_APB_HADDR 800 +#undef CONFIG_AHB_MON +#undef CONFIG_AHB_DTRACE +/* + * Debug Link + */ +#define CONFIG_DSU_UART 1 +#define CONFIG_DSU_JTAG 1 +/* + * Peripherals + */ +/* + * Memory controller + */ +/* + * Leon2 memory controller + */ +#define CONFIG_MCTRL_LEON2 1 +#define CONFIG_MCTRL_8BIT 1 +#define CONFIG_MCTRL_16BIT 1 +#undef CONFIG_MCTRL_5CS +#undef CONFIG_MCTRL_SDRAM +/* + * MIG memory controller + */ +#undef CONFIG_MIG_DDR2 +/* + * MIG Series 7 memory controller + */ +#define CONFIG_MIG_SERIES7 1 +#undef CONFIG_MIG_SERIES_7_MODEL +#undef CONFIG_AHBSTAT_ENABLE +/* + * On-chip RAM/ROM + */ +#undef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBRAM_ENABLE 1 +#undef CONFIG_AHBRAM_SZ1 +#undef CONFIG_AHBRAM_SZ2 +#define CONFIG_AHBRAM_SZ4 1 +#undef CONFIG_AHBRAM_SZ8 +#undef CONFIG_AHBRAM_SZ16 +#undef CONFIG_AHBRAM_SZ32 +#undef CONFIG_AHBRAM_SZ64 +#undef CONFIG_AHBRAM_SZ128 +#undef CONFIG_AHBRAM_SZ256 +#undef CONFIG_AHBRAM_SZ512 +#undef CONFIG_AHBRAM_SZ1024 +#undef CONFIG_AHBRAM_SZ2048 +#undef CONFIG_AHBRAM_SZ4096 +#define CONFIG_AHBRAM_START A00 +#undef CONFIG_AHBRAM_PIPE +/* + * Ethernet + */ +#undef CONFIG_GRETH_ENABLE +/* + * UARTs, timers and irq control + */ +#define CONFIG_UART1_ENABLE 1 +#undef CONFIG_UA1_FIFO1 +#undef CONFIG_UA1_FIFO2 +#undef CONFIG_UA1_FIFO4 +#undef CONFIG_UA1_FIFO8 +#undef CONFIG_UA1_FIFO16 +#define CONFIG_UA1_FIFO32 1 +#define CONFIG_IRQ3_ENABLE 1 +#undef CONFIG_IRQ3_SEC +#define CONFIG_GPT_ENABLE 1 +#define CONFIG_GPT_NTIM (2) +#define CONFIG_GPT_SW (8) +#define CONFIG_GPT_TW (32) +#define CONFIG_GPT_IRQ (8) +#define CONFIG_GPT_SEPIRQ 1 +#undef CONFIG_GPT_WDOGEN +#define CONFIG_GRGPIO_ENABLE 1 +#define CONFIG_GRGPIO_WIDTH (7) +#define CONFIG_GRGPIO_IMASK 0000 +#define CONFIG_I2C_ENABLE 1 +/* + * Keybord and VGA interface + */ +#undef CONFIG_KBD_ENABLE +#undef CONFIG_VGA_ENABLE +#undef CONFIG_SVGA_ENABLE +/* + * SPI + */ +/* + * SPI memory controller + */ +#define CONFIG_SPIMCTRL 1 +#undef CONFIG_SPIMCTRL_SDCARD +#define CONFIG_SPIMCTRL_READCMD 0B +#undef CONFIG_SPIMCTRL_DUMMYBYTE +#undef CONFIG_SPIMCTRL_DUALOUTPUT +#define CONFIG_SPIMCTRL_OFFSET 0 +#define CONFIG_SPIMCTRL_SCALER (1) +#define CONFIG_SPIMCTRL_ASCALER (8) +#define CONFIG_SPIMCTRL_PWRUPCNT (0) +/* + * SPI controller(s) + */ +#undef CONFIG_SPICTRL_ENABLE +/* + * VHDL Debugging + */ +#undef CONFIG_DEBUG_UART diff --git a/designs/leon3-xilinx-ac701/config.help b/designs/leon3-xilinx-ac701/config.help new file mode 100644 index 00000000..c114477f --- /dev/null +++ b/designs/leon3-xilinx-ac701/config.help @@ -0,0 +1,1101 @@ + + +Prompt for target technology +CONFIG_SYN_INFERRED + Selects the target technology for memory and pads. + The following are available: + + - Inferred: Generic FPGA or ASIC targets if your synthesis tool + is capable of inferring RAMs and pads automatically. + + - Actel ProAsic/P/3, IGLOO and Axcelerator FPGAs + - Aeroflex UT25CRH Rad-Hard 0.25 um CMOS + - Altera: Most Altera FPGA families + - Altera-CycloneIII: Altera Cyclone-III/IV FPGA family + - Altera-Stratix: Altera Stratix FPGA family + - Altera-StratixII: Altera Stratix/Cyclone-II FPGA families + - Altera-StratixIII: Altera Stratix-III FPGA family + - Altera-StratixIV: Altera Stratix-III FPGA family + - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS + - IHP25: IHP 0.25 um CMOS + - IHP25RH: IHP Rad-Hard 0.25 um CMOS + - Lattice : EC/ECP/XP FPGAs + - Quicklogic : Eclipse/E/II FPGAs + - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries + - Xilinx-Spartan/2/3/6: Xilinx Spartan/2/3/6 libraries + - Xilinx-Spartan3E: Xilinx Spartan3E libraries + - Xilinx-Virtex/E: Xilinx Virtex/E libraries + - Xilinx-Virtex2/4/5/6/7: Xilinx Virtex2/4/5/6/7 libraries + + Note: Level of technology support depends on type of GRLIB + distribution. A technology may be present in this list while the + tech support files are missing from the GRLIB distribution. + Actel support is only available in commercial and FT distributions. + +Ram library +CONFIG_MEM_VIRAGE + Select RAM generators for ASIC targets. + +Infer ram +CONFIG_SYN_INFER_RAM + Say Y here if you want the synthesis tool to infer your + RAM automatically. Say N to directly instantiate technology- + specific RAM cells for the selected target technology package. + +Infer pads +CONFIG_SYN_INFER_PADS + Say Y here if you want the synthesis tool to infer pads. + Say N to directly instantiate technology-specific pads from + the selected target technology package. + +No async reset +CONFIG_SYN_NO_ASYNC + Say Y here if you disable asynchronous reset in some of the IP cores. + Might be necessary if the target library does not have cells with + asynchronous set/reset. + +Scan support +CONFIG_SYN_SCAN + Say Y here to enable scan support in some cores. This will enable + the scan support generics where available and add logic to make + the design testable using full-scan. + +Use Virtex CLKDLL for clock synchronisation +CONFIG_CLK_INFERRED + Certain target technologies include clock generators to scale or + phase-adjust the system and SDRAM clocks. This is currently supported + for Xilinx, Altera and Proasic3 FPGAs. Depending on technology, you + can select to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), + the Xilinx DCM (Virtex-2, Spartan3, Virtex-4), the Xilinx PLLE2 (Virtex-7, + Kintex-7, Artix-4), the Altera ALTDLL (Stratix, Cyclone), or the + Proasic3 PLL. Choose the 'inferred' option to skip a clock generator. + +Clock multiplier +CONFIG_CLK_MUL + When using the Xilinx DCM, Xilinx PLLE2 or Altera ALTPLL, + the system clock can be multiplied with a factor of 2 - 32, + and divided by a factor of 1 - 32. This makes it possible to + generate almost any desired processor frequency. When using + the Xilinx CLKDLL generator, the resulting frequency scale f + actor (mul/div) must be one of 1/2, 1 or 2. On Proasic3, + the factor can be 1 - 128. + + WARNING: The resulting clock must be within the limits specified + by the target FPGA family. + +Clock divider +CONFIG_CLK_DIV + When using the Xilinx DCM, Xilinx PLLE2 or Altera ALTPLL, + the system clock can be multiplied with a factor of 2 - 32, + and divided by a factor of 1 - 32. This makes it possible to + generate almost any desired processor frequency. When using + the Xilinx CLKDLL generator, the resulting frequency scale f + actor (mul/div) must be one of 1/2, 1 or 2. On Proasic3, + the factor can be 1 - 128. + + WARNING: The resulting clock must be within the limits specified + by the target FPGA family. + +Output clock divider +CONFIG_OCLK_DIV + When using the Proasic3 PLL, the system clock is generated by three + parameters: input clock multiplication, input clock division and + output clock division. Only certain values of these parameters + are allowed, but unfortunately this is not documented by Actel. + To find the correct values, run the Libero Smartgen tool and + insert you desired input and output clock frequencies in the + Static PLL configurator. The mul/div factors can then be read + out from tool. + +Output clock divider, 2nd clock +CONFIG_OCLKB_DIV + See help for 'Ouput division factor'. Set this to 0 to disable the + second clock output. + +Output clock divider, 3rd clock +CONFIG_OCLKC_DIV + See help for 'Ouput division factor'. Set this to 0 to disable the + third clock output. + +System clock multiplier +CONFIG_CLKDLL_1_2 + The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0, + or 2.0. Useful when the target board has an oscillator with a too high + (or low) frequency for your design. The divided clock will be used as the + main clock for the whole processor (except PCI and ethernet clocks). + +System clock multiplier +CONFIG_DCM_2_3 + The Xilinx DCM and Altera ALTDLL can scale the input clock with a large + range of factors. Useful when the target board has an oscillator with a + too high (or low) frequency for your design. The divided clock will + be used as the main clock for the whole processor (except PCI and + ethernet clocks). NOTE: the resulting frequency must be at least + 24 MHz or the DCM and ALTDLL might not work. + +Enable CLKDLL for PCI clock +CONFIG_PCI_CLKDLL + Say Y here to re-synchronize the PCI clock using a + Virtex BUFGDLL macro. Will improve PCI clock-to-output + delays on the expense of input-setup requirements. + +Use PCI clock system clock +CONFIG_PCI_SYSCLK + Say Y here to the PCI clock to generate the system clock. + The PCI clock can be scaled using the DCM or CLKDLL to + generate a suitable processor clock. + +External SDRAM clock feedback +CONFIG_CLK_NOFB + Say Y here to disable the external clock feedback to synchronize the + SDRAM clock. This option is necessary if your board or design does not + have an external clock feedback that is connected to the pllref input + of the clock generator. + +Number of processors +CONFIG_PROC_NUM + The number of processor cores. The LEON3MP design can accomodate + up to 4 LEON3 processor cores. Use 1 unless you know what you are + doing ... + +Force values from example configuration +CONFIG_LEON3_MIN + If you select any other value than Custom-configuration then the + configuration choices will be forced to settings corresponding to + the selected example configuration. The example configurations are + described in the document LEON/GRLIB Design and Configuration Guide + located at doc/guide.pdf. + + Due to limitations in the configuration tool it is not possible to + update all choices without first saving the configuration and + restarting the tool. Perform the steps below to set the processor + configuration to example configuration values: + + 1. Select example configuration (MIN, GP, HP). This will result + in most processor configuration menus being disabled. + 2. Go back to the main menu and select Save and Exit + 3. Start the xconfig tool again + 4. Go into processor configuration and select Custom-configuration. + All configuration values can now be changed again and have been + initialized to example configuration that was selected earlier. + 5. Make any changes and then quit xconfig via Save and Exit + + Some options set from the example configuration may need to be changed. + One such setting is the FPU multiplier, if the FPU is enabled, where + timing is improved for several FPGA technologies by selecting the + technology specific multiplier and where the DW multiplier is generally + a good choice for ASIC. + +Number of SPARC register windows +CONFIG_IU_NWINDOWS + The SPARC architecture (and LEON) allows 2 - 32 register windows. + However, any number except 8 will require that you modify and + recompile your run-time system or kernel. Unless you know what + you are doing, use 8. + +SPARC V8 multiply and divide instruction +CONFIG_IU_V8MULDIV + If you say Y here, the SPARC V8 multiply and divide instructions + will be implemented. The instructions are: UMUL, UMULCC, SMUL, + SMULCC, UDIV, UDIVCC, SDIV, SDIVCC. In code containing frequent + integer multiplications and divisions, significant performance + increase can be achieved. Emulated floating-point operations will + also benefit from this option. + + By default, the gcc compiler does not emit multiply or divide + instructions and your code must be compiled with -mv8 to see any + performance increase. On the other hand, code compiled with -mv8 + will generate an illegal instruction trap when executed on processors + with this option disabled. + + The divider consumes approximately 2 kgates, the multiplier 6 kgates. + +Multiplier latency +CONFIG_IU_MUL_LATENCY_2 + Implementation options for the integer multiplier. + + Type Implementation issue-rate/latency + 2-clocks 32x32 pipelined multiplier 1/2 + 4-clocks 16x16 standard multiplier 4/4 + 5-clocks 16x16 pipelined multiplier 4/5 + +MAC operation +CONFIG_IU_MUL_MAC + If you say Y here, the SPARC V8e UMAC/SMAC (multiply-accumulate) + instructions will be enabled. The instructions implement a + single-cycle 16x16->32 bits multiply with a 40-bits accumulator. + The details of these instructions can be found in the LEON manual, + This option is only available when 16x16 multiplier is used. + +Multiplier structure +CONFIG_IU_MUL_INFERRED + Structure options for the integer multiplier. The multiplier + can be implemented with the following structures: + + * Inferred by the synthesis tool + * Generated using Module Generators from NTNU + * Using technology specific netlists (TechSpec) + * Using Synopsys Designware (DW02_mult and DW_mult_pipe) + +Branch prediction +CONFIG_IU_BP + Enabling branch prediction will improve performance with + up to 20%, depending on application. The timing and area + overhead are minor, so it is recommended to always enable + this option. + +Single vector trapping +CONFIG_IU_SVT + Single-vector trapping is a SPARC V8e option to reduce code-size + in small applications. If enabled, the processor will jump to + the address of trap 0 (tt = 0x00) for all traps. No trap table + is then needed. The trap type is present in %psr.tt and must + be decoded by the O/S. Saves 4 Kbyte of code, but increases + trap and interrupt overhead. Currently, the only O/S supporting + this option is eCos. To enable SVT, the O/S must also set bit 13 + in %asr17. + +Load latency +CONFIG_IU_LDELAY + Defines the pipeline load delay (= pipeline cycles before the data + from a load instruction is available for the next instruction). + One cycle gives best performance, but might create a critical path + on targets with slow (data) cache memories. A 2-cycle delay can + improve timing but will reduce performance with about 5%. + + Note that the load delay must be 1 to support the CASA instruction. + +Reset address +CONFIG_IU_RSTADDR + By default, a SPARC processor starts execution at address 0. + With this option, any 4-kbyte aligned reset start address can be + choosen. Keep at 0 unless you really know what you are doing. + +No tagged arithmetic +CONFIG_NOTAG + Say Y here to disable tagged arithmetic and the CASA instructions. + This will save some area in minimal systems that do not need + these features. + +Power-down +CONFIG_PWD + Say Y here to enable the power-down feature of the processor. + Might reduce the maximum frequency slightly on FPGA targets. + For details on the power-down operation, see the LEON3 manual. + +Hardware watchpoints +CONFIG_IU_WATCHPOINTS + The processor can have up to 4 hardware watchpoints, allowing to + create both data and instruction breakpoints at any memory location, + also in PROM. Each watchpoint will use approximately 500 gates. + Use 0 to disable the watchpoint function. + +Floating-point enable +CONFIG_FPU_ENABLE + Say Y here to enable the floating-point interface for the MEIKO + or GRFPU. Note that no FPU's are provided with the GPL version + of GRLIB. Both the Gaisler GRFPU and the Meiko FPU are commercial + cores and must be obtained separately. + +FPU selection +CONFIG_FPU_GRFPU + Select between Gaisler Research's GRFPU and GRFPU-lite FPUs or the Sun + Meiko FPU core. All cores are fully IEEE-754 compatible and support + all SPARC FPU instructions. + +GRFPU Multiplier +CONFIG_FPU_GRFPU_INFMUL + On FPGA targets choose inferred multiplier. For ASIC implementations + choose between Synopsys Design Ware (DW) multiplier or Module + Generator (ModGen) multiplier. The DW multiplier gives better results + (smaller area and better timing) but requires a DW license. + The ModGen multiplier is part of GRLIB and does not require a license. + The Technology Specific multiplier option selects a pre-designed + multiplier using technology specific macrocells when available, else + an inferred multiplier is used. + +Shared GRFPU +CONFIG_FPU_GRFPU_SH + If enabled multiple CPU cores will share one GRFPU. + +GRFPC Configuration +CONFIG_FPU_GRFPC0 + Configures the GRFPU-LITE controller. + + In simple configuration controller executes FP instructions + in parallel with integer instructions. FP operands are fetched + in the register file stage and the result is written in the write + stage. This option uses least area resources. + + Data forwarding configuration gives ~ 10 % higher FP performance than + the simple configuration by adding data forwarding between the pipeline + stages. + + Non-blocking controller allows FP load and store instructions to + execute in parallel with FP instructions. The performance increase is + ~ 20 % for FP applications. This option uses most logic resources and + is suitable for ASIC implementations. + +Floating-point netlist +CONFIG_FPU_NETLIST + Say Y here to use a VHDL netlist of the GRFPU-Lite. This is + only available in certain versions of grlib. + +Enable Instruction cache +CONFIG_ICACHE_ENABLE + The instruction cache should always be enabled to allow + maximum performance. Some low-end system might want to + save area and disable the cache, but this will reduce + the performance with a factor of 2 - 3. + +Enable Data cache +CONFIG_DCACHE_ENABLE + The data cache should always be enabled to allow + maximum performance. Some low-end system might want to + save area and disable the cache, but this will reduce + the performance with a factor of 2 at least. + +Instruction cache associativity +CONFIG_ICACHE_ASSO1 + The instruction cache can be implemented as a multi-way cache with + 1 - 4 ways. Higher associativity usually increases the cache hit + rate and thereby the performance. The downside is higher power + consumption and increased gate-count for tag comparators. + + Note that a 1-way cache is effectively a direct-mapped cache. + +Instruction cache way size +CONFIG_ICACHE_SZ1 + The size of each way in the instuction cache (kbytes). Valid values + are 1 - 64 in binary steps. Note that the full range is only supported + by the generic and virtex2 targets. Most target packages are limited + to 2 - 16 kbyte. Large way size gives higher performance but might + affect the maximum frequency (on ASIC targets). The total instruction + cache size is the number of way multiplied with the way size. + +Instruction cache line size +CONFIG_ICACHE_LZ16 + The instruction cache line size. Can be set to either 16 or 32 + bytes per line. Instruction caches typically benefit from larger + line sizes, but on small caches it migh be better with 16 bytes/line + to limit eviction miss rate. + +Instruction cache replacement algorithm +CONFIG_ICACHE_ALGORND + Cache replacement algorithm for caches with 2 - 4 ways. The 'random' + algorithm selects the way to evict randomly. The least-recently-replaced + (LRR) algorithm evicts the way least recently replaced. The least- + recently-used (LRU) algorithm evicts the way least recently accessed. + The random algorithm uses a simple 1- or 2-bit counter to select + the eviction way and has low area overhead. The LRR scheme uses one + extra bit in the tag ram and has therefore also low area overhead. + However, the LRR scheme can only be used with 2-way caches. The LRU + scheme has typically the best performance but also highest area overhead. + A 2-way LRU uses 1 flip-flop per line, a 3-way LRU uses 3 flip-flops + per line, and a 4-way LRU uses 5 flip-flops per line to store the access + history. + +Instruction cache locking +CONFIG_ICACHE_LOCK + Say Y here to enable cache locking in the instruction cache. + Locking can be done on cache-line level, but will increase the + width of the tag ram with one bit. If you don't know what + locking is good for, it is safe to say N. + +Data cache associativity +CONFIG_DCACHE_ASSO1 + The data cache can be implemented as a multi-way cache with + 1 - 4 ways. Higher associativity usually increases the cache hit + rate and thereby the performance. The downside is higher power + consumption and increased gate-count for tag comparators. + + Note that a 1-way cache is effectively a direct-mapped cache. + +Data cache way size +CONFIG_DCACHE_SZ1 + The size of each way in the data cache (kbytes). Valid values are + 1 - 64 in binary steps. Note that the full range is only supported + by the generic and virtex2 targets. Most target packages are limited + to 2 - 16 kbyte. A large cache gives higher performance but the + data cache is timing critical an a too large setting might affect + the maximum frequency (on ASIC targets). The total data cache size + is the number of way multiplied with the way size. + +Data cache line size +CONFIG_DCACHE_LZ16 + The data cache line size. Can be set to either 16 or 32 bytes per + line. A smaller line size gives better associativity and higher + cache hit rate, but requires a larger tag memory. + +Data cache replacement algorithm +CONFIG_DCACHE_ALGORND + See the explanation for instruction cache replacement algorithm. + +Data cache locking +CONFIG_DCACHE_LOCK + Say Y here to enable cache locking in the data cache. + Locking can be done on cache-line level, but will increase the + width of the tag ram with one bit. If you don't know what + locking is good for, it is safe to say N. + +Data cache snooping +CONFIG_DCACHE_SNOOP + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. + +Separate snoop tags +CONFIG_DCACHE_SNOOP_SEPTAG + Enable a separate memory to store the data tags used for snooping. + This is necessary when snooping support is wanted in systems + with MMU, typically for SMP systems. In this case, the snoop + tags will contain the physical tag address while the normal + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. + +Fixed cacheability map +CONFIG_CACHE_FIXED + If this variable is 0, the cacheable memory regions are defined + by the AHB plug&play information (default). To overriden the + plug&play settings, this variable can be set to indicate which + areas should be cached. The value is treated as a 16-bit hex value + with each bit defining if a 256 Mbyte segment should be cached or not. + The right-most (LSB) bit defines the cacheability of AHB address + 0 - 256 MByte, while the left-most bit (MSB) defines AHB address + 3840 - 4096 MByte. If the bit is set, the corresponding area is + cacheable. A value of 00F3 defines address 0 - 0x20000000 and + 0x40000000 - 0x80000000 as cacheable. + +Local data ram +CONFIG_DCACHE_LRAM + Say Y here to add a local ram to the data cache controller. + Accesses to the ram (load/store) will be performed at 0 waitstates + and store data will never be written back to the AHB bus. + +Size of local data ram +CONFIG_DCACHE_LRAM_SZ1 + Defines the size of the local data ram in Kbytes. Note that most + technology libraries do not support larger rams than 16 Kbyte. + +Start address of local data ram +CONFIG_DCACHE_LRSTART + Defines the 8 MSB bits of start address of the local data ram. + By default set to 8f (start address = 0x8f000000), but any value + (except 0) is possible. Note that the local data ram 'shadows' + a 16 Mbyte block of the address space. + +MMU enable +CONFIG_MMU_ENABLE + Say Y here to enable the Memory Management Unit. + +MMU split icache/dcache table lookaside buffer +CONFIG_MMU_COMBINED + Select "combined" for a combined icache/dcache table lookaside buffer, + "split" for a split icache/dcache table lookaside buffer + +MMU tlb replacement scheme +CONFIG_MMU_REPARRAY + Select "LRU" to use the "least recently used" algorithm for TLB + replacement, or "Increment" for a simple incremental replacement + scheme. + +Combined i/dcache tlb +CONFIG_MMU_I2 + Select the number of entries for the instruction TLB, or the + combined icache/dcache TLB if such is used. + +Split tlb, dcache +CONFIG_MMU_D2 + Select the number of entries for the dcache TLB. + +Fast writebuffer +CONFIG_MMU_FASTWB + Only selectable if split tlb is enabled. In case fast writebuffer is + enabled the tlb hit will be made concurrent to the cache hit. This + leads to higher store performance, but increased power and area. + +MMU pagesize +CONFIG_MMU_PAGE_4K + The deafult SPARC V8 SRMMU page size is 4 Kbyte. This limits the + cache way size to 4 Kbyte, and total data cache size to 16 Kbyte, + when the MMU is used. To increase the maximum data cache size, + the MMU pages size can be increased to up 32 Kbyte. This will + give a maximum data cache size of 128 Kbyte. + + Note that an MMU page size different than 4 Kbyte will require + a special linux tool-chain if glibc is used. If you don't know + what you are doing, stay with 4 Kbyte ... + +DSU enable +CONFIG_DSU_ENABLE + The debug support unit (DSU) allows non-intrusive debugging and tracing + of both executed instructions and AHB transfers. If you want to enable + the DSU, say Y here and select the configuration below. + +Trace buffer enable +CONFIG_DSU_TRACEBUF + Say Y to enable the trace buffer. The buffer is not necessary for + debugging, only for tracing instructions and data transfers. + +Enable instruction tracing +CONFIG_DSU_ITRACE + If you say Y here, an instruction trace buffer will be implemented + in each processor. The trace buffer will trace executed instructions + and their results, and place them in a circular buffer. The buffer + can be read out by any AHB master, and in particular by the debug + communication link. + +Size of trace buffer +CONFIG_DSU_ITRACESZ1 + Select the buffer size (in kbytes) for the instruction trace buffer. + Each line in the buffer needs 16 bytes. A 128-entry buffer will thus + need 2 kbyte. + +Enable AHB tracing +CONFIG_DSU_ATRACE + If you say Y here, an AHB trace buffer will be implemented in the + debug support unit processor. The AHB buffer will trace all transfers + on the AHB bus and save them in a circular buffer. The trace buffer + can be read out by any AHB master, and in particular by the debug + communication link. + +Size of trace buffer +CONFIG_DSU_ATRACESZ1 + Select the buffer size (in kbytes) for the AHB trace buffer. + Each line in the buffer needs 16 bytes. A 128-entry buffer will thus + need 2 kbyte. + + +LEON3FT enable +CONFIG_LEON3FT_EN + Say Y here to use the fault-tolerant LEON3FT core instead of the + standard non-FT LEON3. + +IU Register file protection +CONFIG_IUFT_NONE + Select the FT implementation in the LEON3FT integer unit + register file. The options include parity, parity with + sparing, 7-bit BCH and TMR. + +FPU Register file protection +CONFIG_FPUFT_NONE + Say Y to enable SEU protection of the FPU register file. + The GRFPU-Lite will be protected with parity, PDMR and TMR. + The GRFPU can use PDMR or TMR only. + +Cache memory error injection +CONFIG_RF_ERRINJ + Say Y here to enable error injection in to the IU/FPU regfiles. + Affects only simulation. + +Cache memory protection +CONFIG_CACHE_FT_EN + Enable SEU error-correction in the cache memories. + +Cache memory error injection +CONFIG_CACHE_ERRINJ + Say Y here to enable error injection in to the cache memories. + Affects only simulation. + +Leon3ft netlist +CONFIG_LEON3_NETLIST + Say Y here to use a VHDL netlist of the LEON3FT. This is + only available in certain versions of grlib. + +IU assembly printing +CONFIG_IU_DISAS + Enable printing of executed instructions to the console. + +IU assembly printing in netlist +CONFIG_IU_DISAS_NET + Enable printing of executed instructions to the console also + when simulating a netlist. NOTE: with this option enabled, it + will not be possible to pass place&route. + +32-bit program counters +CONFIG_DEBUG_PC32 + Since the LSB 2 bits of the program counters always are zero, they are + normally not implemented. If you say Y here, the program counters will + be implemented with full 32 bits, making debugging of the VHDL model + much easier. Turn of this option for synthesis or you will be wasting + area. +CONFIG_AHB_DEFMST + Sets the default AHB master (see AMBA 2.0 specification for definition). + Should not be set to a value larger than the number of AHB masters - 1. + For highest processor performance, leave it at 0. + +Default AHB master +CONFIG_AHB_RROBIN + Say Y here to enable round-robin arbitration of the AHB bus. A N will + select fixed priority, with the master with the highest bus index having + the highest priority. + +Support AHB split-transactions +CONFIG_AHB_SPLIT + Say Y here to enable AHB split-transaction support in the AHB arbiter. + Unless you actually have an AHB slave that can generate AHB split + responses, say N and save some gates. + +Enable full PnP decoding +CONFIG_AHB_FPNPEN + Say Y here to enable full decoding of the PnP configuration records in + in the AHB arbiter. When disabled the user-defined registers in the + PnP configuration records are not mapped in the configuration area. + +IO area start address +CONFIG_AHB_IOADDR + Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined + in the plug&play extentions of the AMBA bus. Should be kept to FFF + unless you really know what you are doing. + +APB bridge address +CONFIG_APB_HADDR + Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be + kept at 800 for software compatibility. + +AHB monitor +CONFIG_AHB_MON + Say Y to enable the AHB bus monitor. The monitor will check for + illegal AHB transactions during simulation. It has no impact on + synthesis. + +Report AHB errors +CONFIG_AHB_MONERR + Print out detected AHB violations on console. + +Report AHB warnings +CONFIG_AHB_MONWAR + Print out detected AHB warnings on console. + +Write trace to console +CONFIG_AHB_DTRACE + Say yes here to write a trace of all AHB transfers to the + simulator console. Has not impact on final netlist. + +DSU enable +CONFIG_DSU_UART + Say Y to enable the AHB uart (serial-to-AHB). This is the most + commonly used debug communication link. + +JTAG Enable +CONFIG_DSU_JTAG + Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done + with GRMON through the boards JTAG chain at speeds of up to 800 kbits/s. + + The TAP controller can be implemented in custom macros on + Altera, Actel Proasic/3 and Xilinx devices. The commercial + GRLIB also includes a generic TAP controller in VHDL. + + Supported JTAG cables are Xilinx Parallel Cable III and IV, + Xilinx Platform cables (USB), and Altera parallel and USB cables, + Amontech JTAG key, various FTDI chip based USB/JTAG devices, and + Actel Flash Pro 3/4 cable. + +Ethernet DSU enable +CONFIG_DSU_ETH + Say Y to enable the Ethernet Debug Communication Link (EDCL). The link + provides a DSU gateway between ethernet and the AHB bus. Debugging is + done at 10 or 100 Mbit/s, using the GRMON debug monitor. You must + enable the GRETH Ethernet MAC for this option to become active. + +Size of EDCL trace buffer +CONFIG_DSU_ETHSZ1 + Select the buffer size (in kbytes) for the EDCL. 1 or 2 kbyte is + usually enough, while a larger buffer will increase the transfer rate. + When operating at 100 Mbit, use a buffer size of at least 8 kbyte for + maximum throughput. + +MSB IP address +CONFIG_DSU_IPMSB + Set the MSB 16 bits of the IP address of the EDCL. + +LSB IP address +CONFIG_DSU_IPLSB + Set the LSB 16 bits of the IP address of the EDCL. + +MSB ethernet address +CONFIG_DSU_ETHMSB + Set the MSB 24 bits of the ethernet address of the EDCL. + +LSB ethernet address +CONFIG_DSU_ETHLSB + Set the LSB 24 bits of the ethernet address of the EDCL. + +Programmable MAC/IP address +CONFIG_DSU_ETH_PROG + Say Y to make the LSB 4 bits of the EDCL MAC and IP address + configurable using the ethi.edcladdr inputs. +Leon2 memory controller +CONFIG_MCTRL_LEON2 + Say Y here to enable the LEON2 memory controller. The controller + can access PROM, I/O, SRAM and SDRAM. The bus width for PROM + and SRAM is programmable to 8-, 16- or 32-bits. + +8-bit memory support +CONFIG_MCTRL_8BIT + If you say Y here, the PROM/SRAM memory controller will support + 8-bit mode, i.e. operate from 8-bit devices as if they were 32-bit. + Say N to save a few hundred gates. + +16-bit memory support +CONFIG_MCTRL_16BIT + If you say Y here, the PROM/SRAM memory controller will support + 16-bit mode, i.e. operate from 16-bit devices as if they were 32-bit. + Say N to save a few hundred gates. + +Write strobe feedback +CONFIG_MCTRL_WFB + If you say Y here, the PROM/SRAM write strobes (WRITEN, WEN) will + be used to enable the data bus drivers during write cycles. This + will guarantee that the data is still valid on the rising edge of + the write strobe. If you say N, the write strobes and the data bus + drivers will be clocked on the rising edge, potentially creating + a hold time problem in external memory or I/O. However, in all + practical cases, there is enough capacitance in the data bus lines + to keep the value stable for a few (many?) nano-seconds after the + buffers have been disabled, making it safe to say N and remove a + combinational path in the netlist that might be difficult to + analyze. + +Write strobe feedback +CONFIG_MCTRL_5CS + If you say Y here, the 5th (RAMSN[4]) SRAM chip select signal will + be enabled. If you don't intend to use it, say N and save some gates. + +SDRAM controller enable +CONFIG_MCTRL_SDRAM + Say Y here to enabled the PC100/PC133 SDRAM controller. If you don't + intend to use SDRAM, say N and save about 1 kgates. + +SDRAM controller inverted clock +CONFIG_MCTRL_SDRAM_INVCLK + If you say Y here, the SDRAM controller output signals will be delayed + with 1/2 clock in respect to the SDRAM clock. This will allow the used + of an SDRAM clock which in not strictly in phase with the internal + clock. This option will limit the SDRAM frequency to 40 - 50 MHz. + + On FPGA targets without SDRAM clock synchronizations through PLL/DLL, + say Y. On ASIC targets, say N and tell your foundry to balance the + SDRAM clock output. + +SDRAM separate address buses +CONFIG_MCTRL_SDRAM_SEPBUS + Say Y here if your SDRAM is connected through separate address + and data buses (SA & SD). This is the case on the GR-CPCI-XC2V6000 + board, but not on the GR-PCI-XC2V3000 or Avnet XCV1500E boards. + +64-bit data bus +CONFIG_MCTRL_SDRAM_BUS64 + Say Y here to enable 64-bit SDRAM data bus. + +Page burst enable +CONFIG_MCTRL_PAGE + Say Y here to enable SDRAM page burst operation. This will implement + read operations using page bursts rather than 8-word bursts and save + about 500 gates (100 LUTs). Note that not all SDRAM supports page + burst, so use this option with care. + +Programmable page burst enable +CONFIG_MCTRL_PROGPAGE + Say Y here to enable programmable SDRAM page burst operation. This + will allow to dynamically enable/disable page burst by setting + bit 17 in MCFG2. + +AHB status register +CONFIG_AHBSTAT_ENABLE + Say Y here to enable the AHB status register (AHBSTAT IP). + The register will latch the AHB address and master index when + an error response is returned by any AHB slave. + +SDRAM separate address buses +CONFIG_AHBSTAT_NFTSLV + The AHB status register can also latch the AHB address on an external + input. Select here how many of such inputs are required. + +On-chip rom +CONFIG_AHBROM_ENABLE + Say Y here to add a block on on-chip rom to the AHB bus. The ram + provides 0-waitstates read access, burst support, and 8-, 16- + and 32-bit data size. The rom will be syntheised into block rams + on Xilinx and Altera FPGA devices, and into gates on ASIC + technologies. GRLIB includes a utility to automatically create + the rom VHDL model (ahbrom.vhd) from an ELF file. Refer to the GRLIB + documentation for details. + +On-chip rom address +CONFIG_AHBROM_START + Set the start address of AHB ROM (HADDR[31:20]). The ROM will occupy + a 1 Mbyte slot at the selected address. Default is 000, corresponding + to AHB address 0x00000000. When address 0x0 is selected, the rom area + of any other memory controller is set to 0x10000000 to avoid conflicts. + +Enable pipeline register for on-chip rom +CONFIG_AHBROM_PIPE + Say Y here to add a data pipeline register to the on-chip rom. + This should be done when the rom is implemenented in (ASIC) gates, + or in logic cells on FPGAs. Do not use this option when the rom is + implemented in block rams. If enabled, the rom will operate with + one waitstate. + +On-chip ram +CONFIG_AHBRAM_ENABLE + Say Y here to add a block on on-chip ram to the AHB bus. The ram + provides 0-waitstates read access and 0/1 waitstates write access. + All AHB burst types are supported, as well as 8-, 16- and 32-bit + data size. + +On-chip ram size +CONFIG_AHBRAM_SZ1 + Set the size of the on-chip AHB ram. The ram is infered/instantiated + as four byte-wide ram slices to allow byte and half-word write + accesses. It is therefore essential that the target package can + infer byte-wide rams. This is currently supported on the generic, + virtex, virtex2, proasic and axellerator targets. + +On-chip ram address +CONFIG_AHBRAM_START + Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy + a 1 Mbyte slot at the selected address. Default is A00, corresponding + to AHB address 0xA0000000. + +On-chip ram pipeline stage +CONFIG_AHBRAM_PIPE + Set this option to add an extra pipeline stage to the read data of the + on-chip RAM. This can improve timing, especially when the memory is + large, at the cost of adding an additional cycle delay on read. +Gaisler Ethernet MAC enable +CONFIG_GRETH_ENABLE + Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has + one AHB master interface to read and write packets to memory, and one + APB slave interface for accessing the control registers. + +Gaisler Ethernet 1G MAC enable +CONFIG_GRETH_GIGA + Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC . + The 1G MAC is only available in the commercial version of GRLIB, + so do NOT enable it if you are using the GPL version. + +CONFIG_GRETH_FIFO4 + Set the depth of the receive and transmit FIFOs in the MAC core. + The MAC core will perform AHB burst read/writes with half the + size of the FIFO depth. + +CONFIG_GRETH_FT + Enable fault-tolerance (parity with sparing) for internal RAM + in Ethernet core. Note that FT for EDCL buffer is enabled via + separate setting. + +CONFIG_GRETH_EDCLFT + Enable protection for EDCL buffer. This is typically not used as + the EDCL debug link is not used in harsh environments. +UART1 enable +CONFIG_UART1_ENABLE + Say Y here to enable UART1, or the console UART. This is needed to + get any print-out from LEON3 systems regardless of operating system. + +UART1 FIFO +CONFIG_UA1_FIFO1 + The UART has configurable transmitt and receive FIFO's, which can + be set to 1 - 32 bytes. Use 1 for minimum area, or 8 - 32 for + maximum throughput. + + +LEON3 interrupt controller +CONFIG_IRQ3_ENABLE + Say Y here to enable the LEON3 interrupt controller. This is needed + if you want to be able to receive interrupts. Operating systems like + Linux, RTEMS and eCos needs this option to be enabled. If you intend + to use the Bare-C run-time and not use interrupts, you could disable + the interrupt controller and save about 500 gates. + +LEON3 interrupt controller broadcast +CONFIG_IRQ3_BROADCAST_ENABLE + If enabled the broadcast register is used to determine which + interrupt should be sent to all cpus instead of just the first + one that consumes it. + +Secondary interrupts +CONFIG_IRQ3_SEC + The interrupt controller handles 15 interrupts by default (1 - 15). + These correspond to the 15 SPARC asyncronous traps (0x11 - 0x1F), + and AMBA interrupts 1 - 15. This option will enable 16 additional + (secondary) interrupts, corresponding to AMBA interrupts 16 - 31. + The secondary interrupts will be multiplexed onto one of the first + 15 interrupts. The total number of handled interrupts can then + be up to 30 (14 primary and 16 secondary). + +Number of interrupts +CONFIG_IRQ3_NSEC + Defines which of the first 15 interrupts should be used for the + secondary (16 - 31) interrupts. Interrupt 15 should be avoided + since it is not maskable by the processor. +Timer module enable +CONFIG_GPT_ENABLE + Say Y here to enable the Modular Timer Unit. The timer unit consists + of one common scaler and up to 7 independent timers. The timer unit + is needed for Linux, RTEMS, eCos and the Bare-C run-times. + +Timer module enable +CONFIG_GPT_NTIM + Set the number of timers in the timer unit (1 - 7). + +Scaler width +CONFIG_GPT_SW + Set the width if the common pre-scaler (2 - 16 bits). The scaler + is used to divide the system clock down to 1 MHz, so 8 bits should + be sufficient for most implementations (allows clocks up to 256 MHz). + +Timer width +CONFIG_GPT_TW + Set the width if the timers (2 - 32 bits). 32 bits is recommended + for the Bare-C run-time, lower values (e.g. 16 bits) can work with + RTEMS and Linux. + +Timer Interrupt +CONFIG_GPT_IRQ + Set the interrupt number for the first timer. Remaining timers will + have incrementing interrupts, unless the separate-interrupts option + below is disabled. + +Watchdog enable +CONFIG_GPT_WDOGEN + Say Y here to enable the watchdog functionality in the timer unit. + +Watchdog time-out value +CONFIG_GPT_WDOG + This value will be loaded in the watchdog timer at reset. + +GPIO port +CONFIG_GRGPIO_ENABLE + Say Y here to enable a general purpose I/O port. The port can be + configured from 1 - 32 bits, whith each port signal individually + programmable as input or output. The port signals can also serve + as interrupt inputs. + +GPIO port witdth +CONFIG_GRGPIO_WIDTH + Number of bits in the I/O port. Must be in the range of 1 - 32. + +GPIO interrupt mask +CONFIG_GRGPIO_IMASK + The I/O port interrupt mask defines which bits in the I/O port + should be able to create an interrupt. + +OpenCores I2C Master +CONFIG_I2C_ENABLE + Say Y here to enable the OpenCores I2C master. +Text-mode VGA +CONFIG_VGA_ENABLE + Say Y here to enable a simple text-mode VGA controller. The controller + generate 48x36 characters on a 640x480 pixel screen. The pixel clock + is 25 MHz. + +SVGA frame buffer +CONFIG_SVGA_ENABLE + Say Y here to enable a graphical frame buffer. The frame buffer + can be configured up to 1024x768 pixels and 8-, 16- or 32-bit + colour depth. + +PS2 KBD interface +CONFIG_KBD_ENABLE + Say Y here to enable a PS/2 keyboard or mouse interface. + +SPI memory controller +CONFIG_SPIMCTRL + Say Y here to enable a simple SPI memory controller. + The controller maps a SPI memory device into AMBA address space and + also has a simple interface that allows sending commands directly + to the SPI device. + +SD card support +CONFIG_SPIMCTRL_SDCARD + Memory device connected to controller is SD card. + +Read command +CONFIG_SPIMCTRL_READCMD + Read instruction for SPI memory device (hex). + +Dummy byte +CONFIG_SPIMCTRL_DUMMYBYTE + Output dummy byte after address when issuing read instruction. + +Dual output +CONFIG_SPIMCTRL_DUALOUTPUT + Memory device supports dual output when reading data. + +Address offset +CONFIG_SPIMCTRL_OFFSET + Offset that will be added by core on SPI memory address (hex). + +Clock scaler +CONFIG_SPIMCTRL_SCALER + Selects the divisor used when dividing the system clock to produce + the memory device clock. The divisor used is two to the power of the + specified value. This value must be at least 1. + +Alternate clock scaler +CONFIG_SPIMCTRL_ASCALER + Selects the divisor used when dividing the system clock to produce + the alternate memory device clock. If the selected memory device is + a SD Card this clock will be used during card initialization. The + divisor used is two to the power of the specified value. This + value must be at least 1. + +Power-up cnt +CONFIG_SPIMCTRL_PWRUPCNT + Number of system clock cycles to wait before issuing first command. +Gaisler Research SPI controller +CONFIG_SPICTRL_ENABLE + Say Y here to enable the SPI controller(s) + +CONFIG_SPICTRL_NUM + Number of SPI controllers to implement in design. Note that most + template designs are limited to one SPI controller. + Configuration options made here in xconfig will apply to all + implemented SPI controllers. + +CONFIG_SPICTRL_MAXWLEN + 0: Core will support lengths up to 32 bits + 1-2: Illegal values + 3-15: Maximum word length will be value+1 (4-16) + +CONFIG_SPICTRL_SYNCRAM + Say Y here to use SYNCRAM_2P components for the core's receive + and transmit queues. This is the recommended setting, particularly + if the core is implemented with support for automatic mode. + +CONFIG_SPICTRL_FT + Fault-tolerance for internal buffers. Only applicable if core + buffers are implemented with SYNCRAM components. + +UART debugging +CONFIG_DEBUG_UART + During simulation, the output from the UARTs is printed on the + simulator console. Since the ratio between the system clock and + UART baud-rate is quite high, simulating UART output will be very + slow. If you say Y here, the UARTs will print a character as soon + as it is stored in the transmitter data register. The transmitter + ready flag will be permanently set, speeding up simulation. However, + the output on the UART tx line will be garbled. Has not impact on + synthesis, but will cause the LEON test bench to fail. + +FPU register tracing +CONFIG_DEBUG_FPURF + If you say Y here, all writes to the floating-point unit register file + will be printed on the simulator console. + diff --git a/designs/leon3-xilinx-ac701/config.in b/designs/leon3-xilinx-ac701/config.in new file mode 100644 index 00000000..64841dab --- /dev/null +++ b/designs/leon3-xilinx-ac701/config.in @@ -0,0 +1,83 @@ +# +# LEON3 configuration written in linux configuration language +# +# Written by Jiri Gaisler, Gaisler Research +# +# Comments and bug reports to support@gaisler.com +# +# + +#define_bool CONFIG_MCTRL_RMW y +define_bool CONFIG_LEON3FT_PRESENT y +define_bool CONFIG_HAS_SHARED_GRFPU y + +mainmenu_name "LEON3MP Design Configuration" + +mainmenu_option next_comment + comment 'Synthesis ' + source lib/techmap/gencomp/tech.in +endmenu + +mainmenu_option next_comment + comment 'Clock generation' + source lib/techmap/clocks/clkgen.in +endmenu + +source lib/gaisler/leon3/leon3.in +source lib/grlib/amba/amba.in + +mainmenu_option next_comment + comment 'Debug Link ' + source lib/gaisler/uart/dcom.in + source lib/gaisler/jtag/jtag.in + source lib/gaisler/net/edcl.in +endmenu + +mainmenu_option next_comment +comment 'Peripherals ' + + mainmenu_option next_comment + comment 'Memory controller ' + source lib/esa/memoryctrl/mctrl.in + source lib/gaisler/ddr/mig.in + source lib/gaisler/ddr/mig_series7.in + source lib/gaisler/misc/ahbstat.in + endmenu + + mainmenu_option next_comment + comment 'On-chip RAM/ROM ' + source lib/gaisler/misc/ahbrom.in + source lib/gaisler/misc/ahbram.in + endmenu + + mainmenu_option next_comment + comment 'Ethernet ' + source lib/gaisler/greth/greth.in + endmenu + + mainmenu_option next_comment + comment 'UARTs, timers and irq control ' + source lib/gaisler/uart/uart1.in + source lib/gaisler/irqmp/irqmp.in + source lib/gaisler/misc/gptimer.in + source lib/gaisler/misc/grgpio.in + source lib/gaisler/i2c/i2c.in + endmenu + + mainmenu_option next_comment + comment 'Keybord and VGA interface' + source lib/gaisler/misc/ps2vga.in + endmenu + + mainmenu_option next_comment + comment 'SPI' + source lib/gaisler/spi/spimctrl.in + source lib/gaisler/spi/spictrl.in + endmenu + +endmenu + +mainmenu_option next_comment +comment 'VHDL Debugging ' + source lib/grlib/util/debug.in +endmenu diff --git a/designs/leon3-xilinx-ac701/config.vhd b/designs/leon3-xilinx-ac701/config.vhd new file mode 100644 index 00000000..f893e815 --- /dev/null +++ b/designs/leon3-xilinx-ac701/config.vhd @@ -0,0 +1,207 @@ + + + + + +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2009 Aeroflex Gaisler +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is +-- Technology and synthesis options + constant CFG_FABTECH : integer := artix7; + constant CFG_MEMTECH : integer := artix7; + constant CFG_PADTECH : integer := artix7; + constant CFG_NOASYNC : integer := 0; + constant CFG_SCAN : integer := 0; +-- Clock generator + constant CFG_CLKTECH : integer := artix7; + constant CFG_CLKMUL : integer := (4); + constant CFG_CLKDIV : integer := (8); + constant CFG_OCLKDIV : integer := 1; + constant CFG_OCLKBDIV : integer := 0; + constant CFG_OCLKCDIV : integer := 0; + constant CFG_PCIDLL : integer := 0; + constant CFG_PCISYSCLK: integer := 0; + constant CFG_CLK_NOFB : integer := 0; +-- LEON3 processor core + constant CFG_LEON3 : integer := 1; + constant CFG_NCPU : integer := (1); + constant CFG_NWIN : integer := (8); + constant CFG_V8 : integer := 2 + 4*0; + constant CFG_MAC : integer := 0; + constant CFG_BP : integer := 1; + constant CFG_SVT : integer := 1; + constant CFG_RSTADDR : integer := 16#00000#; + constant CFG_LDDEL : integer := (1); + constant CFG_NOTAG : integer := 0; + constant CFG_NWP : integer := (2); + constant CFG_PWD : integer := 1*2; + constant CFG_FPU : integer := 0 + 16*0 + 32*0; + constant CFG_GRFPUSH : integer := 0; + constant CFG_ICEN : integer := 1; + constant CFG_ISETS : integer := 2; + constant CFG_ISETSZ : integer := 4; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 2; + constant CFG_ILOCK : integer := 0; + constant CFG_ILRAMEN : integer := 0; + constant CFG_ILRAMADDR: integer := 16#8E#; + constant CFG_ILRAMSZ : integer := 1; + constant CFG_DCEN : integer := 1; + constant CFG_DSETS : integer := 2; + constant CFG_DSETSZ : integer := 4; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 2; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 1*2 + 4*1; + constant CFG_DFIXED : integer := 16#0#; + constant CFG_DLRAMEN : integer := 0; + constant CFG_DLRAMADDR: integer := 16#8F#; + constant CFG_DLRAMSZ : integer := 1; + constant CFG_MMUEN : integer := 1; + constant CFG_ITLBNUM : integer := 8; + constant CFG_DTLBNUM : integer := 8; + constant CFG_TLB_TYPE : integer := 0 + 1*2; + constant CFG_TLB_REP : integer := 0; + constant CFG_MMU_PAGE : integer := 0; + constant CFG_DSU : integer := 1; + constant CFG_ITBSZ : integer := 4; + constant CFG_ATBSZ : integer := 4; + constant CFG_LEON3FT_EN : integer := 0; + constant CFG_IUFT_EN : integer := 0; + constant CFG_FPUFT_EN : integer := 0; + constant CFG_RF_ERRINJ : integer := 0; + constant CFG_CACHE_FT_EN : integer := 0; + constant CFG_CACHE_ERRINJ : integer := 0; + constant CFG_LEON3_NETLIST: integer := 0; + constant CFG_DISAS : integer := 0 + 0; + constant CFG_PCLOW : integer := 2; +-- AMBA settings + constant CFG_DEFMST : integer := (0); + constant CFG_RROBIN : integer := 1; + constant CFG_SPLIT : integer := 0; + constant CFG_FPNPEN : integer := 1; + constant CFG_AHBIO : integer := 16#FFF#; + constant CFG_APBADDR : integer := 16#800#; + constant CFG_AHB_MON : integer := 0; + constant CFG_AHB_MONERR : integer := 0; + constant CFG_AHB_MONWAR : integer := 0; + constant CFG_AHB_DTRACE : integer := 0; +-- DSU UART + constant CFG_AHB_UART : integer := 1; +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := 1; +-- Ethernet DSU + constant CFG_DSU_ETH : integer := 0 + 0 + 0; + constant CFG_ETH_BUF : integer := 1; + constant CFG_ETH_IPM : integer := 16#C0A8#; + constant CFG_ETH_IPL : integer := 16#0033#; + constant CFG_ETH_ENM : integer := 16#020000#; + constant CFG_ETH_ENL : integer := 16#000009#; +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := 1; + constant CFG_MCTRL_RAM8BIT : integer := 1; + constant CFG_MCTRL_RAM16BIT : integer := 1; + constant CFG_MCTRL_5CS : integer := 0; + constant CFG_MCTRL_SDEN : integer := 0; + constant CFG_MCTRL_SEPBUS : integer := 0; + constant CFG_MCTRL_INVCLK : integer := 0; + constant CFG_MCTRL_SD64 : integer := 0; + constant CFG_MCTRL_PAGE : integer := 0 + 0; +-- Xilinx MIG + constant CFG_MIG_DDR2 : integer := 0; + constant CFG_MIG_RANKS : integer := 1; + constant CFG_MIG_COLBITS : integer := 10; + constant CFG_MIG_ROWBITS : integer := 13; + constant CFG_MIG_BANKBITS: integer := 2; + constant CFG_MIG_HMASK : integer := 16#F00#; +-- Xilinx MIG Series 7 + constant CFG_MIG_SERIES7 : integer := 1; + constant CFG_MIG_SERIES7_MODEL : integer := 0; +-- AHB status register + constant CFG_AHBSTAT : integer := 0; + constant CFG_AHBSTATN : integer := 1; +-- AHB ROM + constant CFG_AHBROMEN : integer := 0; + constant CFG_AHBROPIP : integer := 0; + constant CFG_AHBRODDR : integer := 16#000#; + constant CFG_ROMADDR : integer := 16#000#; + constant CFG_ROMMASK : integer := 16#E00# + 16#000#; +-- AHB RAM + constant CFG_AHBRAMEN : integer := 1; + constant CFG_AHBRSZ : integer := 4; + constant CFG_AHBRADDR : integer := 16#A00#; + constant CFG_AHBRPIPE : integer := 0; +-- Gaisler Ethernet core + constant CFG_GRETH : integer := 0; + constant CFG_GRETH1G : integer := 0; + constant CFG_ETH_FIFO : integer := 8; + + constant CFG_GRETH_FT : integer := 0; + constant CFG_GRETH_EDCLFT : integer := 0; + +-- UART 1 + constant CFG_UART1_ENABLE : integer := 1; + constant CFG_UART1_FIFO : integer := 32; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := 1; + constant CFG_IRQ3_NSEC : integer := 0; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := 1; + constant CFG_GPT_NTIM : integer := (2); + constant CFG_GPT_SW : integer := (8); + constant CFG_GPT_TW : integer := (32); + constant CFG_GPT_IRQ : integer := (8); + constant CFG_GPT_SEPIRQ : integer := 1; + constant CFG_GPT_WDOGEN : integer := 0; + constant CFG_GPT_WDOG : integer := 16#0#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := 1; + constant CFG_GRGPIO_IMASK : integer := 16#0000#; + constant CFG_GRGPIO_WIDTH : integer := (7); + +-- I2C master + constant CFG_I2C_ENABLE : integer := 1; + +-- VGA and PS2/ interface + constant CFG_KBD_ENABLE : integer := 0; + constant CFG_VGA_ENABLE : integer := 0; + constant CFG_SVGA_ENABLE : integer := 0; + +-- SPI memory controller + constant CFG_SPIMCTRL : integer := 1; + constant CFG_SPIMCTRL_SDCARD : integer := 0; + constant CFG_SPIMCTRL_READCMD : integer := 16#0B#; + constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0; + constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0; + constant CFG_SPIMCTRL_SCALER : integer := (1); + constant CFG_SPIMCTRL_ASCALER : integer := (8); + constant CFG_SPIMCTRL_PWRUPCNT : integer := (0); + constant CFG_SPIMCTRL_OFFSET : integer := 16#0#; + +-- SPI controller + constant CFG_SPICTRL_ENABLE : integer := 0; + constant CFG_SPICTRL_NUM : integer := 1; + constant CFG_SPICTRL_SLVS : integer := 1; + constant CFG_SPICTRL_FIFO : integer := 1; + constant CFG_SPICTRL_SLVREG : integer := 0; + constant CFG_SPICTRL_ODMODE : integer := 0; + constant CFG_SPICTRL_AM : integer := 0; + constant CFG_SPICTRL_ASEL : integer := 0; + constant CFG_SPICTRL_TWEN : integer := 0; + constant CFG_SPICTRL_MAXWLEN : integer := 0; + constant CFG_SPICTRL_SYNCRAM : integer := 0; + constant CFG_SPICTRL_FT : integer := 0; + +-- GRLIB debugging + constant CFG_DUART : integer := 0; +end; diff --git a/designs/leon3-xilinx-ac701/config.vhd.h b/designs/leon3-xilinx-ac701/config.vhd.h new file mode 100644 index 00000000..60fcd11e --- /dev/null +++ b/designs/leon3-xilinx-ac701/config.vhd.h @@ -0,0 +1,205 @@ +-- Technology and synthesis options + constant CFG_FABTECH : integer := CONFIG_SYN_TECH; + constant CFG_MEMTECH : integer := CFG_RAM_TECH; + constant CFG_PADTECH : integer := CFG_PAD_TECH; + constant CFG_NOASYNC : integer := CONFIG_SYN_NO_ASYNC; + constant CFG_SCAN : integer := CONFIG_SYN_SCAN; + +-- Clock generator + constant CFG_CLKTECH : integer := CFG_CLK_TECH; + constant CFG_CLKMUL : integer := CONFIG_CLK_MUL; + constant CFG_CLKDIV : integer := CONFIG_CLK_DIV; + constant CFG_OCLKDIV : integer := CONFIG_OCLK_DIV; + constant CFG_OCLKBDIV : integer := CONFIG_OCLKB_DIV; + constant CFG_OCLKCDIV : integer := CONFIG_OCLKC_DIV; + constant CFG_PCIDLL : integer := CONFIG_PCI_CLKDLL; + constant CFG_PCISYSCLK: integer := CONFIG_PCI_SYSCLK; + constant CFG_CLK_NOFB : integer := CONFIG_CLK_NOFB; + +-- LEON3 processor core + constant CFG_LEON3 : integer := CONFIG_LEON3; + constant CFG_NCPU : integer := CONFIG_PROC_NUM; + constant CFG_NWIN : integer := CONFIG_IU_NWINDOWS; + constant CFG_V8 : integer := CFG_IU_V8 + 4*CFG_IU_MUL_STRUCT; + constant CFG_MAC : integer := CONFIG_IU_MUL_MAC; + constant CFG_BP : integer := CONFIG_IU_BP; + constant CFG_SVT : integer := CONFIG_IU_SVT; + constant CFG_RSTADDR : integer := 16#CONFIG_IU_RSTADDR#; + constant CFG_LDDEL : integer := CONFIG_IU_LDELAY; + constant CFG_NOTAG : integer := CONFIG_NOTAG; + constant CFG_NWP : integer := CONFIG_IU_WATCHPOINTS; + constant CFG_PWD : integer := CONFIG_PWD*2; + constant CFG_FPU : integer := CONFIG_FPU + 16*CONFIG_FPU_NETLIST + 32*CONFIG_FPU_GRFPU_SHARED; + constant CFG_GRFPUSH : integer := CONFIG_FPU_GRFPU_SHARED; + constant CFG_ICEN : integer := CONFIG_ICACHE_ENABLE; + constant CFG_ISETS : integer := CFG_IU_ISETS; + constant CFG_ISETSZ : integer := CFG_ICACHE_SZ; + constant CFG_ILINE : integer := CFG_ILINE_SZ; + constant CFG_IREPL : integer := CFG_ICACHE_ALGORND; + constant CFG_ILOCK : integer := CONFIG_ICACHE_LOCK; + constant CFG_ILRAMEN : integer := CONFIG_ICACHE_LRAM; + constant CFG_ILRAMADDR: integer := 16#CONFIG_ICACHE_LRSTART#; + constant CFG_ILRAMSZ : integer := CFG_ILRAM_SIZE; + constant CFG_DCEN : integer := CONFIG_DCACHE_ENABLE; + constant CFG_DSETS : integer := CFG_IU_DSETS; + constant CFG_DSETSZ : integer := CFG_DCACHE_SZ; + constant CFG_DLINE : integer := CFG_DLINE_SZ; + constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; + constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; + constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; + constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; + constant CFG_DLRAMSZ : integer := CFG_DLRAM_SIZE; + constant CFG_MMUEN : integer := CONFIG_MMUEN; + constant CFG_ITLBNUM : integer := CONFIG_ITLBNUM; + constant CFG_DTLBNUM : integer := CONFIG_DTLBNUM; + constant CFG_TLB_TYPE : integer := CONFIG_TLB_TYPE + CFG_MMU_FASTWB*2; + constant CFG_TLB_REP : integer := CONFIG_TLB_REP; + constant CFG_MMU_PAGE : integer := CONFIG_MMU_PAGE; + constant CFG_DSU : integer := CONFIG_DSU_ENABLE; + constant CFG_ITBSZ : integer := CFG_DSU_ITB; + constant CFG_ATBSZ : integer := CFG_DSU_ATB; + constant CFG_LEON3FT_EN : integer := CONFIG_LEON3FT_EN; + constant CFG_IUFT_EN : integer := CONFIG_IUFT_EN; + constant CFG_FPUFT_EN : integer := CONFIG_FPUFT; + constant CFG_RF_ERRINJ : integer := CONFIG_RF_ERRINJ; + constant CFG_CACHE_FT_EN : integer := CONFIG_CACHE_FT_EN; + constant CFG_CACHE_ERRINJ : integer := CONFIG_CACHE_ERRINJ; + constant CFG_LEON3_NETLIST: integer := CONFIG_LEON3_NETLIST; + constant CFG_DISAS : integer := CONFIG_IU_DISAS + CONFIG_IU_DISAS_NET; + constant CFG_PCLOW : integer := CFG_DEBUG_PC32; + +-- AMBA settings + constant CFG_DEFMST : integer := CONFIG_AHB_DEFMST; + constant CFG_RROBIN : integer := CONFIG_AHB_RROBIN; + constant CFG_SPLIT : integer := CONFIG_AHB_SPLIT; + constant CFG_FPNPEN : integer := CONFIG_AHB_FPNPEN; + constant CFG_AHBIO : integer := 16#CONFIG_AHB_IOADDR#; + constant CFG_APBADDR : integer := 16#CONFIG_APB_HADDR#; + constant CFG_AHB_MON : integer := CONFIG_AHB_MON; + constant CFG_AHB_MONERR : integer := CONFIG_AHB_MONERR; + constant CFG_AHB_MONWAR : integer := CONFIG_AHB_MONWAR; + constant CFG_AHB_DTRACE : integer := CONFIG_AHB_DTRACE; + +-- DSU UART + constant CFG_AHB_UART : integer := CONFIG_DSU_UART; + +-- JTAG based DSU interface + constant CFG_AHB_JTAG : integer := CONFIG_DSU_JTAG; + +-- Ethernet DSU + constant CFG_DSU_ETH : integer := CONFIG_DSU_ETH + CONFIG_DSU_ETH_PROG + CONFIG_DSU_ETH_DIS; + constant CFG_ETH_BUF : integer := CFG_DSU_ETHB; + constant CFG_ETH_IPM : integer := 16#CONFIG_DSU_IPMSB#; + constant CFG_ETH_IPL : integer := 16#CONFIG_DSU_IPLSB#; + constant CFG_ETH_ENM : integer := 16#CONFIG_DSU_ETHMSB#; + constant CFG_ETH_ENL : integer := 16#CONFIG_DSU_ETHLSB#; + +-- LEON2 memory controller + constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2; + constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT; + constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT; + constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS; + constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM; + constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS; + constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK; + constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64; + constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE; + +-- Xilinx MIG + constant CFG_MIG_DDR2 : integer := CONFIG_MIG_DDR2; + constant CFG_MIG_RANKS : integer := CONFIG_MIG_RANKS; + constant CFG_MIG_COLBITS : integer := CONFIG_MIG_COLBITS; + constant CFG_MIG_ROWBITS : integer := CONFIG_MIG_ROWBITS; + constant CFG_MIG_BANKBITS: integer := CONFIG_MIG_BANKBITS; + constant CFG_MIG_HMASK : integer := 16#CONFIG_MIG_HMASK#; + + +-- Xilinx MIG Series 7 + constant CFG_MIG_SERIES7 : integer := CONFIG_MIG_SERIES7; + constant CFG_MIG_SERIES7_MODEL : integer := CONFIG_MIG_SERIES7_MODEL; + +-- AHB status register + constant CFG_AHBSTAT : integer := CONFIG_AHBSTAT_ENABLE; + constant CFG_AHBSTATN : integer := CONFIG_AHBSTAT_NFTSLV; + +-- AHB ROM + constant CFG_AHBROMEN : integer := CONFIG_AHBROM_ENABLE; + constant CFG_AHBROPIP : integer := CONFIG_AHBROM_PIPE; + constant CFG_AHBRODDR : integer := 16#CONFIG_AHBROM_START#; + constant CFG_ROMADDR : integer := 16#CONFIG_ROM_START#; + constant CFG_ROMMASK : integer := 16#E00# + 16#CONFIG_ROM_START#; + +-- AHB RAM + constant CFG_AHBRAMEN : integer := CONFIG_AHBRAM_ENABLE; + constant CFG_AHBRSZ : integer := CFG_AHBRAMSZ; + constant CFG_AHBRADDR : integer := 16#CONFIG_AHBRAM_START#; + constant CFG_AHBRPIPE : integer := CONFIG_AHBRAM_PIPE; +-- Gaisler Ethernet core + constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE; + constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA; + constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO; +#ifdef CONFIG_LEON3FT_PRESENT + constant CFG_GRETH_FT : integer := CONFIG_GRETH_FT; + constant CFG_GRETH_EDCLFT : integer := CONFIG_GRETH_EDCLFT; +#endif +-- UART 1 + constant CFG_UART1_ENABLE : integer := CONFIG_UART1_ENABLE; + constant CFG_UART1_FIFO : integer := CFG_UA1_FIFO; + +-- LEON3 interrupt controller + constant CFG_IRQ3_ENABLE : integer := CONFIG_IRQ3_ENABLE; + constant CFG_IRQ3_NSEC : integer := CONFIG_IRQ3_NSEC; + +-- Modular timer + constant CFG_GPT_ENABLE : integer := CONFIG_GPT_ENABLE; + constant CFG_GPT_NTIM : integer := CONFIG_GPT_NTIM; + constant CFG_GPT_SW : integer := CONFIG_GPT_SW; + constant CFG_GPT_TW : integer := CONFIG_GPT_TW; + constant CFG_GPT_IRQ : integer := CONFIG_GPT_IRQ; + constant CFG_GPT_SEPIRQ : integer := CONFIG_GPT_SEPIRQ; + constant CFG_GPT_WDOGEN : integer := CONFIG_GPT_WDOGEN; + constant CFG_GPT_WDOG : integer := 16#CONFIG_GPT_WDOG#; + +-- GPIO port + constant CFG_GRGPIO_ENABLE : integer := CONFIG_GRGPIO_ENABLE; + constant CFG_GRGPIO_IMASK : integer := 16#CONFIG_GRGPIO_IMASK#; + constant CFG_GRGPIO_WIDTH : integer := CONFIG_GRGPIO_WIDTH; + +-- I2C master + constant CFG_I2C_ENABLE : integer := CONFIG_I2C_ENABLE; + +-- VGA and PS2/ interface + constant CFG_KBD_ENABLE : integer := CONFIG_KBD_ENABLE; + constant CFG_VGA_ENABLE : integer := CONFIG_VGA_ENABLE; + constant CFG_SVGA_ENABLE : integer := CONFIG_SVGA_ENABLE; + +-- SPI memory controller + constant CFG_SPIMCTRL : integer := CONFIG_SPIMCTRL; + constant CFG_SPIMCTRL_SDCARD : integer := CONFIG_SPIMCTRL_SDCARD; + constant CFG_SPIMCTRL_READCMD : integer := 16#CONFIG_SPIMCTRL_READCMD#; + constant CFG_SPIMCTRL_DUMMYBYTE : integer := CONFIG_SPIMCTRL_DUMMYBYTE; + constant CFG_SPIMCTRL_DUALOUTPUT : integer := CONFIG_SPIMCTRL_DUALOUTPUT; + constant CFG_SPIMCTRL_SCALER : integer := CONFIG_SPIMCTRL_SCALER; + constant CFG_SPIMCTRL_ASCALER : integer := CONFIG_SPIMCTRL_ASCALER; + constant CFG_SPIMCTRL_PWRUPCNT : integer := CONFIG_SPIMCTRL_PWRUPCNT; + constant CFG_SPIMCTRL_OFFSET : integer := 16#CONFIG_SPIMCTRL_OFFSET#; + +-- SPI controller + constant CFG_SPICTRL_ENABLE : integer := CONFIG_SPICTRL_ENABLE; + constant CFG_SPICTRL_NUM : integer := CONFIG_SPICTRL_NUM; + constant CFG_SPICTRL_SLVS : integer := CONFIG_SPICTRL_SLVS; + constant CFG_SPICTRL_FIFO : integer := CONFIG_SPICTRL_FIFO; + constant CFG_SPICTRL_SLVREG : integer := CONFIG_SPICTRL_SLVREG; + constant CFG_SPICTRL_ODMODE : integer := CONFIG_SPICTRL_ODMODE; + constant CFG_SPICTRL_AM : integer := CONFIG_SPICTRL_AM; + constant CFG_SPICTRL_ASEL : integer := CONFIG_SPICTRL_ASEL; + constant CFG_SPICTRL_TWEN : integer := CONFIG_SPICTRL_TWEN; + constant CFG_SPICTRL_MAXWLEN : integer := CONFIG_SPICTRL_MAXWLEN; + constant CFG_SPICTRL_SYNCRAM : integer := CONFIG_SPICTRL_SYNCRAM; + constant CFG_SPICTRL_FT : integer := CONFIG_SPICTRL_FT; + +-- GRLIB debugging + constant CFG_DUART : integer := CONFIG_DEBUG_UART; + diff --git a/designs/leon3-xilinx-ac701/config.vhd.in b/designs/leon3-xilinx-ac701/config.vhd.in new file mode 100644 index 00000000..0b22306b --- /dev/null +++ b/designs/leon3-xilinx-ac701/config.vhd.in @@ -0,0 +1,19 @@ +#include "config.h" +#include "tkconfig.h" + +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench configuration +-- Copyright (C) 2009 Aeroflex Gaisler +------------------------------------------------------------------------------ + + +library techmap; +use techmap.gencomp.all; + +package config is + +#include "config.vhd.h" + + + +end; diff --git a/designs/leon3-xilinx-ac701/ddr_dummy.vhd b/designs/leon3-xilinx-ac701/ddr_dummy.vhd new file mode 100644 index 00000000..cf6a9d46 --- /dev/null +++ b/designs/leon3-xilinx-ac701/ddr_dummy.vhd @@ -0,0 +1,141 @@ +---------------------------------------------------------------------------- +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2012 Aeroflex Gaisler +---------------------------------------------------------------------------- +-- Package: ddr_dummy +-- File:ddr_dummy.vhd +-- Author:Fredrik Ringhage - Gaisler Research +-- Description: Xilinx MIG wrapper +------------------------------------------------------------------------------ + + +library ieee; +use ieee.std_logic_1164.all; +library techmap; +use techmap.gencomp.all; +-- pragma translate_off +library unisim; +use unisim.IBUF; +-- pragma translate_on + +library work; + +entity ddr_dummy is + generic ( + USE_MIG_INTERFACE_MODEL : boolean := false; + nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank + BANK_WIDTH : integer := 3; -- # of bank address + CKE_WIDTH : integer := 1; -- # of clock enable outputs + CS_WIDTH : integer := 1; -- # of chip select + DM_WIDTH : integer := 8; -- # of data mask + DQ_WIDTH : integer := 64; -- # of data bits + DQS_WIDTH : integer := 8; -- # of strobe pairs + ODT_WIDTH : integer := 1; -- # of ODT outputs + ROW_WIDTH : integer := 14 -- # of row/column address + ); + port ( + ddr_ck_p : out std_logic_vector(0 downto 0); + ddr_ck_n : out std_logic_vector(0 downto 0); + ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0); + ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0); + ddr_cas_n : out std_logic; + ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0); + ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0); + ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0); + ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0); + ddr_ras_n : out std_logic; + ddr_we_n : out std_logic; + ddr_reset_n : out std_logic; + ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0); + ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0); + ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0) + ); +end; + +architecture rtl of ddr_dummy is + + component OBUF generic (IOSTANDARD : string := "SSTL15"); + port (O : out std_ulogic; I : in std_ulogic); + end component; + + component IOBUF generic (IOSTANDARD : string := "SSTL15_T_DCI"); + port (O : out std_ulogic; IO : inout std_logic; I, T : in std_ulogic); + end component; + + component OBUFDS generic(IOSTANDARD : string := "DIFF_SSTL15"); + port(O : out std_ulogic; OB : out std_ulogic; I : in std_ulogic); +end component; + + component IOBUFDS generic (IOSTANDARD : string := "DIFF_SSTL15"); + port (O : out std_ulogic; IO, IOB : inout std_logic; I, T : in std_ulogic); + end component; + + signal in_dq : std_logic_vector(DQ_WIDTH-1 downto 0); + signal in_dqs : std_logic_vector(DQS_WIDTH-1 downto 0); + +begin + + io_cas : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_cas_n, I => '0'); + + io_ras : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_ras_n, I => '0'); + + io_we : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_we_n, I => '0'); + + io_ck : OBUFDS generic map (IOSTANDARD => "DIFF_SSTL15") + port map (O => ddr_ck_p(0), OB => ddr_ck_n(0), I => '0'); + + io_addr_gen : for i in 0 to ROW_WIDTH-1 generate + begin + io_addr : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_addr(i), I => '0'); + end generate io_addr_gen; + + io_ba_gen : for i in 0 to BANK_WIDTH-1 generate + begin + io_addr : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_ba(i), I => '0'); + end generate io_ba_gen; + + io_cs_gen : for i in 0 to CS_WIDTH*nCS_PER_RANK-1 generate + begin + io_cs : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_cs_n(i), I => '0'); + end generate io_cs_gen; + + io_odt_gen : for i in 0 to ODT_WIDTH-1 generate + begin + io_odt : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_odt(i), I => '0'); + end generate io_odt_gen; + + io_dm_gen : for i in 0 to DM_WIDTH-1 generate + begin + io_dm : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_dm(i), I => '0'); + end generate io_dm_gen; + + io_cke_gen : for i in 0 to CKE_WIDTH-1 generate + begin + io_cke : OBUF generic map (IOSTANDARD => "SSTL15") + port map (O => ddr_cke(i), I => '0'); + end generate io_cke_gen; + + op_reset : OBUF generic map (IOSTANDARD => "LVCMOS15") + port map (O => ddr_reset_n, I => '1'); + + io_dq_gen : for i in 0 to DQ_WIDTH-1 generate + begin + io_dq : IOBUF generic map (IOSTANDARD => "SSTL15_T_DCI") + port map (O => in_dq(i), IO => ddr_dq(i), I => '0', T => '0'); + end generate io_dq_gen; + + io_dqs_gen : for i in 0 to DQS_WIDTH-1 generate + begin + io_dqs : IOBUFDS generic map (IOSTANDARD => "DIFF_SSTL15_T_DCI") + port map (O => in_dqs(i), IO => ddr_dqs(i), IOB => ddr_dqs_n(i), I => '0', T => '1'); + end generate io_dqs_gen; + +end architecture rtl; \ No newline at end of file diff --git a/designs/leon3-xilinx-ac701/lconfig.tk b/designs/leon3-xilinx-ac701/lconfig.tk new file mode 100755 index 00000000..e587d7a9 --- /dev/null +++ b/designs/leon3-xilinx-ac701/lconfig.tk @@ -0,0 +1,7081 @@ +# FILE: header.tk +# This file is boilerplate TCL/TK function definitions for 'make xconfig'. +# +# CHANGES +# ======= +# +# 8 January 1999, Michael Elizabeth Chastain, +# - Remove unused do_cmd function (part of the 2.0 sound support). +# - Arrange buttons in three columns for better screen fitting. +# - Add CONSTANT_Y, CONSTANT_M, CONSTANT_N for commands like: +# dep_tristate 'foo' CONFIG_FOO m +# +# 23 January 1999, Michael Elizabeth Chastain, +# - Shut vfix the hell up. +# +# 24 January 1999, Michael Elizabeth Chastain, +# - Improve the exit message (Jeff Ronne). + +# +# This is a handy replacement for ".widget cget" that requires neither tk4 +# nor additional source code uglification. +# +proc cget { w option } { + return "[lindex [$w configure $option] 4]" +} + +# +# Function to compensate for broken config.in scripts like the sound driver, +# which make dependencies on variables that are never even conditionally +# defined. +# +proc vfix { var } { + global $var + if [ catch {eval concat $$var} ] { + set $var 4 + } +} + +# +# Constant values used by certain dep_tristate commands. +# +set CONSTANT_Y 1 +set CONSTANT_M 2 +set CONSTANT_N 0 +set CONSTANT_E 4 + +# +# Create a "reference" object to steal colors from. +# +button .ref + +# +# On monochrome displays, -disabledforeground is blank by default; that's +# bad. Fill it with -foreground instead. +# +if { [cget .ref -disabledforeground] == "" } { + .ref configure -disabledforeground [cget .ref -foreground] +} + + +# +# Define some macros we will need to parse the config.in file. +# + +proc mainmenu_name { text } { + wm title . "$text" +} + +proc menu_option { w menu_num text } { + global menus_per_column + global processed_top_level + set processed_top_level [expr $processed_top_level + 1] + if { $processed_top_level <= $menus_per_column } then { + set myframe left + } elseif { $processed_top_level <= [expr 2 * $menus_per_column] } then { + set myframe middle + } else { + set myframe right + } + button .f0.x$menu_num -anchor w -text "$text" \ + -command "$w .$w \"$text\"" + pack .f0.x$menu_num -pady 0 -side top -fill x -in .f0.$myframe +} + +proc load_configfile { w title func } { + catch {destroy $w} + toplevel $w -class Dialog + global loadfile + frame $w.x + label $w.bm -bitmap questhead + pack $w.bm -pady 10 -side top -padx 10 + label $w.x.l -text "Enter filename:" -relief raised + entry $w.x.x -width 35 -relief sunken -borderwidth 2 \ + -textvariable loadfile + pack $w.x.l $w.x.x -anchor w -side left + pack $w.x -side top -pady 10 + wm title $w "$title" + + set oldFocus [focus] + frame $w.f + button $w.f.back -text "OK" -width 20 \ + -command "destroy $w; focus $oldFocus;$func .fileio" + button $w.f.canc -text "Cancel" \ + -width 20 -command "destroy $w; focus $oldFocus" + pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 + pack $w.f -pady 10 -side bottom -padx 10 -anchor w + focus $w + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + wm geometry $w +$winx+$winy +} + +bind all {maybe_exit .maybe} + +proc maybe_exit { w } { + catch {destroy $w} + toplevel $w -class Dialog + label $w.bm -bitmap questhead + pack $w.bm -pady 10 -side top -padx 10 + message $w.m -width 400 -aspect 300 \ + -text "Changes will be lost. Are you sure?" -relief flat + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Are you sure?" + + set oldFocus [focus] + frame $w.f + button $w.f.back -text "OK" -width 20 \ + -command "exit 1" + button $w.f.canc -text "Cancel" \ + -width 20 -command "destroy $w; focus $oldFocus" + pack $w.f.back $w.f.canc -side left -pady 10 -padx 45 + pack $w.f -pady 10 -side bottom -padx 10 -anchor w + bind $w "exit 1" + bind $w "destroy $w; focus $oldFocus" + focus $w + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + wm geometry $w +$winx+$winy +} + +proc read_config_file { w } { + global loadfile + if { [string length $loadfile] != 0 && [file readable $loadfile] == 1 } then { + read_config $loadfile + } else { + catch {destroy $w} + toplevel $w -class Dialog + message $w.m -width 400 -aspect 300 -text \ + "Unable to read file $loadfile" \ + -relief raised + label $w.bm -bitmap error + pack $w.bm $w.m -pady 10 -side top -padx 10 + wm title $w "Xconfig Internal Error" + + set oldFocus [focus] + frame $w.f + button $w.f.back -text "Bummer" \ + -width 10 -command "destroy $w; focus $oldFocus" + pack $w.f.back -side bottom -pady 10 -anchor s + pack $w.f -pady 10 -side top -padx 10 -anchor s + focus $w + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + wm geometry $w +$winx+$winy + } +} + +proc write_config_file { w } { + global loadfile + if { [string length $loadfile] != 0 + && ([file writable $loadfile] == 1 || ([file exists $loadfile] == 0 && [file writable [file dirname $loadfile]] == 1)) } then { + writeconfig $loadfile .null + } else { + catch {destroy $w} + toplevel $w -class Dialog + message $w.m -width 400 -aspect 300 -text \ + "Unable to write file $loadfile" \ + -relief raised + label $w.bm -bitmap error + pack $w.bm $w.m -pady 10 -side top -padx 10 + wm title $w "Xconfig Internal Error" + + set oldFocus [focus] + frame $w.f + button $w.f.back -text "OK" \ + -width 10 -command "destroy $w; focus $oldFocus" + pack $w.f.back -side bottom -pady 10 -anchor s + pack $w.f -pady 10 -side top -padx 10 -anchor s + focus $w + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + wm geometry $w +$winx+$winy + } +} + +proc read_config { filename } { + set file1 [open $filename r] + clear_choices + while { [gets $file1 line] >= 0} { + if [regexp {([0-9A-Za-z_]+)=([ynm])} $line foo var value] { + if { $value == "y" } then { set cmd "global $var; set $var 1" } + if { $value == "n" } then { set cmd "global $var; set $var 0" } + if { $value == "m" } then { set cmd "global $var; set $var 2" } + eval $cmd + } + if [regexp {# ([0-9A-Za-z_]+) is not set} $line foo var] { + set cmd "global $var; set $var 0" + eval $cmd + } + if [regexp {([0-9A-Za-z_]+)=([0-9A-Fa-f]+)} $line foo var value] { + set cmd "global $var; set $var $value" + eval $cmd + } + if [regexp {([0-9A-Za-z_]+)="([^"]*)"} $line foo var value] { + set cmd "global $var; set $var \"$value\"" + eval $cmd + } + } + close $file1 + update_choices + update_mainmenu +} +proc write_comment { file1 file2 text } { + puts $file1 "" + puts $file1 "#" + puts $file1 "# $text" + puts $file1 "#" + puts $file2 "/*" + puts $file2 " * $text" + puts $file2 " */" +} + +proc effective_dep { deplist } { + global CONFIG_MODULES + set depend 1 + foreach i $deplist { + if {$i == 0} then {set depend 0} + if {$i == 2 && $depend == 1} then {set depend 2} + } + if {$depend == 2 && $CONFIG_MODULES == 0} then {set depend 0} + return $depend +} + +proc sync_tristate { var dep } { + global CONFIG_MODULES + if {$dep == 0 && ($var == 1 || $var == 2)} then { + set var 0 + } elseif {$dep == 2 && $var == 1} then { + set var 2 + } elseif {$var == 2 && $CONFIG_MODULES == 0} then { + if {$dep == 1} then {set var 1} else {set var 0} + } + return $var +} + +proc sync_bool { var dep modset } { + set var [sync_tristate $var $dep] + if {$dep == 2 && $var == 2} then { + set var $modset + } + return $var +} + +proc write_tristate { file1 file2 varname variable deplist modset } { + set variable [sync_tristate $variable [effective_dep $deplist]] + if { $variable == 2 } \ + then { set variable $modset } + if { $variable == 1 } \ + then { puts $file1 "$varname=y"; \ + puts $file2 "#define $varname 1" } \ + elseif { $variable == 2 } \ + then { puts $file1 "$varname=m"; \ + puts $file2 "#undef $varname"; \ + puts $file2 "#define ${varname}_MODULE 1" } \ + elseif { $variable == 0 } \ + then { puts $file1 "# $varname is not set"; \ + puts $file2 "#undef $varname"} \ + else { \ + puts stdout "ERROR - Attempting to write value for unconfigured variable ($varname)." \ + } +} + +proc write_int { file1 file2 varname variable dep } { + if { $dep == 0 } \ + then { puts $file1 "# $varname is not set"; \ + puts $file2 "#undef $varname"} \ + else { + puts $file1 "$varname=$variable"; \ + puts $file2 "#define $varname ($variable)"; \ + } +} + +proc write_hex { file1 file2 varname variable dep } { + if { $dep == 0 } \ + then { puts $file1 "# $varname is not set"; \ + puts $file2 "#undef $varname"} \ + else { + puts $file1 "$varname=$variable"; \ + puts -nonewline $file2 "#define $varname "; \ + puts $file2 [exec echo $variable | sed s/^0\[xX\]//]; \ + } +} + +proc write_string { file1 file2 varname variable dep } { + if { $dep == 0 } \ + then { puts $file1 "# $varname is not set"; \ + puts $file2 "#undef $varname"} \ + else { + puts $file1 "$varname=\"$variable\""; \ + puts $file2 "#define $varname \"$variable\""; \ + } +} + +proc option_name {w mnum line text helpidx} { + button $w.x$line.l -text "$text" -relief groove -anchor w + $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ + -activeback [cget $w.x$line.l -bg] + button $w.x$line.help -text "Help" -relief raised \ + -command "dohelp .dohelp $helpidx .menu$mnum" + pack $w.x$line.help -side right -fill y + pack $w.x$line.l -side right -fill both -expand on +} + +proc toggle_switch2 {w mnum line text variable} { + frame $w.x$line -relief sunken + radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ + -relief groove -width 2 -command "update_active" +# radiobutton $w.x$line.m -text "-" -variable $variable -value 2 \ +# -relief groove -width 2 -command "update_active" + radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ + -relief groove -width 2 -command "update_active" + + option_name $w $mnum $line $text $variable + + pack $w.x$line.n $w.x$line.y -side right -fill y +} + +proc toggle_switch3 {w mnum line text variable} { + frame $w.x$line -relief sunken + radiobutton $w.x$line.y -text "y" -variable $variable -value 1 \ + -relief groove -width 2 -command "update_active" + radiobutton $w.x$line.m -text "m" -variable $variable -value 2 \ + -relief groove -width 2 -command "update_active" + radiobutton $w.x$line.n -text "n" -variable $variable -value 0 \ + -relief groove -width 2 -command "update_active" + + option_name $w $mnum $line $text $variable + + global CONFIG_MODULES + if {($CONFIG_MODULES == 0)} then { + $w.x$line.m configure -state disabled + } + pack $w.x$line.n $w.x$line.m $w.x$line.y -side right -fill y +} + +proc bool {w mnum line text variable} { + toggle_switch2 $w $mnum $line $text $variable +# $w.x$line.m configure -state disabled + pack $w.x$line -anchor w -fill both -expand on +} + +proc tristate {w mnum line text variable } { + toggle_switch3 $w $mnum $line $text $variable + pack $w.x$line -anchor w -fill both -expand on +} + +proc dep_tristate {w mnum line text variable } { + tristate $w $mnum $line $text $variable +} + +proc dep_bool {w mnum line text variable } { + bool $w $mnum $line $text $variable +} + +proc int { w mnum line text variable } { + frame $w.x$line + entry $w.x$line.x -width 11 -relief sunken -borderwidth 2 \ + -textvariable $variable + option_name $w $mnum $line $text $variable + pack $w.x$line.x -anchor w -side right -fill y + pack $w.x$line -anchor w -fill both -expand on +} + +proc hex { w mnum line text variable } { + int $w $mnum $line $text $variable +} + +proc istring { w mnum line text variable } { + frame $w.x$line + entry $w.x$line.x -width 18 -relief sunken -borderwidth 2 \ + -textvariable $variable + option_name $w $mnum $line $text $variable + pack $w.x$line.x -anchor w -side right -fill y + pack $w.x$line -anchor w -fill both -expand on +} + +proc minimenu { w mnum line text variable helpidx } { + frame $w.x$line + menubutton $w.x$line.x -textvariable $variable -menu \ + $w.x$line.x.menu -relief raised \ + -anchor w + option_name $w $mnum $line $text $helpidx + pack $w.x$line.x -anchor w -side right -fill y + pack $w.x$line -anchor w -fill both -expand on +} + +proc menusplit {w m n} { + if { $n > 2 } then { + update idletasks + set menuoptsize [expr [$m yposition 2] - [$m yposition 1]] + set maxsize [winfo screenheight $w] + set splitpoint [expr $maxsize * 4 / 5 / $menuoptsize - 1] + for {set i [expr $splitpoint + 1]} {$i <= $n} {incr i $splitpoint} { + $m entryconfigure $i -columnbreak 1 + } + } +} + +proc menutitle {text menu w} { + wm title $w "$text" +} + +proc submenu { w mnum line text subnum } { + frame $w.x$line + button $w.x$line.l -text "" -width 9 -relief groove + $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ + -activeback [cget $w.x$line.l -bg] -state disabled + button $w.x$line.m -text "$text" -relief raised -anchor w \ + -command "catch {destroy .menu$subnum}; menu$subnum .menu$subnum \"$text\"" + pack $w.x$line.l -side left -fill both + pack $w.x$line.m -anchor w -side right -fill both -expand on + pack $w.x$line -anchor w -fill both -expand on +} + +proc comment {w mnum line text } { + frame $w.x$line + button $w.x$line.l -text "" -width 15 -relief groove + $w.x$line.l configure -activefore [cget $w.x$line.l -fg] \ + -activeback [cget $w.x$line.l -bg] -state disabled + button $w.x$line.m -text "$text" -relief groove -anchor w + $w.x$line.m configure -activefore [cget $w.x$line.m -fg] \ + -activeback [cget $w.x$line.m -bg] + pack $w.x$line.l -side left -fill both + pack $w.x$line.m -anchor w -side right -fill both -expand on + pack $w.x$line -anchor w -fill both -expand on +} + +proc readhelp {tag fn} { + set message "" + set b 0 + if { [file readable $fn] == 1} then { + set fhandle [open $fn r] + while {[gets $fhandle inline] >= 0} { + if { $b == 0 } { + if { [regexp $tag $inline ] } { + set b 1 + set message "$inline:\n" + } + } else { + if { [regexp {^[^ \t]} $inline]} { + break + } + set message "$message\n$inline" + } + } + close $fhandle + } + return $message +} + +proc dohelp {w var parent} { + catch {destroy $w} + toplevel $w -class Dialog + + set filefound 0 + set found 0 + set lineno 0 + + if { [file readable config.help] == 1} then { + set filefound 1 + # First escape sed regexp special characters in var: + set var [exec echo "$var" | sed s/\[\]\[\/.^$*\]/\\\\&/g] + # Now pick out right help text: + set message [readhelp $var config.help] + set found [expr [string length "$message"] > 0] + } + + frame $w.f1 + pack $w.f1 -fill both -expand on + + # Do the OK button + # + set oldFocus [focus] + frame $w.f2 + button $w.f2.ok -text "OK" \ + -width 10 -command "destroy $w; catch {focus $oldFocus}" + pack $w.f2.ok -side bottom -pady 6 -anchor n + pack $w.f2 -side bottom -padx 10 -anchor s + + scrollbar $w.f1.vscroll -command "$w.f1.canvas yview" + pack $w.f1.vscroll -side right -fill y + + canvas $w.f1.canvas -relief flat -borderwidth 0 \ + -yscrollcommand "$w.f1.vscroll set" + frame $w.f1.f + pack $w.f1.canvas -side right -fill y -expand on + + if { $found == 0 } then { + if { $filefound == 0 } then { + message $w.f1.f.m -width 750 -aspect 300 -relief flat -text \ + "No help available - unable to open file config.help." + } else { + message $w.f1.f.m -width 400 -aspect 300 -relief flat -text \ + "No help available for $var" + } + label $w.f1.bm -bitmap error + wm title $w "RTFM" + } else { + text $w.f1.f.m -width 73 -relief flat -wrap word + $w.f1.f.m insert 0.0 $message + $w.f1.f.m conf -state disabled -height [$w.f1.f.m index end] + + label $w.f1.bm -bitmap info + wm title $w "Configuration help" + } + pack $w.f1.f.m -side left + pack $w.f1.bm $w.f1.f -side left -padx 10 + + focus $w + set winx [expr [winfo x $parent]+20] + set winy [expr [winfo y $parent]+20] + wm geometry $w +$winx+$winy + set sizok [expr [winfo reqheight $w.f2.ok] + 12] + set maxy [expr [winfo screenheight .] * 3 / 4] + set canvtotal [winfo reqheight $w.f1.f.m] + if [expr $sizok + $canvtotal < $maxy] { + set sizy $canvtotal + } else { + set sizy [expr $maxy - $sizok] + } + $w.f1.canvas configure -height $sizy -width [winfo reqwidth $w.f1.f.m] \ + -scrollregion "0 0 [winfo reqwidth $w.f1.f.m] \ + [winfo reqheight $w.f1.f.m]" + $w.f1.canvas create window 0 0 -anchor nw -window $w.f1.f + update idletasks + + set maxy [winfo screenheight .] + if [expr $sizok + $canvtotal < $maxy] { + set sizy [expr $sizok + $canvtotal] + } else { + set sizy $maxy + } + wm maxsize $w [winfo width $w] $sizy +} + +bind all { catch {exec cp -f .config .config.old}; \ + writeconfig .config config.h; wrapup .wrap } + +proc wrapup {w } { + catch {destroy $w} + toplevel $w -class Dialog + + global CONFIG_MODVERSIONS; vfix CONFIG_MODVERSIONS + message $w.m -width 460 -aspect 300 -relief raised -text \ + "End of design configuration. " + label $w.bm -bitmap info + pack $w.bm $w.m -pady 10 -side top -padx 10 + wm title $w "LEON build instructions" + + set oldFocus [focus] + frame $w.f + button $w.f.back -text "OK" \ + -width 10 -command "exit 2" + pack $w.f.back -side bottom -pady 10 -anchor s + pack $w.f -pady 10 -side top -padx 10 -anchor s + focus $w + bind $w "exit 2" + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + wm geometry $w +$winx+$winy + +} + +proc unregister_active {num} { + global active_menus + set index [lsearch -exact $active_menus $num] + if {$index != -1} then {set active_menus [lreplace $active_menus $index $index]} +} + +proc update_active {} { + global active_menus total_menus + set max 0 + if {[llength $active_menus] > 0} then { + set max [lindex $active_menus end] + update_define [toplevel_menu [lindex $active_menus 0]] $max 0 + } + foreach i $active_menus { + if {[winfo exists .menu$i] == 0} then { + unregister_active $i + } else { + update_menu$i + } + } + update_define [expr $max + 1] $total_menus 1 + update_mainmenu +} + +proc configure_entry {w option items} { + foreach i $items { + $w.$i configure -state $option + } +} + +proc validate_int {name val default} { + if {([exec echo $val | sed s/^-//g | tr -d \[:digit:\] ] != "")} then { + global $name; set $name $default + } +} + +proc validate_hex {name val default} { + if {([exec echo $val | tr -d \[:xdigit:\] ] != "")} then { + global $name; set $name $default + } +} + +proc update_define {first last allow_update} { + for {set i $first} {$i <= $last} {incr i} { + update_define_menu$i + if {$allow_update == 1} then update + } +} + +# +# Next set up the particulars for the top level menu, and define a few +# buttons which we will stick down at the bottom. +# + +frame .f0 +frame .f0.left +frame .f0.middle +frame .f0.right + +set active_menus [list] +set processed_top_level 0 +set ARCH sparc +set menus_per_column 4 +set total_menus 25 + +proc toplevel_menu {num} { + if {$num == 4} then {return 3} + if {$num == 5} then {return 3} + if {$num == 6} then {return 3} + if {$num == 7} then {return 3} + if {$num == 8} then {return 3} + if {$num == 9} then {return 3} + if {$num == 10} then {return 3} + if {$num == 14} then {return 13} + if {$num == 15} then {return 14} + if {$num == 16} then {return 14} + if {$num == 17} then {return 14} + if {$num == 18} then {return 13} + if {$num == 19} then {return 13} + if {$num == 20} then {return 13} + if {$num == 21} then {return 13} + if {$num == 22} then {return 13} + if {$num == 23} then {return 22} + if {$num == 24} then {return 22} + return $num +} + +mainmenu_name "LEON3MP Design Configuration" +menu_option menu1 1 "Synthesis " +proc menu1 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 1} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 1]] + message $w.m -width 400 -aspect 300 -text \ + "Synthesis " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Synthesis " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 1; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu2 .menu2 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 1; menu0 .menu0 \"$title\"" + $w.f.prev configure -state disabled + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + global tmpvar_0 + minimenu $w.config.f 1 0 "Target technology " tmpvar_0 CONFIG_SYN_INFERRED + menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Target technology \"" + $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_0 -value "Inferred" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-Stratix" -variable tmpvar_0 -value "Altera-Stratix" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixII" -variable tmpvar_0 -value "Altera-StratixII" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIII" -variable tmpvar_0 -value "Altera-StratixIII" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-StratixIV" -variable tmpvar_0 -value "Altera-StratixIV" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-CycloneIII" -variable tmpvar_0 -value "Altera-CycloneIII" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-Others" -variable tmpvar_0 -value "Altera-Others" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator" -variable tmpvar_0 -value "Actel-Axcelerator" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Axcelerator-DSP" -variable tmpvar_0 -value "Actel-Axcelerator-DSP" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic" -variable tmpvar_0 -value "Actel-Proasic" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-ProasicPlus" -variable tmpvar_0 -value "Actel-ProasicPlus" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3" -variable tmpvar_0 -value "Actel-Proasic3" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3E" -variable tmpvar_0 -value "Actel-Proasic3E" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Proasic3L" -variable tmpvar_0 -value "Actel-Proasic3L" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-IGLOO/p/L" -variable tmpvar_0 -value "Actel-IGLOO/p/L" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-Fusion" -variable tmpvar_0 -value "Actel-Fusion" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT025CRH" -variable tmpvar_0 -value "Aeroflex-UT025CRH" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT130HBD" -variable tmpvar_0 -value "Aeroflex-UT130HBD" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT90NHBD" -variable tmpvar_0 -value "Aeroflex-UT90NHBD" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18" -variable tmpvar_0 -value "Atmel-ATC18" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Atmel-ATC18RHA" -variable tmpvar_0 -value "Atmel-ATC18RHA" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "IBM-CMOS9SF" -variable tmpvar_0 -value "IBM-CMOS9SF" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Custom1" -variable tmpvar_0 -value "Custom1" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "eASIC90" -variable tmpvar_0 -value "eASIC90" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "eASIC45" -variable tmpvar_0 -value "eASIC45" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "IHP25" -variable tmpvar_0 -value "IHP25" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "IHP25RH" -variable tmpvar_0 -value "IHP25RH" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Lattice-EC/ECP/XP" -variable tmpvar_0 -value "Lattice-EC/ECP/XP" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Quicklogic-Eclipse" -variable tmpvar_0 -value "Quicklogic-Eclipse" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Peregrine" -variable tmpvar_0 -value "Peregrine" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T" -variable tmpvar_0 -value "RH-LIB18T" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_0 -value "RH-UMC" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "SAED32" -variable tmpvar_0 -value "SAED32" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "DARE" -variable tmpvar_0 -value "DARE" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "SMIC130" -variable tmpvar_0 -value "SMIC130" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "TM65Gplus" -variable tmpvar_0 -value "TM65Gplus" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "TSMC90" -variable tmpvar_0 -value "TSMC90" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "UMC180" -variable tmpvar_0 -value "UMC180" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Artix7" -variable tmpvar_0 -value "Xilinx-Artix7" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Kintex7" -variable tmpvar_0 -value "Xilinx-Kintex7" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3" -variable tmpvar_0 -value "Xilinx-Spartan3" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan3E" -variable tmpvar_0 -value "Xilinx-Spartan3E" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Spartan6" -variable tmpvar_0 -value "Xilinx-Spartan6" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-VirtexE" -variable tmpvar_0 -value "Xilinx-VirtexE" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex2" -variable tmpvar_0 -value "Xilinx-Virtex2" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex4" -variable tmpvar_0 -value "Xilinx-Virtex4" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex5" -variable tmpvar_0 -value "Xilinx-Virtex5" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex6" -variable tmpvar_0 -value "Xilinx-Virtex6" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Virtex7" -variable tmpvar_0 -value "Xilinx-Virtex7" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-Zynq7000" -variable tmpvar_0 -value "Xilinx-Zynq7000" -command "update_active" + menusplit $w $w.config.f.x0.x.menu 50 + global tmpvar_1 + minimenu $w.config.f 1 1 "Memory Library " tmpvar_1 CONFIG_MEM_INFERRED + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Memory Library \"" + $w.config.f.x1.x.menu add radiobutton -label "Inferred" -variable tmpvar_1 -value "Inferred" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "UMC18" -variable tmpvar_1 -value "UMC18" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "RH-UMC" -variable tmpvar_1 -value "RH-UMC" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "SAED32" -variable tmpvar_1 -value "SAED32" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "DARE" -variable tmpvar_1 -value "DARE" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "Artisan" -variable tmpvar_1 -value "Artisan" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "Custom1" -variable tmpvar_1 -value "Custom1" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "EASIC45" -variable tmpvar_1 -value "EASIC45" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "Virage" -variable tmpvar_1 -value "Virage" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "Virage-TSMC90" -variable tmpvar_1 -value "Virage-TSMC90" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 10 + bool $w.config.f 1 2 "Infer RAM" CONFIG_SYN_INFER_RAM + bool $w.config.f 1 3 "Infer pads" CONFIG_SYN_INFER_PADS + bool $w.config.f 1 4 "Disable asynchronous reset" CONFIG_SYN_NO_ASYNC + bool $w.config.f 1 5 "Enable scan support " CONFIG_SYN_SCAN + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu1 {} { + global CONFIG_SYN_INFERRED + global CONFIG_SYN_CUSTOM1 + global CONFIG_SYN_ATC18 + global CONFIG_SYN_TSMC90 + global CONFIG_SYN_EASIC45 + global CONFIG_SYN_UMC + global CONFIG_SYN_RHUMC + global CONFIG_SYN_DARE + global CONFIG_SYN_SAED32 + global CONFIG_SYN_ARTISAN + if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_EASIC45 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_DARE == 1 || $CONFIG_SYN_SAED32 == 1 || $CONFIG_SYN_ARTISAN == 1)} then {configure_entry .menu1.config.f.x1 normal {x l}} else {configure_entry .menu1.config.f.x1 disabled {x l}} + global CONFIG_SYN_INFER_RAM + if {($CONFIG_SYN_INFERRED != 1)} then { + configure_entry .menu1.config.f.x2 normal {n l y}} else {configure_entry .menu1.config.f.x2 disabled {y n l}} + global CONFIG_SYN_INFER_PADS + if {($CONFIG_SYN_INFERRED != 1)} then { + configure_entry .menu1.config.f.x3 normal {n l y}} else {configure_entry .menu1.config.f.x3 disabled {y n l}} +} + + +proc update_define_menu1 {} { + update_define_mainmenu + global CONFIG_MODULES + global tmpvar_0 + global CONFIG_SYN_INFERRED + if {$tmpvar_0 == "Inferred"} then {set CONFIG_SYN_INFERRED 1} else {set CONFIG_SYN_INFERRED 0} + global CONFIG_SYN_STRATIX + if {$tmpvar_0 == "Altera-Stratix"} then {set CONFIG_SYN_STRATIX 1} else {set CONFIG_SYN_STRATIX 0} + global CONFIG_SYN_STRATIXII + if {$tmpvar_0 == "Altera-StratixII"} then {set CONFIG_SYN_STRATIXII 1} else {set CONFIG_SYN_STRATIXII 0} + global CONFIG_SYN_STRATIXIII + if {$tmpvar_0 == "Altera-StratixIII"} then {set CONFIG_SYN_STRATIXIII 1} else {set CONFIG_SYN_STRATIXIII 0} + global CONFIG_SYN_STRATIXIV + if {$tmpvar_0 == "Altera-StratixIV"} then {set CONFIG_SYN_STRATIXIV 1} else {set CONFIG_SYN_STRATIXIV 0} + global CONFIG_SYN_CYCLONEIII + if {$tmpvar_0 == "Altera-CycloneIII"} then {set CONFIG_SYN_CYCLONEIII 1} else {set CONFIG_SYN_CYCLONEIII 0} + global CONFIG_SYN_ALTERA + if {$tmpvar_0 == "Altera-Others"} then {set CONFIG_SYN_ALTERA 1} else {set CONFIG_SYN_ALTERA 0} + global CONFIG_SYN_AXCEL + if {$tmpvar_0 == "Actel-Axcelerator"} then {set CONFIG_SYN_AXCEL 1} else {set CONFIG_SYN_AXCEL 0} + global CONFIG_SYN_AXDSP + if {$tmpvar_0 == "Actel-Axcelerator-DSP"} then {set CONFIG_SYN_AXDSP 1} else {set CONFIG_SYN_AXDSP 0} + global CONFIG_SYN_PROASIC + if {$tmpvar_0 == "Actel-Proasic"} then {set CONFIG_SYN_PROASIC 1} else {set CONFIG_SYN_PROASIC 0} + global CONFIG_SYN_PROASICPLUS + if {$tmpvar_0 == "Actel-ProasicPlus"} then {set CONFIG_SYN_PROASICPLUS 1} else {set CONFIG_SYN_PROASICPLUS 0} + global CONFIG_SYN_PROASIC3 + if {$tmpvar_0 == "Actel-Proasic3"} then {set CONFIG_SYN_PROASIC3 1} else {set CONFIG_SYN_PROASIC3 0} + global CONFIG_SYN_PROASIC3E + if {$tmpvar_0 == "Actel-Proasic3E"} then {set CONFIG_SYN_PROASIC3E 1} else {set CONFIG_SYN_PROASIC3E 0} + global CONFIG_SYN_PROASIC3L + if {$tmpvar_0 == "Actel-Proasic3L"} then {set CONFIG_SYN_PROASIC3L 1} else {set CONFIG_SYN_PROASIC3L 0} + global CONFIG_SYN_IGLOO + if {$tmpvar_0 == "Actel-IGLOO/p/L"} then {set CONFIG_SYN_IGLOO 1} else {set CONFIG_SYN_IGLOO 0} + global CONFIG_SYN_FUSION + if {$tmpvar_0 == "Actel-Fusion"} then {set CONFIG_SYN_FUSION 1} else {set CONFIG_SYN_FUSION 0} + global CONFIG_SYN_UT025CRH + if {$tmpvar_0 == "Aeroflex-UT025CRH"} then {set CONFIG_SYN_UT025CRH 1} else {set CONFIG_SYN_UT025CRH 0} + global CONFIG_SYN_UT130HBD + if {$tmpvar_0 == "Aeroflex-UT130HBD"} then {set CONFIG_SYN_UT130HBD 1} else {set CONFIG_SYN_UT130HBD 0} + global CONFIG_SYN_UT90NHBD + if {$tmpvar_0 == "Aeroflex-UT90NHBD"} then {set CONFIG_SYN_UT90NHBD 1} else {set CONFIG_SYN_UT90NHBD 0} + global CONFIG_SYN_ATC18 + if {$tmpvar_0 == "Atmel-ATC18"} then {set CONFIG_SYN_ATC18 1} else {set CONFIG_SYN_ATC18 0} + global CONFIG_SYN_ATC18RHA + if {$tmpvar_0 == "Atmel-ATC18RHA"} then {set CONFIG_SYN_ATC18RHA 1} else {set CONFIG_SYN_ATC18RHA 0} + global CONFIG_SYN_CMOS9SF + if {$tmpvar_0 == "IBM-CMOS9SF"} then {set CONFIG_SYN_CMOS9SF 1} else {set CONFIG_SYN_CMOS9SF 0} + global CONFIG_SYN_CUSTOM1 + if {$tmpvar_0 == "Custom1"} then {set CONFIG_SYN_CUSTOM1 1} else {set CONFIG_SYN_CUSTOM1 0} + global CONFIG_SYN_EASIC90 + if {$tmpvar_0 == "eASIC90"} then {set CONFIG_SYN_EASIC90 1} else {set CONFIG_SYN_EASIC90 0} + global CONFIG_SYN_EASIC45 + if {$tmpvar_0 == "eASIC45"} then {set CONFIG_SYN_EASIC45 1} else {set CONFIG_SYN_EASIC45 0} + global CONFIG_SYN_IHP25 + if {$tmpvar_0 == "IHP25"} then {set CONFIG_SYN_IHP25 1} else {set CONFIG_SYN_IHP25 0} + global CONFIG_SYN_IHP25RH + if {$tmpvar_0 == "IHP25RH"} then {set CONFIG_SYN_IHP25RH 1} else {set CONFIG_SYN_IHP25RH 0} + global CONFIG_SYN_LATTICE + if {$tmpvar_0 == "Lattice-EC/ECP/XP"} then {set CONFIG_SYN_LATTICE 1} else {set CONFIG_SYN_LATTICE 0} + global CONFIG_SYN_ECLIPSE + if {$tmpvar_0 == "Quicklogic-Eclipse"} then {set CONFIG_SYN_ECLIPSE 1} else {set CONFIG_SYN_ECLIPSE 0} + global CONFIG_SYN_PEREGRINE + if {$tmpvar_0 == "Peregrine"} then {set CONFIG_SYN_PEREGRINE 1} else {set CONFIG_SYN_PEREGRINE 0} + global CONFIG_SYN_RH_LIB18T + if {$tmpvar_0 == "RH-LIB18T"} then {set CONFIG_SYN_RH_LIB18T 1} else {set CONFIG_SYN_RH_LIB18T 0} + global CONFIG_SYN_RHUMC + if {$tmpvar_0 == "RH-UMC"} then {set CONFIG_SYN_RHUMC 1} else {set CONFIG_SYN_RHUMC 0} + global CONFIG_SYN_SAED32 + if {$tmpvar_0 == "SAED32"} then {set CONFIG_SYN_SAED32 1} else {set CONFIG_SYN_SAED32 0} + global CONFIG_SYN_DARE + if {$tmpvar_0 == "DARE"} then {set CONFIG_SYN_DARE 1} else {set CONFIG_SYN_DARE 0} + global CONFIG_SYN_SMIC13 + if {$tmpvar_0 == "SMIC130"} then {set CONFIG_SYN_SMIC13 1} else {set CONFIG_SYN_SMIC13 0} + global CONFIG_SYN_TM65GPLUS + if {$tmpvar_0 == "TM65Gplus"} then {set CONFIG_SYN_TM65GPLUS 1} else {set CONFIG_SYN_TM65GPLUS 0} + global CONFIG_SYN_TSMC90 + if {$tmpvar_0 == "TSMC90"} then {set CONFIG_SYN_TSMC90 1} else {set CONFIG_SYN_TSMC90 0} + global CONFIG_SYN_UMC + if {$tmpvar_0 == "UMC180"} then {set CONFIG_SYN_UMC 1} else {set CONFIG_SYN_UMC 0} + global CONFIG_SYN_ARTIX7 + if {$tmpvar_0 == "Xilinx-Artix7"} then {set CONFIG_SYN_ARTIX7 1} else {set CONFIG_SYN_ARTIX7 0} + global CONFIG_SYN_KINTEX7 + if {$tmpvar_0 == "Xilinx-Kintex7"} then {set CONFIG_SYN_KINTEX7 1} else {set CONFIG_SYN_KINTEX7 0} + global CONFIG_SYN_SPARTAN3 + if {$tmpvar_0 == "Xilinx-Spartan3"} then {set CONFIG_SYN_SPARTAN3 1} else {set CONFIG_SYN_SPARTAN3 0} + global CONFIG_SYN_SPARTAN3E + if {$tmpvar_0 == "Xilinx-Spartan3E"} then {set CONFIG_SYN_SPARTAN3E 1} else {set CONFIG_SYN_SPARTAN3E 0} + global CONFIG_SYN_SPARTAN6 + if {$tmpvar_0 == "Xilinx-Spartan6"} then {set CONFIG_SYN_SPARTAN6 1} else {set CONFIG_SYN_SPARTAN6 0} + global CONFIG_SYN_VIRTEXE + if {$tmpvar_0 == "Xilinx-VirtexE"} then {set CONFIG_SYN_VIRTEXE 1} else {set CONFIG_SYN_VIRTEXE 0} + global CONFIG_SYN_VIRTEX2 + if {$tmpvar_0 == "Xilinx-Virtex2"} then {set CONFIG_SYN_VIRTEX2 1} else {set CONFIG_SYN_VIRTEX2 0} + global CONFIG_SYN_VIRTEX4 + if {$tmpvar_0 == "Xilinx-Virtex4"} then {set CONFIG_SYN_VIRTEX4 1} else {set CONFIG_SYN_VIRTEX4 0} + global CONFIG_SYN_VIRTEX5 + if {$tmpvar_0 == "Xilinx-Virtex5"} then {set CONFIG_SYN_VIRTEX5 1} else {set CONFIG_SYN_VIRTEX5 0} + global CONFIG_SYN_VIRTEX6 + if {$tmpvar_0 == "Xilinx-Virtex6"} then {set CONFIG_SYN_VIRTEX6 1} else {set CONFIG_SYN_VIRTEX6 0} + global CONFIG_SYN_VIRTEX7 + if {$tmpvar_0 == "Xilinx-Virtex7"} then {set CONFIG_SYN_VIRTEX7 1} else {set CONFIG_SYN_VIRTEX7 0} + global CONFIG_SYN_ZYNQ7000 + if {$tmpvar_0 == "Xilinx-Zynq7000"} then {set CONFIG_SYN_ZYNQ7000 1} else {set CONFIG_SYN_ZYNQ7000 0} + global tmpvar_1 + global CONFIG_MEM_INFERRED + if {$tmpvar_1 == "Inferred"} then {set CONFIG_MEM_INFERRED 1} else {set CONFIG_MEM_INFERRED 0} + global CONFIG_MEM_UMC + if {$tmpvar_1 == "UMC18"} then {set CONFIG_MEM_UMC 1} else {set CONFIG_MEM_UMC 0} + global CONFIG_MEM_RHUMC + if {$tmpvar_1 == "RH-UMC"} then {set CONFIG_MEM_RHUMC 1} else {set CONFIG_MEM_RHUMC 0} + global CONFIG_MEM_SAED32 + if {$tmpvar_1 == "SAED32"} then {set CONFIG_MEM_SAED32 1} else {set CONFIG_MEM_SAED32 0} + global CONFIG_MEM_DARE + if {$tmpvar_1 == "DARE"} then {set CONFIG_MEM_DARE 1} else {set CONFIG_MEM_DARE 0} + global CONFIG_MEM_ARTISAN + if {$tmpvar_1 == "Artisan"} then {set CONFIG_MEM_ARTISAN 1} else {set CONFIG_MEM_ARTISAN 0} + global CONFIG_MEM_CUSTOM1 + if {$tmpvar_1 == "Custom1"} then {set CONFIG_MEM_CUSTOM1 1} else {set CONFIG_MEM_CUSTOM1 0} + global CONFIG_MEM_EASIC45 + if {$tmpvar_1 == "EASIC45"} then {set CONFIG_MEM_EASIC45 1} else {set CONFIG_MEM_EASIC45 0} + global CONFIG_MEM_VIRAGE + if {$tmpvar_1 == "Virage"} then {set CONFIG_MEM_VIRAGE 1} else {set CONFIG_MEM_VIRAGE 0} + global CONFIG_MEM_VIRAGE90 + if {$tmpvar_1 == "Virage-TSMC90"} then {set CONFIG_MEM_VIRAGE90 1} else {set CONFIG_MEM_VIRAGE90 0} + global CONFIG_SYN_INFER_RAM + if {($CONFIG_SYN_INFERRED != 1)} then { + set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM&15]} else {set CONFIG_SYN_INFER_RAM [expr $CONFIG_SYN_INFER_RAM|16]} + global CONFIG_SYN_INFER_PADS + if {($CONFIG_SYN_INFERRED != 1)} then { + set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS&15]} else {set CONFIG_SYN_INFER_PADS [expr $CONFIG_SYN_INFER_PADS|16]} +} + + +menu_option menu2 2 "Clock generation" +proc menu2 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 2} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 2]] + message $w.m -width 400 -aspect 300 -text \ + "Clock generation" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Clock generation" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu3 .menu3 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 2; menu1 .menu1 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + global tmpvar_2 + minimenu $w.config.f 2 0 "Clock generator " tmpvar_2 CONFIG_CLK_INFERRED + menu $w.config.f.x0.x.menu -tearoffcommand "menutitle \"Clock generator \"" + $w.config.f.x0.x.menu add radiobutton -label "Inferred" -variable tmpvar_2 -value "Inferred" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Actel-HCLKBUF" -variable tmpvar_2 -value "Actel-HCLKBUF" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Aeroflex-UT130HBD" -variable tmpvar_2 -value "Aeroflex-UT130HBD" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Altera-ALTPLL" -variable tmpvar_2 -value "Altera-ALTPLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Lattice-EXPLL" -variable tmpvar_2 -value "Lattice-EXPLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Proasic3-PLL" -variable tmpvar_2 -value "Proasic3-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Proasic3E-PLL" -variable tmpvar_2 -value "Proasic3E-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Proasic3L-PLL" -variable tmpvar_2 -value "Proasic3L-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Fusion-PLL" -variable tmpvar_2 -value "Fusion-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "RH-LIB18T-PLL" -variable tmpvar_2 -value "RH-LIB18T-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "RHUMC-PLL" -variable tmpvar_2 -value "RHUMC-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "DARE-PLL" -variable tmpvar_2 -value "DARE-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "SAED32-PLL" -variable tmpvar_2 -value "SAED32-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "EASIC45-PLL" -variable tmpvar_2 -value "EASIC45-PLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-PLLE2" -variable tmpvar_2 -value "Xilinx-PLLE2" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-CLKDLL" -variable tmpvar_2 -value "Xilinx-CLKDLL" -command "update_active" + $w.config.f.x0.x.menu add radiobutton -label "Xilinx-DCM" -variable tmpvar_2 -value "Xilinx-DCM" -command "update_active" + menusplit $w $w.config.f.x0.x.menu 17 + int $w.config.f 2 1 "Clock multiplication factor (allowed values are tech dependent)" CONFIG_CLK_MUL + int $w.config.f 2 2 "Clock division factor (allowed values are tech dependent)" CONFIG_CLK_DIV + int $w.config.f 2 3 "Outout division factor (1 - 32)" CONFIG_OCLK_DIV + int $w.config.f 2 4 "Outout division factor, 2nd clk (0 - 32, see help)" CONFIG_OCLKB_DIV + int $w.config.f 2 5 "Outout division factor, 3rd clk (0 - 32, see help)" CONFIG_OCLKC_DIV + bool $w.config.f 2 6 "Enable Xilinx CLKDLL for PCI clock" CONFIG_PCI_CLKDLL + bool $w.config.f 2 7 "Disable external feedback for SDRAM clock" CONFIG_CLK_NOFB + bool $w.config.f 2 8 "Use PCI clock as system clock" CONFIG_PCI_SYSCLK + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu2 {} { + global CONFIG_CLK_DCM + global CONFIG_CLK_ALTDLL + global CONFIG_CLK_LATDLL + global CONFIG_CLK_PRO3PLL + global CONFIG_CLK_PRO3EPLL + global CONFIG_CLK_PRO3LPLL + global CONFIG_CLK_CLKDLL + global CONFIG_CLK_LIB18T + global CONFIG_CLK_FUSPLL + global CONFIG_CLK_CLKPLLE2 + global CONFIG_CLK_MUL + if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1 || $CONFIG_CLK_FUSPLL == 1 || $CONFIG_CLK_CLKPLLE2 == 1)} then {.menu2.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x1.l configure -state normal; } else {.menu2.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x1.l configure -state disabled} + global CONFIG_CLK_DIV + if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1 || $CONFIG_CLK_FUSPLL == 1 || $CONFIG_CLK_CLKPLLE2 == 1)} then {.menu2.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x2.l configure -state normal; } else {.menu2.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x2.l configure -state disabled} + global CONFIG_OCLK_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {.menu2.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x3.l configure -state normal; } else {.menu2.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x3.l configure -state disabled} + global CONFIG_OCLKB_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {.menu2.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x4.l configure -state normal; } else {.menu2.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x4.l configure -state disabled} + global CONFIG_OCLKC_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {.menu2.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu2.config.f.x5.l configure -state normal; } else {.menu2.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu2.config.f.x5.l configure -state disabled} + global CONFIG_PCI_CLKDLL + if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { + configure_entry .menu2.config.f.x6 normal {n l y}} else {configure_entry .menu2.config.f.x6 disabled {y n l}} + global CONFIG_CLK_NOFB + if {($CONFIG_CLK_DCM == 1)} then { + configure_entry .menu2.config.f.x7 normal {n l y}} else {configure_entry .menu2.config.f.x7 disabled {y n l}} + global CONFIG_PCI_ENABLE + global CONFIG_PCI_SYSCLK + if {($CONFIG_PCI_ENABLE != 1)} then { + configure_entry .menu2.config.f.x8 normal {n l y}} else {configure_entry .menu2.config.f.x8 disabled {y n l}} +} + + +proc update_define_menu2 {} { + update_define_mainmenu + global CONFIG_MODULES + global tmpvar_2 + global CONFIG_CLK_INFERRED + if {$tmpvar_2 == "Inferred"} then {set CONFIG_CLK_INFERRED 1} else {set CONFIG_CLK_INFERRED 0} + global CONFIG_CLK_HCLKBUF + if {$tmpvar_2 == "Actel-HCLKBUF"} then {set CONFIG_CLK_HCLKBUF 1} else {set CONFIG_CLK_HCLKBUF 0} + global CONFIG_CLK_UT130HBD + if {$tmpvar_2 == "Aeroflex-UT130HBD"} then {set CONFIG_CLK_UT130HBD 1} else {set CONFIG_CLK_UT130HBD 0} + global CONFIG_CLK_ALTDLL + if {$tmpvar_2 == "Altera-ALTPLL"} then {set CONFIG_CLK_ALTDLL 1} else {set CONFIG_CLK_ALTDLL 0} + global CONFIG_CLK_LATDLL + if {$tmpvar_2 == "Lattice-EXPLL"} then {set CONFIG_CLK_LATDLL 1} else {set CONFIG_CLK_LATDLL 0} + global CONFIG_CLK_PRO3PLL + if {$tmpvar_2 == "Proasic3-PLL"} then {set CONFIG_CLK_PRO3PLL 1} else {set CONFIG_CLK_PRO3PLL 0} + global CONFIG_CLK_PRO3EPLL + if {$tmpvar_2 == "Proasic3E-PLL"} then {set CONFIG_CLK_PRO3EPLL 1} else {set CONFIG_CLK_PRO3EPLL 0} + global CONFIG_CLK_PRO3LPLL + if {$tmpvar_2 == "Proasic3L-PLL"} then {set CONFIG_CLK_PRO3LPLL 1} else {set CONFIG_CLK_PRO3LPLL 0} + global CONFIG_CLK_FUSPLL + if {$tmpvar_2 == "Fusion-PLL"} then {set CONFIG_CLK_FUSPLL 1} else {set CONFIG_CLK_FUSPLL 0} + global CONFIG_CLK_LIB18T + if {$tmpvar_2 == "RH-LIB18T-PLL"} then {set CONFIG_CLK_LIB18T 1} else {set CONFIG_CLK_LIB18T 0} + global CONFIG_CLK_RHUMC + if {$tmpvar_2 == "RHUMC-PLL"} then {set CONFIG_CLK_RHUMC 1} else {set CONFIG_CLK_RHUMC 0} + global CONFIG_CLK_DARE + if {$tmpvar_2 == "DARE-PLL"} then {set CONFIG_CLK_DARE 1} else {set CONFIG_CLK_DARE 0} + global CONFIG_CLK_SAED32 + if {$tmpvar_2 == "SAED32-PLL"} then {set CONFIG_CLK_SAED32 1} else {set CONFIG_CLK_SAED32 0} + global CONFIG_CLK_EASIC45 + if {$tmpvar_2 == "EASIC45-PLL"} then {set CONFIG_CLK_EASIC45 1} else {set CONFIG_CLK_EASIC45 0} + global CONFIG_CLK_CLKPLLE2 + if {$tmpvar_2 == "Xilinx-PLLE2"} then {set CONFIG_CLK_CLKPLLE2 1} else {set CONFIG_CLK_CLKPLLE2 0} + global CONFIG_CLK_CLKDLL + if {$tmpvar_2 == "Xilinx-CLKDLL"} then {set CONFIG_CLK_CLKDLL 1} else {set CONFIG_CLK_CLKDLL 0} + global CONFIG_CLK_DCM + if {$tmpvar_2 == "Xilinx-DCM"} then {set CONFIG_CLK_DCM 1} else {set CONFIG_CLK_DCM 0} + global CONFIG_CLK_MUL + if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1 || $CONFIG_CLK_FUSPLL == 1 || $CONFIG_CLK_CLKPLLE2 == 1)} then {validate_int CONFIG_CLK_MUL "$CONFIG_CLK_MUL" 2} + global CONFIG_CLK_DIV + if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1 || $CONFIG_CLK_FUSPLL == 1 || $CONFIG_CLK_CLKPLLE2 == 1)} then {validate_int CONFIG_CLK_DIV "$CONFIG_CLK_DIV" 2} + global CONFIG_OCLK_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {validate_int CONFIG_OCLK_DIV "$CONFIG_OCLK_DIV" 1} + global CONFIG_OCLKB_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {validate_int CONFIG_OCLKB_DIV "$CONFIG_OCLKB_DIV" 0} + global CONFIG_OCLKC_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {validate_int CONFIG_OCLKC_DIV "$CONFIG_OCLKC_DIV" 0} + global CONFIG_PCI_CLKDLL + if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then { + set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL&15]} else {set CONFIG_PCI_CLKDLL [expr $CONFIG_PCI_CLKDLL|16]} + global CONFIG_CLK_NOFB + if {($CONFIG_CLK_DCM == 1)} then { + set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB&15]} else {set CONFIG_CLK_NOFB [expr $CONFIG_CLK_NOFB|16]} + global CONFIG_PCI_ENABLE + global CONFIG_PCI_SYSCLK + if {($CONFIG_PCI_ENABLE != 1)} then { + set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK&15]} else {set CONFIG_PCI_SYSCLK [expr $CONFIG_PCI_SYSCLK|16]} +} + + +menu_option menu3 3 "Processor " +proc menu3 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 3} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 3]] + message $w.m -width 400 -aspect 300 -text \ + "Processor " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Processor " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; break" + set nextscript "catch {focus $oldFocus}; menu4 .menu4 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 3; menu2 .menu2 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 3 0 "Enable LEON3 SPARC V8 Processor" CONFIG_LEON3 + int $w.config.f 3 1 "Number of processors" CONFIG_PROC_NUM + global tmpvar_3 + minimenu $w.config.f 3 2 "Force values from example configuration (see help)" tmpvar_3 CONFIG_LEON3_MIN + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Force values from example configuration (see help)\"" + $w.config.f.x2.x.menu add radiobutton -label "Minimal-configuration" -variable tmpvar_3 -value "Minimal-configuration" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "General-purpose-cfg" -variable tmpvar_3 -value "General-purpose-cfg" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "High-Performance-cfg" -variable tmpvar_3 -value "High-Performance-cfg" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "Custom-configuration" -variable tmpvar_3 -value "Custom-configuration" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 4 + submenu $w.config.f 3 3 "Integer unit " 4 + submenu $w.config.f 3 4 "Floating-point unit" 5 + submenu $w.config.f 3 5 "Cache system" 6 + submenu $w.config.f 3 6 "MMU" 7 + submenu $w.config.f 3 7 "Debug Support Unit " 8 + submenu $w.config.f 3 8 "Fault-tolerance " 9 + submenu $w.config.f 3 9 "VHDL debug settings " 10 + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu3 {} { + global CONFIG_LEON3 + global CONFIG_PROC_NUM + if {($CONFIG_LEON3 == 1)} then {.menu3.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu3.config.f.x1.l configure -state normal; } else {.menu3.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu3.config.f.x1.l configure -state disabled} + if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x2 normal {x l}} else {configure_entry .menu3.config.f.x2 disabled {x l}} + global CONFIG_LEON3_CUSTOM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {configure_entry .menu3.config.f.x3 normal {m}} else {configure_entry .menu3.config.f.x3 disabled {m}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {configure_entry .menu3.config.f.x4 normal {m}} else {configure_entry .menu3.config.f.x4 disabled {m}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {configure_entry .menu3.config.f.x5 normal {m}} else {configure_entry .menu3.config.f.x5 disabled {m}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {configure_entry .menu3.config.f.x6 normal {m}} else {configure_entry .menu3.config.f.x6 disabled {m}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {configure_entry .menu3.config.f.x7 normal {m}} else {configure_entry .menu3.config.f.x7 disabled {m}} + if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x8 normal {m}} else {configure_entry .menu3.config.f.x8 disabled {m}} + if {($CONFIG_LEON3 == 1)} then {configure_entry .menu3.config.f.x9 normal {m}} else {configure_entry .menu3.config.f.x9 disabled {m}} +} + + +proc update_define_menu3 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_IU_NWINDOWS + global CONFIG_IU_V8MULDIV + global CONFIG_IU_BP + global CONFIG_IU_SVT + global CONFIG_NOTAG + global CONFIG_IU_LDELAY + global CONFIG_IU_WATCHPOINTS + global CONFIG_PWD + global CONFIG_IU_RSTADDR + global CONFIG_FPU_ENABLE + global CONFIG_ICACHE_ENABLE + global CONFIG_ICACHE_ASSO1 + global CONFIG_ICACHE_SZ2 + global CONFIG_ICACHE_LZ16 + global CONFIG_ICACHE_ALGORND + global CONFIG_ICACHE_LOCK + global CONFIG_DCACHE_ENABLE + global CONFIG_DCACHE_ASSO1 + global CONFIG_DCACHE_SZ2 + global CONFIG_DCACHE_LZ16 + global CONFIG_DCACHE_ALGORND + global CONFIG_DCACHE_LOCK + global CONFIG_DCACHE_SNOOP + global CONFIG_CACHE_FIXED + global CONFIG_MMU_ENABLE + global CONFIG_DSU_ENABLE + global CONFIG_IU_MUL_LATENCY_5 + global CONFIG_IU_MUL_MAC + global CONFIG_ICACHE_ASSO2 + global CONFIG_ICACHE_SZ4 + global CONFIG_ICACHE_LRAM + global CONFIG_DCACHE_ASSO2 + global CONFIG_DCACHE_SZ4 + global CONFIG_DCACHE_SNOOP_FAST + global CONFIG_DCACHE_SNOOP_SEPTAG + global CONFIG_DCACHE_LRAM + global CONFIG_MMU_SPLIT + global CONFIG_MMU_REPARRAY + global CONFIG_MMU_I8 + global CONFIG_MMU_D8 + global CONFIG_MMU_FASTWB + global CONFIG_MMU_PAGE_4K + global CONFIG_DSU_ITRACE + global CONFIG_DSU_ITRACESZ4 + global CONFIG_DSU_ATRACESZ4 + global CONFIG_IU_MUL_LATENCY_2 + global CONFIG_FPU_GRFPU + global CONFIG_FPU_GRFPU_INFMUL + global CONFIG_ICACHE_ALGOLRU + global CONFIG_DCACHE_ALGOLRU + global CONFIG_MMU_I16 + global CONFIG_MMU_D16 + global CONFIG_LEON3 + global CONFIG_PROC_NUM + if {($CONFIG_LEON3 == 1)} then {validate_int CONFIG_PROC_NUM "$CONFIG_PROC_NUM" 1} + global tmpvar_3 + global CONFIG_LEON3_MIN + if {$tmpvar_3 == "Minimal-configuration"} then {set CONFIG_LEON3_MIN 1} else {set CONFIG_LEON3_MIN 0} + global CONFIG_LEON3_GP + if {$tmpvar_3 == "General-purpose-cfg"} then {set CONFIG_LEON3_GP 1} else {set CONFIG_LEON3_GP 0} + global CONFIG_LEON3_HP + if {$tmpvar_3 == "High-Performance-cfg"} then {set CONFIG_LEON3_HP 1} else {set CONFIG_LEON3_HP 0} + global CONFIG_LEON3_CUSTOM + if {$tmpvar_3 == "Custom-configuration"} then {set CONFIG_LEON3_CUSTOM 1} else {set CONFIG_LEON3_CUSTOM 0} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {set CONFIG_IU_NWINDOWS 8 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_IU_V8MULDIV $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_IU_BP $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_IU_SVT $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_NOTAG $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {set CONFIG_IU_LDELAY 1 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {set CONFIG_IU_WATCHPOINTS 0 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_PWD $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {set CONFIG_IU_RSTADDR 00000 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_FPU_ENABLE $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ASSO1 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_SZ2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_LZ16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ALGORND $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_ICACHE_LOCK $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ASSO1 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SZ2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_LZ16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ALGORND $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_DCACHE_LOCK $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_DCACHE_SNOOP $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {set CONFIG_CACHE_FIXED 0 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_MMU_ENABLE $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then { global CONSTANT_N +set CONFIG_DSU_ENABLE $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {set CONFIG_IU_NWINDOWS 8 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_IU_V8MULDIV $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_IU_MUL_LATENCY_5 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_IU_MUL_MAC $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_IU_BP $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_IU_SVT $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_NOTAG $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {set CONFIG_IU_LDELAY 1 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {set CONFIG_IU_WATCHPOINTS 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_PWD $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {set CONFIG_IU_RSTADDR 00000 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_FPU_ENABLE $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ASSO2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_SZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_LZ16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ALGORND $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_ICACHE_LOCK $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_ICACHE_LRAM $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ASSO2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_LZ16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ALGORND $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_DCACHE_LOCK $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SNOOP $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SNOOP_FAST $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SNOOP_SEPTAG $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {set CONFIG_CACHE_FIXED 0 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_N +set CONFIG_DCACHE_LRAM $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_SPLIT $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_REPARRAY $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_I8 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_D8 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_FASTWB $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_PAGE_4K $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ITRACE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ITRACESZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ATRACESZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {set CONFIG_IU_NWINDOWS 8 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_IU_V8MULDIV $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_IU_MUL_LATENCY_2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_N +set CONFIG_IU_MUL_MAC $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_IU_BP $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_IU_SVT $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_N +set CONFIG_NOTAG $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {set CONFIG_IU_LDELAY 1 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {set CONFIG_IU_WATCHPOINTS 4 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_PWD $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {set CONFIG_IU_RSTADDR 00000 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_FPU_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_FPU_GRFPU $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_FPU_GRFPU_INFMUL $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ASSO2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_SZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_LZ16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_ICACHE_ALGOLRU $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_N +set CONFIG_ICACHE_LOCK $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_N +set CONFIG_ICACHE_LRAM $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ASSO2 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_LZ16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_ALGOLRU $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_N +set CONFIG_DCACHE_LOCK $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SNOOP $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SNOOP_FAST $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DCACHE_SNOOP_SEPTAG $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {set CONFIG_CACHE_FIXED 0 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_N +set CONFIG_DCACHE_LRAM $CONSTANT_N } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_SPLIT $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_REPARRAY $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_I16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_D16 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_FASTWB $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_MMU_PAGE_4K $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ENABLE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ITRACE $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ITRACESZ4 $CONSTANT_Y } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then { global CONSTANT_Y +set CONFIG_DSU_ATRACESZ4 $CONSTANT_Y } +} + + +proc menu4 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 4} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 4]] + message $w.m -width 400 -aspect 300 -text \ + "Integer unit " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Integer unit " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu5 .menu5 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 4; menu3 .menu3 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + int $w.config.f 4 0 "SPARC register windows" CONFIG_IU_NWINDOWS + bool $w.config.f 4 1 "SPARC V8 MUL/DIV instructions" CONFIG_IU_V8MULDIV + global tmpvar_4 + minimenu $w.config.f 4 2 "Hardware multiplier latency" tmpvar_4 CONFIG_IU_MUL_LATENCY_2 + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Hardware multiplier latency\"" + $w.config.f.x2.x.menu add radiobutton -label "2-cycles" -variable tmpvar_4 -value "2-cycles" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "4-cycles" -variable tmpvar_4 -value "4-cycles" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "5-cycles" -variable tmpvar_4 -value "5-cycles" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 3 + bool $w.config.f 4 3 "SPARC V8e SMAC/UMAC instructions " CONFIG_IU_MUL_MAC + global tmpvar_5 + minimenu $w.config.f 4 4 "Multipler structure " tmpvar_5 CONFIG_IU_MUL_INFERRED + menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Multipler structure \"" + $w.config.f.x4.x.menu add radiobutton -label "Inferred" -variable tmpvar_5 -value "Inferred" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "NTNU_Modgen" -variable tmpvar_5 -value "NTNU_Modgen" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "TechSpec" -variable tmpvar_5 -value "TechSpec" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "Designware" -variable tmpvar_5 -value "Designware" -command "update_active" + menusplit $w $w.config.f.x4.x.menu 4 + bool $w.config.f 4 5 "Branch prediction " CONFIG_IU_BP + bool $w.config.f 4 6 "Single-vector trapping" CONFIG_IU_SVT + bool $w.config.f 4 7 "Disable tagged ADD/SUB and CASA" CONFIG_NOTAG + int $w.config.f 4 8 "Load delay" CONFIG_IU_LDELAY + int $w.config.f 4 9 "Hardware watchpoints" CONFIG_IU_WATCHPOINTS + bool $w.config.f 4 10 "Enable power-down mode " CONFIG_PWD + hex $w.config.f 4 11 " Reset start address (addr\[31:12\]) " CONFIG_IU_RSTADDR + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu4 {} { + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_IU_NWINDOWS + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {.menu4.config.f.x0.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x0.l configure -state normal; } else {.menu4.config.f.x0.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x0.l configure -state disabled} + global CONFIG_IU_V8MULDIV + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu4.config.f.x1 normal {n l y}} else {configure_entry .menu4.config.f.x1 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x2 normal {x l}} else {configure_entry .menu4.config.f.x2 disabled {x l}} + global CONFIG_IU_MUL_LATENCY_4 + global CONFIG_IU_MUL_LATENCY_5 + global CONFIG_IU_MUL_MAC + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { + configure_entry .menu4.config.f.x3 normal {n l y}} else {configure_entry .menu4.config.f.x3 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1)} then {configure_entry .menu4.config.f.x4 normal {x l}} else {configure_entry .menu4.config.f.x4 disabled {x l}} + global CONFIG_IU_BP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu4.config.f.x5 normal {n l y}} else {configure_entry .menu4.config.f.x5 disabled {y n l}} + global CONFIG_IU_SVT + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu4.config.f.x6 normal {n l y}} else {configure_entry .menu4.config.f.x6 disabled {y n l}} + global CONFIG_NOTAG + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu4.config.f.x7 normal {n l y}} else {configure_entry .menu4.config.f.x7 disabled {y n l}} + global CONFIG_IU_LDELAY + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {.menu4.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x8.l configure -state normal; } else {.menu4.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x8.l configure -state disabled} + global CONFIG_IU_WATCHPOINTS + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {.menu4.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x9.l configure -state normal; } else {.menu4.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x9.l configure -state disabled} + global CONFIG_PWD + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu4.config.f.x10 normal {n l y}} else {configure_entry .menu4.config.f.x10 disabled {y n l}} + global CONFIG_IU_RSTADDR + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {.menu4.config.f.x11.x configure -state normal -foreground [ cget .ref -foreground ]; .menu4.config.f.x11.l configure -state normal; } else {.menu4.config.f.x11.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu4.config.f.x11.l configure -state disabled} +} + + +proc update_define_menu4 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_IU_NWINDOWS + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {validate_int CONFIG_IU_NWINDOWS "$CONFIG_IU_NWINDOWS" 8} + global CONFIG_IU_V8MULDIV + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV&15]} else {set CONFIG_IU_V8MULDIV [expr $CONFIG_IU_V8MULDIV|16]} + global tmpvar_4 + global CONFIG_IU_MUL_LATENCY_2 + if {$tmpvar_4 == "2-cycles"} then {set CONFIG_IU_MUL_LATENCY_2 1} else {set CONFIG_IU_MUL_LATENCY_2 0} + global CONFIG_IU_MUL_LATENCY_4 + if {$tmpvar_4 == "4-cycles"} then {set CONFIG_IU_MUL_LATENCY_4 1} else {set CONFIG_IU_MUL_LATENCY_4 0} + global CONFIG_IU_MUL_LATENCY_5 + if {$tmpvar_4 == "5-cycles"} then {set CONFIG_IU_MUL_LATENCY_5 1} else {set CONFIG_IU_MUL_LATENCY_5 0} + global CONFIG_IU_MUL_MAC + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then { + set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC&15]} else {set CONFIG_IU_MUL_MAC [expr $CONFIG_IU_MUL_MAC|16]} + global tmpvar_5 + global CONFIG_IU_MUL_INFERRED + if {$tmpvar_5 == "Inferred"} then {set CONFIG_IU_MUL_INFERRED 1} else {set CONFIG_IU_MUL_INFERRED 0} + global CONFIG_IU_MUL_MODGEN + if {$tmpvar_5 == "NTNU_Modgen"} then {set CONFIG_IU_MUL_MODGEN 1} else {set CONFIG_IU_MUL_MODGEN 0} + global CONFIG_IU_MUL_TECHSPEC + if {$tmpvar_5 == "TechSpec"} then {set CONFIG_IU_MUL_TECHSPEC 1} else {set CONFIG_IU_MUL_TECHSPEC 0} + global CONFIG_IU_MUL_DW + if {$tmpvar_5 == "Designware"} then {set CONFIG_IU_MUL_DW 1} else {set CONFIG_IU_MUL_DW 0} + global CONFIG_IU_BP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_IU_BP [expr $CONFIG_IU_BP&15]} else {set CONFIG_IU_BP [expr $CONFIG_IU_BP|16]} + global CONFIG_IU_SVT + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_IU_SVT [expr $CONFIG_IU_SVT&15]} else {set CONFIG_IU_SVT [expr $CONFIG_IU_SVT|16]} + global CONFIG_NOTAG + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_NOTAG [expr $CONFIG_NOTAG&15]} else {set CONFIG_NOTAG [expr $CONFIG_NOTAG|16]} + global CONFIG_IU_LDELAY + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {validate_int CONFIG_IU_LDELAY "$CONFIG_IU_LDELAY" 1} + global CONFIG_IU_WATCHPOINTS + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {validate_int CONFIG_IU_WATCHPOINTS "$CONFIG_IU_WATCHPOINTS" 0} + global CONFIG_PWD + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_PWD [expr $CONFIG_PWD&15]} else {set CONFIG_PWD [expr $CONFIG_PWD|16]} + global CONFIG_IU_RSTADDR + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {validate_hex CONFIG_IU_RSTADDR "$CONFIG_IU_RSTADDR" 00000} +} + + +proc menu5 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 5} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 5]] + message $w.m -width 400 -aspect 300 -text \ + "Floating-point unit" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Floating-point unit" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu6 .menu6 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 5; menu4 .menu4 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 5 0 "Enable FPU " CONFIG_FPU_ENABLE + global tmpvar_6 + minimenu $w.config.f 5 1 "FPU core" tmpvar_6 CONFIG_FPU_GRFPU + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"FPU core\"" + $w.config.f.x1.x.menu add radiobutton -label "GRFPU" -variable tmpvar_6 -value "GRFPU" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "GRFPU-LITE" -variable tmpvar_6 -value "GRFPU-LITE" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "Meiko" -variable tmpvar_6 -value "Meiko" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 3 + global tmpvar_7 + minimenu $w.config.f 5 2 "GRFPU multiplier" tmpvar_7 CONFIG_FPU_GRFPU_INFMUL + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"GRFPU multiplier\"" + $w.config.f.x2.x.menu add radiobutton -label "Inferred" -variable tmpvar_7 -value "Inferred" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "DW" -variable tmpvar_7 -value "DW" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "ModGen" -variable tmpvar_7 -value "ModGen" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "TechSpec" -variable tmpvar_7 -value "TechSpec" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 4 + bool $w.config.f 5 3 "Shared GRFPU " CONFIG_FPU_GRFPU_SH + global tmpvar_8 + minimenu $w.config.f 5 4 "GRFPU-LITE controller" tmpvar_8 CONFIG_FPU_GRFPC0 + menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"GRFPU-LITE controller\"" + $w.config.f.x4.x.menu add radiobutton -label "Simple" -variable tmpvar_8 -value "Simple" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "Data-forwarding" -variable tmpvar_8 -value "Data-forwarding" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "Non-blocking" -variable tmpvar_8 -value "Non-blocking" -command "update_active" + menusplit $w $w.config.f.x4.x.menu 3 + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu5 {} { + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_FPU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu5.config.f.x0 normal {n l y}} else {configure_entry .menu5.config.f.x0 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu5.config.f.x1 normal {x l}} else {configure_entry .menu5.config.f.x1 disabled {x l}} + global CONFIG_FPU_GRFPU + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then {configure_entry .menu5.config.f.x2 normal {x l}} else {configure_entry .menu5.config.f.x2 disabled {x l}} + global CONFIG_HAS_SHARED_GRFPU + global CONFIG_FPU_GRFPU_SH + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_HAS_SHARED_GRFPU == 1 && $CONFIG_FPU_GRFPU == 1)} then { + configure_entry .menu5.config.f.x3 normal {n l y}} else {configure_entry .menu5.config.f.x3 disabled {y n l}} + global CONFIG_FPU_GRFPULITE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then {configure_entry .menu5.config.f.x4 normal {x l}} else {configure_entry .menu5.config.f.x4 disabled {x l}} +} + + +proc update_define_menu5 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_FPU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE&15]} else {set CONFIG_FPU_ENABLE [expr $CONFIG_FPU_ENABLE|16]} + global tmpvar_6 + global CONFIG_FPU_GRFPU + if {$tmpvar_6 == "GRFPU"} then {set CONFIG_FPU_GRFPU 1} else {set CONFIG_FPU_GRFPU 0} + global CONFIG_FPU_GRFPULITE + if {$tmpvar_6 == "GRFPU-LITE"} then {set CONFIG_FPU_GRFPULITE 1} else {set CONFIG_FPU_GRFPULITE 0} + global CONFIG_FPU_MEIKO + if {$tmpvar_6 == "Meiko"} then {set CONFIG_FPU_MEIKO 1} else {set CONFIG_FPU_MEIKO 0} + global tmpvar_7 + global CONFIG_FPU_GRFPU_INFMUL + if {$tmpvar_7 == "Inferred"} then {set CONFIG_FPU_GRFPU_INFMUL 1} else {set CONFIG_FPU_GRFPU_INFMUL 0} + global CONFIG_FPU_GRFPU_DWMUL + if {$tmpvar_7 == "DW"} then {set CONFIG_FPU_GRFPU_DWMUL 1} else {set CONFIG_FPU_GRFPU_DWMUL 0} + global CONFIG_FPU_GRFPU_MODGEN + if {$tmpvar_7 == "ModGen"} then {set CONFIG_FPU_GRFPU_MODGEN 1} else {set CONFIG_FPU_GRFPU_MODGEN 0} + global CONFIG_FPU_GRFPU_TECHSPEC + if {$tmpvar_7 == "TechSpec"} then {set CONFIG_FPU_GRFPU_TECHSPEC 1} else {set CONFIG_FPU_GRFPU_TECHSPEC 0} + global CONFIG_HAS_SHARED_GRFPU + global CONFIG_FPU_GRFPU_SH + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_HAS_SHARED_GRFPU == 1 && $CONFIG_FPU_GRFPU == 1)} then { + set CONFIG_FPU_GRFPU_SH [expr $CONFIG_FPU_GRFPU_SH&15]} else {set CONFIG_FPU_GRFPU_SH [expr $CONFIG_FPU_GRFPU_SH|16]} + global tmpvar_8 + global CONFIG_FPU_GRFPC0 + if {$tmpvar_8 == "Simple"} then {set CONFIG_FPU_GRFPC0 1} else {set CONFIG_FPU_GRFPC0 0} + global CONFIG_FPU_GRFPC1 + if {$tmpvar_8 == "Data-forwarding"} then {set CONFIG_FPU_GRFPC1 1} else {set CONFIG_FPU_GRFPC1 0} + global CONFIG_FPU_GRFPC2 + if {$tmpvar_8 == "Non-blocking"} then {set CONFIG_FPU_GRFPC2 1} else {set CONFIG_FPU_GRFPC2 0} +} + + +proc menu6 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 6} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 6]] + message $w.m -width 400 -aspect 300 -text \ + "Cache system" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Cache system" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu7 .menu7 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 6; menu5 .menu5 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 6 0 "Enable instruction cache " CONFIG_ICACHE_ENABLE + global tmpvar_9 + minimenu $w.config.f 6 1 "Associativity (sets) " tmpvar_9 CONFIG_ICACHE_ASSO1 + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"Associativity (sets) \"" + $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_9 -value "1" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_9 -value "2" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "3" -variable tmpvar_9 -value "3" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_9 -value "4" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 4 + global tmpvar_10 + minimenu $w.config.f 6 2 "Way size (kbytes/way)" tmpvar_10 CONFIG_ICACHE_SZ1 + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Way size (kbytes/way)\"" + $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_10 -value "1" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_10 -value "2" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_10 -value "4" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_10 -value "8" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_10 -value "16" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_10 -value "32" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_10 -value "64" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "128" -variable tmpvar_10 -value "128" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "256" -variable tmpvar_10 -value "256" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 9 + global tmpvar_11 + minimenu $w.config.f 6 3 "Line size (bytes/line)" tmpvar_11 CONFIG_ICACHE_LZ16 + menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" + $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_11 -value "16" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_11 -value "32" -command "update_active" + menusplit $w $w.config.f.x3.x.menu 2 + global tmpvar_12 + minimenu $w.config.f 6 4 "Replacement alorithm" tmpvar_12 CONFIG_ICACHE_ALGORND + menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" + $w.config.f.x4.x.menu add radiobutton -label "Random" -variable tmpvar_12 -value "Random" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "Direct" -variable tmpvar_12 -value "Direct" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "LRR" -variable tmpvar_12 -value "LRR" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "LRU" -variable tmpvar_12 -value "LRU" -command "update_active" + menusplit $w $w.config.f.x4.x.menu 4 + bool $w.config.f 6 5 "Cache locking " CONFIG_ICACHE_LOCK + bool $w.config.f 6 6 "Enable local instruction RAM " CONFIG_ICACHE_LRAM + global tmpvar_13 + minimenu $w.config.f 6 7 "Local data RAM size (kbytes)" tmpvar_13 CONFIG_ICACHE_LRAM_SZ1 + menu $w.config.f.x7.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x7.x.menu add radiobutton -label "1" -variable tmpvar_13 -value "1" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "2" -variable tmpvar_13 -value "2" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "4" -variable tmpvar_13 -value "4" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "8" -variable tmpvar_13 -value "8" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "16" -variable tmpvar_13 -value "16" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "32" -variable tmpvar_13 -value "32" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "64" -variable tmpvar_13 -value "64" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "128" -variable tmpvar_13 -value "128" -command "update_active" + $w.config.f.x7.x.menu add radiobutton -label "256" -variable tmpvar_13 -value "256" -command "update_active" + menusplit $w $w.config.f.x7.x.menu 9 + hex $w.config.f 6 8 " Local instruction RAM start address (8 MSB) " CONFIG_ICACHE_LRSTART + bool $w.config.f 6 9 "Enable data cache " CONFIG_DCACHE_ENABLE + global tmpvar_14 + minimenu $w.config.f 6 10 "Associativity (sets)" tmpvar_14 CONFIG_DCACHE_ASSO1 + menu $w.config.f.x10.x.menu -tearoffcommand "menutitle \"Associativity (sets)\"" + $w.config.f.x10.x.menu add radiobutton -label "1" -variable tmpvar_14 -value "1" -command "update_active" + $w.config.f.x10.x.menu add radiobutton -label "2" -variable tmpvar_14 -value "2" -command "update_active" + $w.config.f.x10.x.menu add radiobutton -label "3" -variable tmpvar_14 -value "3" -command "update_active" + $w.config.f.x10.x.menu add radiobutton -label "4" -variable tmpvar_14 -value "4" -command "update_active" + menusplit $w $w.config.f.x10.x.menu 4 + global tmpvar_15 + minimenu $w.config.f 6 11 "Set size (kbytes/set)" tmpvar_15 CONFIG_DCACHE_SZ1 + menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Set size (kbytes/set)\"" + $w.config.f.x11.x.menu add radiobutton -label "1" -variable tmpvar_15 -value "1" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "2" -variable tmpvar_15 -value "2" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "4" -variable tmpvar_15 -value "4" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "8" -variable tmpvar_15 -value "8" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "16" -variable tmpvar_15 -value "16" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "32" -variable tmpvar_15 -value "32" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "64" -variable tmpvar_15 -value "64" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "128" -variable tmpvar_15 -value "128" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "256" -variable tmpvar_15 -value "256" -command "update_active" + menusplit $w $w.config.f.x11.x.menu 9 + global tmpvar_16 + minimenu $w.config.f 6 12 "Line size (bytes/line)" tmpvar_16 CONFIG_DCACHE_LZ16 + menu $w.config.f.x12.x.menu -tearoffcommand "menutitle \"Line size (bytes/line)\"" + $w.config.f.x12.x.menu add radiobutton -label "16" -variable tmpvar_16 -value "16" -command "update_active" + $w.config.f.x12.x.menu add radiobutton -label "32" -variable tmpvar_16 -value "32" -command "update_active" + menusplit $w $w.config.f.x12.x.menu 2 + global tmpvar_17 + minimenu $w.config.f 6 13 "Replacement alorithm" tmpvar_17 CONFIG_DCACHE_ALGORND + menu $w.config.f.x13.x.menu -tearoffcommand "menutitle \"Replacement alorithm\"" + $w.config.f.x13.x.menu add radiobutton -label "Random" -variable tmpvar_17 -value "Random" -command "update_active" + $w.config.f.x13.x.menu add radiobutton -label "Direct" -variable tmpvar_17 -value "Direct" -command "update_active" + $w.config.f.x13.x.menu add radiobutton -label "LRR" -variable tmpvar_17 -value "LRR" -command "update_active" + $w.config.f.x13.x.menu add radiobutton -label "LRU" -variable tmpvar_17 -value "LRU" -command "update_active" + menusplit $w $w.config.f.x13.x.menu 4 + bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK + bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM + global tmpvar_18 + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu6 {} { + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_ICACHE_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu6.config.f.x0 normal {n l y}} else {configure_entry .menu6.config.f.x0 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x1 normal {x l}} else {configure_entry .menu6.config.f.x1 disabled {x l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x2 normal {x l}} else {configure_entry .menu6.config.f.x2 disabled {x l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x3 normal {x l}} else {configure_entry .menu6.config.f.x3 disabled {x l}} + global CONFIG_ICACHE_ASSO1 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x4 normal {x l}} else {configure_entry .menu6.config.f.x4 disabled {x l}} + global CONFIG_ICACHE_LOCK + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { + configure_entry .menu6.config.f.x5 normal {n l y}} else {configure_entry .menu6.config.f.x5 disabled {y n l}} + global CONFIG_MMU_ENABLE + global CONFIG_ICACHE_LRAM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { + configure_entry .menu6.config.f.x6 normal {n l y}} else {configure_entry .menu6.config.f.x6 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x7 normal {x l}} else {configure_entry .menu6.config.f.x7 disabled {x l}} + global CONFIG_ICACHE_LRSTART + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {.menu6.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x8.l configure -state normal; } else {.menu6.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x8.l configure -state disabled} + global CONFIG_DCACHE_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu6.config.f.x9 normal {n l y}} else {configure_entry .menu6.config.f.x9 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x10 normal {x l}} else {configure_entry .menu6.config.f.x10 disabled {x l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x11 normal {x l}} else {configure_entry .menu6.config.f.x11 disabled {x l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {configure_entry .menu6.config.f.x12 normal {x l}} else {configure_entry .menu6.config.f.x12 disabled {x l}} + global CONFIG_DCACHE_ASSO1 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {configure_entry .menu6.config.f.x13 normal {x l}} else {configure_entry .menu6.config.f.x13 disabled {x l}} + global CONFIG_DCACHE_LOCK + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { + configure_entry .menu6.config.f.x14 normal {n l y}} else {configure_entry .menu6.config.f.x14 disabled {y n l}} + global CONFIG_DCACHE_SNOOP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { + configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} + global CONFIG_DCACHE_SNOOP_SEPTAG + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} + global CONFIG_CACHE_FIXED + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} + global CONFIG_DCACHE_LRAM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} + global CONFIG_DCACHE_LRSTART + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} +} + + +proc update_define_menu6 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_ICACHE_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE&15]} else {set CONFIG_ICACHE_ENABLE [expr $CONFIG_ICACHE_ENABLE|16]} + global tmpvar_9 + global CONFIG_ICACHE_ASSO1 + if {$tmpvar_9 == "1"} then {set CONFIG_ICACHE_ASSO1 1} else {set CONFIG_ICACHE_ASSO1 0} + global CONFIG_ICACHE_ASSO2 + if {$tmpvar_9 == "2"} then {set CONFIG_ICACHE_ASSO2 1} else {set CONFIG_ICACHE_ASSO2 0} + global CONFIG_ICACHE_ASSO3 + if {$tmpvar_9 == "3"} then {set CONFIG_ICACHE_ASSO3 1} else {set CONFIG_ICACHE_ASSO3 0} + global CONFIG_ICACHE_ASSO4 + if {$tmpvar_9 == "4"} then {set CONFIG_ICACHE_ASSO4 1} else {set CONFIG_ICACHE_ASSO4 0} + global tmpvar_10 + global CONFIG_ICACHE_SZ1 + if {$tmpvar_10 == "1"} then {set CONFIG_ICACHE_SZ1 1} else {set CONFIG_ICACHE_SZ1 0} + global CONFIG_ICACHE_SZ2 + if {$tmpvar_10 == "2"} then {set CONFIG_ICACHE_SZ2 1} else {set CONFIG_ICACHE_SZ2 0} + global CONFIG_ICACHE_SZ4 + if {$tmpvar_10 == "4"} then {set CONFIG_ICACHE_SZ4 1} else {set CONFIG_ICACHE_SZ4 0} + global CONFIG_ICACHE_SZ8 + if {$tmpvar_10 == "8"} then {set CONFIG_ICACHE_SZ8 1} else {set CONFIG_ICACHE_SZ8 0} + global CONFIG_ICACHE_SZ16 + if {$tmpvar_10 == "16"} then {set CONFIG_ICACHE_SZ16 1} else {set CONFIG_ICACHE_SZ16 0} + global CONFIG_ICACHE_SZ32 + if {$tmpvar_10 == "32"} then {set CONFIG_ICACHE_SZ32 1} else {set CONFIG_ICACHE_SZ32 0} + global CONFIG_ICACHE_SZ64 + if {$tmpvar_10 == "64"} then {set CONFIG_ICACHE_SZ64 1} else {set CONFIG_ICACHE_SZ64 0} + global CONFIG_ICACHE_SZ128 + if {$tmpvar_10 == "128"} then {set CONFIG_ICACHE_SZ128 1} else {set CONFIG_ICACHE_SZ128 0} + global CONFIG_ICACHE_SZ256 + if {$tmpvar_10 == "256"} then {set CONFIG_ICACHE_SZ256 1} else {set CONFIG_ICACHE_SZ256 0} + global tmpvar_11 + global CONFIG_ICACHE_LZ16 + if {$tmpvar_11 == "16"} then {set CONFIG_ICACHE_LZ16 1} else {set CONFIG_ICACHE_LZ16 0} + global CONFIG_ICACHE_LZ32 + if {$tmpvar_11 == "32"} then {set CONFIG_ICACHE_LZ32 1} else {set CONFIG_ICACHE_LZ32 0} + global tmpvar_12 + global CONFIG_ICACHE_ALGORND + if {$tmpvar_12 == "Random"} then {set CONFIG_ICACHE_ALGORND 1} else {set CONFIG_ICACHE_ALGORND 0} + global CONFIG_ICACHE_ALGODIR + if {$tmpvar_12 == "Direct"} then {set CONFIG_ICACHE_ALGODIR 1} else {set CONFIG_ICACHE_ALGODIR 0} + global CONFIG_ICACHE_ALGOLRR + if {$tmpvar_12 == "LRR"} then {set CONFIG_ICACHE_ALGOLRR 1} else {set CONFIG_ICACHE_ALGOLRR 0} + global CONFIG_ICACHE_ALGOLRU + if {$tmpvar_12 == "LRU"} then {set CONFIG_ICACHE_ALGOLRU 1} else {set CONFIG_ICACHE_ALGOLRU 0} + global CONFIG_ICACHE_LOCK + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { + set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK&15]} else {set CONFIG_ICACHE_LOCK [expr $CONFIG_ICACHE_LOCK|16]} + global CONFIG_MMU_ENABLE + global CONFIG_ICACHE_LRAM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { + set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM&15]} else {set CONFIG_ICACHE_LRAM [expr $CONFIG_ICACHE_LRAM|16]} + global tmpvar_13 + global CONFIG_ICACHE_LRAM_SZ1 + if {$tmpvar_13 == "1"} then {set CONFIG_ICACHE_LRAM_SZ1 1} else {set CONFIG_ICACHE_LRAM_SZ1 0} + global CONFIG_ICACHE_LRAM_SZ2 + if {$tmpvar_13 == "2"} then {set CONFIG_ICACHE_LRAM_SZ2 1} else {set CONFIG_ICACHE_LRAM_SZ2 0} + global CONFIG_ICACHE_LRAM_SZ4 + if {$tmpvar_13 == "4"} then {set CONFIG_ICACHE_LRAM_SZ4 1} else {set CONFIG_ICACHE_LRAM_SZ4 0} + global CONFIG_ICACHE_LRAM_SZ8 + if {$tmpvar_13 == "8"} then {set CONFIG_ICACHE_LRAM_SZ8 1} else {set CONFIG_ICACHE_LRAM_SZ8 0} + global CONFIG_ICACHE_LRAM_SZ16 + if {$tmpvar_13 == "16"} then {set CONFIG_ICACHE_LRAM_SZ16 1} else {set CONFIG_ICACHE_LRAM_SZ16 0} + global CONFIG_ICACHE_LRAM_SZ32 + if {$tmpvar_13 == "32"} then {set CONFIG_ICACHE_LRAM_SZ32 1} else {set CONFIG_ICACHE_LRAM_SZ32 0} + global CONFIG_ICACHE_LRAM_SZ64 + if {$tmpvar_13 == "64"} then {set CONFIG_ICACHE_LRAM_SZ64 1} else {set CONFIG_ICACHE_LRAM_SZ64 0} + global CONFIG_ICACHE_LRAM_SZ128 + if {$tmpvar_13 == "128"} then {set CONFIG_ICACHE_LRAM_SZ128 1} else {set CONFIG_ICACHE_LRAM_SZ128 0} + global CONFIG_ICACHE_LRAM_SZ256 + if {$tmpvar_13 == "256"} then {set CONFIG_ICACHE_LRAM_SZ256 1} else {set CONFIG_ICACHE_LRAM_SZ256 0} + global CONFIG_ICACHE_LRSTART + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {validate_hex CONFIG_ICACHE_LRSTART "$CONFIG_ICACHE_LRSTART" 8e} + global CONFIG_DCACHE_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE&15]} else {set CONFIG_DCACHE_ENABLE [expr $CONFIG_DCACHE_ENABLE|16]} + global tmpvar_14 + global CONFIG_DCACHE_ASSO1 + if {$tmpvar_14 == "1"} then {set CONFIG_DCACHE_ASSO1 1} else {set CONFIG_DCACHE_ASSO1 0} + global CONFIG_DCACHE_ASSO2 + if {$tmpvar_14 == "2"} then {set CONFIG_DCACHE_ASSO2 1} else {set CONFIG_DCACHE_ASSO2 0} + global CONFIG_DCACHE_ASSO3 + if {$tmpvar_14 == "3"} then {set CONFIG_DCACHE_ASSO3 1} else {set CONFIG_DCACHE_ASSO3 0} + global CONFIG_DCACHE_ASSO4 + if {$tmpvar_14 == "4"} then {set CONFIG_DCACHE_ASSO4 1} else {set CONFIG_DCACHE_ASSO4 0} + global tmpvar_15 + global CONFIG_DCACHE_SZ1 + if {$tmpvar_15 == "1"} then {set CONFIG_DCACHE_SZ1 1} else {set CONFIG_DCACHE_SZ1 0} + global CONFIG_DCACHE_SZ2 + if {$tmpvar_15 == "2"} then {set CONFIG_DCACHE_SZ2 1} else {set CONFIG_DCACHE_SZ2 0} + global CONFIG_DCACHE_SZ4 + if {$tmpvar_15 == "4"} then {set CONFIG_DCACHE_SZ4 1} else {set CONFIG_DCACHE_SZ4 0} + global CONFIG_DCACHE_SZ8 + if {$tmpvar_15 == "8"} then {set CONFIG_DCACHE_SZ8 1} else {set CONFIG_DCACHE_SZ8 0} + global CONFIG_DCACHE_SZ16 + if {$tmpvar_15 == "16"} then {set CONFIG_DCACHE_SZ16 1} else {set CONFIG_DCACHE_SZ16 0} + global CONFIG_DCACHE_SZ32 + if {$tmpvar_15 == "32"} then {set CONFIG_DCACHE_SZ32 1} else {set CONFIG_DCACHE_SZ32 0} + global CONFIG_DCACHE_SZ64 + if {$tmpvar_15 == "64"} then {set CONFIG_DCACHE_SZ64 1} else {set CONFIG_DCACHE_SZ64 0} + global CONFIG_DCACHE_SZ128 + if {$tmpvar_15 == "128"} then {set CONFIG_DCACHE_SZ128 1} else {set CONFIG_DCACHE_SZ128 0} + global CONFIG_DCACHE_SZ256 + if {$tmpvar_15 == "256"} then {set CONFIG_DCACHE_SZ256 1} else {set CONFIG_DCACHE_SZ256 0} + global tmpvar_16 + global CONFIG_DCACHE_LZ16 + if {$tmpvar_16 == "16"} then {set CONFIG_DCACHE_LZ16 1} else {set CONFIG_DCACHE_LZ16 0} + global CONFIG_DCACHE_LZ32 + if {$tmpvar_16 == "32"} then {set CONFIG_DCACHE_LZ32 1} else {set CONFIG_DCACHE_LZ32 0} + global tmpvar_17 + global CONFIG_DCACHE_ALGORND + if {$tmpvar_17 == "Random"} then {set CONFIG_DCACHE_ALGORND 1} else {set CONFIG_DCACHE_ALGORND 0} + global CONFIG_DCACHE_ALGODIR + if {$tmpvar_17 == "Direct"} then {set CONFIG_DCACHE_ALGODIR 1} else {set CONFIG_DCACHE_ALGODIR 0} + global CONFIG_DCACHE_ALGOLRR + if {$tmpvar_17 == "LRR"} then {set CONFIG_DCACHE_ALGOLRR 1} else {set CONFIG_DCACHE_ALGOLRR 0} + global CONFIG_DCACHE_ALGOLRU + if {$tmpvar_17 == "LRU"} then {set CONFIG_DCACHE_ALGOLRU 1} else {set CONFIG_DCACHE_ALGOLRU 0} + global CONFIG_DCACHE_LOCK + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { + set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK&15]} else {set CONFIG_DCACHE_LOCK [expr $CONFIG_DCACHE_LOCK|16]} + global CONFIG_DCACHE_SNOOP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { + set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} + global CONFIG_DCACHE_SNOOP_SEPTAG + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { + set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} + global CONFIG_CACHE_FIXED + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {validate_hex CONFIG_CACHE_FIXED "$CONFIG_CACHE_FIXED" 0} + global CONFIG_DCACHE_LRAM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { + set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM&15]} else {set CONFIG_DCACHE_LRAM [expr $CONFIG_DCACHE_LRAM|16]} + global tmpvar_18 + global CONFIG_DCACHE_LRAM_SZ1 + if {$tmpvar_18 == "1"} then {set CONFIG_DCACHE_LRAM_SZ1 1} else {set CONFIG_DCACHE_LRAM_SZ1 0} + global CONFIG_DCACHE_LRAM_SZ2 + if {$tmpvar_18 == "2"} then {set CONFIG_DCACHE_LRAM_SZ2 1} else {set CONFIG_DCACHE_LRAM_SZ2 0} + global CONFIG_DCACHE_LRAM_SZ4 + if {$tmpvar_18 == "4"} then {set CONFIG_DCACHE_LRAM_SZ4 1} else {set CONFIG_DCACHE_LRAM_SZ4 0} + global CONFIG_DCACHE_LRAM_SZ8 + if {$tmpvar_18 == "8"} then {set CONFIG_DCACHE_LRAM_SZ8 1} else {set CONFIG_DCACHE_LRAM_SZ8 0} + global CONFIG_DCACHE_LRAM_SZ16 + if {$tmpvar_18 == "16"} then {set CONFIG_DCACHE_LRAM_SZ16 1} else {set CONFIG_DCACHE_LRAM_SZ16 0} + global CONFIG_DCACHE_LRAM_SZ32 + if {$tmpvar_18 == "32"} then {set CONFIG_DCACHE_LRAM_SZ32 1} else {set CONFIG_DCACHE_LRAM_SZ32 0} + global CONFIG_DCACHE_LRAM_SZ64 + if {$tmpvar_18 == "64"} then {set CONFIG_DCACHE_LRAM_SZ64 1} else {set CONFIG_DCACHE_LRAM_SZ64 0} + global CONFIG_DCACHE_LRAM_SZ128 + if {$tmpvar_18 == "128"} then {set CONFIG_DCACHE_LRAM_SZ128 1} else {set CONFIG_DCACHE_LRAM_SZ128 0} + global CONFIG_DCACHE_LRAM_SZ256 + if {$tmpvar_18 == "256"} then {set CONFIG_DCACHE_LRAM_SZ256 1} else {set CONFIG_DCACHE_LRAM_SZ256 0} + global CONFIG_DCACHE_LRSTART + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {validate_hex CONFIG_DCACHE_LRSTART "$CONFIG_DCACHE_LRSTART" 8f} +} + + +proc menu7 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 7} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 7]] + message $w.m -width 400 -aspect 300 -text \ + "MMU" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "MMU" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu8 .menu8 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 7; menu6 .menu6 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 7 0 "Enable MMU " CONFIG_MMU_ENABLE + global tmpvar_19 + minimenu $w.config.f 7 1 "MMU type " tmpvar_19 CONFIG_MMU_COMBINED + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"MMU type \"" + $w.config.f.x1.x.menu add radiobutton -label "combined" -variable tmpvar_19 -value "combined" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "split" -variable tmpvar_19 -value "split" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 2 + global tmpvar_20 + minimenu $w.config.f 7 2 "TLB replacement sheme " tmpvar_20 CONFIG_MMU_REPARRAY + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"TLB replacement sheme \"" + $w.config.f.x2.x.menu add radiobutton -label "LRU" -variable tmpvar_20 -value "LRU" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "Increment" -variable tmpvar_20 -value "Increment" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 2 + global tmpvar_21 + minimenu $w.config.f 7 3 "Instruction (or combined) TLB entries" tmpvar_21 CONFIG_MMU_I2 + menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Instruction (or combined) TLB entries\"" + $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_21 -value "2" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_21 -value "4" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_21 -value "8" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_21 -value "16" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "32" -variable tmpvar_21 -value "32" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "64" -variable tmpvar_21 -value "64" -command "update_active" + menusplit $w $w.config.f.x3.x.menu 6 + global tmpvar_22 + minimenu $w.config.f 7 4 "Data TLB entries" tmpvar_22 CONFIG_MMU_D2 + menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"Data TLB entries\"" + $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_22 -value "2" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_22 -value "4" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_22 -value "8" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_22 -value "16" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_22 -value "32" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_22 -value "64" -command "update_active" + menusplit $w $w.config.f.x4.x.menu 6 + bool $w.config.f 7 5 "Fast writebuffer " CONFIG_MMU_FASTWB + global tmpvar_23 + minimenu $w.config.f 7 6 "MMU page size" tmpvar_23 CONFIG_MMU_PAGE_4K + menu $w.config.f.x6.x.menu -tearoffcommand "menutitle \"MMU page size\"" + $w.config.f.x6.x.menu add radiobutton -label "4K" -variable tmpvar_23 -value "4K" -command "update_active" + $w.config.f.x6.x.menu add radiobutton -label "8K" -variable tmpvar_23 -value "8K" -command "update_active" + $w.config.f.x6.x.menu add radiobutton -label "16K" -variable tmpvar_23 -value "16K" -command "update_active" + $w.config.f.x6.x.menu add radiobutton -label "32K" -variable tmpvar_23 -value "32K" -command "update_active" + $w.config.f.x6.x.menu add radiobutton -label "Programmable" -variable tmpvar_23 -value "Programmable" -command "update_active" + menusplit $w $w.config.f.x6.x.menu 5 + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu7 {} { + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_MMU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu7.config.f.x0 normal {n l y}} else {configure_entry .menu7.config.f.x0 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x1 normal {x l}} else {configure_entry .menu7.config.f.x1 disabled {x l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x2 normal {x l}} else {configure_entry .menu7.config.f.x2 disabled {x l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x3 normal {x l}} else {configure_entry .menu7.config.f.x3 disabled {x l}} + global CONFIG_MMU_SPLIT + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {configure_entry .menu7.config.f.x4 normal {x l}} else {configure_entry .menu7.config.f.x4 disabled {x l}} + global CONFIG_MMU_FASTWB + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { + configure_entry .menu7.config.f.x5 normal {n l y}} else {configure_entry .menu7.config.f.x5 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then {configure_entry .menu7.config.f.x6 normal {x l}} else {configure_entry .menu7.config.f.x6 disabled {x l}} +} + + +proc update_define_menu7 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_MMU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE&15]} else {set CONFIG_MMU_ENABLE [expr $CONFIG_MMU_ENABLE|16]} + global tmpvar_19 + global CONFIG_MMU_COMBINED + if {$tmpvar_19 == "combined"} then {set CONFIG_MMU_COMBINED 1} else {set CONFIG_MMU_COMBINED 0} + global CONFIG_MMU_SPLIT + if {$tmpvar_19 == "split"} then {set CONFIG_MMU_SPLIT 1} else {set CONFIG_MMU_SPLIT 0} + global tmpvar_20 + global CONFIG_MMU_REPARRAY + if {$tmpvar_20 == "LRU"} then {set CONFIG_MMU_REPARRAY 1} else {set CONFIG_MMU_REPARRAY 0} + global CONFIG_MMU_REPINCREMENT + if {$tmpvar_20 == "Increment"} then {set CONFIG_MMU_REPINCREMENT 1} else {set CONFIG_MMU_REPINCREMENT 0} + global tmpvar_21 + global CONFIG_MMU_I2 + if {$tmpvar_21 == "2"} then {set CONFIG_MMU_I2 1} else {set CONFIG_MMU_I2 0} + global CONFIG_MMU_I4 + if {$tmpvar_21 == "4"} then {set CONFIG_MMU_I4 1} else {set CONFIG_MMU_I4 0} + global CONFIG_MMU_I8 + if {$tmpvar_21 == "8"} then {set CONFIG_MMU_I8 1} else {set CONFIG_MMU_I8 0} + global CONFIG_MMU_I16 + if {$tmpvar_21 == "16"} then {set CONFIG_MMU_I16 1} else {set CONFIG_MMU_I16 0} + global CONFIG_MMU_I32 + if {$tmpvar_21 == "32"} then {set CONFIG_MMU_I32 1} else {set CONFIG_MMU_I32 0} + global CONFIG_MMU_I64 + if {$tmpvar_21 == "64"} then {set CONFIG_MMU_I64 1} else {set CONFIG_MMU_I64 0} + global tmpvar_22 + global CONFIG_MMU_D2 + if {$tmpvar_22 == "2"} then {set CONFIG_MMU_D2 1} else {set CONFIG_MMU_D2 0} + global CONFIG_MMU_D4 + if {$tmpvar_22 == "4"} then {set CONFIG_MMU_D4 1} else {set CONFIG_MMU_D4 0} + global CONFIG_MMU_D8 + if {$tmpvar_22 == "8"} then {set CONFIG_MMU_D8 1} else {set CONFIG_MMU_D8 0} + global CONFIG_MMU_D16 + if {$tmpvar_22 == "16"} then {set CONFIG_MMU_D16 1} else {set CONFIG_MMU_D16 0} + global CONFIG_MMU_D32 + if {$tmpvar_22 == "32"} then {set CONFIG_MMU_D32 1} else {set CONFIG_MMU_D32 0} + global CONFIG_MMU_D64 + if {$tmpvar_22 == "64"} then {set CONFIG_MMU_D64 1} else {set CONFIG_MMU_D64 0} + global CONFIG_MMU_FASTWB + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { + set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB&15]} else {set CONFIG_MMU_FASTWB [expr $CONFIG_MMU_FASTWB|16]} + global tmpvar_23 + global CONFIG_MMU_PAGE_4K + if {$tmpvar_23 == "4K"} then {set CONFIG_MMU_PAGE_4K 1} else {set CONFIG_MMU_PAGE_4K 0} + global CONFIG_MMU_PAGE_8K + if {$tmpvar_23 == "8K"} then {set CONFIG_MMU_PAGE_8K 1} else {set CONFIG_MMU_PAGE_8K 0} + global CONFIG_MMU_PAGE_16K + if {$tmpvar_23 == "16K"} then {set CONFIG_MMU_PAGE_16K 1} else {set CONFIG_MMU_PAGE_16K 0} + global CONFIG_MMU_PAGE_32K + if {$tmpvar_23 == "32K"} then {set CONFIG_MMU_PAGE_32K 1} else {set CONFIG_MMU_PAGE_32K 0} + global CONFIG_MMU_PAGE_PROG + if {$tmpvar_23 == "Programmable"} then {set CONFIG_MMU_PAGE_PROG 1} else {set CONFIG_MMU_PAGE_PROG 0} +} + + +proc menu8 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 8} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 8]] + message $w.m -width 400 -aspect 300 -text \ + "Debug Support Unit " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Debug Support Unit " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu9 .menu9 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 8; menu7 .menu7 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 8 0 "Enable LEON3 Debug support unit " CONFIG_DSU_ENABLE + bool $w.config.f 8 1 "Instruction trace buffer" CONFIG_DSU_ITRACE + global tmpvar_24 + minimenu $w.config.f 8 2 "Instruction trace buffer size (kbytes)" tmpvar_24 CONFIG_DSU_ITRACESZ1 + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"Instruction trace buffer size (kbytes)\"" + $w.config.f.x2.x.menu add radiobutton -label "1" -variable tmpvar_24 -value "1" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "2" -variable tmpvar_24 -value "2" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_24 -value "4" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_24 -value "8" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_24 -value "16" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 5 + bool $w.config.f 8 3 "AHB trace buffer" CONFIG_DSU_ATRACE + global tmpvar_25 + minimenu $w.config.f 8 4 "AHB trace buffer size (kbytes)" tmpvar_25 CONFIG_DSU_ATRACESZ1 + menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB trace buffer size (kbytes)\"" + $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_25 -value "1" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_25 -value "2" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_25 -value "4" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_25 -value "8" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_25 -value "16" -command "update_active" + menusplit $w $w.config.f.x4.x.menu 5 + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu8 {} { + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_DSU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + configure_entry .menu8.config.f.x0 normal {n l y}} else {configure_entry .menu8.config.f.x0 disabled {y n l}} + global CONFIG_DSU_ITRACE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1)} then { + configure_entry .menu8.config.f.x1 normal {n l y}} else {configure_entry .menu8.config.f.x1 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then {configure_entry .menu8.config.f.x2 normal {x l}} else {configure_entry .menu8.config.f.x2 disabled {x l}} + global CONFIG_DSU_ATRACE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1)} then { + configure_entry .menu8.config.f.x3 normal {n l y}} else {configure_entry .menu8.config.f.x3 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then {configure_entry .menu8.config.f.x4 normal {x l}} else {configure_entry .menu8.config.f.x4 disabled {x l}} +} + + +proc update_define_menu8 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_LEON3_CUSTOM + global CONFIG_DSU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then { + set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE&15]} else {set CONFIG_DSU_ENABLE [expr $CONFIG_DSU_ENABLE|16]} + global CONFIG_DSU_ITRACE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1)} then { + set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE&15]} else {set CONFIG_DSU_ITRACE [expr $CONFIG_DSU_ITRACE|16]} + global tmpvar_24 + global CONFIG_DSU_ITRACESZ1 + if {$tmpvar_24 == "1"} then {set CONFIG_DSU_ITRACESZ1 1} else {set CONFIG_DSU_ITRACESZ1 0} + global CONFIG_DSU_ITRACESZ2 + if {$tmpvar_24 == "2"} then {set CONFIG_DSU_ITRACESZ2 1} else {set CONFIG_DSU_ITRACESZ2 0} + global CONFIG_DSU_ITRACESZ4 + if {$tmpvar_24 == "4"} then {set CONFIG_DSU_ITRACESZ4 1} else {set CONFIG_DSU_ITRACESZ4 0} + global CONFIG_DSU_ITRACESZ8 + if {$tmpvar_24 == "8"} then {set CONFIG_DSU_ITRACESZ8 1} else {set CONFIG_DSU_ITRACESZ8 0} + global CONFIG_DSU_ITRACESZ16 + if {$tmpvar_24 == "16"} then {set CONFIG_DSU_ITRACESZ16 1} else {set CONFIG_DSU_ITRACESZ16 0} + global CONFIG_DSU_ATRACE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1)} then { + set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE&15]} else {set CONFIG_DSU_ATRACE [expr $CONFIG_DSU_ATRACE|16]} + global tmpvar_25 + global CONFIG_DSU_ATRACESZ1 + if {$tmpvar_25 == "1"} then {set CONFIG_DSU_ATRACESZ1 1} else {set CONFIG_DSU_ATRACESZ1 0} + global CONFIG_DSU_ATRACESZ2 + if {$tmpvar_25 == "2"} then {set CONFIG_DSU_ATRACESZ2 1} else {set CONFIG_DSU_ATRACESZ2 0} + global CONFIG_DSU_ATRACESZ4 + if {$tmpvar_25 == "4"} then {set CONFIG_DSU_ATRACESZ4 1} else {set CONFIG_DSU_ATRACESZ4 0} + global CONFIG_DSU_ATRACESZ8 + if {$tmpvar_25 == "8"} then {set CONFIG_DSU_ATRACESZ8 1} else {set CONFIG_DSU_ATRACESZ8 0} + global CONFIG_DSU_ATRACESZ16 + if {$tmpvar_25 == "16"} then {set CONFIG_DSU_ATRACESZ16 1} else {set CONFIG_DSU_ATRACESZ16 0} +} + + +proc menu9 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 9} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 9]] + message $w.m -width 400 -aspect 300 -text \ + "Fault-tolerance " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Fault-tolerance " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu10 .menu10 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 9; menu8 .menu8 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 9 0 "Use LEON3-FT processor core " CONFIG_LEON3FT_EN + global tmpvar_26 + minimenu $w.config.f 9 1 "IU Register file protection " tmpvar_26 CONFIG_IUFT_NONE + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"IU Register file protection \"" + $w.config.f.x1.x.menu add radiobutton -label "None" -variable tmpvar_26 -value "None" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "Parity" -variable tmpvar_26 -value "Parity" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "PDMR" -variable tmpvar_26 -value "PDMR" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "BCH" -variable tmpvar_26 -value "BCH" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "TMR" -variable tmpvar_26 -value "TMR" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 5 + global tmpvar_27 + minimenu $w.config.f 9 2 "FPU Register file protection " tmpvar_27 CONFIG_FPUFT_NONE + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"FPU Register file protection \"" + $w.config.f.x2.x.menu add radiobutton -label "None" -variable tmpvar_27 -value "None" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "Parity" -variable tmpvar_27 -value "Parity" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "PDMR" -variable tmpvar_27 -value "PDMR" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "TMR" -variable tmpvar_27 -value "TMR" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 4 + bool $w.config.f 9 3 "Register file error injection" CONFIG_RF_ERRINJ + bool $w.config.f 9 4 "Cache memory protection " CONFIG_CACHE_FT_EN + int $w.config.f 9 5 "Cache memory error injection" CONFIG_CACHE_ERRINJ + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu9 {} { + global CONFIG_LEON3 + global CONFIG_LEON3FT_PRESENT + global CONFIG_LEON3FT_EN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1)} then { + configure_entry .menu9.config.f.x0 normal {n l y}} else {configure_entry .menu9.config.f.x0 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then {configure_entry .menu9.config.f.x1 normal {x l}} else {configure_entry .menu9.config.f.x1 disabled {x l}} + global CONFIG_FPU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1) && ($CONFIG_FPU_ENABLE == 1)} then {configure_entry .menu9.config.f.x2 normal {x l}} else {configure_entry .menu9.config.f.x2 disabled {x l}} + global CONFIG_RF_ERRINJ + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then { + configure_entry .menu9.config.f.x3 normal {n l y}} else {configure_entry .menu9.config.f.x3 disabled {y n l}} + global CONFIG_CACHE_FT_EN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then { + configure_entry .menu9.config.f.x4 normal {n l y}} else {configure_entry .menu9.config.f.x4 disabled {y n l}} + global CONFIG_CACHE_ERRINJ + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then {.menu9.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu9.config.f.x5.l configure -state normal; } else {.menu9.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu9.config.f.x5.l configure -state disabled} +} + + +proc update_define_menu9 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_LEON3FT_PRESENT + global CONFIG_LEON3FT_EN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1)} then { + set CONFIG_LEON3FT_EN [expr $CONFIG_LEON3FT_EN&15]} else {set CONFIG_LEON3FT_EN [expr $CONFIG_LEON3FT_EN|16]} + global tmpvar_26 + global CONFIG_IUFT_NONE + if {$tmpvar_26 == "None"} then {set CONFIG_IUFT_NONE 1} else {set CONFIG_IUFT_NONE 0} + global CONFIG_IUFT_PAR + if {$tmpvar_26 == "Parity"} then {set CONFIG_IUFT_PAR 1} else {set CONFIG_IUFT_PAR 0} + global CONFIG_IUFT_DMR + if {$tmpvar_26 == "PDMR"} then {set CONFIG_IUFT_DMR 1} else {set CONFIG_IUFT_DMR 0} + global CONFIG_IUFT_BCH + if {$tmpvar_26 == "BCH"} then {set CONFIG_IUFT_BCH 1} else {set CONFIG_IUFT_BCH 0} + global CONFIG_IUFT_TMR + if {$tmpvar_26 == "TMR"} then {set CONFIG_IUFT_TMR 1} else {set CONFIG_IUFT_TMR 0} + global tmpvar_27 + global CONFIG_FPUFT_NONE + if {$tmpvar_27 == "None"} then {set CONFIG_FPUFT_NONE 1} else {set CONFIG_FPUFT_NONE 0} + global CONFIG_FPUFT_PAR + if {$tmpvar_27 == "Parity"} then {set CONFIG_FPUFT_PAR 1} else {set CONFIG_FPUFT_PAR 0} + global CONFIG_FPUFT_DMR + if {$tmpvar_27 == "PDMR"} then {set CONFIG_FPUFT_DMR 1} else {set CONFIG_FPUFT_DMR 0} + global CONFIG_FPUFT_TMR + if {$tmpvar_27 == "TMR"} then {set CONFIG_FPUFT_TMR 1} else {set CONFIG_FPUFT_TMR 0} + global CONFIG_RF_ERRINJ + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then { + set CONFIG_RF_ERRINJ [expr $CONFIG_RF_ERRINJ&15]} else {set CONFIG_RF_ERRINJ [expr $CONFIG_RF_ERRINJ|16]} + global CONFIG_CACHE_FT_EN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then { + set CONFIG_CACHE_FT_EN [expr $CONFIG_CACHE_FT_EN&15]} else {set CONFIG_CACHE_FT_EN [expr $CONFIG_CACHE_FT_EN|16]} + global CONFIG_CACHE_ERRINJ + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then {validate_int CONFIG_CACHE_ERRINJ "$CONFIG_CACHE_ERRINJ" 0} +} + + +proc menu10 {w title} { + set oldFocus [focus] + catch {focus .menu3} + catch {destroy $w; unregister_active 10} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 10]] + message $w.m -width 400 -aspect 300 -text \ + "VHDL debug settings " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "VHDL debug settings " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 10; catch {destroy .menu3}; unregister_active 3; menu11 .menu11 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 10; menu9 .menu9 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 10 0 "Processor disassembly to console " CONFIG_IU_DISAS + bool $w.config.f 10 1 "Processor disassembly in netlist " CONFIG_IU_DISAS_NET + bool $w.config.f 10 2 "32-bit program counters " CONFIG_DEBUG_PC32 + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu3] == 0} then {menu3 .menu3 "Processor "} + set winx [expr [winfo x .menu3]+30]; set winy [expr [winfo y .menu3]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu10 {} { + global CONFIG_LEON3 + global CONFIG_IU_DISAS + if {($CONFIG_LEON3 == 1)} then { + configure_entry .menu10.config.f.x0 normal {n l y}} else {configure_entry .menu10.config.f.x0 disabled {y n l}} + global CONFIG_IU_DISAS_NET + if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { + configure_entry .menu10.config.f.x1 normal {n l y}} else {configure_entry .menu10.config.f.x1 disabled {y n l}} + global CONFIG_DEBUG_PC32 + if {($CONFIG_LEON3 == 1)} then { + configure_entry .menu10.config.f.x2 normal {n l y}} else {configure_entry .menu10.config.f.x2 disabled {y n l}} +} + + +proc update_define_menu10 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_LEON3 + global CONFIG_IU_DISAS + if {($CONFIG_LEON3 == 1)} then { + set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS&15]} else {set CONFIG_IU_DISAS [expr $CONFIG_IU_DISAS|16]} + global CONFIG_IU_DISAS_NET + if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then { + set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET&15]} else {set CONFIG_IU_DISAS_NET [expr $CONFIG_IU_DISAS_NET|16]} + global CONFIG_DEBUG_PC32 + if {($CONFIG_LEON3 == 1)} then { + set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32&15]} else {set CONFIG_DEBUG_PC32 [expr $CONFIG_DEBUG_PC32|16]} +} + + +menu_option menu11 11 "AMBA configuration" +proc menu11 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 11} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 11]] + message $w.m -width 400 -aspect 300 -text \ + "AMBA configuration" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "AMBA configuration" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu12 .menu12 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 11; menu10 .menu10 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + int $w.config.f 11 0 "Default AHB master" CONFIG_AHB_DEFMST + bool $w.config.f 11 1 "Round-robin arbiter " CONFIG_AHB_RROBIN + bool $w.config.f 11 2 "AHB split-transaction support " CONFIG_AHB_SPLIT + bool $w.config.f 11 3 "Enable full plug&play decoding " CONFIG_AHB_FPNPEN + hex $w.config.f 11 4 "I/O area start address (haddr\[31:20\]) " CONFIG_AHB_IOADDR + hex $w.config.f 11 5 "AHB/APB bridge address (haddr\[31:20\]) " CONFIG_APB_HADDR + bool $w.config.f 11 6 "Enable AMBA AHB monitor " CONFIG_AHB_MON + bool $w.config.f 11 7 "Report AHB errors " CONFIG_AHB_MONERR + bool $w.config.f 11 8 "Report AHB warings " CONFIG_AHB_MONWAR + bool $w.config.f 11 9 "Write trace to simulation console " CONFIG_AHB_DTRACE + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu11 {} { + global CONFIG_AHB_MON + global CONFIG_AHB_MONERR + if {($CONFIG_AHB_MON == 1)} then { + configure_entry .menu11.config.f.x7 normal {n l y}} else {configure_entry .menu11.config.f.x7 disabled {y n l}} + global CONFIG_AHB_MONWAR + if {($CONFIG_AHB_MON == 1)} then { + configure_entry .menu11.config.f.x8 normal {n l y}} else {configure_entry .menu11.config.f.x8 disabled {y n l}} +} + + +proc update_define_menu11 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_AHB_MON + global CONFIG_AHB_MONERR + if {($CONFIG_AHB_MON == 1)} then { + set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR&15]} else {set CONFIG_AHB_MONERR [expr $CONFIG_AHB_MONERR|16]} + global CONFIG_AHB_MONWAR + if {($CONFIG_AHB_MON == 1)} then { + set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR&15]} else {set CONFIG_AHB_MONWAR [expr $CONFIG_AHB_MONWAR|16]} +} + + +menu_option menu12 12 "Debug Link " +proc menu12 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 12} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 12]] + message $w.m -width 400 -aspect 300 -text \ + "Debug Link " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Debug Link " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu13 .menu13 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 12; menu11 .menu11 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 12 0 "Serial Debug Link (RS232) " CONFIG_DSU_UART + bool $w.config.f 12 1 "JTAG Debug Link" CONFIG_DSU_JTAG + bool $w.config.f 12 2 "Ethernet Debug Communication Link (EDCL)" CONFIG_DSU_ETH + global tmpvar_28 + minimenu $w.config.f 12 3 "Ethernet/AHB bridge buffer size (kbytes)" tmpvar_28 CONFIG_DSU_ETHSZ1 + menu $w.config.f.x3.x.menu -tearoffcommand "menutitle \"Ethernet/AHB bridge buffer size (kbytes)\"" + $w.config.f.x3.x.menu add radiobutton -label "1" -variable tmpvar_28 -value "1" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "2" -variable tmpvar_28 -value "2" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "4" -variable tmpvar_28 -value "4" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "8" -variable tmpvar_28 -value "8" -command "update_active" + $w.config.f.x3.x.menu add radiobutton -label "16" -variable tmpvar_28 -value "16" -command "update_active" + menusplit $w $w.config.f.x3.x.menu 5 + hex $w.config.f 12 4 "MSB 16 bits of IP address (hex) " CONFIG_DSU_IPMSB + hex $w.config.f 12 5 "LSB 16 bits of IP address (hex) " CONFIG_DSU_IPLSB + hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB + hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB + bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu12 {} { + global CONFIG_GRETH_ENABLE + global CONFIG_DSU_ETH + if {($CONFIG_GRETH_ENABLE == 1)} then { + configure_entry .menu12.config.f.x2 normal {n l y}} else {configure_entry .menu12.config.f.x2 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {configure_entry .menu12.config.f.x3 normal {x l}} else {configure_entry .menu12.config.f.x3 disabled {x l}} + global CONFIG_DSU_IPMSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x4.l configure -state normal; } else {.menu12.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x4.l configure -state disabled} + global CONFIG_DSU_IPLSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled} + global CONFIG_DSU_ETHMSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} + global CONFIG_DSU_ETHLSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} + global CONFIG_DSU_ETH_PROG + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { + configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} + global CONFIG_DSU_ETH_DIS + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { + configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} +} + + +proc update_define_menu12 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_GRETH_ENABLE + global CONFIG_DSU_ETH + if {($CONFIG_GRETH_ENABLE == 1)} then { + set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH&15]} else {set CONFIG_DSU_ETH [expr $CONFIG_DSU_ETH|16]} + global tmpvar_28 + global CONFIG_DSU_ETHSZ1 + if {$tmpvar_28 == "1"} then {set CONFIG_DSU_ETHSZ1 1} else {set CONFIG_DSU_ETHSZ1 0} + global CONFIG_DSU_ETHSZ2 + if {$tmpvar_28 == "2"} then {set CONFIG_DSU_ETHSZ2 1} else {set CONFIG_DSU_ETHSZ2 0} + global CONFIG_DSU_ETHSZ4 + if {$tmpvar_28 == "4"} then {set CONFIG_DSU_ETHSZ4 1} else {set CONFIG_DSU_ETHSZ4 0} + global CONFIG_DSU_ETHSZ8 + if {$tmpvar_28 == "8"} then {set CONFIG_DSU_ETHSZ8 1} else {set CONFIG_DSU_ETHSZ8 0} + global CONFIG_DSU_ETHSZ16 + if {$tmpvar_28 == "16"} then {set CONFIG_DSU_ETHSZ16 1} else {set CONFIG_DSU_ETHSZ16 0} + global CONFIG_DSU_IPMSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPMSB "$CONFIG_DSU_IPMSB" C0A8} + global CONFIG_DSU_IPLSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_IPLSB "$CONFIG_DSU_IPLSB" 0033} + global CONFIG_DSU_ETHMSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} + global CONFIG_DSU_ETHLSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} + global CONFIG_DSU_ETH_PROG + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { + set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} + global CONFIG_DSU_ETH_DIS + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { + set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} +} + + +menu_option menu13 13 "Peripherals " +proc menu13 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 13} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 13]] + message $w.m -width 400 -aspect 300 -text \ + "Peripherals " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Peripherals " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; break" + set nextscript "catch {focus $oldFocus}; menu14 .menu14 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 13; menu12 .menu12 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + submenu $w.config.f 13 0 "Memory controller " 14 + submenu $w.config.f 13 1 "On-chip RAM/ROM " 18 + submenu $w.config.f 13 2 "Ethernet " 19 + submenu $w.config.f 13 3 "UARTs, timers and irq control " 20 + submenu $w.config.f 13 4 "Keybord and VGA interface" 21 + submenu $w.config.f 13 5 "SPI" 22 + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu13 {} { +} + + +proc update_define_menu13 {} { + update_define_mainmenu + global CONFIG_MODULES +} + + +proc menu14 {w title} { + set oldFocus [focus] + catch {focus .menu13} + catch {destroy $w; unregister_active 14} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 14]] + message $w.m -width 400 -aspect 300 -text \ + "Memory controller " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Memory controller " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; break" + set nextscript "catch {focus $oldFocus}; menu15 .menu15 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 14; menu13 .menu13 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + submenu $w.config.f 14 0 "Leon2 memory controller " 15 + submenu $w.config.f 14 1 "MIG memory controller " 16 + submenu $w.config.f 14 2 "MIG Series 7 memory controller " 17 + bool $w.config.f 14 3 "Enable AHB Status Register " CONFIG_AHBSTAT_ENABLE + int $w.config.f 14 4 "Number of correctable-error slaves " CONFIG_AHBSTAT_NFTSLV + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} + set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu14 {} { + global CONFIG_AHBSTAT_ENABLE + global CONFIG_AHBSTAT_NFTSLV + if {($CONFIG_AHBSTAT_ENABLE == 1)} then {.menu14.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu14.config.f.x4.l configure -state normal; } else {.menu14.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu14.config.f.x4.l configure -state disabled} +} + + +proc update_define_menu14 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_AHBSTAT_ENABLE + global CONFIG_AHBSTAT_NFTSLV + if {($CONFIG_AHBSTAT_ENABLE == 1)} then {validate_int CONFIG_AHBSTAT_NFTSLV "$CONFIG_AHBSTAT_NFTSLV" 1} +} + + +proc menu15 {w title} { + set oldFocus [focus] + catch {focus .menu14} + catch {destroy $w; unregister_active 15} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 15]] + message $w.m -width 400 -aspect 300 -text \ + "Leon2 memory controller " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Leon2 memory controller " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu16 .menu16 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 15; menu14 .menu14 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 15 0 "Enable Leon2 memory controller " CONFIG_MCTRL_LEON2 + bool $w.config.f 15 1 "8-bit PROM/SRAM bus support " CONFIG_MCTRL_8BIT + bool $w.config.f 15 2 "16-bit PROM/SRAM bus support " CONFIG_MCTRL_16BIT + bool $w.config.f 15 3 "5th SRAM chip-select " CONFIG_MCTRL_5CS + bool $w.config.f 15 4 "SDRAM controller " CONFIG_MCTRL_SDRAM + bool $w.config.f 15 5 "Separate address and data buses" CONFIG_MCTRL_SDRAM_SEPBUS + bool $w.config.f 15 6 "64-bit SDRAM data bus" CONFIG_MCTRL_SDRAM_BUS64 + bool $w.config.f 15 7 "Unsynchronized sdclock" CONFIG_MCTRL_SDRAM_INVCLK + bool $w.config.f 15 8 "Enable page burst operation " CONFIG_MCTRL_PAGE + bool $w.config.f 15 9 "Enable programmable page burst " CONFIG_MCTRL_PROGPAGE + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controller "} + set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu15 {} { + global CONFIG_MCTRL_LEON2 + global CONFIG_MCTRL_8BIT + if {($CONFIG_MCTRL_LEON2 == 1)} then { + configure_entry .menu15.config.f.x1 normal {n l y}} else {configure_entry .menu15.config.f.x1 disabled {y n l}} + global CONFIG_MCTRL_16BIT + if {($CONFIG_MCTRL_LEON2 == 1)} then { + configure_entry .menu15.config.f.x2 normal {n l y}} else {configure_entry .menu15.config.f.x2 disabled {y n l}} + global CONFIG_MCTRL_5CS + if {($CONFIG_MCTRL_LEON2 == 1)} then { + configure_entry .menu15.config.f.x3 normal {n l y}} else {configure_entry .menu15.config.f.x3 disabled {y n l}} + global CONFIG_MCTRL_SDRAM + if {($CONFIG_MCTRL_LEON2 == 1)} then { + configure_entry .menu15.config.f.x4 normal {n l y}} else {configure_entry .menu15.config.f.x4 disabled {y n l}} + global CONFIG_MCTRL_SDRAM_SEPBUS + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { + configure_entry .menu15.config.f.x5 normal {n l y}} else {configure_entry .menu15.config.f.x5 disabled {y n l}} + global CONFIG_MCTRL_SDRAM_BUS64 + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { + configure_entry .menu15.config.f.x6 normal {n l y}} else {configure_entry .menu15.config.f.x6 disabled {y n l}} + global CONFIG_MCTRL_SDRAM_INVCLK + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { + configure_entry .menu15.config.f.x7 normal {n l y}} else {configure_entry .menu15.config.f.x7 disabled {y n l}} + global CONFIG_MCTRL_PAGE + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { + configure_entry .menu15.config.f.x8 normal {n l y}} else {configure_entry .menu15.config.f.x8 disabled {y n l}} + global CONFIG_MCTRL_PROGPAGE + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { + configure_entry .menu15.config.f.x9 normal {n l y}} else {configure_entry .menu15.config.f.x9 disabled {y n l}} +} + + +proc update_define_menu15 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_MCTRL_LEON2 + global CONFIG_MCTRL_8BIT + if {($CONFIG_MCTRL_LEON2 == 1)} then { + set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT&15]} else {set CONFIG_MCTRL_8BIT [expr $CONFIG_MCTRL_8BIT|16]} + global CONFIG_MCTRL_16BIT + if {($CONFIG_MCTRL_LEON2 == 1)} then { + set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT&15]} else {set CONFIG_MCTRL_16BIT [expr $CONFIG_MCTRL_16BIT|16]} + global CONFIG_MCTRL_5CS + if {($CONFIG_MCTRL_LEON2 == 1)} then { + set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS&15]} else {set CONFIG_MCTRL_5CS [expr $CONFIG_MCTRL_5CS|16]} + global CONFIG_MCTRL_SDRAM + if {($CONFIG_MCTRL_LEON2 == 1)} then { + set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM&15]} else {set CONFIG_MCTRL_SDRAM [expr $CONFIG_MCTRL_SDRAM|16]} + global CONFIG_MCTRL_SDRAM_SEPBUS + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { + set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS&15]} else {set CONFIG_MCTRL_SDRAM_SEPBUS [expr $CONFIG_MCTRL_SDRAM_SEPBUS|16]} + global CONFIG_MCTRL_SDRAM_BUS64 + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { + set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64&15]} else {set CONFIG_MCTRL_SDRAM_BUS64 [expr $CONFIG_MCTRL_SDRAM_BUS64|16]} + global CONFIG_MCTRL_SDRAM_INVCLK + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then { + set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK&15]} else {set CONFIG_MCTRL_SDRAM_INVCLK [expr $CONFIG_MCTRL_SDRAM_INVCLK|16]} + global CONFIG_MCTRL_PAGE + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then { + set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE&15]} else {set CONFIG_MCTRL_PAGE [expr $CONFIG_MCTRL_PAGE|16]} + global CONFIG_MCTRL_PROGPAGE + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then { + set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE&15]} else {set CONFIG_MCTRL_PROGPAGE [expr $CONFIG_MCTRL_PROGPAGE|16]} +} + + +proc menu16 {w title} { + set oldFocus [focus] + catch {focus .menu14} + catch {destroy $w; unregister_active 16} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 16]] + message $w.m -width 400 -aspect 300 -text \ + "MIG memory controller " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "MIG memory controller " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu17 .menu17 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 16; menu15 .menu15 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 16 0 "Enable Xilinx MIG memory controller" CONFIG_MIG_DDR2 + int $w.config.f 16 1 "Chip selects (ranks) " CONFIG_MIG_RANKS + int $w.config.f 16 2 "Column bits " CONFIG_MIG_COLBITS + int $w.config.f 16 3 "Row bits " CONFIG_MIG_ROWBITS + int $w.config.f 16 4 "Bank bits " CONFIG_MIG_BANKBITS + hex $w.config.f 16 5 "AHB HMASK " CONFIG_MIG_HMASK + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controller "} + set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu16 {} { + global CONFIG_MIG_DDR2 + global CONFIG_MIG_RANKS + if {($CONFIG_MIG_DDR2 == 1)} then {.menu16.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x1.l configure -state normal; } else {.menu16.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x1.l configure -state disabled} + global CONFIG_MIG_COLBITS + if {($CONFIG_MIG_DDR2 == 1)} then {.menu16.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x2.l configure -state normal; } else {.menu16.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x2.l configure -state disabled} + global CONFIG_MIG_ROWBITS + if {($CONFIG_MIG_DDR2 == 1)} then {.menu16.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x3.l configure -state normal; } else {.menu16.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x3.l configure -state disabled} + global CONFIG_MIG_BANKBITS + if {($CONFIG_MIG_DDR2 == 1)} then {.menu16.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x4.l configure -state normal; } else {.menu16.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x4.l configure -state disabled} + global CONFIG_MIG_HMASK + if {($CONFIG_MIG_DDR2 == 1)} then {.menu16.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu16.config.f.x5.l configure -state normal; } else {.menu16.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu16.config.f.x5.l configure -state disabled} +} + + +proc update_define_menu16 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_MIG_DDR2 + global CONFIG_MIG_RANKS + if {($CONFIG_MIG_DDR2 == 1)} then {validate_int CONFIG_MIG_RANKS "$CONFIG_MIG_RANKS" 1} + global CONFIG_MIG_COLBITS + if {($CONFIG_MIG_DDR2 == 1)} then {validate_int CONFIG_MIG_COLBITS "$CONFIG_MIG_COLBITS" 10} + global CONFIG_MIG_ROWBITS + if {($CONFIG_MIG_DDR2 == 1)} then {validate_int CONFIG_MIG_ROWBITS "$CONFIG_MIG_ROWBITS" 13} + global CONFIG_MIG_BANKBITS + if {($CONFIG_MIG_DDR2 == 1)} then {validate_int CONFIG_MIG_BANKBITS "$CONFIG_MIG_BANKBITS" 2} + global CONFIG_MIG_HMASK + if {($CONFIG_MIG_DDR2 == 1)} then {validate_hex CONFIG_MIG_HMASK "$CONFIG_MIG_HMASK" F00} +} + + +proc menu17 {w title} { + set oldFocus [focus] + catch {focus .menu14} + catch {destroy $w; unregister_active 17} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 17]] + message $w.m -width 400 -aspect 300 -text \ + "MIG Series 7 memory controller " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "MIG Series 7 memory controller " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 17; catch {destroy .menu14}; unregister_active 14; menu18 .menu18 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 17; menu16 .menu16 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 17 0 "Enable Xilinx DDR3 MIG memory controller" CONFIG_MIG_SERIES7 + bool $w.config.f 17 1 "Enable fast simulation model " CONFIG_MIG_SERIES_7_MODEL + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu14] == 0} then {menu14 .menu14 "Memory controller "} + set winx [expr [winfo x .menu14]+30]; set winy [expr [winfo y .menu14]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu17 {} { +} + + +proc update_define_menu17 {} { + update_define_mainmenu + global CONFIG_MODULES +} + + +proc menu18 {w title} { + set oldFocus [focus] + catch {focus .menu13} + catch {destroy $w; unregister_active 18} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 18]] + message $w.m -width 400 -aspect 300 -text \ + "On-chip RAM/ROM " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "On-chip RAM/ROM " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu19 .menu19 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 18; menu17 .menu17 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 18 0 "On-chip AHB ROM " CONFIG_AHBROM_ENABLE + hex $w.config.f 18 1 "ROM start address (haddr\[31:20\]) " CONFIG_AHBROM_START + bool $w.config.f 18 2 "Pipelined ROM access " CONFIG_AHBROM_PIPE + bool $w.config.f 18 3 "On-chip AHB RAM " CONFIG_AHBRAM_ENABLE + global tmpvar_29 + minimenu $w.config.f 18 4 "AHB RAM size (Kbyte)" tmpvar_29 CONFIG_AHBRAM_SZ1 + menu $w.config.f.x4.x.menu -tearoffcommand "menutitle \"AHB RAM size (Kbyte)\"" + $w.config.f.x4.x.menu add radiobutton -label "1" -variable tmpvar_29 -value "1" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "2" -variable tmpvar_29 -value "2" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "4" -variable tmpvar_29 -value "4" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "8" -variable tmpvar_29 -value "8" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "16" -variable tmpvar_29 -value "16" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "32" -variable tmpvar_29 -value "32" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "64" -variable tmpvar_29 -value "64" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "128" -variable tmpvar_29 -value "128" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "256" -variable tmpvar_29 -value "256" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "512" -variable tmpvar_29 -value "512" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "1024" -variable tmpvar_29 -value "1024" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "2048" -variable tmpvar_29 -value "2048" -command "update_active" + $w.config.f.x4.x.menu add radiobutton -label "4096" -variable tmpvar_29 -value "4096" -command "update_active" + menusplit $w $w.config.f.x4.x.menu 13 + hex $w.config.f 18 5 "RAM start address (haddr\[31:20\]) " CONFIG_AHBRAM_START + bool $w.config.f 18 6 "Extra pipeline stage " CONFIG_AHBRAM_PIPE + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} + set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu18 {} { + global CONFIG_AHBROM_ENABLE + global CONFIG_AHBROM_START + if {($CONFIG_AHBROM_ENABLE == 1)} then {.menu18.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x1.l configure -state normal; } else {.menu18.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x1.l configure -state disabled} + global CONFIG_AHBROM_PIPE + if {($CONFIG_AHBROM_ENABLE == 1)} then { + configure_entry .menu18.config.f.x2 normal {n l y}} else {configure_entry .menu18.config.f.x2 disabled {y n l}} + global CONFIG_AHBRAM_ENABLE + if {($CONFIG_AHBRAM_ENABLE == 1)} then {configure_entry .menu18.config.f.x4 normal {x l}} else {configure_entry .menu18.config.f.x4 disabled {x l}} + global CONFIG_AHBRAM_START + if {($CONFIG_AHBRAM_ENABLE == 1)} then {.menu18.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu18.config.f.x5.l configure -state normal; } else {.menu18.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu18.config.f.x5.l configure -state disabled} + global CONFIG_AHBRAM_PIPE + if {($CONFIG_AHBRAM_ENABLE == 1)} then { + configure_entry .menu18.config.f.x6 normal {n l y}} else {configure_entry .menu18.config.f.x6 disabled {y n l}} +} + + +proc update_define_menu18 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_AHBROM_ENABLE + global CONFIG_AHBROM_START + if {($CONFIG_AHBROM_ENABLE == 1)} then {validate_hex CONFIG_AHBROM_START "$CONFIG_AHBROM_START" 000} + global CONFIG_AHBROM_PIPE + if {($CONFIG_AHBROM_ENABLE == 1)} then { + set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE&15]} else {set CONFIG_AHBROM_PIPE [expr $CONFIG_AHBROM_PIPE|16]} + global tmpvar_29 + global CONFIG_AHBRAM_SZ1 + if {$tmpvar_29 == "1"} then {set CONFIG_AHBRAM_SZ1 1} else {set CONFIG_AHBRAM_SZ1 0} + global CONFIG_AHBRAM_SZ2 + if {$tmpvar_29 == "2"} then {set CONFIG_AHBRAM_SZ2 1} else {set CONFIG_AHBRAM_SZ2 0} + global CONFIG_AHBRAM_SZ4 + if {$tmpvar_29 == "4"} then {set CONFIG_AHBRAM_SZ4 1} else {set CONFIG_AHBRAM_SZ4 0} + global CONFIG_AHBRAM_SZ8 + if {$tmpvar_29 == "8"} then {set CONFIG_AHBRAM_SZ8 1} else {set CONFIG_AHBRAM_SZ8 0} + global CONFIG_AHBRAM_SZ16 + if {$tmpvar_29 == "16"} then {set CONFIG_AHBRAM_SZ16 1} else {set CONFIG_AHBRAM_SZ16 0} + global CONFIG_AHBRAM_SZ32 + if {$tmpvar_29 == "32"} then {set CONFIG_AHBRAM_SZ32 1} else {set CONFIG_AHBRAM_SZ32 0} + global CONFIG_AHBRAM_SZ64 + if {$tmpvar_29 == "64"} then {set CONFIG_AHBRAM_SZ64 1} else {set CONFIG_AHBRAM_SZ64 0} + global CONFIG_AHBRAM_SZ128 + if {$tmpvar_29 == "128"} then {set CONFIG_AHBRAM_SZ128 1} else {set CONFIG_AHBRAM_SZ128 0} + global CONFIG_AHBRAM_SZ256 + if {$tmpvar_29 == "256"} then {set CONFIG_AHBRAM_SZ256 1} else {set CONFIG_AHBRAM_SZ256 0} + global CONFIG_AHBRAM_SZ512 + if {$tmpvar_29 == "512"} then {set CONFIG_AHBRAM_SZ512 1} else {set CONFIG_AHBRAM_SZ512 0} + global CONFIG_AHBRAM_SZ1024 + if {$tmpvar_29 == "1024"} then {set CONFIG_AHBRAM_SZ1024 1} else {set CONFIG_AHBRAM_SZ1024 0} + global CONFIG_AHBRAM_SZ2048 + if {$tmpvar_29 == "2048"} then {set CONFIG_AHBRAM_SZ2048 1} else {set CONFIG_AHBRAM_SZ2048 0} + global CONFIG_AHBRAM_SZ4096 + if {$tmpvar_29 == "4096"} then {set CONFIG_AHBRAM_SZ4096 1} else {set CONFIG_AHBRAM_SZ4096 0} + global CONFIG_AHBRAM_ENABLE + global CONFIG_AHBRAM_START + if {($CONFIG_AHBRAM_ENABLE == 1)} then {validate_hex CONFIG_AHBRAM_START "$CONFIG_AHBRAM_START" A00} + global CONFIG_AHBRAM_PIPE + if {($CONFIG_AHBRAM_ENABLE == 1)} then { + set CONFIG_AHBRAM_PIPE [expr $CONFIG_AHBRAM_PIPE&15]} else {set CONFIG_AHBRAM_PIPE [expr $CONFIG_AHBRAM_PIPE|16]} +} + + +proc menu19 {w title} { + set oldFocus [focus] + catch {focus .menu13} + catch {destroy $w; unregister_active 19} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 19]] + message $w.m -width 400 -aspect 300 -text \ + "Ethernet " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Ethernet " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu20 .menu20 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 19; menu18 .menu18 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 19 0 "Gaisler Research 10/100/1000 Mbit Ethernet MAC " CONFIG_GRETH_ENABLE + bool $w.config.f 19 1 "Enable 1000 Mbit support " CONFIG_GRETH_GIGA + global tmpvar_30 + minimenu $w.config.f 19 2 "AHB FIFO size (words) " tmpvar_30 CONFIG_GRETH_FIFO4 + menu $w.config.f.x2.x.menu -tearoffcommand "menutitle \"AHB FIFO size (words) \"" + $w.config.f.x2.x.menu add radiobutton -label "4" -variable tmpvar_30 -value "4" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "8" -variable tmpvar_30 -value "8" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "16" -variable tmpvar_30 -value "16" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "32" -variable tmpvar_30 -value "32" -command "update_active" + $w.config.f.x2.x.menu add radiobutton -label "64" -variable tmpvar_30 -value "64" -command "update_active" + menusplit $w $w.config.f.x2.x.menu 5 + bool $w.config.f 19 3 "Enable fault-tolerance" CONFIG_GRETH_FT + bool $w.config.f 19 4 "Enable fault tolerance for EDCL buffer " CONFIG_GRETH_EDCLFT + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} + set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu19 {} { + global CONFIG_GRETH_ENABLE + global CONFIG_GRETH_GIGA + if {($CONFIG_GRETH_ENABLE == 1)} then { + configure_entry .menu19.config.f.x1 normal {n l y}} else {configure_entry .menu19.config.f.x1 disabled {y n l}} + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then {configure_entry .menu19.config.f.x2 normal {x l}} else {configure_entry .menu19.config.f.x2 disabled {x l}} + global CONFIG_LEON3FT_PRESENT + global CONFIG_GRETH_FT + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_LEON3FT_PRESENT == 1)} then { + configure_entry .menu19.config.f.x3 normal {n l y}} else {configure_entry .menu19.config.f.x3 disabled {y n l}} + global CONFIG_GRETH_EDCLFT + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_GRETH_FT == 1)} then { + configure_entry .menu19.config.f.x4 normal {n l y}} else {configure_entry .menu19.config.f.x4 disabled {y n l}} +} + + +proc update_define_menu19 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_GRETH_ENABLE + global CONFIG_GRETH_GIGA + if {($CONFIG_GRETH_ENABLE == 1)} then { + set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA&15]} else {set CONFIG_GRETH_GIGA [expr $CONFIG_GRETH_GIGA|16]} + global tmpvar_30 + global CONFIG_GRETH_FIFO4 + if {$tmpvar_30 == "4"} then {set CONFIG_GRETH_FIFO4 1} else {set CONFIG_GRETH_FIFO4 0} + global CONFIG_GRETH_FIFO8 + if {$tmpvar_30 == "8"} then {set CONFIG_GRETH_FIFO8 1} else {set CONFIG_GRETH_FIFO8 0} + global CONFIG_GRETH_FIFO16 + if {$tmpvar_30 == "16"} then {set CONFIG_GRETH_FIFO16 1} else {set CONFIG_GRETH_FIFO16 0} + global CONFIG_GRETH_FIFO32 + if {$tmpvar_30 == "32"} then {set CONFIG_GRETH_FIFO32 1} else {set CONFIG_GRETH_FIFO32 0} + global CONFIG_GRETH_FIFO64 + if {$tmpvar_30 == "64"} then {set CONFIG_GRETH_FIFO64 1} else {set CONFIG_GRETH_FIFO64 0} + global CONFIG_LEON3FT_PRESENT + global CONFIG_GRETH_FT + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_LEON3FT_PRESENT == 1)} then { + set CONFIG_GRETH_FT [expr $CONFIG_GRETH_FT&15]} else {set CONFIG_GRETH_FT [expr $CONFIG_GRETH_FT|16]} + global CONFIG_GRETH_EDCLFT + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_GRETH_FT == 1)} then { + set CONFIG_GRETH_EDCLFT [expr $CONFIG_GRETH_EDCLFT&15]} else {set CONFIG_GRETH_EDCLFT [expr $CONFIG_GRETH_EDCLFT|16]} +} + + +proc menu20 {w title} { + set oldFocus [focus] + catch {focus .menu13} + catch {destroy $w; unregister_active 20} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 20]] + message $w.m -width 400 -aspect 300 -text \ + "UARTs, timers and irq control " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "UARTs, timers and irq control " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu21 .menu21 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 20; menu19 .menu19 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 20 0 "Enable console UART " CONFIG_UART1_ENABLE + global tmpvar_31 + minimenu $w.config.f 20 1 "UART1 FIFO depth" tmpvar_31 CONFIG_UA1_FIFO1 + menu $w.config.f.x1.x.menu -tearoffcommand "menutitle \"UART1 FIFO depth\"" + $w.config.f.x1.x.menu add radiobutton -label "1" -variable tmpvar_31 -value "1" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "2" -variable tmpvar_31 -value "2" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "4" -variable tmpvar_31 -value "4" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "8" -variable tmpvar_31 -value "8" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "16" -variable tmpvar_31 -value "16" -command "update_active" + $w.config.f.x1.x.menu add radiobutton -label "32" -variable tmpvar_31 -value "32" -command "update_active" + menusplit $w $w.config.f.x1.x.menu 6 + bool $w.config.f 20 2 "Enable LEON3 interrupt controller " CONFIG_IRQ3_ENABLE + bool $w.config.f 20 3 "Enable secondary interrupts " CONFIG_IRQ3_SEC + int $w.config.f 20 4 "Secondary interrupt number (1 - 15) " CONFIG_IRQ3_NSEC + bool $w.config.f 20 5 "Enable Timer Unit " CONFIG_GPT_ENABLE + int $w.config.f 20 6 "Number of timers (1 - 7) " CONFIG_GPT_NTIM + int $w.config.f 20 7 "Scaler width (2 - 16) " CONFIG_GPT_SW + int $w.config.f 20 8 "Timer width (2 - 32) " CONFIG_GPT_TW + int $w.config.f 20 9 "Timer unit interrupt " CONFIG_GPT_IRQ + bool $w.config.f 20 10 "Separate interrupts " CONFIG_GPT_SEPIRQ + bool $w.config.f 20 11 "Watchdog enable " CONFIG_GPT_WDOGEN + hex $w.config.f 20 12 "Initial watchdog time-out value " CONFIG_GPT_WDOG + bool $w.config.f 20 13 "Enable generic GPIO port " CONFIG_GRGPIO_ENABLE + int $w.config.f 20 14 "GPIO width " CONFIG_GRGPIO_WIDTH + hex $w.config.f 20 15 "GPIO interrupt mask " CONFIG_GRGPIO_IMASK + bool $w.config.f 20 16 "Enable I2C master " CONFIG_I2C_ENABLE + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} + set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu20 {} { + global CONFIG_UART1_ENABLE + if {($CONFIG_UART1_ENABLE == 1)} then {configure_entry .menu20.config.f.x1 normal {x l}} else {configure_entry .menu20.config.f.x1 disabled {x l}} + global CONFIG_IRQ3_ENABLE + global CONFIG_IRQ3_SEC + if {($CONFIG_IRQ3_ENABLE == 1)} then { + configure_entry .menu20.config.f.x3 normal {n l y}} else {configure_entry .menu20.config.f.x3 disabled {y n l}} + global CONFIG_IRQ3_NSEC + if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {.menu20.config.f.x4.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x4.l configure -state normal; } else {.menu20.config.f.x4.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x4.l configure -state disabled} + global CONFIG_GPT_ENABLE + global CONFIG_GPT_NTIM + if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x6.l configure -state normal; } else {.menu20.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x6.l configure -state disabled} + global CONFIG_GPT_SW + if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x7.l configure -state normal; } else {.menu20.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x7.l configure -state disabled} + global CONFIG_GPT_TW + if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x8.l configure -state normal; } else {.menu20.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x8.l configure -state disabled} + global CONFIG_GPT_IRQ + if {($CONFIG_GPT_ENABLE == 1)} then {.menu20.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x9.l configure -state normal; } else {.menu20.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x9.l configure -state disabled} + global CONFIG_GPT_SEPIRQ + if {($CONFIG_GPT_ENABLE == 1)} then { + configure_entry .menu20.config.f.x10 normal {n l y}} else {configure_entry .menu20.config.f.x10 disabled {y n l}} + global CONFIG_GPT_WDOGEN + if {($CONFIG_GPT_ENABLE == 1)} then { + configure_entry .menu20.config.f.x11 normal {n l y}} else {configure_entry .menu20.config.f.x11 disabled {y n l}} + global CONFIG_GPT_WDOG + if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {.menu20.config.f.x12.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x12.l configure -state normal; } else {.menu20.config.f.x12.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x12.l configure -state disabled} + global CONFIG_GRGPIO_ENABLE + global CONFIG_GRGPIO_WIDTH + if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu20.config.f.x14.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x14.l configure -state normal; } else {.menu20.config.f.x14.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x14.l configure -state disabled} + global CONFIG_GRGPIO_IMASK + if {($CONFIG_GRGPIO_ENABLE == 1)} then {.menu20.config.f.x15.x configure -state normal -foreground [ cget .ref -foreground ]; .menu20.config.f.x15.l configure -state normal; } else {.menu20.config.f.x15.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu20.config.f.x15.l configure -state disabled} +} + + +proc update_define_menu20 {} { + update_define_mainmenu + global CONFIG_MODULES + global tmpvar_31 + global CONFIG_UA1_FIFO1 + if {$tmpvar_31 == "1"} then {set CONFIG_UA1_FIFO1 1} else {set CONFIG_UA1_FIFO1 0} + global CONFIG_UA1_FIFO2 + if {$tmpvar_31 == "2"} then {set CONFIG_UA1_FIFO2 1} else {set CONFIG_UA1_FIFO2 0} + global CONFIG_UA1_FIFO4 + if {$tmpvar_31 == "4"} then {set CONFIG_UA1_FIFO4 1} else {set CONFIG_UA1_FIFO4 0} + global CONFIG_UA1_FIFO8 + if {$tmpvar_31 == "8"} then {set CONFIG_UA1_FIFO8 1} else {set CONFIG_UA1_FIFO8 0} + global CONFIG_UA1_FIFO16 + if {$tmpvar_31 == "16"} then {set CONFIG_UA1_FIFO16 1} else {set CONFIG_UA1_FIFO16 0} + global CONFIG_UA1_FIFO32 + if {$tmpvar_31 == "32"} then {set CONFIG_UA1_FIFO32 1} else {set CONFIG_UA1_FIFO32 0} + global CONFIG_IRQ3_ENABLE + global CONFIG_IRQ3_SEC + if {($CONFIG_IRQ3_ENABLE == 1)} then { + set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC&15]} else {set CONFIG_IRQ3_SEC [expr $CONFIG_IRQ3_SEC|16]} + global CONFIG_IRQ3_NSEC + if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {validate_int CONFIG_IRQ3_NSEC "$CONFIG_IRQ3_NSEC" 12} + global CONFIG_GPT_ENABLE + global CONFIG_GPT_NTIM + if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_NTIM "$CONFIG_GPT_NTIM" 2} + global CONFIG_GPT_SW + if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_SW "$CONFIG_GPT_SW" 8} + global CONFIG_GPT_TW + if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_TW "$CONFIG_GPT_TW" 32} + global CONFIG_GPT_IRQ + if {($CONFIG_GPT_ENABLE == 1)} then {validate_int CONFIG_GPT_IRQ "$CONFIG_GPT_IRQ" 8} + global CONFIG_GPT_SEPIRQ + if {($CONFIG_GPT_ENABLE == 1)} then { + set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ&15]} else {set CONFIG_GPT_SEPIRQ [expr $CONFIG_GPT_SEPIRQ|16]} + global CONFIG_GPT_WDOGEN + if {($CONFIG_GPT_ENABLE == 1)} then { + set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN&15]} else {set CONFIG_GPT_WDOGEN [expr $CONFIG_GPT_WDOGEN|16]} + global CONFIG_GPT_WDOG + if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {validate_hex CONFIG_GPT_WDOG "$CONFIG_GPT_WDOG" FFFF} + global CONFIG_GRGPIO_ENABLE + global CONFIG_GRGPIO_WIDTH + if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_int CONFIG_GRGPIO_WIDTH "$CONFIG_GRGPIO_WIDTH" 8} + global CONFIG_GRGPIO_IMASK + if {($CONFIG_GRGPIO_ENABLE == 1)} then {validate_hex CONFIG_GRGPIO_IMASK "$CONFIG_GRGPIO_IMASK" 0000} +} + + +proc menu21 {w title} { + set oldFocus [focus] + catch {focus .menu13} + catch {destroy $w; unregister_active 21} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 21]] + message $w.m -width 400 -aspect 300 -text \ + "Keybord and VGA interface" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "Keybord and VGA interface" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu22 .menu22 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 21; menu20 .menu20 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 21 0 "Keyboard/mouse (PS2) interface " CONFIG_KBD_ENABLE + bool $w.config.f 21 1 "Text-based VGA interface " CONFIG_VGA_ENABLE + bool $w.config.f 21 2 "SVGA graphical frame buffer " CONFIG_SVGA_ENABLE + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} + set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu21 {} { + global CONFIG_VGA_ENABLE + global CONFIG_SVGA_ENABLE + if {($CONFIG_VGA_ENABLE == 0)} then { + configure_entry .menu21.config.f.x2 normal {n l y}} else {configure_entry .menu21.config.f.x2 disabled {y n l}} +} + + +proc update_define_menu21 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_VGA_ENABLE + global CONFIG_SVGA_ENABLE + if {($CONFIG_VGA_ENABLE == 0)} then { + set CONFIG_SVGA_ENABLE [expr $CONFIG_SVGA_ENABLE&15]} else {set CONFIG_SVGA_ENABLE [expr $CONFIG_SVGA_ENABLE|16]} +} + + +proc menu22 {w title} { + set oldFocus [focus] + catch {focus .menu13} + catch {destroy $w; unregister_active 22} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 22]] + message $w.m -width 400 -aspect 300 -text \ + "SPI" -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "SPI" + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; break" + set nextscript "catch {focus $oldFocus}; menu23 .menu23 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 22; menu21 .menu21 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + submenu $w.config.f 22 0 "SPI memory controller " 23 + submenu $w.config.f 22 1 "SPI controller(s) " 24 + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu13] == 0} then {menu13 .menu13 "Peripherals "} + set winx [expr [winfo x .menu13]+30]; set winy [expr [winfo y .menu13]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu22 {} { +} + + +proc update_define_menu22 {} { + update_define_mainmenu + global CONFIG_MODULES +} + + +proc menu23 {w title} { + set oldFocus [focus] + catch {focus .menu22} + catch {destroy $w; unregister_active 23} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 23]] + message $w.m -width 400 -aspect 300 -text \ + "SPI memory controller " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "SPI memory controller " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu24 .menu24 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 23; menu22 .menu22 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 23 0 "Enable SPI memory controller " CONFIG_SPIMCTRL + bool $w.config.f 23 1 "Enable SD card support " CONFIG_SPIMCTRL_SDCARD + hex $w.config.f 23 2 "Read instruction " CONFIG_SPIMCTRL_READCMD + bool $w.config.f 23 3 "Read instruction requires dummy byte " CONFIG_SPIMCTRL_DUMMYBYTE + bool $w.config.f 23 4 "Enable dual output for reads " CONFIG_SPIMCTRL_DUALOUTPUT + hex $w.config.f 23 5 "Address offset " CONFIG_SPIMCTRL_OFFSET + int $w.config.f 23 6 "Clock divisor for device clock" CONFIG_SPIMCTRL_SCALER + int $w.config.f 23 7 "Clock divisor for alt. device clock" CONFIG_SPIMCTRL_ASCALER + int $w.config.f 23 8 "Number of clock cycles to idle after power up " CONFIG_SPIMCTRL_PWRUPCNT + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu22] == 0} then {menu22 .menu22 "SPI"} + set winx [expr [winfo x .menu22]+30]; set winy [expr [winfo y .menu22]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu23 {} { + global CONFIG_SPIMCTRL + global CONFIG_SPIMCTRL_SDCARD + if {($CONFIG_SPIMCTRL == 1)} then { + configure_entry .menu23.config.f.x1 normal {n l y}} else {configure_entry .menu23.config.f.x1 disabled {y n l}} + global CONFIG_SPIMCTRL_READCMD + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {.menu23.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x2.l configure -state normal; } else {.menu23.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x2.l configure -state disabled} + global CONFIG_SPIMCTRL_DUMMYBYTE + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then { + configure_entry .menu23.config.f.x3 normal {n l y}} else {configure_entry .menu23.config.f.x3 disabled {y n l}} + global CONFIG_SPIMCTRL_DUALOUTPUT + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then { + configure_entry .menu23.config.f.x4 normal {n l y}} else {configure_entry .menu23.config.f.x4 disabled {y n l}} + global CONFIG_SPIMCTRL_OFFSET + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {.menu23.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x5.l configure -state normal; } else {.menu23.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x5.l configure -state disabled} + global CONFIG_SPIMCTRL_SCALER + if {($CONFIG_SPIMCTRL == 1)} then {.menu23.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x6.l configure -state normal; } else {.menu23.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x6.l configure -state disabled} + global CONFIG_SPIMCTRL_ASCALER + if {($CONFIG_SPIMCTRL == 1)} then {.menu23.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x7.l configure -state normal; } else {.menu23.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x7.l configure -state disabled} + global CONFIG_SPIMCTRL_PWRUPCNT + if {($CONFIG_SPIMCTRL == 1)} then {.menu23.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu23.config.f.x8.l configure -state normal; } else {.menu23.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu23.config.f.x8.l configure -state disabled} +} + + +proc update_define_menu23 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_SPIMCTRL + global CONFIG_SPIMCTRL_SDCARD + if {($CONFIG_SPIMCTRL == 1)} then { + set CONFIG_SPIMCTRL_SDCARD [expr $CONFIG_SPIMCTRL_SDCARD&15]} else {set CONFIG_SPIMCTRL_SDCARD [expr $CONFIG_SPIMCTRL_SDCARD|16]} + global CONFIG_SPIMCTRL_READCMD + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {validate_hex CONFIG_SPIMCTRL_READCMD "$CONFIG_SPIMCTRL_READCMD" 0B} + global CONFIG_SPIMCTRL_DUMMYBYTE + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then { + set CONFIG_SPIMCTRL_DUMMYBYTE [expr $CONFIG_SPIMCTRL_DUMMYBYTE&15]} else {set CONFIG_SPIMCTRL_DUMMYBYTE [expr $CONFIG_SPIMCTRL_DUMMYBYTE|16]} + global CONFIG_SPIMCTRL_DUALOUTPUT + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then { + set CONFIG_SPIMCTRL_DUALOUTPUT [expr $CONFIG_SPIMCTRL_DUALOUTPUT&15]} else {set CONFIG_SPIMCTRL_DUALOUTPUT [expr $CONFIG_SPIMCTRL_DUALOUTPUT|16]} + global CONFIG_SPIMCTRL_OFFSET + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {validate_hex CONFIG_SPIMCTRL_OFFSET "$CONFIG_SPIMCTRL_OFFSET" 0} + global CONFIG_SPIMCTRL_SCALER + if {($CONFIG_SPIMCTRL == 1)} then {validate_int CONFIG_SPIMCTRL_SCALER "$CONFIG_SPIMCTRL_SCALER" 1} + global CONFIG_SPIMCTRL_ASCALER + if {($CONFIG_SPIMCTRL == 1)} then {validate_int CONFIG_SPIMCTRL_ASCALER "$CONFIG_SPIMCTRL_ASCALER" 8} + global CONFIG_SPIMCTRL_PWRUPCNT + if {($CONFIG_SPIMCTRL == 1)} then {validate_int CONFIG_SPIMCTRL_PWRUPCNT "$CONFIG_SPIMCTRL_PWRUPCNT" 0} +} + + +proc menu24 {w title} { + set oldFocus [focus] + catch {focus .menu22} + catch {destroy $w; unregister_active 24} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 24]] + message $w.m -width 400 -aspect 300 -text \ + "SPI controller(s) " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "SPI controller(s) " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; break" + set nextscript "catch {focus $oldFocus}; destroy $w; unregister_active 24; catch {destroy .menu22}; unregister_active 22; catch {destroy .menu13}; unregister_active 13; menu25 .menu25 \"$title\"" + frame $w.f + button $w.f.back -text "OK" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + bind all $nextscript + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 24; menu23 .menu23 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 24 0 "Enable SPI controller(s) " CONFIG_SPICTRL_ENABLE + int $w.config.f 24 1 "Number of SPI controllers " CONFIG_SPICTRL_NUM + int $w.config.f 24 2 "Slave select lines " CONFIG_SPICTRL_SLVS + int $w.config.f 24 3 "FIFO depth (2^N) " CONFIG_SPICTRL_FIFO + bool $w.config.f 24 4 "Enable slave select registers" CONFIG_SPICTRL_SLVREG + bool $w.config.f 24 5 "Enable automatic slave select" CONFIG_SPICTRL_ASEL + bool $w.config.f 24 6 "Support automated transfers " CONFIG_SPICTRL_AM + bool $w.config.f 24 7 "Support open drain mode " CONFIG_SPICTRL_ODMODE + bool $w.config.f 24 8 "Support three-wire mode " CONFIG_SPICTRL_TWEN + int $w.config.f 24 9 "Maximum supported word length (see help!) " CONFIG_SPICTRL_MAXWLEN + bool $w.config.f 24 10 "Use SYNCRAM for rx and tx queues " CONFIG_SPICTRL_SYNCRAM + global tmpvar_32 + minimenu $w.config.f 24 11 "Fault-tolerance" tmpvar_32 CONFIG_SPICTRL_NOFT + menu $w.config.f.x11.x.menu -tearoffcommand "menutitle \"Fault-tolerance\"" + $w.config.f.x11.x.menu add radiobutton -label "None" -variable tmpvar_32 -value "None" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "Parity-DMR" -variable tmpvar_32 -value "Parity-DMR" -command "update_active" + $w.config.f.x11.x.menu add radiobutton -label "TMR" -variable tmpvar_32 -value "TMR" -command "update_active" + menusplit $w $w.config.f.x11.x.menu 3 + + + + focus $w + update_active + global winx; global winy + if {[winfo exists .menu22] == 0} then {menu22 .menu22 "SPI"} + set winx [expr [winfo x .menu22]+30]; set winy [expr [winfo y .menu22]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu24 {} { + global CONFIG_SPICTRL_ENABLE + global CONFIG_SPICTRL_NUM + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu24.config.f.x1.x configure -state normal -foreground [ cget .ref -foreground ]; .menu24.config.f.x1.l configure -state normal; } else {.menu24.config.f.x1.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu24.config.f.x1.l configure -state disabled} + global CONFIG_SPICTRL_SLVS + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu24.config.f.x2.x configure -state normal -foreground [ cget .ref -foreground ]; .menu24.config.f.x2.l configure -state normal; } else {.menu24.config.f.x2.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu24.config.f.x2.l configure -state disabled} + global CONFIG_SPICTRL_FIFO + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu24.config.f.x3.x configure -state normal -foreground [ cget .ref -foreground ]; .menu24.config.f.x3.l configure -state normal; } else {.menu24.config.f.x3.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu24.config.f.x3.l configure -state disabled} + global CONFIG_SPICTRL_SLVREG + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + configure_entry .menu24.config.f.x4 normal {n l y}} else {configure_entry .menu24.config.f.x4 disabled {y n l}} + global CONFIG_SPICTRL_ASEL + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + configure_entry .menu24.config.f.x5 normal {n l y}} else {configure_entry .menu24.config.f.x5 disabled {y n l}} + global CONFIG_SPICTRL_AM + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + configure_entry .menu24.config.f.x6 normal {n l y}} else {configure_entry .menu24.config.f.x6 disabled {y n l}} + global CONFIG_SPICTRL_ODMODE + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + configure_entry .menu24.config.f.x7 normal {n l y}} else {configure_entry .menu24.config.f.x7 disabled {y n l}} + global CONFIG_SPICTRL_TWEN + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + configure_entry .menu24.config.f.x8 normal {n l y}} else {configure_entry .menu24.config.f.x8 disabled {y n l}} + global CONFIG_SPICTRL_MAXWLEN + if {($CONFIG_SPICTRL_ENABLE == 1)} then {.menu24.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu24.config.f.x9.l configure -state normal; } else {.menu24.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu24.config.f.x9.l configure -state disabled} + global CONFIG_SPICTRL_SYNCRAM + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + configure_entry .menu24.config.f.x10 normal {n l y}} else {configure_entry .menu24.config.f.x10 disabled {y n l}} + if {($CONFIG_SPICTRL_ENABLE == 1) && ($CONFIG_SPICTRL_SYNCRAM == 1)} then {configure_entry .menu24.config.f.x11 normal {x l}} else {configure_entry .menu24.config.f.x11 disabled {x l}} +} + + +proc update_define_menu24 {} { + update_define_mainmenu + global CONFIG_MODULES + global CONFIG_SPICTRL_ENABLE + global CONFIG_SPICTRL_NUM + if {($CONFIG_SPICTRL_ENABLE == 1)} then {validate_int CONFIG_SPICTRL_NUM "$CONFIG_SPICTRL_NUM" 1} + global CONFIG_SPICTRL_SLVS + if {($CONFIG_SPICTRL_ENABLE == 1)} then {validate_int CONFIG_SPICTRL_SLVS "$CONFIG_SPICTRL_SLVS" 1} + global CONFIG_SPICTRL_FIFO + if {($CONFIG_SPICTRL_ENABLE == 1)} then {validate_int CONFIG_SPICTRL_FIFO "$CONFIG_SPICTRL_FIFO" 1} + global CONFIG_SPICTRL_SLVREG + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + set CONFIG_SPICTRL_SLVREG [expr $CONFIG_SPICTRL_SLVREG&15]} else {set CONFIG_SPICTRL_SLVREG [expr $CONFIG_SPICTRL_SLVREG|16]} + global CONFIG_SPICTRL_ASEL + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + set CONFIG_SPICTRL_ASEL [expr $CONFIG_SPICTRL_ASEL&15]} else {set CONFIG_SPICTRL_ASEL [expr $CONFIG_SPICTRL_ASEL|16]} + global CONFIG_SPICTRL_AM + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + set CONFIG_SPICTRL_AM [expr $CONFIG_SPICTRL_AM&15]} else {set CONFIG_SPICTRL_AM [expr $CONFIG_SPICTRL_AM|16]} + global CONFIG_SPICTRL_ODMODE + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + set CONFIG_SPICTRL_ODMODE [expr $CONFIG_SPICTRL_ODMODE&15]} else {set CONFIG_SPICTRL_ODMODE [expr $CONFIG_SPICTRL_ODMODE|16]} + global CONFIG_SPICTRL_TWEN + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + set CONFIG_SPICTRL_TWEN [expr $CONFIG_SPICTRL_TWEN&15]} else {set CONFIG_SPICTRL_TWEN [expr $CONFIG_SPICTRL_TWEN|16]} + global CONFIG_SPICTRL_MAXWLEN + if {($CONFIG_SPICTRL_ENABLE == 1)} then {validate_int CONFIG_SPICTRL_MAXWLEN "$CONFIG_SPICTRL_MAXWLEN" 0} + global CONFIG_SPICTRL_SYNCRAM + if {($CONFIG_SPICTRL_ENABLE == 1)} then { + set CONFIG_SPICTRL_SYNCRAM [expr $CONFIG_SPICTRL_SYNCRAM&15]} else {set CONFIG_SPICTRL_SYNCRAM [expr $CONFIG_SPICTRL_SYNCRAM|16]} + global tmpvar_32 + global CONFIG_SPICTRL_NOFT + if {$tmpvar_32 == "None"} then {set CONFIG_SPICTRL_NOFT 1} else {set CONFIG_SPICTRL_NOFT 0} + global CONFIG_SPICTRL_DMRFT + if {$tmpvar_32 == "Parity-DMR"} then {set CONFIG_SPICTRL_DMRFT 1} else {set CONFIG_SPICTRL_DMRFT 0} + global CONFIG_SPICTRL_TMRFT + if {$tmpvar_32 == "TMR"} then {set CONFIG_SPICTRL_TMRFT 1} else {set CONFIG_SPICTRL_TMRFT 0} +} + + +menu_option menu25 25 "VHDL Debugging " +proc menu25 {w title} { + set oldFocus [focus] + catch {destroy $w; unregister_active 25} + toplevel $w -class Dialog + wm withdraw $w + global active_menus + set active_menus [lsort -integer [linsert $active_menus end 25]] + message $w.m -width 400 -aspect 300 -text \ + "VHDL Debugging " -relief raised + pack $w.m -pady 10 -side top -padx 10 + wm title $w "VHDL Debugging " + + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 25; break" + set nextscript "catch {focus $oldFocus}; menu26 .menu26 \"$title\"" + frame $w.f + button $w.f.back -text "Main Menu" \ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 25" + button $w.f.next -text "Next" -underline 0\ + -width 15 -command $nextscript + $w.f.next configure -state disabled + bind all "puts \"no more menus\" " + button $w.f.prev -text "Prev" -underline 0\ + -width 15 -command "catch {focus $oldFocus}; destroy $w; unregister_active 25; menu24 .menu24 \"$title\"" + bind $w "catch {focus $oldFocus}; destroy $w; unregister_active 25; menu24 .menu24 \"$title\";break" + pack $w.f.back $w.f.next $w.f.prev -side left -expand on + pack $w.f -pady 10 -side bottom -anchor w -fill x + frame $w.topline -relief ridge -borderwidth 2 -height 2 + pack $w.topline -side top -fill x + + frame $w.botline -relief ridge -borderwidth 2 -height 2 + pack $w.botline -side bottom -fill x + + frame $w.config + pack $w.config -fill y -expand on + + scrollbar $w.config.vscroll -command "$w.config.canvas yview" + pack $w.config.vscroll -side right -fill y + + canvas $w.config.canvas -height 1\ + -relief flat -borderwidth 0 -yscrollcommand "$w.config.vscroll set" \ + -width [expr [winfo screenwidth .] * 1 / 2] + frame $w.config.f + bind $w "$w.config.canvas yview scroll 1 unit;break;" + bind $w "$w.config.canvas yview scroll -1 unit;break;" + bind $w "$w.config.canvas yview scroll 1 page;break;" + bind $w "$w.config.canvas yview scroll -1 page;break;" + bind $w "$w.config.canvas yview moveto 0;break;" + bind $w "$w.config.canvas yview moveto 1 ;break;" + pack $w.config.canvas -side right -fill y + + + bool $w.config.f 25 0 "Accelerated UART tracing " CONFIG_DEBUG_UART + + + + focus $w + update_active + global winx; global winy + set winx [expr [winfo x .]+30]; set winy [expr [winfo y .]+30] + if {[winfo exists $w]} then {wm geometry $w +$winx+$winy} + update idletasks + if {[winfo exists $w]} then {$w.config.canvas create window 0 0 -anchor nw -window $w.config.f + + $w.config.canvas configure \ + -width [expr [winfo reqwidth $w.config.f] + 1]\ + -scrollregion "-1 -1 [expr [winfo reqwidth $w.config.f] + 1] \ + [expr [winfo reqheight $w.config.f] + 1]" + + set winy [expr [winfo reqh $w] - [winfo reqh $w.config.canvas]] + set scry [expr [winfo screenh $w] / 2] + set maxy [expr [winfo screenh $w] * 3 / 4] + set canvtotal [expr [winfo reqh $w.config.f] + 2] + if [expr $winy + $canvtotal < $maxy] { + $w.config.canvas configure -height $canvtotal + } else { + $w.config.canvas configure -height [expr $scry - $winy] + } + } + update idletasks + if {[winfo exists $w]} then { + wm maxsize $w [winfo width $w] [winfo screenheight $w] + wm minsize $w [winfo width $w] 100 + + wm deiconify $w +} +} + +proc update_menu25 {} { +} + + +proc update_define_menu25 {} { + update_define_mainmenu + global CONFIG_MODULES +} + + +proc update_mainmenu {} { +} + + +set tmpvar_0 "(not set)" +set CONFIG_SYN_INFERRED 0 +set CONFIG_SYN_STRATIX 0 +set CONFIG_SYN_STRATIXII 0 +set CONFIG_SYN_STRATIXIII 0 +set CONFIG_SYN_STRATIXIV 0 +set CONFIG_SYN_CYCLONEIII 0 +set CONFIG_SYN_ALTERA 0 +set CONFIG_SYN_AXCEL 0 +set CONFIG_SYN_AXDSP 0 +set CONFIG_SYN_PROASIC 0 +set CONFIG_SYN_PROASICPLUS 0 +set CONFIG_SYN_PROASIC3 0 +set CONFIG_SYN_PROASIC3E 0 +set CONFIG_SYN_PROASIC3L 0 +set CONFIG_SYN_IGLOO 0 +set CONFIG_SYN_FUSION 0 +set CONFIG_SYN_UT025CRH 0 +set CONFIG_SYN_UT130HBD 0 +set CONFIG_SYN_UT90NHBD 0 +set CONFIG_SYN_ATC18 0 +set CONFIG_SYN_ATC18RHA 0 +set CONFIG_SYN_CMOS9SF 0 +set CONFIG_SYN_CUSTOM1 0 +set CONFIG_SYN_EASIC90 0 +set CONFIG_SYN_EASIC45 0 +set CONFIG_SYN_IHP25 0 +set CONFIG_SYN_IHP25RH 0 +set CONFIG_SYN_LATTICE 0 +set CONFIG_SYN_ECLIPSE 0 +set CONFIG_SYN_PEREGRINE 0 +set CONFIG_SYN_RH_LIB18T 0 +set CONFIG_SYN_RHUMC 0 +set CONFIG_SYN_SAED32 0 +set CONFIG_SYN_DARE 0 +set CONFIG_SYN_SMIC13 0 +set CONFIG_SYN_TM65GPLUS 0 +set CONFIG_SYN_TSMC90 0 +set CONFIG_SYN_UMC 0 +set CONFIG_SYN_ARTIX7 0 +set CONFIG_SYN_KINTEX7 0 +set CONFIG_SYN_SPARTAN3 0 +set CONFIG_SYN_SPARTAN3E 0 +set CONFIG_SYN_SPARTAN6 0 +set CONFIG_SYN_VIRTEXE 0 +set CONFIG_SYN_VIRTEX2 0 +set CONFIG_SYN_VIRTEX4 0 +set CONFIG_SYN_VIRTEX5 0 +set CONFIG_SYN_VIRTEX6 0 +set CONFIG_SYN_VIRTEX7 0 +set CONFIG_SYN_ZYNQ7000 0 +set tmpvar_1 "(not set)" +set CONFIG_MEM_INFERRED 0 +set CONFIG_MEM_UMC 0 +set CONFIG_MEM_RHUMC 0 +set CONFIG_MEM_SAED32 0 +set CONFIG_MEM_DARE 0 +set CONFIG_MEM_ARTISAN 0 +set CONFIG_MEM_CUSTOM1 0 +set CONFIG_MEM_EASIC45 0 +set CONFIG_MEM_VIRAGE 0 +set CONFIG_MEM_VIRAGE90 0 +set CONFIG_SYN_INFER_RAM 0 +set CONFIG_SYN_INFER_PADS 0 +set CONFIG_SYN_NO_ASYNC 0 +set CONFIG_SYN_SCAN 0 +set tmpvar_2 "(not set)" +set CONFIG_CLK_INFERRED 0 +set CONFIG_CLK_HCLKBUF 0 +set CONFIG_CLK_UT130HBD 0 +set CONFIG_CLK_ALTDLL 0 +set CONFIG_CLK_LATDLL 0 +set CONFIG_CLK_PRO3PLL 0 +set CONFIG_CLK_PRO3EPLL 0 +set CONFIG_CLK_PRO3LPLL 0 +set CONFIG_CLK_FUSPLL 0 +set CONFIG_CLK_LIB18T 0 +set CONFIG_CLK_RHUMC 0 +set CONFIG_CLK_DARE 0 +set CONFIG_CLK_SAED32 0 +set CONFIG_CLK_EASIC45 0 +set CONFIG_CLK_CLKPLLE2 0 +set CONFIG_CLK_CLKDLL 0 +set CONFIG_CLK_DCM 0 +set CONFIG_CLK_MUL 2 +set CONFIG_CLK_DIV 2 +set CONFIG_OCLK_DIV 1 +set CONFIG_OCLKB_DIV 0 +set CONFIG_OCLKC_DIV 0 +set CONFIG_PCI_CLKDLL 0 +set CONFIG_CLK_NOFB 0 +set CONFIG_PCI_SYSCLK 0 +set CONFIG_LEON3 0 +set CONFIG_PROC_NUM 1 +set tmpvar_3 "(not set)" +set CONFIG_LEON3_MIN 0 +set CONFIG_LEON3_GP 0 +set CONFIG_LEON3_HP 0 +set CONFIG_LEON3_CUSTOM 0 +set CONFIG_IU_NWINDOWS 8 +set CONFIG_IU_V8MULDIV 0 +set tmpvar_4 "(not set)" +set CONFIG_IU_MUL_LATENCY_2 0 +set CONFIG_IU_MUL_LATENCY_4 0 +set CONFIG_IU_MUL_LATENCY_5 0 +set CONFIG_IU_MUL_MAC 0 +set tmpvar_5 "(not set)" +set CONFIG_IU_MUL_INFERRED 0 +set CONFIG_IU_MUL_MODGEN 0 +set CONFIG_IU_MUL_TECHSPEC 0 +set CONFIG_IU_MUL_DW 0 +set CONFIG_IU_BP 0 +set CONFIG_IU_SVT 0 +set CONFIG_NOTAG 0 +set CONFIG_IU_LDELAY 1 +set CONFIG_IU_WATCHPOINTS 0 +set CONFIG_PWD 0 +set CONFIG_IU_RSTADDR 00000 +set CONFIG_FPU_ENABLE 0 +set tmpvar_6 "(not set)" +set CONFIG_FPU_GRFPU 0 +set CONFIG_FPU_GRFPULITE 0 +set CONFIG_FPU_MEIKO 0 +set tmpvar_7 "(not set)" +set CONFIG_FPU_GRFPU_INFMUL 0 +set CONFIG_FPU_GRFPU_DWMUL 0 +set CONFIG_FPU_GRFPU_MODGEN 0 +set CONFIG_FPU_GRFPU_TECHSPEC 0 +set CONFIG_FPU_GRFPU_SH 0 +set tmpvar_8 "(not set)" +set CONFIG_FPU_GRFPC0 0 +set CONFIG_FPU_GRFPC1 0 +set CONFIG_FPU_GRFPC2 0 +set CONFIG_ICACHE_ENABLE 0 +set tmpvar_9 "(not set)" +set CONFIG_ICACHE_ASSO1 0 +set CONFIG_ICACHE_ASSO2 0 +set CONFIG_ICACHE_ASSO3 0 +set CONFIG_ICACHE_ASSO4 0 +set tmpvar_10 "(not set)" +set CONFIG_ICACHE_SZ1 0 +set CONFIG_ICACHE_SZ2 0 +set CONFIG_ICACHE_SZ4 0 +set CONFIG_ICACHE_SZ8 0 +set CONFIG_ICACHE_SZ16 0 +set CONFIG_ICACHE_SZ32 0 +set CONFIG_ICACHE_SZ64 0 +set CONFIG_ICACHE_SZ128 0 +set CONFIG_ICACHE_SZ256 0 +set tmpvar_11 "(not set)" +set CONFIG_ICACHE_LZ16 0 +set CONFIG_ICACHE_LZ32 0 +set tmpvar_12 "(not set)" +set CONFIG_ICACHE_ALGORND 0 +set CONFIG_ICACHE_ALGODIR 0 +set CONFIG_ICACHE_ALGOLRR 0 +set CONFIG_ICACHE_ALGOLRU 0 +set CONFIG_ICACHE_LOCK 0 +set CONFIG_ICACHE_LRAM 0 +set tmpvar_13 "(not set)" +set CONFIG_ICACHE_LRAM_SZ1 0 +set CONFIG_ICACHE_LRAM_SZ2 0 +set CONFIG_ICACHE_LRAM_SZ4 0 +set CONFIG_ICACHE_LRAM_SZ8 0 +set CONFIG_ICACHE_LRAM_SZ16 0 +set CONFIG_ICACHE_LRAM_SZ32 0 +set CONFIG_ICACHE_LRAM_SZ64 0 +set CONFIG_ICACHE_LRAM_SZ128 0 +set CONFIG_ICACHE_LRAM_SZ256 0 +set CONFIG_ICACHE_LRSTART 8e +set CONFIG_DCACHE_ENABLE 0 +set tmpvar_14 "(not set)" +set CONFIG_DCACHE_ASSO1 0 +set CONFIG_DCACHE_ASSO2 0 +set CONFIG_DCACHE_ASSO3 0 +set CONFIG_DCACHE_ASSO4 0 +set tmpvar_15 "(not set)" +set CONFIG_DCACHE_SZ1 0 +set CONFIG_DCACHE_SZ2 0 +set CONFIG_DCACHE_SZ4 0 +set CONFIG_DCACHE_SZ8 0 +set CONFIG_DCACHE_SZ16 0 +set CONFIG_DCACHE_SZ32 0 +set CONFIG_DCACHE_SZ64 0 +set CONFIG_DCACHE_SZ128 0 +set CONFIG_DCACHE_SZ256 0 +set tmpvar_16 "(not set)" +set CONFIG_DCACHE_LZ16 0 +set CONFIG_DCACHE_LZ32 0 +set tmpvar_17 "(not set)" +set CONFIG_DCACHE_ALGORND 0 +set CONFIG_DCACHE_ALGODIR 0 +set CONFIG_DCACHE_ALGOLRR 0 +set CONFIG_DCACHE_ALGOLRU 0 +set CONFIG_DCACHE_LOCK 0 +set CONFIG_DCACHE_SNOOP 0 +set CONFIG_DCACHE_SNOOP_SEPTAG 0 +set CONFIG_CACHE_FIXED 0 +set CONFIG_DCACHE_LRAM 0 +set tmpvar_18 "(not set)" +set CONFIG_DCACHE_LRAM_SZ1 0 +set CONFIG_DCACHE_LRAM_SZ2 0 +set CONFIG_DCACHE_LRAM_SZ4 0 +set CONFIG_DCACHE_LRAM_SZ8 0 +set CONFIG_DCACHE_LRAM_SZ16 0 +set CONFIG_DCACHE_LRAM_SZ32 0 +set CONFIG_DCACHE_LRAM_SZ64 0 +set CONFIG_DCACHE_LRAM_SZ128 0 +set CONFIG_DCACHE_LRAM_SZ256 0 +set CONFIG_DCACHE_LRSTART 8f +set CONFIG_MMU_ENABLE 0 +set tmpvar_19 "(not set)" +set CONFIG_MMU_COMBINED 0 +set CONFIG_MMU_SPLIT 0 +set tmpvar_20 "(not set)" +set CONFIG_MMU_REPARRAY 0 +set CONFIG_MMU_REPINCREMENT 0 +set tmpvar_21 "(not set)" +set CONFIG_MMU_I2 0 +set CONFIG_MMU_I4 0 +set CONFIG_MMU_I8 0 +set CONFIG_MMU_I16 0 +set CONFIG_MMU_I32 0 +set CONFIG_MMU_I64 0 +set tmpvar_22 "(not set)" +set CONFIG_MMU_D2 0 +set CONFIG_MMU_D4 0 +set CONFIG_MMU_D8 0 +set CONFIG_MMU_D16 0 +set CONFIG_MMU_D32 0 +set CONFIG_MMU_D64 0 +set CONFIG_MMU_FASTWB 0 +set tmpvar_23 "(not set)" +set CONFIG_MMU_PAGE_4K 0 +set CONFIG_MMU_PAGE_8K 0 +set CONFIG_MMU_PAGE_16K 0 +set CONFIG_MMU_PAGE_32K 0 +set CONFIG_MMU_PAGE_PROG 0 +set CONFIG_DSU_ENABLE 0 +set CONFIG_DSU_ITRACE 0 +set tmpvar_24 "(not set)" +set CONFIG_DSU_ITRACESZ1 0 +set CONFIG_DSU_ITRACESZ2 0 +set CONFIG_DSU_ITRACESZ4 0 +set CONFIG_DSU_ITRACESZ8 0 +set CONFIG_DSU_ITRACESZ16 0 +set CONFIG_DSU_ATRACE 0 +set tmpvar_25 "(not set)" +set CONFIG_DSU_ATRACESZ1 0 +set CONFIG_DSU_ATRACESZ2 0 +set CONFIG_DSU_ATRACESZ4 0 +set CONFIG_DSU_ATRACESZ8 0 +set CONFIG_DSU_ATRACESZ16 0 +set CONFIG_LEON3FT_EN 0 +set tmpvar_26 "(not set)" +set CONFIG_IUFT_NONE 0 +set CONFIG_IUFT_PAR 0 +set CONFIG_IUFT_DMR 0 +set CONFIG_IUFT_BCH 0 +set CONFIG_IUFT_TMR 0 +set tmpvar_27 "(not set)" +set CONFIG_FPUFT_NONE 0 +set CONFIG_FPUFT_PAR 0 +set CONFIG_FPUFT_DMR 0 +set CONFIG_FPUFT_TMR 0 +set CONFIG_RF_ERRINJ 0 +set CONFIG_CACHE_FT_EN 0 +set CONFIG_CACHE_ERRINJ 0 +set CONFIG_IU_DISAS 0 +set CONFIG_IU_DISAS_NET 0 +set CONFIG_DEBUG_PC32 0 +set CONFIG_AHB_DEFMST 0 +set CONFIG_AHB_RROBIN 0 +set CONFIG_AHB_SPLIT 0 +set CONFIG_AHB_FPNPEN 0 +set CONFIG_AHB_IOADDR FFF +set CONFIG_APB_HADDR 800 +set CONFIG_AHB_MON 0 +set CONFIG_AHB_MONERR 0 +set CONFIG_AHB_MONWAR 0 +set CONFIG_AHB_DTRACE 0 +set CONFIG_DSU_UART 0 +set CONFIG_DSU_JTAG 0 +set CONFIG_DSU_ETH 0 +set tmpvar_28 "(not set)" +set CONFIG_DSU_ETHSZ1 0 +set CONFIG_DSU_ETHSZ2 0 +set CONFIG_DSU_ETHSZ4 0 +set CONFIG_DSU_ETHSZ8 0 +set CONFIG_DSU_ETHSZ16 0 +set CONFIG_DSU_IPMSB C0A8 +set CONFIG_DSU_IPLSB 0033 +set CONFIG_DSU_ETHMSB 020000 +set CONFIG_DSU_ETHLSB 000000 +set CONFIG_DSU_ETH_PROG 0 +set CONFIG_DSU_ETH_DIS 0 +set CONFIG_MCTRL_LEON2 0 +set CONFIG_MCTRL_8BIT 0 +set CONFIG_MCTRL_16BIT 0 +set CONFIG_MCTRL_5CS 0 +set CONFIG_MCTRL_SDRAM 0 +set CONFIG_MCTRL_SDRAM_SEPBUS 0 +set CONFIG_MCTRL_SDRAM_BUS64 0 +set CONFIG_MCTRL_SDRAM_INVCLK 0 +set CONFIG_MCTRL_PAGE 0 +set CONFIG_MCTRL_PROGPAGE 0 +set CONFIG_MIG_DDR2 0 +set CONFIG_MIG_RANKS 1 +set CONFIG_MIG_COLBITS 10 +set CONFIG_MIG_ROWBITS 13 +set CONFIG_MIG_BANKBITS 2 +set CONFIG_MIG_HMASK F00 +set CONFIG_MIG_SERIES7 0 +set CONFIG_MIG_SERIES_7_MODEL 0 +set CONFIG_AHBSTAT_ENABLE 0 +set CONFIG_AHBSTAT_NFTSLV 1 +set CONFIG_AHBROM_ENABLE 0 +set CONFIG_AHBROM_START 000 +set CONFIG_AHBROM_PIPE 0 +set CONFIG_AHBRAM_ENABLE 0 +set tmpvar_29 "(not set)" +set CONFIG_AHBRAM_SZ1 0 +set CONFIG_AHBRAM_SZ2 0 +set CONFIG_AHBRAM_SZ4 0 +set CONFIG_AHBRAM_SZ8 0 +set CONFIG_AHBRAM_SZ16 0 +set CONFIG_AHBRAM_SZ32 0 +set CONFIG_AHBRAM_SZ64 0 +set CONFIG_AHBRAM_SZ128 0 +set CONFIG_AHBRAM_SZ256 0 +set CONFIG_AHBRAM_SZ512 0 +set CONFIG_AHBRAM_SZ1024 0 +set CONFIG_AHBRAM_SZ2048 0 +set CONFIG_AHBRAM_SZ4096 0 +set CONFIG_AHBRAM_START A00 +set CONFIG_AHBRAM_PIPE 0 +set CONFIG_GRETH_ENABLE 0 +set CONFIG_GRETH_GIGA 0 +set tmpvar_30 "(not set)" +set CONFIG_GRETH_FIFO4 0 +set CONFIG_GRETH_FIFO8 0 +set CONFIG_GRETH_FIFO16 0 +set CONFIG_GRETH_FIFO32 0 +set CONFIG_GRETH_FIFO64 0 +set CONFIG_GRETH_FT 0 +set CONFIG_GRETH_EDCLFT 0 +set CONFIG_UART1_ENABLE 0 +set tmpvar_31 "(not set)" +set CONFIG_UA1_FIFO1 0 +set CONFIG_UA1_FIFO2 0 +set CONFIG_UA1_FIFO4 0 +set CONFIG_UA1_FIFO8 0 +set CONFIG_UA1_FIFO16 0 +set CONFIG_UA1_FIFO32 0 +set CONFIG_IRQ3_ENABLE 0 +set CONFIG_IRQ3_SEC 0 +set CONFIG_IRQ3_NSEC 12 +set CONFIG_GPT_ENABLE 0 +set CONFIG_GPT_NTIM 2 +set CONFIG_GPT_SW 8 +set CONFIG_GPT_TW 32 +set CONFIG_GPT_IRQ 8 +set CONFIG_GPT_SEPIRQ 0 +set CONFIG_GPT_WDOGEN 0 +set CONFIG_GPT_WDOG FFFF +set CONFIG_GRGPIO_ENABLE 0 +set CONFIG_GRGPIO_WIDTH 8 +set CONFIG_GRGPIO_IMASK 0000 +set CONFIG_I2C_ENABLE 0 +set CONFIG_KBD_ENABLE 0 +set CONFIG_VGA_ENABLE 0 +set CONFIG_SVGA_ENABLE 0 +set CONFIG_SPIMCTRL 0 +set CONFIG_SPIMCTRL_SDCARD 0 +set CONFIG_SPIMCTRL_READCMD 0B +set CONFIG_SPIMCTRL_DUMMYBYTE 0 +set CONFIG_SPIMCTRL_DUALOUTPUT 0 +set CONFIG_SPIMCTRL_OFFSET 0 +set CONFIG_SPIMCTRL_SCALER 1 +set CONFIG_SPIMCTRL_ASCALER 8 +set CONFIG_SPIMCTRL_PWRUPCNT 0 +set CONFIG_SPICTRL_ENABLE 0 +set CONFIG_SPICTRL_NUM 1 +set CONFIG_SPICTRL_SLVS 1 +set CONFIG_SPICTRL_FIFO 1 +set CONFIG_SPICTRL_SLVREG 0 +set CONFIG_SPICTRL_ASEL 0 +set CONFIG_SPICTRL_AM 0 +set CONFIG_SPICTRL_ODMODE 0 +set CONFIG_SPICTRL_TWEN 0 +set CONFIG_SPICTRL_MAXWLEN 0 +set CONFIG_SPICTRL_SYNCRAM 0 +set tmpvar_32 "(not set)" +set CONFIG_SPICTRL_NOFT 0 +set CONFIG_SPICTRL_DMRFT 0 +set CONFIG_SPICTRL_TMRFT 0 +set CONFIG_DEBUG_UART 0 +set CONFIG_LEON3FT_PRESENT 4 +set CONFIG_HAS_SHARED_GRFPU 4 +set CONFIG_SYN_ARTISAN 4 +set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 +set CONFIG_MODULES 4 +proc writeconfig {file1 file2} { + set cfg [open $file1 w] + set autocfg [open $file2 w] + set notmod 1 + set notset 0 + puts $cfg "#" + puts $cfg "# Automatically generated make config: don't edit" + puts $cfg "#" + puts $autocfg "/*" + puts $autocfg " * Automatically generated C config: don't edit" + puts $autocfg " */" + puts $autocfg "#define AUTOCONF_INCLUDED" + global CONFIG_LEON3FT_PRESENT + global CONSTANT_Y + write_tristate $cfg $autocfg CONFIG_LEON3FT_PRESENT $CONFIG_LEON3FT_PRESENT [list $notmod] 2 + global CONFIG_HAS_SHARED_GRFPU + write_tristate $cfg $autocfg CONFIG_HAS_SHARED_GRFPU $CONFIG_HAS_SHARED_GRFPU [list $notmod] 2 + write_comment $cfg $autocfg "Synthesis " + global tmpvar_0 + + if { $tmpvar_0 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_INFERRED 0 [list $notmod] 2 } + if { $tmpvar_0 == "Altera-Stratix" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIX 0 [list $notmod] 2 } + if { $tmpvar_0 == "Altera-StratixII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXII 0 [list $notmod] 2 } + if { $tmpvar_0 == "Altera-StratixIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIII 0 [list $notmod] 2 } + if { $tmpvar_0 == "Altera-StratixIV" } then { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIV 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_STRATIXIV 0 [list $notmod] 2 } + if { $tmpvar_0 == "Altera-CycloneIII" } then { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CYCLONEIII 0 [list $notmod] 2 } + if { $tmpvar_0 == "Altera-Others" } then { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ALTERA 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Axcelerator" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXCEL 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Axcelerator-DSP" } then { write_tristate $cfg $autocfg CONFIG_SYN_AXDSP 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_AXDSP 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Proasic" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-ProasicPlus" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASICPLUS 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Proasic3" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Proasic3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3E 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Proasic3L" } then { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3L 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PROASIC3L 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-IGLOO/p/L" } then { write_tristate $cfg $autocfg CONFIG_SYN_IGLOO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IGLOO 0 [list $notmod] 2 } + if { $tmpvar_0 == "Actel-Fusion" } then { write_tristate $cfg $autocfg CONFIG_SYN_FUSION 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_FUSION 0 [list $notmod] 2 } + if { $tmpvar_0 == "Aeroflex-UT025CRH" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT025CRH 0 [list $notmod] 2 } + if { $tmpvar_0 == "Aeroflex-UT130HBD" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT130HBD 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT130HBD 0 [list $notmod] 2 } + if { $tmpvar_0 == "Aeroflex-UT90NHBD" } then { write_tristate $cfg $autocfg CONFIG_SYN_UT90NHBD 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UT90NHBD 0 [list $notmod] 2 } + if { $tmpvar_0 == "Atmel-ATC18" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18 0 [list $notmod] 2 } + if { $tmpvar_0 == "Atmel-ATC18RHA" } then { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ATC18RHA 0 [list $notmod] 2 } + if { $tmpvar_0 == "IBM-CMOS9SF" } then { write_tristate $cfg $autocfg CONFIG_SYN_CMOS9SF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CMOS9SF 0 [list $notmod] 2 } + if { $tmpvar_0 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_CUSTOM1 0 [list $notmod] 2 } + if { $tmpvar_0 == "eASIC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC90 0 [list $notmod] 2 } + if { $tmpvar_0 == "eASIC45" } then { write_tristate $cfg $autocfg CONFIG_SYN_EASIC45 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_EASIC45 0 [list $notmod] 2 } + if { $tmpvar_0 == "IHP25" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25 0 [list $notmod] 2 } + if { $tmpvar_0 == "IHP25RH" } then { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_IHP25RH 0 [list $notmod] 2 } + if { $tmpvar_0 == "Lattice-EC/ECP/XP" } then { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_LATTICE 0 [list $notmod] 2 } + if { $tmpvar_0 == "Quicklogic-Eclipse" } then { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ECLIPSE 0 [list $notmod] 2 } + if { $tmpvar_0 == "Peregrine" } then { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_PEREGRINE 0 [list $notmod] 2 } + if { $tmpvar_0 == "RH-LIB18T" } then { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RH_LIB18T 0 [list $notmod] 2 } + if { $tmpvar_0 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_RHUMC 0 [list $notmod] 2 } + if { $tmpvar_0 == "SAED32" } then { write_tristate $cfg $autocfg CONFIG_SYN_SAED32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SAED32 0 [list $notmod] 2 } + if { $tmpvar_0 == "DARE" } then { write_tristate $cfg $autocfg CONFIG_SYN_DARE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_DARE 0 [list $notmod] 2 } + if { $tmpvar_0 == "SMIC130" } then { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SMIC13 0 [list $notmod] 2 } + if { $tmpvar_0 == "TM65Gplus" } then { write_tristate $cfg $autocfg CONFIG_SYN_TM65GPLUS 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TM65GPLUS 0 [list $notmod] 2 } + if { $tmpvar_0 == "TSMC90" } then { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_TSMC90 0 [list $notmod] 2 } + if { $tmpvar_0 == "UMC180" } then { write_tristate $cfg $autocfg CONFIG_SYN_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_UMC 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Artix7" } then { write_tristate $cfg $autocfg CONFIG_SYN_ARTIX7 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ARTIX7 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Kintex7" } then { write_tristate $cfg $autocfg CONFIG_SYN_KINTEX7 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_KINTEX7 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Spartan3" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Spartan3E" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN3E 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Spartan6" } then { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_SPARTAN6 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-VirtexE" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEXE 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Virtex2" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX2 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Virtex4" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX4 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Virtex5" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX5 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Virtex6" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX6 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX6 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Virtex7" } then { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX7 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_VIRTEX7 0 [list $notmod] 2 } + if { $tmpvar_0 == "Xilinx-Zynq7000" } then { write_tristate $cfg $autocfg CONFIG_SYN_ZYNQ7000 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SYN_ZYNQ7000 0 [list $notmod] 2 } + global tmpvar_1 + global CONFIG_SYN_INFERRED + global CONFIG_SYN_CUSTOM1 + global CONFIG_SYN_ATC18 + global CONFIG_SYN_TSMC90 + global CONFIG_SYN_EASIC45 + global CONFIG_SYN_UMC + global CONFIG_SYN_RHUMC + global CONFIG_SYN_DARE + global CONFIG_SYN_SAED32 + global CONFIG_SYN_ARTISAN + if {($CONFIG_SYN_INFERRED == 1 || $CONFIG_SYN_CUSTOM1 == 1 || $CONFIG_SYN_ATC18 == 1 || $CONFIG_SYN_TSMC90 == 1 || $CONFIG_SYN_EASIC45 == 1 || $CONFIG_SYN_UMC == 1 || $CONFIG_SYN_RHUMC == 1 || $CONFIG_SYN_DARE == 1 || $CONFIG_SYN_SAED32 == 1 || $CONFIG_SYN_ARTISAN == 1)} then { + if { $tmpvar_1 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_INFERRED 0 [list $notmod] 2 } + if { $tmpvar_1 == "UMC18" } then { write_tristate $cfg $autocfg CONFIG_MEM_UMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_UMC 0 [list $notmod] 2 } + if { $tmpvar_1 == "RH-UMC" } then { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_RHUMC 0 [list $notmod] 2 } + if { $tmpvar_1 == "SAED32" } then { write_tristate $cfg $autocfg CONFIG_MEM_SAED32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_SAED32 0 [list $notmod] 2 } + if { $tmpvar_1 == "DARE" } then { write_tristate $cfg $autocfg CONFIG_MEM_DARE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_DARE 0 [list $notmod] 2 } + if { $tmpvar_1 == "Artisan" } then { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_ARTISAN 0 [list $notmod] 2 } + if { $tmpvar_1 == "Custom1" } then { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_CUSTOM1 0 [list $notmod] 2 } + if { $tmpvar_1 == "EASIC45" } then { write_tristate $cfg $autocfg CONFIG_MEM_EASIC45 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_EASIC45 0 [list $notmod] 2 } + if { $tmpvar_1 == "Virage" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE 0 [list $notmod] 2 } + if { $tmpvar_1 == "Virage-TSMC90" } then { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MEM_VIRAGE90 0 [list $notmod] 2 }} + global CONFIG_SYN_INFER_RAM + if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_RAM $CONFIG_SYN_INFER_RAM [list $notmod] 2 } + global CONFIG_SYN_INFER_PADS + if {($CONFIG_SYN_INFERRED != 1)} then {write_tristate $cfg $autocfg CONFIG_SYN_INFER_PADS $CONFIG_SYN_INFER_PADS [list $notmod] 2 } + global CONFIG_SYN_NO_ASYNC + write_tristate $cfg $autocfg CONFIG_SYN_NO_ASYNC $CONFIG_SYN_NO_ASYNC [list $notmod] 2 + global CONFIG_SYN_SCAN + write_tristate $cfg $autocfg CONFIG_SYN_SCAN $CONFIG_SYN_SCAN [list $notmod] 2 + write_comment $cfg $autocfg "Clock generation" + global tmpvar_2 + + if { $tmpvar_2 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_INFERRED 0 [list $notmod] 2 } + if { $tmpvar_2 == "Actel-HCLKBUF" } then { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_HCLKBUF 0 [list $notmod] 2 } + if { $tmpvar_2 == "Aeroflex-UT130HBD" } then { write_tristate $cfg $autocfg CONFIG_CLK_UT130HBD 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_UT130HBD 0 [list $notmod] 2 } + if { $tmpvar_2 == "Altera-ALTPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_ALTDLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "Lattice-EXPLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LATDLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "Proasic3-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3PLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "Proasic3E-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3EPLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3EPLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "Proasic3L-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_PRO3LPLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_PRO3LPLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "Fusion-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_FUSPLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_FUSPLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "RH-LIB18T-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_LIB18T 0 [list $notmod] 2 } + if { $tmpvar_2 == "RHUMC-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_RHUMC 0 [list $notmod] 2 } + if { $tmpvar_2 == "DARE-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_DARE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DARE 0 [list $notmod] 2 } + if { $tmpvar_2 == "SAED32-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_SAED32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_SAED32 0 [list $notmod] 2 } + if { $tmpvar_2 == "EASIC45-PLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_EASIC45 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_EASIC45 0 [list $notmod] 2 } + if { $tmpvar_2 == "Xilinx-PLLE2" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKPLLE2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKPLLE2 0 [list $notmod] 2 } + if { $tmpvar_2 == "Xilinx-CLKDLL" } then { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_CLKDLL 0 [list $notmod] 2 } + if { $tmpvar_2 == "Xilinx-DCM" } then { write_tristate $cfg $autocfg CONFIG_CLK_DCM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_CLK_DCM 0 [list $notmod] 2 } + global CONFIG_CLK_MUL + global CONFIG_CLK_DCM + global CONFIG_CLK_ALTDLL + global CONFIG_CLK_LATDLL + global CONFIG_CLK_PRO3PLL + global CONFIG_CLK_PRO3EPLL + global CONFIG_CLK_PRO3LPLL + global CONFIG_CLK_CLKDLL + global CONFIG_CLK_LIB18T + global CONFIG_CLK_FUSPLL + global CONFIG_CLK_CLKPLLE2 + if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1 || $CONFIG_CLK_FUSPLL == 1 || $CONFIG_CLK_CLKPLLE2 == 1)} then {write_int $cfg $autocfg CONFIG_CLK_MUL $CONFIG_CLK_MUL $notmod } + global CONFIG_CLK_DIV + if {($CONFIG_CLK_DCM == 1 || $CONFIG_CLK_ALTDLL == 1 || $CONFIG_CLK_LATDLL == 1 || $CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_LIB18T == 1 || $CONFIG_CLK_FUSPLL == 1 || $CONFIG_CLK_CLKPLLE2 == 1)} then {write_int $cfg $autocfg CONFIG_CLK_DIV $CONFIG_CLK_DIV $notmod } + global CONFIG_OCLK_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLK_DIV $CONFIG_OCLK_DIV $notmod } + global CONFIG_OCLKB_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLKB_DIV $CONFIG_OCLKB_DIV $notmod } + global CONFIG_OCLKC_DIV + if {($CONFIG_CLK_PRO3PLL == 1 || $CONFIG_CLK_PRO3EPLL == 1 || $CONFIG_CLK_PRO3LPLL == 1 || $CONFIG_CLK_FUSPLL == 1)} then {write_int $cfg $autocfg CONFIG_OCLKC_DIV $CONFIG_OCLKC_DIV $notmod } + global CONFIG_PCI_CLKDLL + if {($CONFIG_CLK_CLKDLL == 1 || $CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_CLKDLL $CONFIG_PCI_CLKDLL [list $notmod] 2 } + global CONFIG_CLK_NOFB + if {($CONFIG_CLK_DCM == 1)} then {write_tristate $cfg $autocfg CONFIG_CLK_NOFB $CONFIG_CLK_NOFB [list $notmod] 2 } + global CONFIG_PCI_SYSCLK + global CONFIG_PCI_ENABLE + if {($CONFIG_PCI_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_PCI_SYSCLK $CONFIG_PCI_SYSCLK [list $notmod] 2 } + write_comment $cfg $autocfg "Processor " + global CONFIG_LEON3 + write_tristate $cfg $autocfg CONFIG_LEON3 $CONFIG_LEON3 [list $notmod] 2 + global CONFIG_PROC_NUM + if {($CONFIG_LEON3 == 1)} then {write_int $cfg $autocfg CONFIG_PROC_NUM $CONFIG_PROC_NUM $notmod } + global tmpvar_3 + if {($CONFIG_LEON3 == 1)} then { + if { $tmpvar_3 == "Minimal-configuration" } then { write_tristate $cfg $autocfg CONFIG_LEON3_MIN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_LEON3_MIN 0 [list $notmod] 2 } + if { $tmpvar_3 == "General-purpose-cfg" } then { write_tristate $cfg $autocfg CONFIG_LEON3_GP 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_LEON3_GP 0 [list $notmod] 2 } + if { $tmpvar_3 == "High-Performance-cfg" } then { write_tristate $cfg $autocfg CONFIG_LEON3_HP 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_LEON3_HP 0 [list $notmod] 2 } + if { $tmpvar_3 == "Custom-configuration" } then { write_tristate $cfg $autocfg CONFIG_LEON3_CUSTOM 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_LEON3_CUSTOM 0 [list $notmod] 2 }} + global CONFIG_IU_NWINDOWS + global CONFIG_LEON3_MIN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS 8 $notmod } + global CONFIG_IU_V8MULDIV + global CONSTANT_N + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONSTANT_N [list $notmod] 2 } + global CONFIG_IU_BP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_BP $CONSTANT_N [list $notmod] 2 } + global CONFIG_IU_SVT + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONSTANT_Y [list $notmod] 2 } + global CONFIG_NOTAG + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_NOTAG $CONSTANT_N [list $notmod] 2 } + global CONFIG_IU_LDELAY + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY 1 $notmod } + global CONFIG_IU_WATCHPOINTS + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS 0 $notmod } + global CONFIG_PWD + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONSTANT_N [list $notmod] 2 } + global CONFIG_IU_RSTADDR + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR 00000 $notmod } + global CONFIG_FPU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONSTANT_N [list $notmod] 2 } + global CONFIG_ICACHE_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_ASSO1 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_SZ2 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_LZ16 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_ALGORND + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_LOCK + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONSTANT_N [list $notmod] 2 } + global CONFIG_DCACHE_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_ASSO1 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_SZ2 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_LZ16 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_ALGORND + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_LOCK + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONSTANT_N [list $notmod] 2 } + global CONFIG_DCACHE_SNOOP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONSTANT_N [list $notmod] 2 } + global CONFIG_CACHE_FIXED + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED 0 $notmod } + global CONFIG_MMU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONSTANT_N [list $notmod] 2 } + global CONFIG_DSU_ENABLE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_MIN == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONSTANT_N [list $notmod] 2 } + global CONFIG_LEON3_GP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS 8 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONSTANT_Y [list $notmod] 2 } + global CONFIG_IU_MUL_LATENCY_5 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_IU_MUL_MAC + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_BP $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_NOTAG $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY 1 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS 2 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR 00000 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_ASSO2 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_SZ4 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONSTANT_N [list $notmod] 2 } + global CONFIG_ICACHE_LRAM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_ASSO2 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_SZ4 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_SNOOP_FAST + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_SNOOP_SEPTAG + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED 0 $notmod } + global CONFIG_DCACHE_LRAM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_SPLIT + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_SPLIT $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_REPARRAY + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_I8 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_I8 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_D8 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_D8 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_FASTWB + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_PAGE_4K + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DSU_ITRACE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DSU_ITRACESZ4 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DSU_ATRACESZ4 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_GP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_LEON3_HP + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS 8 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONSTANT_Y [list $notmod] 2 } + global CONFIG_IU_MUL_LATENCY_2 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_BP $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_NOTAG $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY 1 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS 4 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR 00000 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONSTANT_Y [list $notmod] 2 } + global CONFIG_FPU_GRFPU + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_GRFPU $CONSTANT_Y [list $notmod] 2 } + global CONFIG_FPU_GRFPU_INFMUL + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_ICACHE_ALGOLRU + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_DCACHE_ALGOLRU + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED 0 $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONSTANT_N [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_SPLIT $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_I16 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_I16 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_MMU_D16 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_D16 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 $CONSTANT_Y [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_HP == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 $CONSTANT_Y [list $notmod] 2 } + global CONFIG_LEON3_CUSTOM + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_comment $cfg $autocfg "Integer unit "} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_int $cfg $autocfg CONFIG_IU_NWINDOWS $CONFIG_IU_NWINDOWS $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_V8MULDIV $CONFIG_IU_V8MULDIV [list $notmod] 2 } + global tmpvar_4 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1)} then { + if { $tmpvar_4 == "2-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_2 0 [list $notmod] 2 } + if { $tmpvar_4 == "4-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_4 0 [list $notmod] 2 } + if { $tmpvar_4 == "5-cycles" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_LATENCY_5 0 [list $notmod] 2 }} + global CONFIG_IU_MUL_LATENCY_4 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1) && ($CONFIG_IU_MUL_LATENCY_4 == 1 || $CONFIG_IU_MUL_LATENCY_5 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_MUL_MAC $CONFIG_IU_MUL_MAC [list $notmod] 2 } + global tmpvar_5 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_IU_V8MULDIV == 1)} then { + if { $tmpvar_5 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_INFERRED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_INFERRED 0 [list $notmod] 2 } + if { $tmpvar_5 == "NTNU_Modgen" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_MODGEN 0 [list $notmod] 2 } + if { $tmpvar_5 == "TechSpec" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_TECHSPEC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_TECHSPEC 0 [list $notmod] 2 } + if { $tmpvar_5 == "Designware" } then { write_tristate $cfg $autocfg CONFIG_IU_MUL_DW 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IU_MUL_DW 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_BP $CONFIG_IU_BP [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_SVT $CONFIG_IU_SVT [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_NOTAG $CONFIG_NOTAG [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_int $cfg $autocfg CONFIG_IU_LDELAY $CONFIG_IU_LDELAY $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_int $cfg $autocfg CONFIG_IU_WATCHPOINTS $CONFIG_IU_WATCHPOINTS $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_PWD $CONFIG_PWD [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_hex $cfg $autocfg CONFIG_IU_RSTADDR $CONFIG_IU_RSTADDR $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_comment $cfg $autocfg "Floating-point unit"} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_ENABLE $CONFIG_FPU_ENABLE [list $notmod] 2 } + global tmpvar_6 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1)} then { + if { $tmpvar_6 == "GRFPU" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU 0 [list $notmod] 2 } + if { $tmpvar_6 == "GRFPU-LITE" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPULITE 0 [list $notmod] 2 } + if { $tmpvar_6 == "Meiko" } then { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_MEIKO 0 [list $notmod] 2 }} + global tmpvar_7 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPU == 1)} then { + if { $tmpvar_7 == "Inferred" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_INFMUL 0 [list $notmod] 2 } + if { $tmpvar_7 == "DW" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_DWMUL 0 [list $notmod] 2 } + if { $tmpvar_7 == "ModGen" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_MODGEN 0 [list $notmod] 2 } + if { $tmpvar_7 == "TechSpec" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_TECHSPEC 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_TECHSPEC 0 [list $notmod] 2 }} + global CONFIG_FPU_GRFPU_SH + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_HAS_SHARED_GRFPU == 1 && $CONFIG_FPU_GRFPU == 1)} then {write_tristate $cfg $autocfg CONFIG_FPU_GRFPU_SH $CONFIG_FPU_GRFPU_SH [list $notmod] 2 } + global tmpvar_8 + global CONFIG_FPU_GRFPULITE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_FPU_ENABLE == 1) && ($CONFIG_FPU_GRFPULITE == 1)} then { + if { $tmpvar_8 == "Simple" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC0 0 [list $notmod] 2 } + if { $tmpvar_8 == "Data-forwarding" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC1 0 [list $notmod] 2 } + if { $tmpvar_8 == "Non-blocking" } then { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPU_GRFPC2 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_comment $cfg $autocfg "Cache system"} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_ENABLE $CONFIG_ICACHE_ENABLE [list $notmod] 2 } + global tmpvar_9 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { + if { $tmpvar_9 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO1 0 [list $notmod] 2 } + if { $tmpvar_9 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO2 0 [list $notmod] 2 } + if { $tmpvar_9 == "3" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO3 0 [list $notmod] 2 } + if { $tmpvar_9 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ASSO4 0 [list $notmod] 2 }} + global tmpvar_10 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { + if { $tmpvar_10 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ1 0 [list $notmod] 2 } + if { $tmpvar_10 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ2 0 [list $notmod] 2 } + if { $tmpvar_10 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ4 0 [list $notmod] 2 } + if { $tmpvar_10 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ8 0 [list $notmod] 2 } + if { $tmpvar_10 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ16 0 [list $notmod] 2 } + if { $tmpvar_10 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ32 0 [list $notmod] 2 } + if { $tmpvar_10 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ64 0 [list $notmod] 2 } + if { $tmpvar_10 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ128 0 [list $notmod] 2 } + if { $tmpvar_10 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_SZ256 0 [list $notmod] 2 }} + global tmpvar_11 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1)} then { + if { $tmpvar_11 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ16 0 [list $notmod] 2 } + if { $tmpvar_11 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LZ32 0 [list $notmod] 2 }} + global tmpvar_12 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then { + if { $tmpvar_12 == "Random" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGORND 0 [list $notmod] 2 } + if { $tmpvar_12 == "Direct" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGODIR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGODIR 0 [list $notmod] 2 } + if { $tmpvar_12 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRR 0 [list $notmod] 2 } + if { $tmpvar_12 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_ALGOLRU 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1) && ($CONFIG_ICACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LOCK $CONFIG_ICACHE_LOCK [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM $CONFIG_ICACHE_LRAM [list $notmod] 2 } + global tmpvar_13 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_LRAM == 1)} then { + if { $tmpvar_13 == "1" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ1 0 [list $notmod] 2 } + if { $tmpvar_13 == "2" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ2 0 [list $notmod] 2 } + if { $tmpvar_13 == "4" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ4 0 [list $notmod] 2 } + if { $tmpvar_13 == "8" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ8 0 [list $notmod] 2 } + if { $tmpvar_13 == "16" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ16 0 [list $notmod] 2 } + if { $tmpvar_13 == "32" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ32 0 [list $notmod] 2 } + if { $tmpvar_13 == "64" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ64 0 [list $notmod] 2 } + if { $tmpvar_13 == "128" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ128 0 [list $notmod] 2 } + if { $tmpvar_13 == "256" } then { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_ICACHE_LRAM_SZ256 0 [list $notmod] 2 }} + global CONFIG_ICACHE_LRSTART + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_ICACHE_LRSTART $CONFIG_ICACHE_LRSTART $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_ENABLE $CONFIG_DCACHE_ENABLE [list $notmod] 2 } + global tmpvar_14 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { + if { $tmpvar_14 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO1 0 [list $notmod] 2 } + if { $tmpvar_14 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO2 0 [list $notmod] 2 } + if { $tmpvar_14 == "3" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO3 0 [list $notmod] 2 } + if { $tmpvar_14 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ASSO4 0 [list $notmod] 2 }} + global tmpvar_15 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { + if { $tmpvar_15 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ1 0 [list $notmod] 2 } + if { $tmpvar_15 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ2 0 [list $notmod] 2 } + if { $tmpvar_15 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ4 0 [list $notmod] 2 } + if { $tmpvar_15 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ8 0 [list $notmod] 2 } + if { $tmpvar_15 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ16 0 [list $notmod] 2 } + if { $tmpvar_15 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ32 0 [list $notmod] 2 } + if { $tmpvar_15 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ64 0 [list $notmod] 2 } + if { $tmpvar_15 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ128 0 [list $notmod] 2 } + if { $tmpvar_15 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_SZ256 0 [list $notmod] 2 }} + global tmpvar_16 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { + if { $tmpvar_16 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ16 0 [list $notmod] 2 } + if { $tmpvar_16 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LZ32 0 [list $notmod] 2 }} + global tmpvar_17 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then { + if { $tmpvar_17 == "Random" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGORND 0 [list $notmod] 2 } + if { $tmpvar_17 == "Direct" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGODIR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGODIR 0 [list $notmod] 2 } + if { $tmpvar_17 == "LRR" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRR 0 [list $notmod] 2 } + if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } + global tmpvar_18 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then { + if { $tmpvar_18 == "1" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ1 0 [list $notmod] 2 } + if { $tmpvar_18 == "2" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ2 0 [list $notmod] 2 } + if { $tmpvar_18 == "4" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ4 0 [list $notmod] 2 } + if { $tmpvar_18 == "8" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ8 0 [list $notmod] 2 } + if { $tmpvar_18 == "16" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ16 0 [list $notmod] 2 } + if { $tmpvar_18 == "32" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ32 0 [list $notmod] 2 } + if { $tmpvar_18 == "64" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ64 0 [list $notmod] 2 } + if { $tmpvar_18 == "128" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ128 0 [list $notmod] 2 } + if { $tmpvar_18 == "256" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM_SZ256 0 [list $notmod] 2 }} + global CONFIG_DCACHE_LRSTART + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {write_hex $cfg $autocfg CONFIG_DCACHE_LRSTART $CONFIG_DCACHE_LRSTART $notmod } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_comment $cfg $autocfg "MMU"} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_ENABLE $CONFIG_MMU_ENABLE [list $notmod] 2 } + global tmpvar_19 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then { + if { $tmpvar_19 == "combined" } then { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_COMBINED 0 [list $notmod] 2 } + if { $tmpvar_19 == "split" } then { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_SPLIT 0 [list $notmod] 2 }} + global tmpvar_20 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then { + if { $tmpvar_20 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPARRAY 0 [list $notmod] 2 } + if { $tmpvar_20 == "Increment" } then { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_REPINCREMENT 0 [list $notmod] 2 }} + global tmpvar_21 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then { + if { $tmpvar_21 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_I2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I2 0 [list $notmod] 2 } + if { $tmpvar_21 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_I4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I4 0 [list $notmod] 2 } + if { $tmpvar_21 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_I8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I8 0 [list $notmod] 2 } + if { $tmpvar_21 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_I16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I16 0 [list $notmod] 2 } + if { $tmpvar_21 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_I32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I32 0 [list $notmod] 2 } + if { $tmpvar_21 == "64" } then { write_tristate $cfg $autocfg CONFIG_MMU_I64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_I64 0 [list $notmod] 2 }} + global tmpvar_22 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then { + if { $tmpvar_22 == "2" } then { write_tristate $cfg $autocfg CONFIG_MMU_D2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D2 0 [list $notmod] 2 } + if { $tmpvar_22 == "4" } then { write_tristate $cfg $autocfg CONFIG_MMU_D4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D4 0 [list $notmod] 2 } + if { $tmpvar_22 == "8" } then { write_tristate $cfg $autocfg CONFIG_MMU_D8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D8 0 [list $notmod] 2 } + if { $tmpvar_22 == "16" } then { write_tristate $cfg $autocfg CONFIG_MMU_D16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D16 0 [list $notmod] 2 } + if { $tmpvar_22 == "32" } then { write_tristate $cfg $autocfg CONFIG_MMU_D32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D32 0 [list $notmod] 2 } + if { $tmpvar_22 == "64" } then { write_tristate $cfg $autocfg CONFIG_MMU_D64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_D64 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1) && ($CONFIG_MMU_SPLIT == 1)} then {write_tristate $cfg $autocfg CONFIG_MMU_FASTWB $CONFIG_MMU_FASTWB [list $notmod] 2 } + global tmpvar_23 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE == 1)} then { + if { $tmpvar_23 == "4K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_4K 0 [list $notmod] 2 } + if { $tmpvar_23 == "8K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_8K 0 [list $notmod] 2 } + if { $tmpvar_23 == "16K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_16K 0 [list $notmod] 2 } + if { $tmpvar_23 == "32K" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_32K 0 [list $notmod] 2 } + if { $tmpvar_23 == "Programmable" } then { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_MMU_PAGE_PROG 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_comment $cfg $autocfg "Debug Support Unit "} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ENABLE $CONFIG_DSU_ENABLE [list $notmod] 2 } + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ITRACE $CONFIG_DSU_ITRACE [list $notmod] 2 } + global tmpvar_24 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ITRACE == 1)} then { + if { $tmpvar_24 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ1 0 [list $notmod] 2 } + if { $tmpvar_24 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ2 0 [list $notmod] 2 } + if { $tmpvar_24 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ4 0 [list $notmod] 2 } + if { $tmpvar_24 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ8 0 [list $notmod] 2 } + if { $tmpvar_24 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ITRACESZ16 0 [list $notmod] 2 }} + global CONFIG_DSU_ATRACE + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ATRACE $CONFIG_DSU_ATRACE [list $notmod] 2 } + global tmpvar_25 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DSU_ENABLE == 1) && ($CONFIG_DSU_ATRACE == 1)} then { + if { $tmpvar_25 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ1 0 [list $notmod] 2 } + if { $tmpvar_25 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ2 0 [list $notmod] 2 } + if { $tmpvar_25 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ4 0 [list $notmod] 2 } + if { $tmpvar_25 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ8 0 [list $notmod] 2 } + if { $tmpvar_25 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ATRACESZ16 0 [list $notmod] 2 }} + if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "Fault-tolerance "} + global CONFIG_LEON3FT_EN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1)} then {write_tristate $cfg $autocfg CONFIG_LEON3FT_EN $CONFIG_LEON3FT_EN [list $notmod] 2 } + global tmpvar_26 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then { + if { $tmpvar_26 == "None" } then { write_tristate $cfg $autocfg CONFIG_IUFT_NONE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IUFT_NONE 0 [list $notmod] 2 } + if { $tmpvar_26 == "Parity" } then { write_tristate $cfg $autocfg CONFIG_IUFT_PAR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IUFT_PAR 0 [list $notmod] 2 } + if { $tmpvar_26 == "PDMR" } then { write_tristate $cfg $autocfg CONFIG_IUFT_DMR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IUFT_DMR 0 [list $notmod] 2 } + if { $tmpvar_26 == "BCH" } then { write_tristate $cfg $autocfg CONFIG_IUFT_BCH 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IUFT_BCH 0 [list $notmod] 2 } + if { $tmpvar_26 == "TMR" } then { write_tristate $cfg $autocfg CONFIG_IUFT_TMR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_IUFT_TMR 0 [list $notmod] 2 }} + global tmpvar_27 + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1) && ($CONFIG_FPU_ENABLE == 1)} then { + if { $tmpvar_27 == "None" } then { write_tristate $cfg $autocfg CONFIG_FPUFT_NONE 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPUFT_NONE 0 [list $notmod] 2 } + if { $tmpvar_27 == "Parity" } then { write_tristate $cfg $autocfg CONFIG_FPUFT_PAR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPUFT_PAR 0 [list $notmod] 2 } + if { $tmpvar_27 == "PDMR" } then { write_tristate $cfg $autocfg CONFIG_FPUFT_DMR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPUFT_DMR 0 [list $notmod] 2 } + if { $tmpvar_27 == "TMR" } then { write_tristate $cfg $autocfg CONFIG_FPUFT_TMR 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_FPUFT_TMR 0 [list $notmod] 2 }} + global CONFIG_RF_ERRINJ + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then {write_tristate $cfg $autocfg CONFIG_RF_ERRINJ $CONFIG_RF_ERRINJ [list $notmod] 2 } + global CONFIG_CACHE_FT_EN + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then {write_tristate $cfg $autocfg CONFIG_CACHE_FT_EN $CONFIG_CACHE_FT_EN [list $notmod] 2 } + global CONFIG_CACHE_ERRINJ + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_LEON3FT_EN == 1)} then {write_int $cfg $autocfg CONFIG_CACHE_ERRINJ $CONFIG_CACHE_ERRINJ $notmod } + if {($CONFIG_LEON3 == 1)} then {write_comment $cfg $autocfg "VHDL debug settings "} + global CONFIG_IU_DISAS + if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS $CONFIG_IU_DISAS [list $notmod] 2 } + global CONFIG_IU_DISAS_NET + if {($CONFIG_LEON3 == 1) && ($CONFIG_IU_DISAS == 1)} then {write_tristate $cfg $autocfg CONFIG_IU_DISAS_NET $CONFIG_IU_DISAS_NET [list $notmod] 2 } + global CONFIG_DEBUG_PC32 + if {($CONFIG_LEON3 == 1)} then {write_tristate $cfg $autocfg CONFIG_DEBUG_PC32 $CONFIG_DEBUG_PC32 [list $notmod] 2 } + write_comment $cfg $autocfg "AMBA configuration" + global CONFIG_AHB_DEFMST + write_int $cfg $autocfg CONFIG_AHB_DEFMST $CONFIG_AHB_DEFMST $notmod + global CONFIG_AHB_RROBIN + write_tristate $cfg $autocfg CONFIG_AHB_RROBIN $CONFIG_AHB_RROBIN [list $notmod] 2 + global CONFIG_AHB_SPLIT + write_tristate $cfg $autocfg CONFIG_AHB_SPLIT $CONFIG_AHB_SPLIT [list $notmod] 2 + global CONFIG_AHB_FPNPEN + write_tristate $cfg $autocfg CONFIG_AHB_FPNPEN $CONFIG_AHB_FPNPEN [list $notmod] 2 + global CONFIG_AHB_IOADDR + write_hex $cfg $autocfg CONFIG_AHB_IOADDR $CONFIG_AHB_IOADDR $notmod + global CONFIG_APB_HADDR + write_hex $cfg $autocfg CONFIG_APB_HADDR $CONFIG_APB_HADDR $notmod + global CONFIG_AHB_MON + write_tristate $cfg $autocfg CONFIG_AHB_MON $CONFIG_AHB_MON [list $notmod] 2 + global CONFIG_AHB_MONERR + if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONERR $CONFIG_AHB_MONERR [list $notmod] 2 } + global CONFIG_AHB_MONWAR + if {($CONFIG_AHB_MON == 1)} then {write_tristate $cfg $autocfg CONFIG_AHB_MONWAR $CONFIG_AHB_MONWAR [list $notmod] 2 } + global CONFIG_AHB_DTRACE + write_tristate $cfg $autocfg CONFIG_AHB_DTRACE $CONFIG_AHB_DTRACE [list $notmod] 2 + write_comment $cfg $autocfg "Debug Link " + global CONFIG_DSU_UART + write_tristate $cfg $autocfg CONFIG_DSU_UART $CONFIG_DSU_UART [list $notmod] 2 + global CONFIG_DSU_JTAG + write_tristate $cfg $autocfg CONFIG_DSU_JTAG $CONFIG_DSU_JTAG [list $notmod] 2 + global CONFIG_DSU_ETH + global CONFIG_GRETH_ENABLE + if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH $CONFIG_DSU_ETH [list $notmod] 2 } + global tmpvar_28 + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { + if { $tmpvar_28 == "1" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ1 0 [list $notmod] 2 } + if { $tmpvar_28 == "2" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ2 0 [list $notmod] 2 } + if { $tmpvar_28 == "4" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ4 0 [list $notmod] 2 } + if { $tmpvar_28 == "8" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ8 0 [list $notmod] 2 } + if { $tmpvar_28 == "16" } then { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DSU_ETHSZ16 0 [list $notmod] 2 }} + global CONFIG_DSU_IPMSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPMSB $CONFIG_DSU_IPMSB $notmod } + global CONFIG_DSU_IPLSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_IPLSB $CONFIG_DSU_IPLSB $notmod } + global CONFIG_DSU_ETHMSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHMSB $CONFIG_DSU_ETHMSB $notmod } + global CONFIG_DSU_ETHLSB + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } + global CONFIG_DSU_ETH_PROG + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + global CONFIG_DSU_ETH_DIS + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + write_comment $cfg $autocfg "Peripherals " + write_comment $cfg $autocfg "Memory controller " + write_comment $cfg $autocfg "Leon2 memory controller " + global CONFIG_MCTRL_LEON2 + write_tristate $cfg $autocfg CONFIG_MCTRL_LEON2 $CONFIG_MCTRL_LEON2 [list $notmod] 2 + global CONFIG_MCTRL_8BIT + if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_8BIT $CONFIG_MCTRL_8BIT [list $notmod] 2 } + global CONFIG_MCTRL_16BIT + if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_16BIT $CONFIG_MCTRL_16BIT [list $notmod] 2 } + global CONFIG_MCTRL_5CS + if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_5CS $CONFIG_MCTRL_5CS [list $notmod] 2 } + global CONFIG_MCTRL_SDRAM + if {($CONFIG_MCTRL_LEON2 == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM $CONFIG_MCTRL_SDRAM [list $notmod] 2 } + global CONFIG_MCTRL_SDRAM_SEPBUS + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_SEPBUS $CONFIG_MCTRL_SDRAM_SEPBUS [list $notmod] 2 } + global CONFIG_MCTRL_SDRAM_BUS64 + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_BUS64 $CONFIG_MCTRL_SDRAM_BUS64 [list $notmod] 2 } + global CONFIG_MCTRL_SDRAM_INVCLK + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_SDRAM_SEPBUS == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_SDRAM_INVCLK $CONFIG_MCTRL_SDRAM_INVCLK [list $notmod] 2 } + global CONFIG_MCTRL_PAGE + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PAGE $CONFIG_MCTRL_PAGE [list $notmod] 2 } + global CONFIG_MCTRL_PROGPAGE + if {($CONFIG_MCTRL_LEON2 == 1) && ($CONFIG_MCTRL_SDRAM == 1) && ($CONFIG_MCTRL_PAGE == 1)} then {write_tristate $cfg $autocfg CONFIG_MCTRL_PROGPAGE $CONFIG_MCTRL_PROGPAGE [list $notmod] 2 } + write_comment $cfg $autocfg "MIG memory controller " + global CONFIG_MIG_DDR2 + write_tristate $cfg $autocfg CONFIG_MIG_DDR2 $CONFIG_MIG_DDR2 [list $notmod] 2 + global CONFIG_MIG_RANKS + if {($CONFIG_MIG_DDR2 == 1)} then {write_int $cfg $autocfg CONFIG_MIG_RANKS $CONFIG_MIG_RANKS $notmod } + global CONFIG_MIG_COLBITS + if {($CONFIG_MIG_DDR2 == 1)} then {write_int $cfg $autocfg CONFIG_MIG_COLBITS $CONFIG_MIG_COLBITS $notmod } + global CONFIG_MIG_ROWBITS + if {($CONFIG_MIG_DDR2 == 1)} then {write_int $cfg $autocfg CONFIG_MIG_ROWBITS $CONFIG_MIG_ROWBITS $notmod } + global CONFIG_MIG_BANKBITS + if {($CONFIG_MIG_DDR2 == 1)} then {write_int $cfg $autocfg CONFIG_MIG_BANKBITS $CONFIG_MIG_BANKBITS $notmod } + global CONFIG_MIG_HMASK + if {($CONFIG_MIG_DDR2 == 1)} then {write_hex $cfg $autocfg CONFIG_MIG_HMASK $CONFIG_MIG_HMASK $notmod } + write_comment $cfg $autocfg "MIG Series 7 memory controller " + global CONFIG_MIG_SERIES7 + write_tristate $cfg $autocfg CONFIG_MIG_SERIES7 $CONFIG_MIG_SERIES7 [list $notmod] 2 + global CONFIG_MIG_SERIES_7_MODEL + write_tristate $cfg $autocfg CONFIG_MIG_SERIES_7_MODEL $CONFIG_MIG_SERIES_7_MODEL [list $notmod] 2 + global CONFIG_AHBSTAT_ENABLE + write_tristate $cfg $autocfg CONFIG_AHBSTAT_ENABLE $CONFIG_AHBSTAT_ENABLE [list $notmod] 2 + global CONFIG_AHBSTAT_NFTSLV + if {($CONFIG_AHBSTAT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_AHBSTAT_NFTSLV $CONFIG_AHBSTAT_NFTSLV $notmod } + write_comment $cfg $autocfg "On-chip RAM/ROM " + global CONFIG_AHBROM_ENABLE + write_tristate $cfg $autocfg CONFIG_AHBROM_ENABLE $CONFIG_AHBROM_ENABLE [list $notmod] 2 + global CONFIG_AHBROM_START + if {($CONFIG_AHBROM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBROM_START $CONFIG_AHBROM_START $notmod } + global CONFIG_AHBROM_PIPE + if {($CONFIG_AHBROM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBROM_PIPE $CONFIG_AHBROM_PIPE [list $notmod] 2 } + global CONFIG_AHBRAM_ENABLE + write_tristate $cfg $autocfg CONFIG_AHBRAM_ENABLE $CONFIG_AHBRAM_ENABLE [list $notmod] 2 + global tmpvar_29 + if {($CONFIG_AHBRAM_ENABLE == 1)} then { + if { $tmpvar_29 == "1" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1 0 [list $notmod] 2 } + if { $tmpvar_29 == "2" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2 0 [list $notmod] 2 } + if { $tmpvar_29 == "4" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4 0 [list $notmod] 2 } + if { $tmpvar_29 == "8" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ8 0 [list $notmod] 2 } + if { $tmpvar_29 == "16" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ16 0 [list $notmod] 2 } + if { $tmpvar_29 == "32" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ32 0 [list $notmod] 2 } + if { $tmpvar_29 == "64" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ64 0 [list $notmod] 2 } + if { $tmpvar_29 == "128" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ128 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ128 0 [list $notmod] 2 } + if { $tmpvar_29 == "256" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ256 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ256 0 [list $notmod] 2 } + if { $tmpvar_29 == "512" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ512 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ512 0 [list $notmod] 2 } + if { $tmpvar_29 == "1024" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1024 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ1024 0 [list $notmod] 2 } + if { $tmpvar_29 == "2048" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2048 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ2048 0 [list $notmod] 2 } + if { $tmpvar_29 == "4096" } then { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4096 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_AHBRAM_SZ4096 0 [list $notmod] 2 }} + global CONFIG_AHBRAM_START + if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_AHBRAM_START $CONFIG_AHBRAM_START $notmod } + global CONFIG_AHBRAM_PIPE + if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } + write_comment $cfg $autocfg "Ethernet " + write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA + if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } + global tmpvar_30 + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if { $tmpvar_30 == "4" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO4 0 [list $notmod] 2 } + if { $tmpvar_30 == "8" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO8 0 [list $notmod] 2 } + if { $tmpvar_30 == "16" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO16 0 [list $notmod] 2 } + if { $tmpvar_30 == "32" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO32 0 [list $notmod] 2 } + if { $tmpvar_30 == "64" } then { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_GRETH_FIFO64 0 [list $notmod] 2 }} + global CONFIG_GRETH_FT + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_LEON3FT_PRESENT == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_FT $CONFIG_GRETH_FT [list $notmod] 2 } + global CONFIG_GRETH_EDCLFT + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_LEON3FT_PRESENT == 1) && ($CONFIG_GRETH_FT == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_EDCLFT $CONFIG_GRETH_EDCLFT [list $notmod] 2 } + write_comment $cfg $autocfg "UARTs, timers and irq control " + global CONFIG_UART1_ENABLE + write_tristate $cfg $autocfg CONFIG_UART1_ENABLE $CONFIG_UART1_ENABLE [list $notmod] 2 + global tmpvar_31 + if {($CONFIG_UART1_ENABLE == 1)} then { + if { $tmpvar_31 == "1" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO1 0 [list $notmod] 2 } + if { $tmpvar_31 == "2" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO2 0 [list $notmod] 2 } + if { $tmpvar_31 == "4" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO4 0 [list $notmod] 2 } + if { $tmpvar_31 == "8" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO8 0 [list $notmod] 2 } + if { $tmpvar_31 == "16" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO16 0 [list $notmod] 2 } + if { $tmpvar_31 == "32" } then { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_UA1_FIFO32 0 [list $notmod] 2 }} + global CONFIG_IRQ3_ENABLE + write_tristate $cfg $autocfg CONFIG_IRQ3_ENABLE $CONFIG_IRQ3_ENABLE [list $notmod] 2 + global CONFIG_IRQ3_SEC + if {($CONFIG_IRQ3_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_IRQ3_SEC $CONFIG_IRQ3_SEC [list $notmod] 2 } + global CONFIG_IRQ3_NSEC + if {($CONFIG_IRQ3_ENABLE == 1) && ($CONFIG_IRQ3_SEC == 1)} then {write_int $cfg $autocfg CONFIG_IRQ3_NSEC $CONFIG_IRQ3_NSEC $notmod } + global CONFIG_GPT_ENABLE + write_tristate $cfg $autocfg CONFIG_GPT_ENABLE $CONFIG_GPT_ENABLE [list $notmod] 2 + global CONFIG_GPT_NTIM + if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_NTIM $CONFIG_GPT_NTIM $notmod } + global CONFIG_GPT_SW + if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_SW $CONFIG_GPT_SW $notmod } + global CONFIG_GPT_TW + if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_TW $CONFIG_GPT_TW $notmod } + global CONFIG_GPT_IRQ + if {($CONFIG_GPT_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GPT_IRQ $CONFIG_GPT_IRQ $notmod } + global CONFIG_GPT_SEPIRQ + if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_SEPIRQ $CONFIG_GPT_SEPIRQ [list $notmod] 2 } + global CONFIG_GPT_WDOGEN + if {($CONFIG_GPT_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GPT_WDOGEN $CONFIG_GPT_WDOGEN [list $notmod] 2 } + global CONFIG_GPT_WDOG + if {($CONFIG_GPT_ENABLE == 1) && ($CONFIG_GPT_WDOGEN == 1)} then {write_hex $cfg $autocfg CONFIG_GPT_WDOG $CONFIG_GPT_WDOG $notmod } + global CONFIG_GRGPIO_ENABLE + write_tristate $cfg $autocfg CONFIG_GRGPIO_ENABLE $CONFIG_GRGPIO_ENABLE [list $notmod] 2 + global CONFIG_GRGPIO_WIDTH + if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_GRGPIO_WIDTH $CONFIG_GRGPIO_WIDTH $notmod } + global CONFIG_GRGPIO_IMASK + if {($CONFIG_GRGPIO_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_GRGPIO_IMASK $CONFIG_GRGPIO_IMASK $notmod } + global CONFIG_I2C_ENABLE + write_tristate $cfg $autocfg CONFIG_I2C_ENABLE $CONFIG_I2C_ENABLE [list $notmod] 2 + write_comment $cfg $autocfg "Keybord and VGA interface" + global CONFIG_KBD_ENABLE + write_tristate $cfg $autocfg CONFIG_KBD_ENABLE $CONFIG_KBD_ENABLE [list $notmod] 2 + global CONFIG_VGA_ENABLE + write_tristate $cfg $autocfg CONFIG_VGA_ENABLE $CONFIG_VGA_ENABLE [list $notmod] 2 + global CONFIG_SVGA_ENABLE + if {($CONFIG_VGA_ENABLE == 0)} then {write_tristate $cfg $autocfg CONFIG_SVGA_ENABLE $CONFIG_SVGA_ENABLE [list $notmod] 2 } + write_comment $cfg $autocfg "SPI" + write_comment $cfg $autocfg "SPI memory controller " + global CONFIG_SPIMCTRL + write_tristate $cfg $autocfg CONFIG_SPIMCTRL $CONFIG_SPIMCTRL [list $notmod] 2 + global CONFIG_SPIMCTRL_SDCARD + if {($CONFIG_SPIMCTRL == 1)} then {write_tristate $cfg $autocfg CONFIG_SPIMCTRL_SDCARD $CONFIG_SPIMCTRL_SDCARD [list $notmod] 2 } + global CONFIG_SPIMCTRL_READCMD + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_hex $cfg $autocfg CONFIG_SPIMCTRL_READCMD $CONFIG_SPIMCTRL_READCMD $notmod } + global CONFIG_SPIMCTRL_DUMMYBYTE + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_tristate $cfg $autocfg CONFIG_SPIMCTRL_DUMMYBYTE $CONFIG_SPIMCTRL_DUMMYBYTE [list $notmod] 2 } + global CONFIG_SPIMCTRL_DUALOUTPUT + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_tristate $cfg $autocfg CONFIG_SPIMCTRL_DUALOUTPUT $CONFIG_SPIMCTRL_DUALOUTPUT [list $notmod] 2 } + global CONFIG_SPIMCTRL_OFFSET + if {($CONFIG_SPIMCTRL == 1) && ($CONFIG_SPIMCTRL_SDCARD != 1)} then {write_hex $cfg $autocfg CONFIG_SPIMCTRL_OFFSET $CONFIG_SPIMCTRL_OFFSET $notmod } + global CONFIG_SPIMCTRL_SCALER + if {($CONFIG_SPIMCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SPIMCTRL_SCALER $CONFIG_SPIMCTRL_SCALER $notmod } + global CONFIG_SPIMCTRL_ASCALER + if {($CONFIG_SPIMCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SPIMCTRL_ASCALER $CONFIG_SPIMCTRL_ASCALER $notmod } + global CONFIG_SPIMCTRL_PWRUPCNT + if {($CONFIG_SPIMCTRL == 1)} then {write_int $cfg $autocfg CONFIG_SPIMCTRL_PWRUPCNT $CONFIG_SPIMCTRL_PWRUPCNT $notmod } + write_comment $cfg $autocfg "SPI controller(s) " + global CONFIG_SPICTRL_ENABLE + write_tristate $cfg $autocfg CONFIG_SPICTRL_ENABLE $CONFIG_SPICTRL_ENABLE [list $notmod] 2 + global CONFIG_SPICTRL_NUM + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_NUM $CONFIG_SPICTRL_NUM $notmod } + global CONFIG_SPICTRL_SLVS + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_SLVS $CONFIG_SPICTRL_SLVS $notmod } + global CONFIG_SPICTRL_FIFO + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_FIFO $CONFIG_SPICTRL_FIFO $notmod } + global CONFIG_SPICTRL_SLVREG + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_SLVREG $CONFIG_SPICTRL_SLVREG [list $notmod] 2 } + global CONFIG_SPICTRL_ASEL + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_ASEL $CONFIG_SPICTRL_ASEL [list $notmod] 2 } + global CONFIG_SPICTRL_AM + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_AM $CONFIG_SPICTRL_AM [list $notmod] 2 } + global CONFIG_SPICTRL_ODMODE + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_ODMODE $CONFIG_SPICTRL_ODMODE [list $notmod] 2 } + global CONFIG_SPICTRL_TWEN + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_TWEN $CONFIG_SPICTRL_TWEN [list $notmod] 2 } + global CONFIG_SPICTRL_MAXWLEN + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_int $cfg $autocfg CONFIG_SPICTRL_MAXWLEN $CONFIG_SPICTRL_MAXWLEN $notmod } + global CONFIG_SPICTRL_SYNCRAM + if {($CONFIG_SPICTRL_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_SPICTRL_SYNCRAM $CONFIG_SPICTRL_SYNCRAM [list $notmod] 2 } + global tmpvar_32 + if {($CONFIG_SPICTRL_ENABLE == 1) && ($CONFIG_SPICTRL_SYNCRAM == 1)} then { + if { $tmpvar_32 == "None" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_NOFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_NOFT 0 [list $notmod] 2 } + if { $tmpvar_32 == "Parity-DMR" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_DMRFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_DMRFT 0 [list $notmod] 2 } + if { $tmpvar_32 == "TMR" } then { write_tristate $cfg $autocfg CONFIG_SPICTRL_TMRFT 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_SPICTRL_TMRFT 0 [list $notmod] 2 }} + write_comment $cfg $autocfg "VHDL Debugging " + global CONFIG_DEBUG_UART + write_tristate $cfg $autocfg CONFIG_DEBUG_UART $CONFIG_DEBUG_UART [list $notmod] 2 + close $cfg + close $autocfg +} + + +proc clear_choices { } { + global CONFIG_SYN_INFERRED; set CONFIG_SYN_INFERRED 0 + global CONFIG_SYN_STRATIX; set CONFIG_SYN_STRATIX 0 + global CONFIG_SYN_STRATIXII; set CONFIG_SYN_STRATIXII 0 + global CONFIG_SYN_STRATIXIII; set CONFIG_SYN_STRATIXIII 0 + global CONFIG_SYN_STRATIXIV; set CONFIG_SYN_STRATIXIV 0 + global CONFIG_SYN_CYCLONEIII; set CONFIG_SYN_CYCLONEIII 0 + global CONFIG_SYN_ALTERA; set CONFIG_SYN_ALTERA 0 + global CONFIG_SYN_AXCEL; set CONFIG_SYN_AXCEL 0 + global CONFIG_SYN_AXDSP; set CONFIG_SYN_AXDSP 0 + global CONFIG_SYN_PROASIC; set CONFIG_SYN_PROASIC 0 + global CONFIG_SYN_PROASICPLUS; set CONFIG_SYN_PROASICPLUS 0 + global CONFIG_SYN_PROASIC3; set CONFIG_SYN_PROASIC3 0 + global CONFIG_SYN_PROASIC3E; set CONFIG_SYN_PROASIC3E 0 + global CONFIG_SYN_PROASIC3L; set CONFIG_SYN_PROASIC3L 0 + global CONFIG_SYN_IGLOO; set CONFIG_SYN_IGLOO 0 + global CONFIG_SYN_FUSION; set CONFIG_SYN_FUSION 0 + global CONFIG_SYN_UT025CRH; set CONFIG_SYN_UT025CRH 0 + global CONFIG_SYN_UT130HBD; set CONFIG_SYN_UT130HBD 0 + global CONFIG_SYN_UT90NHBD; set CONFIG_SYN_UT90NHBD 0 + global CONFIG_SYN_ATC18; set CONFIG_SYN_ATC18 0 + global CONFIG_SYN_ATC18RHA; set CONFIG_SYN_ATC18RHA 0 + global CONFIG_SYN_CMOS9SF; set CONFIG_SYN_CMOS9SF 0 + global CONFIG_SYN_CUSTOM1; set CONFIG_SYN_CUSTOM1 0 + global CONFIG_SYN_EASIC90; set CONFIG_SYN_EASIC90 0 + global CONFIG_SYN_EASIC45; set CONFIG_SYN_EASIC45 0 + global CONFIG_SYN_IHP25; set CONFIG_SYN_IHP25 0 + global CONFIG_SYN_IHP25RH; set CONFIG_SYN_IHP25RH 0 + global CONFIG_SYN_LATTICE; set CONFIG_SYN_LATTICE 0 + global CONFIG_SYN_ECLIPSE; set CONFIG_SYN_ECLIPSE 0 + global CONFIG_SYN_PEREGRINE; set CONFIG_SYN_PEREGRINE 0 + global CONFIG_SYN_RH_LIB18T; set CONFIG_SYN_RH_LIB18T 0 + global CONFIG_SYN_RHUMC; set CONFIG_SYN_RHUMC 0 + global CONFIG_SYN_SAED32; set CONFIG_SYN_SAED32 0 + global CONFIG_SYN_DARE; set CONFIG_SYN_DARE 0 + global CONFIG_SYN_SMIC13; set CONFIG_SYN_SMIC13 0 + global CONFIG_SYN_TM65GPLUS; set CONFIG_SYN_TM65GPLUS 0 + global CONFIG_SYN_TSMC90; set CONFIG_SYN_TSMC90 0 + global CONFIG_SYN_UMC; set CONFIG_SYN_UMC 0 + global CONFIG_SYN_ARTIX7; set CONFIG_SYN_ARTIX7 0 + global CONFIG_SYN_KINTEX7; set CONFIG_SYN_KINTEX7 0 + global CONFIG_SYN_SPARTAN3; set CONFIG_SYN_SPARTAN3 0 + global CONFIG_SYN_SPARTAN3E; set CONFIG_SYN_SPARTAN3E 0 + global CONFIG_SYN_SPARTAN6; set CONFIG_SYN_SPARTAN6 0 + global CONFIG_SYN_VIRTEXE; set CONFIG_SYN_VIRTEXE 0 + global CONFIG_SYN_VIRTEX2; set CONFIG_SYN_VIRTEX2 0 + global CONFIG_SYN_VIRTEX4; set CONFIG_SYN_VIRTEX4 0 + global CONFIG_SYN_VIRTEX5; set CONFIG_SYN_VIRTEX5 0 + global CONFIG_SYN_VIRTEX6; set CONFIG_SYN_VIRTEX6 0 + global CONFIG_SYN_VIRTEX7; set CONFIG_SYN_VIRTEX7 0 + global CONFIG_SYN_ZYNQ7000; set CONFIG_SYN_ZYNQ7000 0 + global CONFIG_MEM_INFERRED; set CONFIG_MEM_INFERRED 0 + global CONFIG_MEM_UMC; set CONFIG_MEM_UMC 0 + global CONFIG_MEM_RHUMC; set CONFIG_MEM_RHUMC 0 + global CONFIG_MEM_SAED32; set CONFIG_MEM_SAED32 0 + global CONFIG_MEM_DARE; set CONFIG_MEM_DARE 0 + global CONFIG_MEM_ARTISAN; set CONFIG_MEM_ARTISAN 0 + global CONFIG_MEM_CUSTOM1; set CONFIG_MEM_CUSTOM1 0 + global CONFIG_MEM_EASIC45; set CONFIG_MEM_EASIC45 0 + global CONFIG_MEM_VIRAGE; set CONFIG_MEM_VIRAGE 0 + global CONFIG_MEM_VIRAGE90; set CONFIG_MEM_VIRAGE90 0 + global CONFIG_CLK_INFERRED; set CONFIG_CLK_INFERRED 0 + global CONFIG_CLK_HCLKBUF; set CONFIG_CLK_HCLKBUF 0 + global CONFIG_CLK_UT130HBD; set CONFIG_CLK_UT130HBD 0 + global CONFIG_CLK_ALTDLL; set CONFIG_CLK_ALTDLL 0 + global CONFIG_CLK_LATDLL; set CONFIG_CLK_LATDLL 0 + global CONFIG_CLK_PRO3PLL; set CONFIG_CLK_PRO3PLL 0 + global CONFIG_CLK_PRO3EPLL; set CONFIG_CLK_PRO3EPLL 0 + global CONFIG_CLK_PRO3LPLL; set CONFIG_CLK_PRO3LPLL 0 + global CONFIG_CLK_FUSPLL; set CONFIG_CLK_FUSPLL 0 + global CONFIG_CLK_LIB18T; set CONFIG_CLK_LIB18T 0 + global CONFIG_CLK_RHUMC; set CONFIG_CLK_RHUMC 0 + global CONFIG_CLK_DARE; set CONFIG_CLK_DARE 0 + global CONFIG_CLK_SAED32; set CONFIG_CLK_SAED32 0 + global CONFIG_CLK_EASIC45; set CONFIG_CLK_EASIC45 0 + global CONFIG_CLK_CLKPLLE2; set CONFIG_CLK_CLKPLLE2 0 + global CONFIG_CLK_CLKDLL; set CONFIG_CLK_CLKDLL 0 + global CONFIG_CLK_DCM; set CONFIG_CLK_DCM 0 + global CONFIG_LEON3_MIN; set CONFIG_LEON3_MIN 0 + global CONFIG_LEON3_GP; set CONFIG_LEON3_GP 0 + global CONFIG_LEON3_HP; set CONFIG_LEON3_HP 0 + global CONFIG_LEON3_CUSTOM; set CONFIG_LEON3_CUSTOM 0 + global CONFIG_IU_MUL_LATENCY_2; set CONFIG_IU_MUL_LATENCY_2 0 + global CONFIG_IU_MUL_LATENCY_4; set CONFIG_IU_MUL_LATENCY_4 0 + global CONFIG_IU_MUL_LATENCY_5; set CONFIG_IU_MUL_LATENCY_5 0 + global CONFIG_IU_MUL_INFERRED; set CONFIG_IU_MUL_INFERRED 0 + global CONFIG_IU_MUL_MODGEN; set CONFIG_IU_MUL_MODGEN 0 + global CONFIG_IU_MUL_TECHSPEC; set CONFIG_IU_MUL_TECHSPEC 0 + global CONFIG_IU_MUL_DW; set CONFIG_IU_MUL_DW 0 + global CONFIG_FPU_GRFPU; set CONFIG_FPU_GRFPU 0 + global CONFIG_FPU_GRFPULITE; set CONFIG_FPU_GRFPULITE 0 + global CONFIG_FPU_MEIKO; set CONFIG_FPU_MEIKO 0 + global CONFIG_FPU_GRFPU_INFMUL; set CONFIG_FPU_GRFPU_INFMUL 0 + global CONFIG_FPU_GRFPU_DWMUL; set CONFIG_FPU_GRFPU_DWMUL 0 + global CONFIG_FPU_GRFPU_MODGEN; set CONFIG_FPU_GRFPU_MODGEN 0 + global CONFIG_FPU_GRFPU_TECHSPEC; set CONFIG_FPU_GRFPU_TECHSPEC 0 + global CONFIG_FPU_GRFPC0; set CONFIG_FPU_GRFPC0 0 + global CONFIG_FPU_GRFPC1; set CONFIG_FPU_GRFPC1 0 + global CONFIG_FPU_GRFPC2; set CONFIG_FPU_GRFPC2 0 + global CONFIG_ICACHE_ASSO1; set CONFIG_ICACHE_ASSO1 0 + global CONFIG_ICACHE_ASSO2; set CONFIG_ICACHE_ASSO2 0 + global CONFIG_ICACHE_ASSO3; set CONFIG_ICACHE_ASSO3 0 + global CONFIG_ICACHE_ASSO4; set CONFIG_ICACHE_ASSO4 0 + global CONFIG_ICACHE_SZ1; set CONFIG_ICACHE_SZ1 0 + global CONFIG_ICACHE_SZ2; set CONFIG_ICACHE_SZ2 0 + global CONFIG_ICACHE_SZ4; set CONFIG_ICACHE_SZ4 0 + global CONFIG_ICACHE_SZ8; set CONFIG_ICACHE_SZ8 0 + global CONFIG_ICACHE_SZ16; set CONFIG_ICACHE_SZ16 0 + global CONFIG_ICACHE_SZ32; set CONFIG_ICACHE_SZ32 0 + global CONFIG_ICACHE_SZ64; set CONFIG_ICACHE_SZ64 0 + global CONFIG_ICACHE_SZ128; set CONFIG_ICACHE_SZ128 0 + global CONFIG_ICACHE_SZ256; set CONFIG_ICACHE_SZ256 0 + global CONFIG_ICACHE_LZ16; set CONFIG_ICACHE_LZ16 0 + global CONFIG_ICACHE_LZ32; set CONFIG_ICACHE_LZ32 0 + global CONFIG_ICACHE_ALGORND; set CONFIG_ICACHE_ALGORND 0 + global CONFIG_ICACHE_ALGODIR; set CONFIG_ICACHE_ALGODIR 0 + global CONFIG_ICACHE_ALGOLRR; set CONFIG_ICACHE_ALGOLRR 0 + global CONFIG_ICACHE_ALGOLRU; set CONFIG_ICACHE_ALGOLRU 0 + global CONFIG_ICACHE_LRAM_SZ1; set CONFIG_ICACHE_LRAM_SZ1 0 + global CONFIG_ICACHE_LRAM_SZ2; set CONFIG_ICACHE_LRAM_SZ2 0 + global CONFIG_ICACHE_LRAM_SZ4; set CONFIG_ICACHE_LRAM_SZ4 0 + global CONFIG_ICACHE_LRAM_SZ8; set CONFIG_ICACHE_LRAM_SZ8 0 + global CONFIG_ICACHE_LRAM_SZ16; set CONFIG_ICACHE_LRAM_SZ16 0 + global CONFIG_ICACHE_LRAM_SZ32; set CONFIG_ICACHE_LRAM_SZ32 0 + global CONFIG_ICACHE_LRAM_SZ64; set CONFIG_ICACHE_LRAM_SZ64 0 + global CONFIG_ICACHE_LRAM_SZ128; set CONFIG_ICACHE_LRAM_SZ128 0 + global CONFIG_ICACHE_LRAM_SZ256; set CONFIG_ICACHE_LRAM_SZ256 0 + global CONFIG_DCACHE_ASSO1; set CONFIG_DCACHE_ASSO1 0 + global CONFIG_DCACHE_ASSO2; set CONFIG_DCACHE_ASSO2 0 + global CONFIG_DCACHE_ASSO3; set CONFIG_DCACHE_ASSO3 0 + global CONFIG_DCACHE_ASSO4; set CONFIG_DCACHE_ASSO4 0 + global CONFIG_DCACHE_SZ1; set CONFIG_DCACHE_SZ1 0 + global CONFIG_DCACHE_SZ2; set CONFIG_DCACHE_SZ2 0 + global CONFIG_DCACHE_SZ4; set CONFIG_DCACHE_SZ4 0 + global CONFIG_DCACHE_SZ8; set CONFIG_DCACHE_SZ8 0 + global CONFIG_DCACHE_SZ16; set CONFIG_DCACHE_SZ16 0 + global CONFIG_DCACHE_SZ32; set CONFIG_DCACHE_SZ32 0 + global CONFIG_DCACHE_SZ64; set CONFIG_DCACHE_SZ64 0 + global CONFIG_DCACHE_SZ128; set CONFIG_DCACHE_SZ128 0 + global CONFIG_DCACHE_SZ256; set CONFIG_DCACHE_SZ256 0 + global CONFIG_DCACHE_LZ16; set CONFIG_DCACHE_LZ16 0 + global CONFIG_DCACHE_LZ32; set CONFIG_DCACHE_LZ32 0 + global CONFIG_DCACHE_ALGORND; set CONFIG_DCACHE_ALGORND 0 + global CONFIG_DCACHE_ALGODIR; set CONFIG_DCACHE_ALGODIR 0 + global CONFIG_DCACHE_ALGOLRR; set CONFIG_DCACHE_ALGOLRR 0 + global CONFIG_DCACHE_ALGOLRU; set CONFIG_DCACHE_ALGOLRU 0 + global CONFIG_DCACHE_LRAM_SZ1; set CONFIG_DCACHE_LRAM_SZ1 0 + global CONFIG_DCACHE_LRAM_SZ2; set CONFIG_DCACHE_LRAM_SZ2 0 + global CONFIG_DCACHE_LRAM_SZ4; set CONFIG_DCACHE_LRAM_SZ4 0 + global CONFIG_DCACHE_LRAM_SZ8; set CONFIG_DCACHE_LRAM_SZ8 0 + global CONFIG_DCACHE_LRAM_SZ16; set CONFIG_DCACHE_LRAM_SZ16 0 + global CONFIG_DCACHE_LRAM_SZ32; set CONFIG_DCACHE_LRAM_SZ32 0 + global CONFIG_DCACHE_LRAM_SZ64; set CONFIG_DCACHE_LRAM_SZ64 0 + global CONFIG_DCACHE_LRAM_SZ128; set CONFIG_DCACHE_LRAM_SZ128 0 + global CONFIG_DCACHE_LRAM_SZ256; set CONFIG_DCACHE_LRAM_SZ256 0 + global CONFIG_MMU_COMBINED; set CONFIG_MMU_COMBINED 0 + global CONFIG_MMU_SPLIT; set CONFIG_MMU_SPLIT 0 + global CONFIG_MMU_REPARRAY; set CONFIG_MMU_REPARRAY 0 + global CONFIG_MMU_REPINCREMENT; set CONFIG_MMU_REPINCREMENT 0 + global CONFIG_MMU_I2; set CONFIG_MMU_I2 0 + global CONFIG_MMU_I4; set CONFIG_MMU_I4 0 + global CONFIG_MMU_I8; set CONFIG_MMU_I8 0 + global CONFIG_MMU_I16; set CONFIG_MMU_I16 0 + global CONFIG_MMU_I32; set CONFIG_MMU_I32 0 + global CONFIG_MMU_I64; set CONFIG_MMU_I64 0 + global CONFIG_MMU_D2; set CONFIG_MMU_D2 0 + global CONFIG_MMU_D4; set CONFIG_MMU_D4 0 + global CONFIG_MMU_D8; set CONFIG_MMU_D8 0 + global CONFIG_MMU_D16; set CONFIG_MMU_D16 0 + global CONFIG_MMU_D32; set CONFIG_MMU_D32 0 + global CONFIG_MMU_D64; set CONFIG_MMU_D64 0 + global CONFIG_MMU_PAGE_4K; set CONFIG_MMU_PAGE_4K 0 + global CONFIG_MMU_PAGE_8K; set CONFIG_MMU_PAGE_8K 0 + global CONFIG_MMU_PAGE_16K; set CONFIG_MMU_PAGE_16K 0 + global CONFIG_MMU_PAGE_32K; set CONFIG_MMU_PAGE_32K 0 + global CONFIG_MMU_PAGE_PROG; set CONFIG_MMU_PAGE_PROG 0 + global CONFIG_DSU_ITRACESZ1; set CONFIG_DSU_ITRACESZ1 0 + global CONFIG_DSU_ITRACESZ2; set CONFIG_DSU_ITRACESZ2 0 + global CONFIG_DSU_ITRACESZ4; set CONFIG_DSU_ITRACESZ4 0 + global CONFIG_DSU_ITRACESZ8; set CONFIG_DSU_ITRACESZ8 0 + global CONFIG_DSU_ITRACESZ16; set CONFIG_DSU_ITRACESZ16 0 + global CONFIG_DSU_ATRACESZ1; set CONFIG_DSU_ATRACESZ1 0 + global CONFIG_DSU_ATRACESZ2; set CONFIG_DSU_ATRACESZ2 0 + global CONFIG_DSU_ATRACESZ4; set CONFIG_DSU_ATRACESZ4 0 + global CONFIG_DSU_ATRACESZ8; set CONFIG_DSU_ATRACESZ8 0 + global CONFIG_DSU_ATRACESZ16; set CONFIG_DSU_ATRACESZ16 0 + global CONFIG_IUFT_NONE; set CONFIG_IUFT_NONE 0 + global CONFIG_IUFT_PAR; set CONFIG_IUFT_PAR 0 + global CONFIG_IUFT_DMR; set CONFIG_IUFT_DMR 0 + global CONFIG_IUFT_BCH; set CONFIG_IUFT_BCH 0 + global CONFIG_IUFT_TMR; set CONFIG_IUFT_TMR 0 + global CONFIG_FPUFT_NONE; set CONFIG_FPUFT_NONE 0 + global CONFIG_FPUFT_PAR; set CONFIG_FPUFT_PAR 0 + global CONFIG_FPUFT_DMR; set CONFIG_FPUFT_DMR 0 + global CONFIG_FPUFT_TMR; set CONFIG_FPUFT_TMR 0 + global CONFIG_DSU_ETHSZ1; set CONFIG_DSU_ETHSZ1 0 + global CONFIG_DSU_ETHSZ2; set CONFIG_DSU_ETHSZ2 0 + global CONFIG_DSU_ETHSZ4; set CONFIG_DSU_ETHSZ4 0 + global CONFIG_DSU_ETHSZ8; set CONFIG_DSU_ETHSZ8 0 + global CONFIG_DSU_ETHSZ16; set CONFIG_DSU_ETHSZ16 0 + global CONFIG_AHBRAM_SZ1; set CONFIG_AHBRAM_SZ1 0 + global CONFIG_AHBRAM_SZ2; set CONFIG_AHBRAM_SZ2 0 + global CONFIG_AHBRAM_SZ4; set CONFIG_AHBRAM_SZ4 0 + global CONFIG_AHBRAM_SZ8; set CONFIG_AHBRAM_SZ8 0 + global CONFIG_AHBRAM_SZ16; set CONFIG_AHBRAM_SZ16 0 + global CONFIG_AHBRAM_SZ32; set CONFIG_AHBRAM_SZ32 0 + global CONFIG_AHBRAM_SZ64; set CONFIG_AHBRAM_SZ64 0 + global CONFIG_AHBRAM_SZ128; set CONFIG_AHBRAM_SZ128 0 + global CONFIG_AHBRAM_SZ256; set CONFIG_AHBRAM_SZ256 0 + global CONFIG_AHBRAM_SZ512; set CONFIG_AHBRAM_SZ512 0 + global CONFIG_AHBRAM_SZ1024; set CONFIG_AHBRAM_SZ1024 0 + global CONFIG_AHBRAM_SZ2048; set CONFIG_AHBRAM_SZ2048 0 + global CONFIG_AHBRAM_SZ4096; set CONFIG_AHBRAM_SZ4096 0 + global CONFIG_GRETH_FIFO4; set CONFIG_GRETH_FIFO4 0 + global CONFIG_GRETH_FIFO8; set CONFIG_GRETH_FIFO8 0 + global CONFIG_GRETH_FIFO16; set CONFIG_GRETH_FIFO16 0 + global CONFIG_GRETH_FIFO32; set CONFIG_GRETH_FIFO32 0 + global CONFIG_GRETH_FIFO64; set CONFIG_GRETH_FIFO64 0 + global CONFIG_UA1_FIFO1; set CONFIG_UA1_FIFO1 0 + global CONFIG_UA1_FIFO2; set CONFIG_UA1_FIFO2 0 + global CONFIG_UA1_FIFO4; set CONFIG_UA1_FIFO4 0 + global CONFIG_UA1_FIFO8; set CONFIG_UA1_FIFO8 0 + global CONFIG_UA1_FIFO16; set CONFIG_UA1_FIFO16 0 + global CONFIG_UA1_FIFO32; set CONFIG_UA1_FIFO32 0 + global CONFIG_SPICTRL_NOFT; set CONFIG_SPICTRL_NOFT 0 + global CONFIG_SPICTRL_DMRFT; set CONFIG_SPICTRL_DMRFT 0 + global CONFIG_SPICTRL_TMRFT; set CONFIG_SPICTRL_TMRFT 0 +} + + +proc update_choices { } { + global tmpvar_0 + set tmpvar_0 "Inferred" + global CONFIG_SYN_INFERRED + if { $CONFIG_SYN_INFERRED == 1 } then { set tmpvar_0 "Inferred" } + global CONFIG_SYN_STRATIX + if { $CONFIG_SYN_STRATIX == 1 } then { set tmpvar_0 "Altera-Stratix" } + global CONFIG_SYN_STRATIXII + if { $CONFIG_SYN_STRATIXII == 1 } then { set tmpvar_0 "Altera-StratixII" } + global CONFIG_SYN_STRATIXIII + if { $CONFIG_SYN_STRATIXIII == 1 } then { set tmpvar_0 "Altera-StratixIII" } + global CONFIG_SYN_STRATIXIV + if { $CONFIG_SYN_STRATIXIV == 1 } then { set tmpvar_0 "Altera-StratixIV" } + global CONFIG_SYN_CYCLONEIII + if { $CONFIG_SYN_CYCLONEIII == 1 } then { set tmpvar_0 "Altera-CycloneIII" } + global CONFIG_SYN_ALTERA + if { $CONFIG_SYN_ALTERA == 1 } then { set tmpvar_0 "Altera-Others" } + global CONFIG_SYN_AXCEL + if { $CONFIG_SYN_AXCEL == 1 } then { set tmpvar_0 "Actel-Axcelerator" } + global CONFIG_SYN_AXDSP + if { $CONFIG_SYN_AXDSP == 1 } then { set tmpvar_0 "Actel-Axcelerator-DSP" } + global CONFIG_SYN_PROASIC + if { $CONFIG_SYN_PROASIC == 1 } then { set tmpvar_0 "Actel-Proasic" } + global CONFIG_SYN_PROASICPLUS + if { $CONFIG_SYN_PROASICPLUS == 1 } then { set tmpvar_0 "Actel-ProasicPlus" } + global CONFIG_SYN_PROASIC3 + if { $CONFIG_SYN_PROASIC3 == 1 } then { set tmpvar_0 "Actel-Proasic3" } + global CONFIG_SYN_PROASIC3E + if { $CONFIG_SYN_PROASIC3E == 1 } then { set tmpvar_0 "Actel-Proasic3E" } + global CONFIG_SYN_PROASIC3L + if { $CONFIG_SYN_PROASIC3L == 1 } then { set tmpvar_0 "Actel-Proasic3L" } + global CONFIG_SYN_IGLOO + if { $CONFIG_SYN_IGLOO == 1 } then { set tmpvar_0 "Actel-IGLOO/p/L" } + global CONFIG_SYN_FUSION + if { $CONFIG_SYN_FUSION == 1 } then { set tmpvar_0 "Actel-Fusion" } + global CONFIG_SYN_UT025CRH + if { $CONFIG_SYN_UT025CRH == 1 } then { set tmpvar_0 "Aeroflex-UT025CRH" } + global CONFIG_SYN_UT130HBD + if { $CONFIG_SYN_UT130HBD == 1 } then { set tmpvar_0 "Aeroflex-UT130HBD" } + global CONFIG_SYN_UT90NHBD + if { $CONFIG_SYN_UT90NHBD == 1 } then { set tmpvar_0 "Aeroflex-UT90NHBD" } + global CONFIG_SYN_ATC18 + if { $CONFIG_SYN_ATC18 == 1 } then { set tmpvar_0 "Atmel-ATC18" } + global CONFIG_SYN_ATC18RHA + if { $CONFIG_SYN_ATC18RHA == 1 } then { set tmpvar_0 "Atmel-ATC18RHA" } + global CONFIG_SYN_CMOS9SF + if { $CONFIG_SYN_CMOS9SF == 1 } then { set tmpvar_0 "IBM-CMOS9SF" } + global CONFIG_SYN_CUSTOM1 + if { $CONFIG_SYN_CUSTOM1 == 1 } then { set tmpvar_0 "Custom1" } + global CONFIG_SYN_EASIC90 + if { $CONFIG_SYN_EASIC90 == 1 } then { set tmpvar_0 "eASIC90" } + global CONFIG_SYN_EASIC45 + if { $CONFIG_SYN_EASIC45 == 1 } then { set tmpvar_0 "eASIC45" } + global CONFIG_SYN_IHP25 + if { $CONFIG_SYN_IHP25 == 1 } then { set tmpvar_0 "IHP25" } + global CONFIG_SYN_IHP25RH + if { $CONFIG_SYN_IHP25RH == 1 } then { set tmpvar_0 "IHP25RH" } + global CONFIG_SYN_LATTICE + if { $CONFIG_SYN_LATTICE == 1 } then { set tmpvar_0 "Lattice-EC/ECP/XP" } + global CONFIG_SYN_ECLIPSE + if { $CONFIG_SYN_ECLIPSE == 1 } then { set tmpvar_0 "Quicklogic-Eclipse" } + global CONFIG_SYN_PEREGRINE + if { $CONFIG_SYN_PEREGRINE == 1 } then { set tmpvar_0 "Peregrine" } + global CONFIG_SYN_RH_LIB18T + if { $CONFIG_SYN_RH_LIB18T == 1 } then { set tmpvar_0 "RH-LIB18T" } + global CONFIG_SYN_RHUMC + if { $CONFIG_SYN_RHUMC == 1 } then { set tmpvar_0 "RH-UMC" } + global CONFIG_SYN_SAED32 + if { $CONFIG_SYN_SAED32 == 1 } then { set tmpvar_0 "SAED32" } + global CONFIG_SYN_DARE + if { $CONFIG_SYN_DARE == 1 } then { set tmpvar_0 "DARE" } + global CONFIG_SYN_SMIC13 + if { $CONFIG_SYN_SMIC13 == 1 } then { set tmpvar_0 "SMIC130" } + global CONFIG_SYN_TM65GPLUS + if { $CONFIG_SYN_TM65GPLUS == 1 } then { set tmpvar_0 "TM65Gplus" } + global CONFIG_SYN_TSMC90 + if { $CONFIG_SYN_TSMC90 == 1 } then { set tmpvar_0 "TSMC90" } + global CONFIG_SYN_UMC + if { $CONFIG_SYN_UMC == 1 } then { set tmpvar_0 "UMC180" } + global CONFIG_SYN_ARTIX7 + if { $CONFIG_SYN_ARTIX7 == 1 } then { set tmpvar_0 "Xilinx-Artix7" } + global CONFIG_SYN_KINTEX7 + if { $CONFIG_SYN_KINTEX7 == 1 } then { set tmpvar_0 "Xilinx-Kintex7" } + global CONFIG_SYN_SPARTAN3 + if { $CONFIG_SYN_SPARTAN3 == 1 } then { set tmpvar_0 "Xilinx-Spartan3" } + global CONFIG_SYN_SPARTAN3E + if { $CONFIG_SYN_SPARTAN3E == 1 } then { set tmpvar_0 "Xilinx-Spartan3E" } + global CONFIG_SYN_SPARTAN6 + if { $CONFIG_SYN_SPARTAN6 == 1 } then { set tmpvar_0 "Xilinx-Spartan6" } + global CONFIG_SYN_VIRTEXE + if { $CONFIG_SYN_VIRTEXE == 1 } then { set tmpvar_0 "Xilinx-VirtexE" } + global CONFIG_SYN_VIRTEX2 + if { $CONFIG_SYN_VIRTEX2 == 1 } then { set tmpvar_0 "Xilinx-Virtex2" } + global CONFIG_SYN_VIRTEX4 + if { $CONFIG_SYN_VIRTEX4 == 1 } then { set tmpvar_0 "Xilinx-Virtex4" } + global CONFIG_SYN_VIRTEX5 + if { $CONFIG_SYN_VIRTEX5 == 1 } then { set tmpvar_0 "Xilinx-Virtex5" } + global CONFIG_SYN_VIRTEX6 + if { $CONFIG_SYN_VIRTEX6 == 1 } then { set tmpvar_0 "Xilinx-Virtex6" } + global CONFIG_SYN_VIRTEX7 + if { $CONFIG_SYN_VIRTEX7 == 1 } then { set tmpvar_0 "Xilinx-Virtex7" } + global CONFIG_SYN_ZYNQ7000 + if { $CONFIG_SYN_ZYNQ7000 == 1 } then { set tmpvar_0 "Xilinx-Zynq7000" } + global tmpvar_1 + set tmpvar_1 "Inferred" + global CONFIG_MEM_INFERRED + if { $CONFIG_MEM_INFERRED == 1 } then { set tmpvar_1 "Inferred" } + global CONFIG_MEM_UMC + if { $CONFIG_MEM_UMC == 1 } then { set tmpvar_1 "UMC18" } + global CONFIG_MEM_RHUMC + if { $CONFIG_MEM_RHUMC == 1 } then { set tmpvar_1 "RH-UMC" } + global CONFIG_MEM_SAED32 + if { $CONFIG_MEM_SAED32 == 1 } then { set tmpvar_1 "SAED32" } + global CONFIG_MEM_DARE + if { $CONFIG_MEM_DARE == 1 } then { set tmpvar_1 "DARE" } + global CONFIG_MEM_ARTISAN + if { $CONFIG_MEM_ARTISAN == 1 } then { set tmpvar_1 "Artisan" } + global CONFIG_MEM_CUSTOM1 + if { $CONFIG_MEM_CUSTOM1 == 1 } then { set tmpvar_1 "Custom1" } + global CONFIG_MEM_EASIC45 + if { $CONFIG_MEM_EASIC45 == 1 } then { set tmpvar_1 "EASIC45" } + global CONFIG_MEM_VIRAGE + if { $CONFIG_MEM_VIRAGE == 1 } then { set tmpvar_1 "Virage" } + global CONFIG_MEM_VIRAGE90 + if { $CONFIG_MEM_VIRAGE90 == 1 } then { set tmpvar_1 "Virage-TSMC90" } + global tmpvar_2 + set tmpvar_2 "Inferred" + global CONFIG_CLK_INFERRED + if { $CONFIG_CLK_INFERRED == 1 } then { set tmpvar_2 "Inferred" } + global CONFIG_CLK_HCLKBUF + if { $CONFIG_CLK_HCLKBUF == 1 } then { set tmpvar_2 "Actel-HCLKBUF" } + global CONFIG_CLK_UT130HBD + if { $CONFIG_CLK_UT130HBD == 1 } then { set tmpvar_2 "Aeroflex-UT130HBD" } + global CONFIG_CLK_ALTDLL + if { $CONFIG_CLK_ALTDLL == 1 } then { set tmpvar_2 "Altera-ALTPLL" } + global CONFIG_CLK_LATDLL + if { $CONFIG_CLK_LATDLL == 1 } then { set tmpvar_2 "Lattice-EXPLL" } + global CONFIG_CLK_PRO3PLL + if { $CONFIG_CLK_PRO3PLL == 1 } then { set tmpvar_2 "Proasic3-PLL" } + global CONFIG_CLK_PRO3EPLL + if { $CONFIG_CLK_PRO3EPLL == 1 } then { set tmpvar_2 "Proasic3E-PLL" } + global CONFIG_CLK_PRO3LPLL + if { $CONFIG_CLK_PRO3LPLL == 1 } then { set tmpvar_2 "Proasic3L-PLL" } + global CONFIG_CLK_FUSPLL + if { $CONFIG_CLK_FUSPLL == 1 } then { set tmpvar_2 "Fusion-PLL" } + global CONFIG_CLK_LIB18T + if { $CONFIG_CLK_LIB18T == 1 } then { set tmpvar_2 "RH-LIB18T-PLL" } + global CONFIG_CLK_RHUMC + if { $CONFIG_CLK_RHUMC == 1 } then { set tmpvar_2 "RHUMC-PLL" } + global CONFIG_CLK_DARE + if { $CONFIG_CLK_DARE == 1 } then { set tmpvar_2 "DARE-PLL" } + global CONFIG_CLK_SAED32 + if { $CONFIG_CLK_SAED32 == 1 } then { set tmpvar_2 "SAED32-PLL" } + global CONFIG_CLK_EASIC45 + if { $CONFIG_CLK_EASIC45 == 1 } then { set tmpvar_2 "EASIC45-PLL" } + global CONFIG_CLK_CLKPLLE2 + if { $CONFIG_CLK_CLKPLLE2 == 1 } then { set tmpvar_2 "Xilinx-PLLE2" } + global CONFIG_CLK_CLKDLL + if { $CONFIG_CLK_CLKDLL == 1 } then { set tmpvar_2 "Xilinx-CLKDLL" } + global CONFIG_CLK_DCM + if { $CONFIG_CLK_DCM == 1 } then { set tmpvar_2 "Xilinx-DCM" } + global tmpvar_3 + set tmpvar_3 "Custom-configuration" + global CONFIG_LEON3_MIN + if { $CONFIG_LEON3_MIN == 1 } then { set tmpvar_3 "Minimal-configuration" } + global CONFIG_LEON3_GP + if { $CONFIG_LEON3_GP == 1 } then { set tmpvar_3 "General-purpose-cfg" } + global CONFIG_LEON3_HP + if { $CONFIG_LEON3_HP == 1 } then { set tmpvar_3 "High-Performance-cfg" } + global CONFIG_LEON3_CUSTOM + if { $CONFIG_LEON3_CUSTOM == 1 } then { set tmpvar_3 "Custom-configuration" } + global tmpvar_4 + set tmpvar_4 "5-cycles" + global CONFIG_IU_MUL_LATENCY_2 + if { $CONFIG_IU_MUL_LATENCY_2 == 1 } then { set tmpvar_4 "2-cycles" } + global CONFIG_IU_MUL_LATENCY_4 + if { $CONFIG_IU_MUL_LATENCY_4 == 1 } then { set tmpvar_4 "4-cycles" } + global CONFIG_IU_MUL_LATENCY_5 + if { $CONFIG_IU_MUL_LATENCY_5 == 1 } then { set tmpvar_4 "5-cycles" } + global tmpvar_5 + set tmpvar_5 "Inferred" + global CONFIG_IU_MUL_INFERRED + if { $CONFIG_IU_MUL_INFERRED == 1 } then { set tmpvar_5 "Inferred" } + global CONFIG_IU_MUL_MODGEN + if { $CONFIG_IU_MUL_MODGEN == 1 } then { set tmpvar_5 "NTNU_Modgen" } + global CONFIG_IU_MUL_TECHSPEC + if { $CONFIG_IU_MUL_TECHSPEC == 1 } then { set tmpvar_5 "TechSpec" } + global CONFIG_IU_MUL_DW + if { $CONFIG_IU_MUL_DW == 1 } then { set tmpvar_5 "Designware" } + global tmpvar_6 + set tmpvar_6 "GRFPU" + global CONFIG_FPU_GRFPU + if { $CONFIG_FPU_GRFPU == 1 } then { set tmpvar_6 "GRFPU" } + global CONFIG_FPU_GRFPULITE + if { $CONFIG_FPU_GRFPULITE == 1 } then { set tmpvar_6 "GRFPU-LITE" } + global CONFIG_FPU_MEIKO + if { $CONFIG_FPU_MEIKO == 1 } then { set tmpvar_6 "Meiko" } + global tmpvar_7 + set tmpvar_7 "Inferred" + global CONFIG_FPU_GRFPU_INFMUL + if { $CONFIG_FPU_GRFPU_INFMUL == 1 } then { set tmpvar_7 "Inferred" } + global CONFIG_FPU_GRFPU_DWMUL + if { $CONFIG_FPU_GRFPU_DWMUL == 1 } then { set tmpvar_7 "DW" } + global CONFIG_FPU_GRFPU_MODGEN + if { $CONFIG_FPU_GRFPU_MODGEN == 1 } then { set tmpvar_7 "ModGen" } + global CONFIG_FPU_GRFPU_TECHSPEC + if { $CONFIG_FPU_GRFPU_TECHSPEC == 1 } then { set tmpvar_7 "TechSpec" } + global tmpvar_8 + set tmpvar_8 "Simple" + global CONFIG_FPU_GRFPC0 + if { $CONFIG_FPU_GRFPC0 == 1 } then { set tmpvar_8 "Simple" } + global CONFIG_FPU_GRFPC1 + if { $CONFIG_FPU_GRFPC1 == 1 } then { set tmpvar_8 "Data-forwarding" } + global CONFIG_FPU_GRFPC2 + if { $CONFIG_FPU_GRFPC2 == 1 } then { set tmpvar_8 "Non-blocking" } + global tmpvar_9 + set tmpvar_9 "1" + global CONFIG_ICACHE_ASSO1 + if { $CONFIG_ICACHE_ASSO1 == 1 } then { set tmpvar_9 "1" } + global CONFIG_ICACHE_ASSO2 + if { $CONFIG_ICACHE_ASSO2 == 1 } then { set tmpvar_9 "2" } + global CONFIG_ICACHE_ASSO3 + if { $CONFIG_ICACHE_ASSO3 == 1 } then { set tmpvar_9 "3" } + global CONFIG_ICACHE_ASSO4 + if { $CONFIG_ICACHE_ASSO4 == 1 } then { set tmpvar_9 "4" } + global tmpvar_10 + set tmpvar_10 "4" + global CONFIG_ICACHE_SZ1 + if { $CONFIG_ICACHE_SZ1 == 1 } then { set tmpvar_10 "1" } + global CONFIG_ICACHE_SZ2 + if { $CONFIG_ICACHE_SZ2 == 1 } then { set tmpvar_10 "2" } + global CONFIG_ICACHE_SZ4 + if { $CONFIG_ICACHE_SZ4 == 1 } then { set tmpvar_10 "4" } + global CONFIG_ICACHE_SZ8 + if { $CONFIG_ICACHE_SZ8 == 1 } then { set tmpvar_10 "8" } + global CONFIG_ICACHE_SZ16 + if { $CONFIG_ICACHE_SZ16 == 1 } then { set tmpvar_10 "16" } + global CONFIG_ICACHE_SZ32 + if { $CONFIG_ICACHE_SZ32 == 1 } then { set tmpvar_10 "32" } + global CONFIG_ICACHE_SZ64 + if { $CONFIG_ICACHE_SZ64 == 1 } then { set tmpvar_10 "64" } + global CONFIG_ICACHE_SZ128 + if { $CONFIG_ICACHE_SZ128 == 1 } then { set tmpvar_10 "128" } + global CONFIG_ICACHE_SZ256 + if { $CONFIG_ICACHE_SZ256 == 1 } then { set tmpvar_10 "256" } + global tmpvar_11 + set tmpvar_11 "32" + global CONFIG_ICACHE_LZ16 + if { $CONFIG_ICACHE_LZ16 == 1 } then { set tmpvar_11 "16" } + global CONFIG_ICACHE_LZ32 + if { $CONFIG_ICACHE_LZ32 == 1 } then { set tmpvar_11 "32" } + global tmpvar_12 + set tmpvar_12 "Random" + global CONFIG_ICACHE_ALGORND + if { $CONFIG_ICACHE_ALGORND == 1 } then { set tmpvar_12 "Random" } + global CONFIG_ICACHE_ALGODIR + if { $CONFIG_ICACHE_ALGODIR == 1 } then { set tmpvar_12 "Direct" } + global CONFIG_ICACHE_ALGOLRR + if { $CONFIG_ICACHE_ALGOLRR == 1 } then { set tmpvar_12 "LRR" } + global CONFIG_ICACHE_ALGOLRU + if { $CONFIG_ICACHE_ALGOLRU == 1 } then { set tmpvar_12 "LRU" } + global tmpvar_13 + set tmpvar_13 "4" + global CONFIG_ICACHE_LRAM_SZ1 + if { $CONFIG_ICACHE_LRAM_SZ1 == 1 } then { set tmpvar_13 "1" } + global CONFIG_ICACHE_LRAM_SZ2 + if { $CONFIG_ICACHE_LRAM_SZ2 == 1 } then { set tmpvar_13 "2" } + global CONFIG_ICACHE_LRAM_SZ4 + if { $CONFIG_ICACHE_LRAM_SZ4 == 1 } then { set tmpvar_13 "4" } + global CONFIG_ICACHE_LRAM_SZ8 + if { $CONFIG_ICACHE_LRAM_SZ8 == 1 } then { set tmpvar_13 "8" } + global CONFIG_ICACHE_LRAM_SZ16 + if { $CONFIG_ICACHE_LRAM_SZ16 == 1 } then { set tmpvar_13 "16" } + global CONFIG_ICACHE_LRAM_SZ32 + if { $CONFIG_ICACHE_LRAM_SZ32 == 1 } then { set tmpvar_13 "32" } + global CONFIG_ICACHE_LRAM_SZ64 + if { $CONFIG_ICACHE_LRAM_SZ64 == 1 } then { set tmpvar_13 "64" } + global CONFIG_ICACHE_LRAM_SZ128 + if { $CONFIG_ICACHE_LRAM_SZ128 == 1 } then { set tmpvar_13 "128" } + global CONFIG_ICACHE_LRAM_SZ256 + if { $CONFIG_ICACHE_LRAM_SZ256 == 1 } then { set tmpvar_13 "256" } + global tmpvar_14 + set tmpvar_14 "1" + global CONFIG_DCACHE_ASSO1 + if { $CONFIG_DCACHE_ASSO1 == 1 } then { set tmpvar_14 "1" } + global CONFIG_DCACHE_ASSO2 + if { $CONFIG_DCACHE_ASSO2 == 1 } then { set tmpvar_14 "2" } + global CONFIG_DCACHE_ASSO3 + if { $CONFIG_DCACHE_ASSO3 == 1 } then { set tmpvar_14 "3" } + global CONFIG_DCACHE_ASSO4 + if { $CONFIG_DCACHE_ASSO4 == 1 } then { set tmpvar_14 "4" } + global tmpvar_15 + set tmpvar_15 "4" + global CONFIG_DCACHE_SZ1 + if { $CONFIG_DCACHE_SZ1 == 1 } then { set tmpvar_15 "1" } + global CONFIG_DCACHE_SZ2 + if { $CONFIG_DCACHE_SZ2 == 1 } then { set tmpvar_15 "2" } + global CONFIG_DCACHE_SZ4 + if { $CONFIG_DCACHE_SZ4 == 1 } then { set tmpvar_15 "4" } + global CONFIG_DCACHE_SZ8 + if { $CONFIG_DCACHE_SZ8 == 1 } then { set tmpvar_15 "8" } + global CONFIG_DCACHE_SZ16 + if { $CONFIG_DCACHE_SZ16 == 1 } then { set tmpvar_15 "16" } + global CONFIG_DCACHE_SZ32 + if { $CONFIG_DCACHE_SZ32 == 1 } then { set tmpvar_15 "32" } + global CONFIG_DCACHE_SZ64 + if { $CONFIG_DCACHE_SZ64 == 1 } then { set tmpvar_15 "64" } + global CONFIG_DCACHE_SZ128 + if { $CONFIG_DCACHE_SZ128 == 1 } then { set tmpvar_15 "128" } + global CONFIG_DCACHE_SZ256 + if { $CONFIG_DCACHE_SZ256 == 1 } then { set tmpvar_15 "256" } + global tmpvar_16 + set tmpvar_16 "32" + global CONFIG_DCACHE_LZ16 + if { $CONFIG_DCACHE_LZ16 == 1 } then { set tmpvar_16 "16" } + global CONFIG_DCACHE_LZ32 + if { $CONFIG_DCACHE_LZ32 == 1 } then { set tmpvar_16 "32" } + global tmpvar_17 + set tmpvar_17 "Random" + global CONFIG_DCACHE_ALGORND + if { $CONFIG_DCACHE_ALGORND == 1 } then { set tmpvar_17 "Random" } + global CONFIG_DCACHE_ALGODIR + if { $CONFIG_DCACHE_ALGODIR == 1 } then { set tmpvar_17 "Direct" } + global CONFIG_DCACHE_ALGOLRR + if { $CONFIG_DCACHE_ALGOLRR == 1 } then { set tmpvar_17 "LRR" } + global CONFIG_DCACHE_ALGOLRU + if { $CONFIG_DCACHE_ALGOLRU == 1 } then { set tmpvar_17 "LRU" } + global tmpvar_18 + set tmpvar_18 "4" + global CONFIG_DCACHE_LRAM_SZ1 + if { $CONFIG_DCACHE_LRAM_SZ1 == 1 } then { set tmpvar_18 "1" } + global CONFIG_DCACHE_LRAM_SZ2 + if { $CONFIG_DCACHE_LRAM_SZ2 == 1 } then { set tmpvar_18 "2" } + global CONFIG_DCACHE_LRAM_SZ4 + if { $CONFIG_DCACHE_LRAM_SZ4 == 1 } then { set tmpvar_18 "4" } + global CONFIG_DCACHE_LRAM_SZ8 + if { $CONFIG_DCACHE_LRAM_SZ8 == 1 } then { set tmpvar_18 "8" } + global CONFIG_DCACHE_LRAM_SZ16 + if { $CONFIG_DCACHE_LRAM_SZ16 == 1 } then { set tmpvar_18 "16" } + global CONFIG_DCACHE_LRAM_SZ32 + if { $CONFIG_DCACHE_LRAM_SZ32 == 1 } then { set tmpvar_18 "32" } + global CONFIG_DCACHE_LRAM_SZ64 + if { $CONFIG_DCACHE_LRAM_SZ64 == 1 } then { set tmpvar_18 "64" } + global CONFIG_DCACHE_LRAM_SZ128 + if { $CONFIG_DCACHE_LRAM_SZ128 == 1 } then { set tmpvar_18 "128" } + global CONFIG_DCACHE_LRAM_SZ256 + if { $CONFIG_DCACHE_LRAM_SZ256 == 1 } then { set tmpvar_18 "256" } + global tmpvar_19 + set tmpvar_19 "combined" + global CONFIG_MMU_COMBINED + if { $CONFIG_MMU_COMBINED == 1 } then { set tmpvar_19 "combined" } + global CONFIG_MMU_SPLIT + if { $CONFIG_MMU_SPLIT == 1 } then { set tmpvar_19 "split" } + global tmpvar_20 + set tmpvar_20 "Increment" + global CONFIG_MMU_REPARRAY + if { $CONFIG_MMU_REPARRAY == 1 } then { set tmpvar_20 "LRU" } + global CONFIG_MMU_REPINCREMENT + if { $CONFIG_MMU_REPINCREMENT == 1 } then { set tmpvar_20 "Increment" } + global tmpvar_21 + set tmpvar_21 "8" + global CONFIG_MMU_I2 + if { $CONFIG_MMU_I2 == 1 } then { set tmpvar_21 "2" } + global CONFIG_MMU_I4 + if { $CONFIG_MMU_I4 == 1 } then { set tmpvar_21 "4" } + global CONFIG_MMU_I8 + if { $CONFIG_MMU_I8 == 1 } then { set tmpvar_21 "8" } + global CONFIG_MMU_I16 + if { $CONFIG_MMU_I16 == 1 } then { set tmpvar_21 "16" } + global CONFIG_MMU_I32 + if { $CONFIG_MMU_I32 == 1 } then { set tmpvar_21 "32" } + global CONFIG_MMU_I64 + if { $CONFIG_MMU_I64 == 1 } then { set tmpvar_21 "64" } + global tmpvar_22 + set tmpvar_22 "8" + global CONFIG_MMU_D2 + if { $CONFIG_MMU_D2 == 1 } then { set tmpvar_22 "2" } + global CONFIG_MMU_D4 + if { $CONFIG_MMU_D4 == 1 } then { set tmpvar_22 "4" } + global CONFIG_MMU_D8 + if { $CONFIG_MMU_D8 == 1 } then { set tmpvar_22 "8" } + global CONFIG_MMU_D16 + if { $CONFIG_MMU_D16 == 1 } then { set tmpvar_22 "16" } + global CONFIG_MMU_D32 + if { $CONFIG_MMU_D32 == 1 } then { set tmpvar_22 "32" } + global CONFIG_MMU_D64 + if { $CONFIG_MMU_D64 == 1 } then { set tmpvar_22 "64" } + global tmpvar_23 + set tmpvar_23 "4K" + global CONFIG_MMU_PAGE_4K + if { $CONFIG_MMU_PAGE_4K == 1 } then { set tmpvar_23 "4K" } + global CONFIG_MMU_PAGE_8K + if { $CONFIG_MMU_PAGE_8K == 1 } then { set tmpvar_23 "8K" } + global CONFIG_MMU_PAGE_16K + if { $CONFIG_MMU_PAGE_16K == 1 } then { set tmpvar_23 "16K" } + global CONFIG_MMU_PAGE_32K + if { $CONFIG_MMU_PAGE_32K == 1 } then { set tmpvar_23 "32K" } + global CONFIG_MMU_PAGE_PROG + if { $CONFIG_MMU_PAGE_PROG == 1 } then { set tmpvar_23 "Programmable" } + global tmpvar_24 + set tmpvar_24 "1" + global CONFIG_DSU_ITRACESZ1 + if { $CONFIG_DSU_ITRACESZ1 == 1 } then { set tmpvar_24 "1" } + global CONFIG_DSU_ITRACESZ2 + if { $CONFIG_DSU_ITRACESZ2 == 1 } then { set tmpvar_24 "2" } + global CONFIG_DSU_ITRACESZ4 + if { $CONFIG_DSU_ITRACESZ4 == 1 } then { set tmpvar_24 "4" } + global CONFIG_DSU_ITRACESZ8 + if { $CONFIG_DSU_ITRACESZ8 == 1 } then { set tmpvar_24 "8" } + global CONFIG_DSU_ITRACESZ16 + if { $CONFIG_DSU_ITRACESZ16 == 1 } then { set tmpvar_24 "16" } + global tmpvar_25 + set tmpvar_25 "1" + global CONFIG_DSU_ATRACESZ1 + if { $CONFIG_DSU_ATRACESZ1 == 1 } then { set tmpvar_25 "1" } + global CONFIG_DSU_ATRACESZ2 + if { $CONFIG_DSU_ATRACESZ2 == 1 } then { set tmpvar_25 "2" } + global CONFIG_DSU_ATRACESZ4 + if { $CONFIG_DSU_ATRACESZ4 == 1 } then { set tmpvar_25 "4" } + global CONFIG_DSU_ATRACESZ8 + if { $CONFIG_DSU_ATRACESZ8 == 1 } then { set tmpvar_25 "8" } + global CONFIG_DSU_ATRACESZ16 + if { $CONFIG_DSU_ATRACESZ16 == 1 } then { set tmpvar_25 "16" } + global tmpvar_26 + set tmpvar_26 "None" + global CONFIG_IUFT_NONE + if { $CONFIG_IUFT_NONE == 1 } then { set tmpvar_26 "None" } + global CONFIG_IUFT_PAR + if { $CONFIG_IUFT_PAR == 1 } then { set tmpvar_26 "Parity" } + global CONFIG_IUFT_DMR + if { $CONFIG_IUFT_DMR == 1 } then { set tmpvar_26 "PDMR" } + global CONFIG_IUFT_BCH + if { $CONFIG_IUFT_BCH == 1 } then { set tmpvar_26 "BCH" } + global CONFIG_IUFT_TMR + if { $CONFIG_IUFT_TMR == 1 } then { set tmpvar_26 "TMR" } + global tmpvar_27 + set tmpvar_27 "None" + global CONFIG_FPUFT_NONE + if { $CONFIG_FPUFT_NONE == 1 } then { set tmpvar_27 "None" } + global CONFIG_FPUFT_PAR + if { $CONFIG_FPUFT_PAR == 1 } then { set tmpvar_27 "Parity" } + global CONFIG_FPUFT_DMR + if { $CONFIG_FPUFT_DMR == 1 } then { set tmpvar_27 "PDMR" } + global CONFIG_FPUFT_TMR + if { $CONFIG_FPUFT_TMR == 1 } then { set tmpvar_27 "TMR" } + global tmpvar_28 + set tmpvar_28 "2" + global CONFIG_DSU_ETHSZ1 + if { $CONFIG_DSU_ETHSZ1 == 1 } then { set tmpvar_28 "1" } + global CONFIG_DSU_ETHSZ2 + if { $CONFIG_DSU_ETHSZ2 == 1 } then { set tmpvar_28 "2" } + global CONFIG_DSU_ETHSZ4 + if { $CONFIG_DSU_ETHSZ4 == 1 } then { set tmpvar_28 "4" } + global CONFIG_DSU_ETHSZ8 + if { $CONFIG_DSU_ETHSZ8 == 1 } then { set tmpvar_28 "8" } + global CONFIG_DSU_ETHSZ16 + if { $CONFIG_DSU_ETHSZ16 == 1 } then { set tmpvar_28 "16" } + global tmpvar_29 + set tmpvar_29 "4" + global CONFIG_AHBRAM_SZ1 + if { $CONFIG_AHBRAM_SZ1 == 1 } then { set tmpvar_29 "1" } + global CONFIG_AHBRAM_SZ2 + if { $CONFIG_AHBRAM_SZ2 == 1 } then { set tmpvar_29 "2" } + global CONFIG_AHBRAM_SZ4 + if { $CONFIG_AHBRAM_SZ4 == 1 } then { set tmpvar_29 "4" } + global CONFIG_AHBRAM_SZ8 + if { $CONFIG_AHBRAM_SZ8 == 1 } then { set tmpvar_29 "8" } + global CONFIG_AHBRAM_SZ16 + if { $CONFIG_AHBRAM_SZ16 == 1 } then { set tmpvar_29 "16" } + global CONFIG_AHBRAM_SZ32 + if { $CONFIG_AHBRAM_SZ32 == 1 } then { set tmpvar_29 "32" } + global CONFIG_AHBRAM_SZ64 + if { $CONFIG_AHBRAM_SZ64 == 1 } then { set tmpvar_29 "64" } + global CONFIG_AHBRAM_SZ128 + if { $CONFIG_AHBRAM_SZ128 == 1 } then { set tmpvar_29 "128" } + global CONFIG_AHBRAM_SZ256 + if { $CONFIG_AHBRAM_SZ256 == 1 } then { set tmpvar_29 "256" } + global CONFIG_AHBRAM_SZ512 + if { $CONFIG_AHBRAM_SZ512 == 1 } then { set tmpvar_29 "512" } + global CONFIG_AHBRAM_SZ1024 + if { $CONFIG_AHBRAM_SZ1024 == 1 } then { set tmpvar_29 "1024" } + global CONFIG_AHBRAM_SZ2048 + if { $CONFIG_AHBRAM_SZ2048 == 1 } then { set tmpvar_29 "2048" } + global CONFIG_AHBRAM_SZ4096 + if { $CONFIG_AHBRAM_SZ4096 == 1 } then { set tmpvar_29 "4096" } + global tmpvar_30 + set tmpvar_30 "8" + global CONFIG_GRETH_FIFO4 + if { $CONFIG_GRETH_FIFO4 == 1 } then { set tmpvar_30 "4" } + global CONFIG_GRETH_FIFO8 + if { $CONFIG_GRETH_FIFO8 == 1 } then { set tmpvar_30 "8" } + global CONFIG_GRETH_FIFO16 + if { $CONFIG_GRETH_FIFO16 == 1 } then { set tmpvar_30 "16" } + global CONFIG_GRETH_FIFO32 + if { $CONFIG_GRETH_FIFO32 == 1 } then { set tmpvar_30 "32" } + global CONFIG_GRETH_FIFO64 + if { $CONFIG_GRETH_FIFO64 == 1 } then { set tmpvar_30 "64" } + global tmpvar_31 + set tmpvar_31 "1" + global CONFIG_UA1_FIFO1 + if { $CONFIG_UA1_FIFO1 == 1 } then { set tmpvar_31 "1" } + global CONFIG_UA1_FIFO2 + if { $CONFIG_UA1_FIFO2 == 1 } then { set tmpvar_31 "2" } + global CONFIG_UA1_FIFO4 + if { $CONFIG_UA1_FIFO4 == 1 } then { set tmpvar_31 "4" } + global CONFIG_UA1_FIFO8 + if { $CONFIG_UA1_FIFO8 == 1 } then { set tmpvar_31 "8" } + global CONFIG_UA1_FIFO16 + if { $CONFIG_UA1_FIFO16 == 1 } then { set tmpvar_31 "16" } + global CONFIG_UA1_FIFO32 + if { $CONFIG_UA1_FIFO32 == 1 } then { set tmpvar_31 "32" } + global tmpvar_32 + set tmpvar_32 "None" + global CONFIG_SPICTRL_NOFT + if { $CONFIG_SPICTRL_NOFT == 1 } then { set tmpvar_32 "None" } + global CONFIG_SPICTRL_DMRFT + if { $CONFIG_SPICTRL_DMRFT == 1 } then { set tmpvar_32 "Parity-DMR" } + global CONFIG_SPICTRL_TMRFT + if { $CONFIG_SPICTRL_TMRFT == 1 } then { set tmpvar_32 "TMR" } +} + + +proc update_define_mainmenu {} { + global CONFIG_MODULES + global CONFIG_LEON3FT_PRESENT + global CONFIG_HAS_SHARED_GRFPU + global CONSTANT_Y + set CONFIG_LEON3FT_PRESENT $CONSTANT_Y + set CONFIG_HAS_SHARED_GRFPU $CONSTANT_Y +} + + +# FILE: tail.tk +# This file is boilerplate TCL/TK function definitions for 'make xconfig'. +# +# CHANGES +# ======= +# +# 8 January 1998, Michael Elizabeth Chastain, +# Arrange buttons in three columns for better screen fitting. +# + +# +# Read the user's settings from .config. These will override whatever is +# in config.in. Don't do this if the user specified a -D to force +# the defaults. +# + +set defaults defconfig + +if { [file readable .config] == 1} then { + if { $argc > 0 } then { + if { [lindex $argv 0] != "-D" } then { + read_config .config + if { [lindex $argv 0] == "-regen" } then { + catch {exec cp -f .config .config.old}; + writeconfig .config config.h + exit 2 + } + } + else + { + read_config $defaults + } + } else { + read_config .config + } +} else { + read_config $defaults +} + +update_define 1 $total_menus 0 +update_mainmenu + +button .f0.right.save -anchor w -text "Save and Exit" -underline 0\ + -command { catch {exec cp -f .config .config.old}; \ + writeconfig .config config.h; wrapup .wrap } + +button .f0.right.quit -anchor w -text "Quit Without Saving" -underline 0\ + -command { maybe_exit .maybe } + +button .f0.right.load -anchor w -text "Load Configuration from File" \ + -command { load_configfile .load "Load Configuration from file" read_config_file +} + +button .f0.right.store -anchor w -text "Store Configuration to File" \ + -command { load_configfile .load "Store Configuration to file" write_config_file } + +# +# Now pack everything. +# + +pack .f0.right.store .f0.right.load .f0.right.quit .f0.right.save \ + -padx 0 -pady 0 -side bottom -fill x +pack .f0.left .f0.middle .f0.right -side left -padx 5 -pady 0 -fill y +pack .f0 -padx 5 -pady 5 + +update idletasks +set winy [expr 10 + [winfo reqheight .f0]] +set scry [lindex [wm maxsize .] 1] +set winx [expr 10 + [winfo reqwidth .f0]] +set scrx [lindex [wm maxsize .] 0] +if {$winx < $scrx} then {set maxx -1} else {set maxx $winx} +if {$winy < $scry} then {set maxy -1} else {set maxy $winy} +.f0 configure -width $winx -height $winy +wm maxsize . $maxx $maxy + +# +# If we cannot write our config files, disable the write button. +# +if { [file exists .config] == 1 } then { + if { [file writable .config] == 0 } then { + .f0.right.save configure -state disabled + } + } else { + if { [file writable .] == 0 } then { + .f0.right.save configure -state disabled + } + } + +#if { [file exists include/linux/autoconf.h] == 1 } then { +# if { [file writable include/linux/autoconf.h] == 0 } then { +# .f0.right.save configure -state disabled +# } +# } else { +# if { [file writable include/linux/] == 0 } then { +# .f0.right.save configure -state disabled +# } +# } diff --git a/designs/leon3-xilinx-ac701/leon3mp.vhd b/designs/leon3-xilinx-ac701/leon3mp.vhd new file mode 100644 index 00000000..f05a6b33 --- /dev/null +++ b/designs/leon3-xilinx-ac701/leon3mp.vhd @@ -0,0 +1,911 @@ +----------------------------------------------------------------------------- +-- LEON3 Xilinx KC705 Demonstration design +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib, techmap; +use grlib.amba.all; +use grlib.stdlib.all; +use techmap.gencomp.all; +use techmap.allclkgen.all; +library gaisler; +use gaisler.memctrl.all; +use gaisler.leon3.all; +use gaisler.uart.all; +use gaisler.misc.all; +use gaisler.spi.all; +use gaisler.i2c.all; +use gaisler.net.all; +use gaisler.jtag.all; +-- pragma translate_off +use gaisler.sim.all; +library unisim; +use unisim.all; +-- pragma translate_on + + +library esa; +use esa.memoryctrl.all; + +use work.config.all; + +entity leon3mp is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console + pclow : integer := CFG_PCLOW; + testahb : boolean := false; + SIM_BYPASS_INIT_CAL : string := "OFF"; + SIMULATION : string := "FALSE"; + USE_MIG_INTERFACE_MODEL : boolean := false + ); + port ( + reset : in std_ulogic; + clk200p : in std_ulogic; -- 200 MHz clock + clk200n : in std_ulogic; -- 200 MHz clock +-- spi_sel_n : inout std_ulogic; +-- spi_clk : out std_ulogic; +-- spi_miso : in std_ulogic; + ddr3_dq : inout std_logic_vector(63 downto 0); + ddr3_dqs_p : inout std_logic_vector(7 downto 0); + ddr3_dqs_n : inout std_logic_vector(7 downto 0); + ddr3_addr : out std_logic_vector(13 downto 0); + ddr3_ba : out std_logic_vector(2 downto 0); + ddr3_ras_n : out std_logic; + ddr3_cas_n : out std_logic; + ddr3_we_n : out std_logic; + ddr3_reset_n : out std_logic; + ddr3_ck_p : out std_logic_vector(0 downto 0); + ddr3_ck_n : out std_logic_vector(0 downto 0); + ddr3_cke : out std_logic_vector(0 downto 0); + ddr3_cs_n : out std_logic_vector(0 downto 0); + ddr3_dm : out std_logic_vector(7 downto 0); + ddr3_odt : out std_logic_vector(0 downto 0); + dsurx : in std_ulogic; + dsutx : out std_ulogic; + dsuctsn : in std_ulogic; + dsurtsn : out std_ulogic; + button : in std_logic_vector(3 downto 0); + switch : inout std_logic_vector(3 downto 0); + led : out std_logic_vector(3 downto 0); + iic_scl : inout std_ulogic; + iic_sda : inout std_ulogic; + gtrefclk_p : in std_logic; + gtrefclk_n : in std_logic; + phy_txclk : out std_logic; + phy_txd : out std_logic_vector(3 downto 0); + phy_txctl_txen : out std_ulogic; + phy_rxd : in std_logic_vector(3 downto 0); + phy_rxctl_rxdv : in std_ulogic; + phy_rxclk : in std_ulogic; + phy_reset : out std_ulogic; + phy_mdio : inout std_logic; + phy_mdc : out std_ulogic; + sfp_clock_mux : out std_logic_vector(1 downto 0) + ); +end; + +architecture rtl of leon3mp is + +component ahb2mig_series7 + generic( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#f00#; + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + SIM_BYPASS_INIT_CAL : string := "OFF"; + SIMULATION : string := "FALSE"; + USE_MIG_INTERFACE_MODEL : boolean := false + ); + port( + ddr3_dq : inout std_logic_vector(63 downto 0); + ddr3_dqs_p : inout std_logic_vector(7 downto 0); + ddr3_dqs_n : inout std_logic_vector(7 downto 0); + ddr3_addr : out std_logic_vector(13 downto 0); + ddr3_ba : out std_logic_vector(2 downto 0); + ddr3_ras_n : out std_logic; + ddr3_cas_n : out std_logic; + ddr3_we_n : out std_logic; + ddr3_reset_n : out std_logic; + ddr3_ck_p : out std_logic_vector(0 downto 0); + ddr3_ck_n : out std_logic_vector(0 downto 0); + ddr3_cke : out std_logic_vector(0 downto 0); + ddr3_cs_n : out std_logic_vector(0 downto 0); + ddr3_dm : out std_logic_vector(7 downto 0); + ddr3_odt : out std_logic_vector(0 downto 0); + ahbso : out ahb_slv_out_type; + ahbsi : in ahb_slv_in_type; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + calib_done : out std_logic; + rst_n_syn : in std_logic; + rst_n_async : in std_logic; + clk_amba : in std_logic; + sys_clk_p : in std_logic; + sys_clk_n : in std_logic; + clk_ref_i : in std_logic; + ui_clk : out std_logic; + ui_clk_sync_rst : out std_logic + ); +end component ; + +component ddr_dummy + port ( + ddr_dq : inout std_logic_vector(63 downto 0); + ddr_dqs : inout std_logic_vector(7 downto 0); + ddr_dqs_n : inout std_logic_vector(7 downto 0); + ddr_addr : out std_logic_vector(13 downto 0); + ddr_ba : out std_logic_vector(2 downto 0); + ddr_ras_n : out std_logic; + ddr_cas_n : out std_logic; + ddr_we_n : out std_logic; + ddr_reset_n : out std_logic; + ddr_ck_p : out std_logic_vector(0 downto 0); + ddr_ck_n : out std_logic_vector(0 downto 0); + ddr_cke : out std_logic_vector(0 downto 0); + ddr_cs_n : out std_logic_vector(0 downto 0); + ddr_dm : out std_logic_vector(7 downto 0); + ddr_odt : out std_logic_vector(0 downto 0) + ); +end component ; + +component IBUFDS_GTE2 + port ( + O : out std_ulogic; + ODIV2 : out std_ulogic; + CEB : in std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; + +component IDELAYCTRL + port ( + RDY : out std_ulogic; + REFCLK : in std_ulogic; + RST : in std_ulogic + ); +end component; + +component IODELAYE1 + generic ( + DELAY_SRC : string := "I"; + IDELAY_TYPE : string := "DEFAULT"; + IDELAY_VALUE : integer := 0 + ); + port ( + CNTVALUEOUT : out std_logic_vector(4 downto 0); + DATAOUT : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + CINVCTRL : in std_ulogic; + CLKIN : in std_ulogic; + CNTVALUEIN : in std_logic_vector(4 downto 0); + DATAIN : in std_ulogic; + IDATAIN : in std_ulogic; + INC : in std_ulogic; + ODATAIN : in std_ulogic; + RST : in std_ulogic; + T : in std_ulogic + ); +end component; + + +component BUFG port (O : out std_logic; I : in std_logic); end component; + +--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH; +constant maxahbm : integer := 16; +constant maxahbs : integer := 16; +constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT; + +signal vcc, gnd : std_logic; +signal memi : memory_in_type; +signal memo : memory_out_type; +signal wpo : wprot_out_type; +signal sdi : sdctrl_in_type; +signal sdo : sdram_out_type; +signal sdo2, sdo3 : sdctrl_out_type; + +signal apbi : apb_slv_in_type; +signal apbo : apb_slv_out_vector := (others => apb_none); +signal ahbsi : ahb_slv_in_type; +signal ahbso : ahb_slv_out_vector := (others => ahbs_none); +signal ahbmi : ahb_mst_in_type; +signal vahbmi : ahb_mst_in_type; +signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); +signal vahbmo : ahb_mst_out_type; + +signal ui_clk : std_ulogic; +signal clkm, rstn, rstraw, sdclkl : std_ulogic; +signal clk_200 : std_ulogic; +signal clk25, clk40, clk65 : std_ulogic; + +signal cgi, cgi2 : clkgen_in_type; +signal cgo, cgo2 : clkgen_out_type; +signal u1i, u2i, dui : uart_in_type; +signal u1o, u2o, duo : uart_out_type; + +signal irqi : irq_in_vector(0 to CFG_NCPU-1); +signal irqo : irq_out_vector(0 to CFG_NCPU-1); + +signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); +signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); + +signal dsui : dsu_in_type; +signal dsuo : dsu_out_type; + +signal gmiii : eth_in_type; +signal gmiio : eth_out_type; + +signal rgmiii,rgmiii_buf : eth_in_type; +signal rgmiio : eth_out_type; + +signal sgmiii : eth_sgmii_in_type; +signal sgmiio : eth_sgmii_out_type; + +signal sgmiirst : std_logic; + +signal ethernet_phy_int : std_logic; + +signal rxd1 : std_logic; +signal txd1 : std_logic; + +signal ethi : eth_in_type; +signal etho : eth_out_type; +signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic; +signal rstgtxn : std_logic; + +signal gpti : gptimer_in_type; +signal gpto : gptimer_out_type; + +signal gpioi : gpio_in_type; +signal gpioo : gpio_out_type; + +signal clklock, elock, ulock : std_ulogic; + +signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic; +signal tck, tckn, tms, tdi, tdo : std_ulogic; + +signal lcd_datal : std_logic_vector(11 downto 0); +signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic; + +signal i2ci, dvi_i2ci : i2c_in_type; +signal i2co, dvi_i2co : i2c_out_type; + +constant BOARD_FREQ : integer := 200000; -- input frequency in KHz +constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz + +signal stati : ahbstat_in_type; + +signal fpi : grfpu_in_vector_type; +signal fpo : grfpu_out_vector_type; + +signal dsurx_int : std_logic; +signal dsutx_int : std_logic; +signal dsuctsn_int : std_logic; +signal dsurtsn_int : std_logic; + +signal dsu_sel : std_logic; + +signal idelay_reset_cnt : std_logic_vector(3 downto 0); +signal idelayctrl_reset : std_logic; +signal io_ref : std_logic; + +signal clkref : std_logic; + +signal migrstn : std_logic; + +signal spmi : spimctrl_in_type; +signal spmo : spimctrl_out_type; + +begin + +---------------------------------------------------------------------- +--- Reset and Clock generation ------------------------------------- +---------------------------------------------------------------------- + + vcc <= '1'; gnd <= '0'; + cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; + + clk_gen0 : if (CFG_MIG_SERIES7 = 0) generate + clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk); + clkgen0 : clkgen -- clock generator + generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ) + port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open); + end generate; + + reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst); + rst0 : rstgen -- reset generator + generic map (acthigh => 1, syncin => 1) + port map (rst, clkm, lock, rstn, rstraw); + lock <= calib_done when CFG_MIG_SERIES7 = 1 else cgo.clklock; + + rst1 : rstgen -- reset generator + generic map (acthigh => 1) + port map (rst, clkm, '1', migrstn, open); + +---------------------------------------------------------------------- +--- AHB CONTROLLER -------------------------------------------------- +---------------------------------------------------------------------- + + ahb0 : ahbctrl -- AHB arbiter/multiplexer + generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, + rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN, + nahbm => maxahbm, nahbs => maxahbs) + port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); + +---------------------------------------------------------------------- +--- LEON3 processor and DSU ----------------------------------------- +---------------------------------------------------------------------- + + nosh : if CFG_GRFPUSH = 0 generate + cpu : for i in 0 to CFG_NCPU-1 generate + l3ft : if CFG_LEON3FT_EN /= 0 generate + leon3ft0 : leon3ft -- LEON3 processor + generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, + CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ, + CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE) + port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i), clkm); + end generate; + + l3s : if CFG_LEON3FT_EN = 0 generate + u0 : leon3s -- LEON3 processor + generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, + CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP) + port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i)); + end generate; + end generate; + end generate; + + sh : if CFG_GRFPUSH = 1 generate + cpu : for i in 0 to CFG_NCPU-1 generate + l3ft : if CFG_LEON3FT_EN /= 0 generate + leon3ft0 : leon3ftsh -- LEON3 processor + generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, + CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ, + CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE) + port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i)); + + end generate; + l3s : if CFG_LEON3FT_EN = 0 generate + u0 : leon3sh -- LEON3 processor + generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, + 0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, + CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, + CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, + CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, + CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, + CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE) + port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, + irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i)); + end generate; + end generate; + + grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech) + port map (clkm, rstn, fpi, fpo); + + end generate; + + led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error); + + -- LEON3 Debug Support Unit + dsugen : if CFG_DSU = 1 generate + dsu0 : dsu3 -- LEON3 Debug Support Unit + generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, + ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) + port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); + dsui.enable <= '1'; + dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break); + dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact); + ndsuact <= not dsuo.active; + end generate; + + nodsu : if CFG_DSU = 0 generate + dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none; + end generate; + + -- Debug UART + dcomgen : if CFG_AHB_UART = 1 generate + dcom0 : ahbuart + generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) + port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); + dui.extclk <= '0'; + end generate; + + nouah : if CFG_AHB_UART = 0 generate + apbo(7) <= apb_none; + duo.txd <= '0'; + duo.rtsn <= '0'; + dui.extclk <= '0'; + end generate; + + + sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (switch(3), '0', '1', dsu_sel); + + dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd; + dui.rxd <= dsurx_int when dsu_sel = '1' else '1'; + u1i.rxd <= dsurx_int when dsu_sel = '0' else '1'; + dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn; + dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1'; + u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1'; + + dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int); + dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int); + dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int); + dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int); + + + ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate + ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1) + port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1), + open, open, open, open, open, open, open, gnd); + end generate; + + nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate; + +---------------------------------------------------------------------- +--- SPI Memory Controller-------------------------------------------- +---------------------------------------------------------------------- + +-- mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate +-- mctrl0 : mctrl generic map (hindex => 0, pindex => 0, +-- paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT, +-- ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN, +-- invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS, +-- pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0) +-- port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + + +-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate +-- spimctrl0 : spimctrl -- SPI Memory Controller +-- generic map (hindex => 0, hirq => 0, faddr => 16#000#, fmask => 16#ff8#, +-- ioaddr => 16#002#, iomask => 16#fff#, +-- spliten => CFG_SPLIT, oepol => 0, +-- sdcard => CFG_SPIMCTRL_SDCARD, +-- readcmd => CFG_SPIMCTRL_READCMD, +-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE, +-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT, +-- scaler => CFG_SPIMCTRL_SCALER, +-- altscaler => CFG_SPIMCTRL_ASCALER, +-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT) +-- port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo); +-- +-- +-- miso_pad : inpad generic map (tech => padtech) +-- port map (spi_miso, spmi.miso); +-- sck_pad : outpad generic map (tech => padtech) +-- port map (spi_clk, spmo.sck); +-- slvsel0_pad : odpad generic map (tech => padtech) +-- port map (spi_sel_n, spmo.csn); +-- end generate; +-- +-- nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or +-- (CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or +-- (CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate +-- miso_pad : inpad generic map (tech => padtech) +-- port map (spi_miso, spmi.miso); +-- sck_pad : outpad generic map (tech => padtech) +-- port map (spi_clk, '0'); +-- slvsel0_pad : odpad generic map (tech => padtech) +-- port map (spi_sel_n, '1'); +-- end generate; + + +---------------------------------------------------------------------- +--- DDR3 memory controller ------------------------------------------ +---------------------------------------------------------------------- + + mig_gen : if (CFG_MIG_SERIES7 = 1) generate + ddrc : ahb2mig_series7 generic map( + hindex => 4, haddr => 16#400#, hmask => 16#C00#, + pindex => 4, paddr => 4, + SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, + SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL) + port map( + ddr3_dq => ddr3_dq, + ddr3_dqs_p => ddr3_dqs_p, + ddr3_dqs_n => ddr3_dqs_n, + ddr3_addr => ddr3_addr, + ddr3_ba => ddr3_ba, + ddr3_ras_n => ddr3_ras_n, + ddr3_cas_n => ddr3_cas_n, + ddr3_we_n => ddr3_we_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_ck_p => ddr3_ck_p, + ddr3_ck_n => ddr3_ck_n, + ddr3_cke => ddr3_cke, + ddr3_cs_n => ddr3_cs_n, + ddr3_dm => ddr3_dm, + ddr3_odt => ddr3_odt, + ahbsi => ahbsi, + ahbso => ahbso(4), + apbi => apbi, + apbo => apbo(4), + calib_done => calib_done, + rst_n_syn => migrstn, + rst_n_async => rstraw, + clk_amba => clkm, + sys_clk_p => clk200p, + sys_clk_n => clk200n, + clk_ref_i => clkref, + ui_clk => clkm, + ui_clk_sync_rst => open + ); + + clkgenmigref0 : clkgen + generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000) + port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open); + + end generate; + + no_mig_gen : if (CFG_MIG_SERIES7 = 0) generate + + ahbram0 : ahbram + generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 32) + port map ( rstn, clkm, ahbsi, ahbso(4)); + + ddrdummy0 : ddr_dummy + port map ( + ddr_dq => ddr3_dq, + ddr_dqs => ddr3_dqs_p, + ddr_dqs_n => ddr3_dqs_n, + ddr_addr => ddr3_addr, + ddr_ba => ddr3_ba, + ddr_ras_n => ddr3_ras_n, + ddr_cas_n => ddr3_cas_n, + ddr_we_n => ddr3_we_n, + ddr_reset_n => ddr3_reset_n, + ddr_ck_p => ddr3_ck_p, + ddr_ck_n => ddr3_ck_n, + ddr_cke => ddr3_cke, + ddr_cs_n => ddr3_cs_n, + ddr_dm => ddr3_dm, + ddr_odt => ddr3_odt + ); + + calib_done <= '1'; + + end generate; + + led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) + port map (led(2), calib_done); + led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) + port map (led(3), lock); + +----------------------------------------------------------------------- +--- ETHERNET --------------------------------------------------------- +----------------------------------------------------------------------- + + eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC + e1 : grethm + generic map( + hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, + pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 14, memtech => memtech, + mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO, + nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7, + macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1, + ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, + giga => CFG_GRETH1G, ramdebug => 2) + port map( rst => rstn, clk => clkm, ahbmi => ahbmi, + ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), + apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho); + + ----------------------------------------------------------------------------- + -- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay + -- mode of the IDELAY. + -- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have + -- to be LOC'ed in the UCF file. + ----------------------------------------------------------------------------- + dlyctrl0 : IDELAYCTRL port map ( + RDY => OPEN, + REFCLK => io_ref, + RST => idelayctrl_reset + ); + + delay_rgmii_rx_ctl0 : IODELAYE1 generic map( + DELAY_SRC => "I", + IDELAY_TYPE => "FIXED", + IDELAY_VALUE => 20 + ) + port map( + IDATAIN => rgmiii_buf.rx_dv, + ODATAIN => '0', + DATAOUT => rgmiii.rx_dv, + DATAIN => '0', + C => '0', + T => '1', + CE => '0', + INC => '0', + CINVCTRL => '0', + CLKIN => '0', + CNTVALUEIN => "00000", + CNTVALUEOUT => OPEN, + RST => '0' + ); + + rgmii_rxd : for i in 0 to 3 generate + delay_rgmii_rxd0 : IODELAYE1 generic map( + DELAY_SRC => "I", + IDELAY_TYPE => "FIXED", + IDELAY_VALUE => 20 + ) + port map( + IDATAIN => rgmiii_buf.rxd(i), + ODATAIN => '0', + DATAOUT => rgmiii.rxd(i), + DATAIN => '0', + C => '0', + T => '1', + CE => '0', + INC => '0', + CINVCTRL => '0', + CLKIN => '0', + CNTVALUEIN => "00000", + CNTVALUEOUT => OPEN, + RST => '0' + ); + end generate; + + -- Generate a synchron delayed reset for Xilinx IO delay + rst1 : rstgen + generic map (acthigh => 1) + port map (rst, io_ref, lock, rstgtxn, OPEN); + + process (io_ref,rstgtxn) + begin + if (rstgtxn = '0') then + idelay_reset_cnt <= (others => '0'); + idelayctrl_reset <= '1'; + elsif rising_edge(io_ref) then + if (idelay_reset_cnt > "1110") then + idelay_reset_cnt <= (others => '1'); + idelayctrl_reset <= '0'; + else + idelay_reset_cnt <= idelay_reset_cnt + 1; + idelayctrl_reset <= '1'; + end if; + end if; + end process; + + -- RGMII Interface + rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech, + gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1, + pirq => 11, use90degtxclk => 1) + port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11)); + + egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1) + port map (phy_txclk, rgmiio.tx_clk); + + erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4) + port map (phy_rxclk, rgmiii.rx_clk); + + erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4) + port map (phy_rxd, rgmiii_buf.rxd(3 downto 0)); + + erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv); + + etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4) + port map (phy_txd, rgmiio.txd(3 downto 0)); + + etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1) + port map (phy_txctl_txen, rgmiio.tx_en); + + emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i); + + emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (phy_mdc, rgmiio.mdc); + + rgmiii.mdint <= '0'; -- No interrupt on Marvell 88E1116R PHY + erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (phy_reset, rstraw); + + sfp_clock_mux_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 2) + port map (sfp_clock_mux, "00"); + + -- GTX Clock + rgmiii.gtx_clk <= gtx_clk; + + -- 125MHz input clock + ibufds_gtrefclk : IBUFDS_GTE2 + port map ( + I => gtrefclk_p, + IB => gtrefclk_n, + CEB => '0', + O => gtx_clk_nobuf, + ODIV2 => open + ); + + cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; + + clkgen_gtrefclk : clkgen + generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000) + port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, gtx_clk90, io_ref, open, open, cgi2, cgo2, open, open, open); + + end generate; + + noeth0 : if CFG_GRETH = 0 generate + -- TODO: + end generate; + +---------------------------------------------------------------------- +--- I2C Controller -------------------------------------------------- +---------------------------------------------------------------------- + + --i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master + i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11, filter => 9) + port map (rstn, clkm, apbi, apbo(9), i2ci, i2co); + + i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl); + + i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda); + --end generate i2cm; + +---------------------------------------------------------------------- +--- APB Bridge and various periherals ------------------------------- +---------------------------------------------------------------------- + + apb0 : apbctrl -- AHB/APB bridge + generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2) + port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); + + irqctrl : if CFG_IRQ3_ENABLE /= 0 generate + irqctrl0 : irqmp -- interrupt controller + generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) + port map (rstn, clkm, apbi, apbo(2), irqo, irqi); + end generate; + irq3 : if CFG_IRQ3_ENABLE = 0 generate + x : for i in 0 to CFG_NCPU-1 generate + irqi(i).irl <= "0000"; + end generate; + apbo(2) <= apb_none; + end generate; + + gpt : if CFG_GPT_ENABLE /= 0 generate + timer0 : gptimer -- timer unit + generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, + sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, + nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG) + port map (rstn, clkm, apbi, apbo(3), gpti, gpto); + gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; + end generate; + + nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; + + gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit + grgpio0: grgpio + generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7) + port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10), + gpioi => gpioi, gpioo => gpioo); + pio_pads : for i in 0 to 2 generate + pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v) + port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); + end generate; + pio_pads2 : for i in 3 to 5 generate + pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) + port map (button(i-2), gpioi.din(i)); + end generate; + end generate; + + ua1 : if CFG_UART1_ENABLE /= 0 generate + uart1 : apbuart -- UART 1 + generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, + fifosize => CFG_UART1_FIFO) + port map (rstn, clkm, apbi, apbo(1), u1i, u1o); + u1i.extclk <= '0'; + end generate; + noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; + + ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register + ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7, + nftslv => CFG_AHBSTATN) + port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15)); + end generate; + +----------------------------------------------------------------------- +--- AHB ROM ---------------------------------------------------------- +----------------------------------------------------------------------- + + bpromgen : if CFG_AHBROMEN /= 0 generate + brom : entity work.ahbrom + generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP) + port map ( rstn, clkm, ahbsi, ahbso(7)); + end generate; + +----------------------------------------------------------------------- +--- AHB RAM ---------------------------------------------------------- +----------------------------------------------------------------------- + + ocram : if CFG_AHBRAMEN = 1 generate + ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR, + tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) + port map ( rstn, clkm, ahbsi, ahbso(5)); + end generate; + +----------------------------------------------------------------------- +--- Test report module ---------------------------------------------- +----------------------------------------------------------------------- + + -- pragma translate_off + test0_gen : if (testahb = true) generate + test0 : ahbrep generic map (hindex => 3, haddr => 16#200#) + port map (rstn, clkm, ahbsi, ahbso(3)); + end generate; + -- pragma translate_on + + test1_gen : if (testahb = false) generate + ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#, + tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ) + port map ( rstn, clkm, ahbsi, ahbso(3)); + end generate; + + ----------------------------------------------------------------------- + --- Drive unused bus elements --------------------------------------- + ----------------------------------------------------------------------- + + nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate + ahbmo(i) <= ahbm_none; + end generate; + + ----------------------------------------------------------------------- + --- Boot message ---------------------------------------------------- + ----------------------------------------------------------------------- + + -- pragma translate_off + x : report_design + generic map ( + msg1 => "LEON3 Xilinx AC701 Demonstration design", + fabtech => tech_table(fabtech), memtech => tech_table(memtech), + mdel => 1 + ); + -- pragma translate_on + end; + diff --git a/designs/leon3-xilinx-ac701/prom.h b/designs/leon3-xilinx-ac701/prom.h new file mode 100644 index 00000000..e283ab8b --- /dev/null +++ b/designs/leon3-xilinx-ac701/prom.h @@ -0,0 +1,10 @@ +#define MCFG1 0x10380133 +#define MCFG2 0xe6B86e60 +#define MCFG3 0x000ff000 +#define ASDCFG 0x80000000 +#define DSDCFG 0xe6A06e60 +#define L2MCTRLIO 0x80000000 +#define IRQCTRL 0x80000200 +#define RAMSTART 0x40000000 +#define RAMSIZE 0x00100000 + diff --git a/designs/leon3-xilinx-ac701/prom.srec b/designs/leon3-xilinx-ac701/prom.srec new file mode 100755 index 00000000..a2497cbf --- /dev/null +++ b/designs/leon3-xilinx-ac701/prom.srec @@ -0,0 +1,37 @@ +S00C000070726F6D2E737265635A +S113000081D8200003000004821060E08188400051 +S1130010819000008198000081800000A180000090 +S113002001000000030020408210600FC2A00040C5 +S11300308410000001000000010000000100000025 +S11300400100000001000000801080020100000097 +S11300500100000001000000010000000100000098 +S1130060874440008608E01F881000008A100000C2 +S11300708C1000008E100000A0100000A2100000E0 +S1130080A4100000A6100000A8100000AA10000090 +S1130090AC100000AE1000009010000092100000A0 +S11300A09410000096100000981000009A100000B0 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b/designs/leon3-xilinx-ac701/sgmii_kc705.vhd @@ -0,0 +1,640 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: sgmii +-- File: sgmii.vhd +-- Author: Fredrik Ringhage - Aeroflex Gaisler +-- Description: GMII to SGMII interface +------------------------------------------------------------------------------ + +-------------------------------------------------------------------------------- +-- Description: This is the top level vhdl example design for the +-- Ethernet 1000BASE-X PCS/PMA core. +-- +-- This design example instantiates IOB flip-flops +-- and input/output buffers on the GMII. +-- +-- A Transmitter Elastic Buffer is instantiated on the Tx +-- GMII path to perform clock compenstation between the +-- core and the external MAC driving the Tx GMII. +-- +-- This design example can be synthesised. +-- +-- +-- +-- ---------------------------------------------------------------- +-- | Example Design | +-- | | +-- | ---------------------------------------------- | +-- | | Core Block (wrapper) | | +-- | | | | +-- | | -------------- -------------- | | +-- | | | Core | | tranceiver | | | +-- | | | | | | | | +-- | --------- | | | | | | | +-- | | | | | | | | | | +-- | | Tx | | | | | | | | +-- ---->|Elastic|----->| GMII |--------->| TXP |---------> +-- | |Buffer | | | Tx | | TXN | | | +-- | | | | | | | | | | +-- | --------- | | | | | | | +-- | GMII | | | | | | | +-- | IOBs | | | | | | | +-- | | | | | | | | +-- | | | GMII | | RXP | | | +-- <-------------------| Rx |<---------| RXN |<--------- +-- | | | | | | | | +-- | | -------------- -------------- | | +-- | | | | +-- | ---------------------------------------------- | +-- | | +-- ---------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- + + +library unisim; +use unisim.vcomponents.all; + +library ieee; +use ieee.std_logic_1164.all; + +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; + +library gaisler; +use gaisler.misc.all; +use gaisler.net.all; + + +-------------------------------------------------------------------------------- +-- The entity declaration for the example design +-------------------------------------------------------------------------------- + +entity sgmii_kc705 is + generic( + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + autonegotiation : integer := 1 + ); + port( + -- Tranceiver Interface + sgmiii : in eth_sgmii_in_type; + sgmiio : out eth_sgmii_out_type; + -- GMII Interface (client MAC <=> PCS) + gmiii : out eth_in_type; + gmiio : in eth_out_type; + -- Asynchronous reset for entire core. + reset : in std_logic; + -- APB Status bus + apb_clk : in std_logic; + apb_rstn : in std_logic; + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type + + ); +end sgmii_kc705; + +architecture top_level of sgmii_kc705 is + + ------------------------------------------------------------------------------ + -- Component Declaration for the Core Block (core wrapper). + ------------------------------------------------------------------------------ + component sgmii_block + port( + -- Transceiver Interface + ------------------------ + drpaddr_in : in std_logic_vector(8 downto 0); + drpclk_in : in std_logic; + drpdi_in : in std_logic_vector(15 downto 0); + drpdo_out : out std_logic_vector(15 downto 0); + drpen_in : in std_logic; + drprdy_out : out std_logic; + drpwe_in : in std_logic; + + gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver + txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD. + txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD. + rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA. + rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA. + + txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz) + resetdone : out std_logic; -- The GT transceiver has completed its reset cycle + mmcm_locked : in std_logic; -- Locked signal from MMCM + userclk : in std_logic; -- 62.5MHz clock. + userclk2 : in std_logic; -- 125MHz clock. + independent_clock_bufg : in std_logic; + pma_reset : in std_logic; -- transceiver PMA reset signal + + + -- GMII Interface + ----------------- + sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). + sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). + sgmii_clk_en : out std_logic; -- Clock enable for client MAC + + gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC. + gmii_tx_en : in std_logic; -- Transmit control signal from client MAC. + gmii_tx_er : in std_logic; -- Transmit control signal from client MAC. + gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC. + gmii_rx_dv : out std_logic; -- Received control signal to client MAC. + gmii_rx_er : out std_logic; -- Received control signal to client MAC. + gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII. + + -- Management: MDIO Interface + ----------------------------- + + configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface. + + an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed + an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV) + an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0 + link_timer_value : in std_logic_vector(8 downto 0); -- Programmable Auto-Negotiation Link Timer Control + + -- Speed Control + ---------------- + speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds + speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed + + -- General IO's + --------------- + status_vector : out std_logic_vector(15 downto 0); -- Core status. + reset : in std_logic; -- Asynchronous reset for entire core. + signal_detect : in std_logic -- Input from PMD to indicate presence of optical input. + + ); + + end component; + +component MMCME2_ADV + generic ( + BANDWIDTH : string := "OPTIMIZED"; + CLKFBOUT_MULT_F : real := 5.000; + CLKFBOUT_PHASE : real := 0.000; + CLKFBOUT_USE_FINE_PS : boolean := FALSE; + CLKIN1_PERIOD : real := 0.000; + CLKIN2_PERIOD : real := 0.000; + CLKOUT0_DIVIDE_F : real := 1.000; + CLKOUT0_DUTY_CYCLE : real := 0.500; + CLKOUT0_PHASE : real := 0.000; + CLKOUT0_USE_FINE_PS : boolean := FALSE; + CLKOUT1_DIVIDE : integer := 1; + CLKOUT1_DUTY_CYCLE : real := 0.500; + CLKOUT1_PHASE : real := 0.000; + CLKOUT1_USE_FINE_PS : boolean := FALSE; + CLKOUT2_DIVIDE : integer := 1; + CLKOUT2_DUTY_CYCLE : real := 0.500; + CLKOUT2_PHASE : real := 0.000; + CLKOUT2_USE_FINE_PS : boolean := FALSE; + CLKOUT3_DIVIDE : integer := 1; + CLKOUT3_DUTY_CYCLE : real := 0.500; + CLKOUT3_PHASE : real := 0.000; + CLKOUT3_USE_FINE_PS : boolean := FALSE; + CLKOUT4_CASCADE : boolean := FALSE; + CLKOUT4_DIVIDE : integer := 1; + CLKOUT4_DUTY_CYCLE : real := 0.500; + CLKOUT4_PHASE : real := 0.000; + CLKOUT4_USE_FINE_PS : boolean := FALSE; + CLKOUT5_DIVIDE : integer := 1; + CLKOUT5_DUTY_CYCLE : real := 0.500; + CLKOUT5_PHASE : real := 0.000; + CLKOUT5_USE_FINE_PS : boolean := FALSE; + CLKOUT6_DIVIDE : integer := 1; + CLKOUT6_DUTY_CYCLE : real := 0.500; + CLKOUT6_PHASE : real := 0.000; + CLKOUT6_USE_FINE_PS : boolean := FALSE; + COMPENSATION : string := "ZHOLD"; + DIVCLK_DIVIDE : integer := 1; + REF_JITTER1 : real := 0.0; + REF_JITTER2 : real := 0.0; + SS_EN : string := "FALSE"; + SS_MODE : string := "CENTER_HIGH"; + SS_MOD_PERIOD : integer := 10000; + STARTUP_WAIT : boolean := FALSE + ); + port ( + CLKFBOUT : out std_ulogic := '0'; + CLKFBOUTB : out std_ulogic := '0'; + CLKFBSTOPPED : out std_ulogic := '0'; + CLKINSTOPPED : out std_ulogic := '0'; + CLKOUT0 : out std_ulogic := '0'; + CLKOUT0B : out std_ulogic := '0'; + CLKOUT1 : out std_ulogic := '0'; + CLKOUT1B : out std_ulogic := '0'; + CLKOUT2 : out std_ulogic := '0'; + CLKOUT2B : out std_ulogic := '0'; + CLKOUT3 : out std_ulogic := '0'; + CLKOUT3B : out std_ulogic := '0'; + CLKOUT4 : out std_ulogic := '0'; + CLKOUT5 : out std_ulogic := '0'; + CLKOUT6 : out std_ulogic := '0'; + DO : out std_logic_vector (15 downto 0); + DRDY : out std_ulogic := '0'; + LOCKED : out std_ulogic := '0'; + PSDONE : out std_ulogic := '0'; + CLKFBIN : in std_ulogic; + CLKIN1 : in std_ulogic; + CLKIN2 : in std_ulogic; + CLKINSEL : in std_ulogic; + DADDR : in std_logic_vector(6 downto 0); + DCLK : in std_ulogic; + DEN : in std_ulogic; + DI : in std_logic_vector(15 downto 0); + DWE : in std_ulogic; + PSCLK : in std_ulogic; + PSEN : in std_ulogic; + PSINCDEC : in std_ulogic; + PWRDWN : in std_ulogic; + RST : in std_ulogic + ); +end component; + +----- component IBUFDS_GTE2 ----- +component IBUFDS_GTE2 + generic ( + CLKCM_CFG : boolean := TRUE; + CLKRCV_TRST : boolean := TRUE; + CLKSWING_CFG : bit_vector := "11" + ); + port ( + O : out std_ulogic; + ODIV2 : out std_ulogic; + CEB : in std_ulogic; + I : in std_ulogic; + IB : in std_ulogic + ); +end component; + +constant pconfig : apb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0), + 1 => apb_iobar(paddr, pmask)); + + ------------------------------------------------------------------------------ + -- internal signals used in this top level example design. + ------------------------------------------------------------------------------ + + -- clock generation signals for tranceiver + signal gtrefclk : std_logic; + signal txoutclk : std_logic; + signal resetdone : std_logic; + signal mmcm_locked : std_logic; + signal mmcm_reset : std_logic; + signal clkfbout : std_logic; + signal clkout0 : std_logic; + signal clkout1 : std_logic; + signal userclk : std_logic; + signal userclk2 : std_logic; + + -- PMA reset generation signals for tranceiver + signal pma_reset_pipe : std_logic_vector(3 downto 0); + signal pma_reset : std_logic; + + -- clock generation signals for SGMII clock + signal sgmii_clk_r : std_logic; + signal sgmii_clk_f : std_logic; + signal sgmii_clk_en : std_logic; + signal sgmii_clk : std_logic; + signal sgmii_clk_int : std_logic; + + -- GMII signals + signal gmii_txd : std_logic_vector(7 downto 0); + signal gmii_tx_en : std_logic; + signal gmii_tx_er : std_logic; + signal gmii_rxd : std_logic_vector(7 downto 0); + signal gmii_rx_dv : std_logic; + signal gmii_rx_er : std_logic; + signal gmii_isolate : std_logic; + signal gmii_txd_int : std_logic_vector(7 downto 0); + signal gmii_tx_en_int : std_logic; + signal gmii_tx_er_int : std_logic; + signal gmii_rxd_int : std_logic_vector(7 downto 0); + signal gmii_rx_dv_int : std_logic; + signal gmii_rx_er_int : std_logic; + + -- Extra registers to ease IOB placement + signal status_vector_int : std_logic_vector(15 downto 0); + signal status_vector_apb : std_logic_vector(15 downto 0); + + -- These attributes will stop timing errors being reported in back annotated + -- SDF simulation. + attribute ASYNC_REG : string; + attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE"; + + -- Configuration register + + signal speed_is_10_100 : std_logic; + signal speed_is_100 : std_logic; + + signal configuration_vector : std_logic_vector(4 downto 0); + + signal an_interrupt : std_logic; + signal an_adv_config_vector : std_logic_vector(15 downto 0); + signal an_restart_config : std_logic; + signal link_timer_value : std_logic_vector(8 downto 0); + + signal status_vector : std_logic_vector(15 downto 0); + signal synchronization_done : std_logic; + signal linkup : std_logic; + signal signal_detect : std_logic; + + attribute clock_signal : string; + attribute clock_signal of sgmii_clk : signal is "yes"; + attribute clock_signal of sgmii_clk_int : signal is "yes"; + +begin + + ----------------------------------------------------------------------------- + -- Default for KC705 + ----------------------------------------------------------------------------- + + -- Remove AN during simulation i.e. "00000" + configuration_vector <= "10000" when (autonegotiation = 1) else "00000"; + + --an_adv_config_vector <= x"4001"; + an_adv_config_vector <= "0000000000100001"; + an_restart_config <= '0'; + link_timer_value <= "000110010"; + + -- Core Status vector outputs + synchronization_done <= status_vector_int(1); + linkup <= status_vector_int(0); + signal_detect <= '1'; + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.pirq <= (others => '0'); + apbo.prdata(31 downto 16) <= (others => '0'); + apbo.prdata(15 downto 0) <= status_vector_apb; + + gmiii.gtx_clk <= sgmii_clk; + gmiii.tx_clk <= sgmii_clk; + gmiii.rx_clk <= sgmii_clk; + gmii_txd <= gmiio.txd; + gmii_tx_en <= gmiio.tx_en; + gmii_tx_er <= gmiio.tx_er; + gmiii.rxd <= gmii_rxd; + gmiii.rx_dv <= gmii_rx_dv; + gmiii.rx_er <= gmii_rx_er; + + gmiii.edclsepahb <= '0'; + gmiii.edcldisable <= '0'; + gmiii.phyrstaddr <= (others => '0'); + gmiii.edcladdr <= (others => '0'); + + gmiii.rmii_clk <= sgmii_clk; + gmiii.rx_col <= '0'; + gmiii.rx_crs <= '0'; + + sgmiio.mdio_o <= gmiio.mdio_o; + sgmiio.mdio_oe <= gmiio.mdio_oe; + gmiii.mdio_i <= sgmiii.mdio_i; + sgmiio.mdc <= gmiio.mdc; + gmiii.mdint <= sgmiii.mdint; + sgmiio.reset <= apb_rstn; + + ----------------------------------------------------------------------------- + -- Transceiver Clock Management + ----------------------------------------------------------------------------- + + -- Clock circuitry for the GT Transceiver uses a differential input clock. + -- gtrefclk is routed to the tranceiver. + ibufds_gtrefclk : IBUFDS_GTE2 + port map ( + I => sgmiii.clkp, + IB => sgmiii.clkn, + CEB => '0', + O => gtrefclk, + ODIV2 => open + ); + + -- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is + -- routed to an MMCM module where it is used to create phase and frequency + -- related 62.5MHz and 125MHz clock sources + mmcm_adv_inst : MMCME2_ADV + generic map + (BANDWIDTH => "OPTIMIZED", + CLKOUT4_CASCADE => FALSE, + COMPENSATION => "ZHOLD", +-- STARTUP_WAIT => FALSE, + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT_F => 16.000, + CLKFBOUT_PHASE => 0.000, + CLKFBOUT_USE_FINE_PS => FALSE, + CLKOUT0_DIVIDE_F => 8.000, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.5, + CLKOUT0_USE_FINE_PS => FALSE, + CLKOUT1_DIVIDE => 16, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.5, + CLKOUT1_USE_FINE_PS => FALSE, + CLKIN1_PERIOD => 16.0, + REF_JITTER1 => 0.010) + port map + -- Output clocks + (CLKFBOUT => clkfbout, + CLKFBOUTB => open, + CLKOUT0 => clkout0, + CLKOUT0B => open, + CLKOUT1 => clkout1, + CLKOUT1B => open, + CLKOUT2 => open, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + -- Input clock control + CLKFBIN => clkfbout, + CLKIN1 => txoutclk, + CLKIN2 => '0', + -- Tied to always select the primary input clock + CLKINSEL => '1', + -- Ports for dynamic reconfiguration + DADDR => (others => '0'), + DCLK => '0', + DEN => '0', + DI => (others => '0'), + DO => open, + DRDY => open, + DWE => '0', + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + -- Other control and status signals + LOCKED => mmcm_locked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open, + PWRDWN => '0', + RST => mmcm_reset); + + mmcm_reset <= reset or (not resetdone); + + -- This 62.5MHz clock is placed onto global clock routing and is then used + -- for tranceiver TXUSRCLK/RXUSRCLK. + bufg_userclk: BUFG + port map ( + I => clkout1, + O => userclk + ); + + -- This 125MHz clock is placed onto global clock routing and is then used + -- to clock all Ethernet core logic. + bufg_userclk2: BUFG + port map ( + I => clkout0, + O => userclk2 + ); + + ----------------------------------------------------------------------------- + -- Transceiver PMA reset circuitry + ----------------------------------------------------------------------------- + + -- Create a reset pulse of a decent length + process(reset, apb_clk) + begin + if (reset = '1') then + pma_reset_pipe <= "1111"; + elsif apb_clk'event and apb_clk = '1' then + pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset; + end if; + end process; + + pma_reset <= pma_reset_pipe(3); + + ------------------------------------------------------------------------------ + -- Instantiate the Core Block (core wrapper). + ------------------------------------------------------------------------------ + + speed_is_10_100 <= not gmiio.gbit; + speed_is_100 <= gmiio.speed; + + core_wrapper : sgmii_block + port map ( + drpaddr_in => "000000000", + drpclk_in => '0', + drpdi_in => "0000000000000000", + drpdo_out => OPEN, + drpen_in => '0', + drprdy_out => OPEN, + drpwe_in => '0', + gtrefclk => gtrefclk, + txp => sgmiio.txp, + txn => sgmiio.txn, + rxp => sgmiii.rxp, + rxn => sgmiii.rxn, + txoutclk => txoutclk, + resetdone => resetdone, + mmcm_locked => mmcm_locked, + userclk => userclk, + userclk2 => userclk2, + independent_clock_bufg => apb_clk, + pma_reset => pma_reset, + sgmii_clk_r => sgmii_clk_r, + sgmii_clk_f => sgmii_clk_f, + sgmii_clk_en => sgmii_clk_en, + gmii_txd => gmii_txd_int, + gmii_tx_en => gmii_tx_en_int, + gmii_tx_er => gmii_tx_er_int, + gmii_rxd => gmii_rxd_int, + gmii_rx_dv => gmii_rx_dv_int, + gmii_rx_er => gmii_rx_er_int, + gmii_isolate => gmii_isolate, + configuration_vector => configuration_vector, + an_interrupt => an_interrupt, + an_adv_config_vector => an_adv_config_vector, + an_restart_config => an_restart_config, + link_timer_value => link_timer_value, + speed_is_10_100 => speed_is_10_100, + speed_is_100 => speed_is_100, + status_vector => status_vector_int, + reset => reset, + signal_detect => signal_detect + ); + + ----------------------------------------------------------------------------- + -- GMII transmitter data logic + ----------------------------------------------------------------------------- + + -- Drive input GMII signals through IOB input flip-flops (inferred). + process (userclk2) + begin + if userclk2'event and userclk2 = '1' then + gmii_txd_int <= gmii_txd; + gmii_tx_en_int <= gmii_tx_en; + gmii_tx_er_int <= gmii_tx_er; + + end if; + end process; + + ----------------------------------------------------------------------------- + -- SGMII clock logic + ----------------------------------------------------------------------------- + + process (userclk2) + begin + if userclk2'event and userclk2 = '1' then + sgmii_clk_int <= sgmii_clk_r; + end if; + end process; + + sgmii_clk <= userclk2 when (gmiio.gbit = '1') else sgmii_clk_int; + + ----------------------------------------------------------------------------- + -- GMII receiver data logic + ----------------------------------------------------------------------------- + + -- Drive input GMII signals through IOB output flip-flops (inferred). + process (userclk2) + begin + if userclk2'event and userclk2 = '1' then + gmii_rxd <= gmii_rxd_int; + gmii_rx_dv <= gmii_rx_dv_int; + gmii_rx_er <= gmii_rx_er_int; + + end if; + end process; + + ----------------------------------------------------------------------------- + -- Extra registers to ease IOB placement + ----------------------------------------------------------------------------- + process (userclk2) + begin + if userclk2'event and userclk2 = '1' then + status_vector <= status_vector_int; + end if; + end process; + + ----------------------------------------------------------------------------- + -- Extra registers to ease CDC placement + ----------------------------------------------------------------------------- + process (apb_clk) + begin + if apb_clk'event and apb_clk = '1' then + status_vector_apb <= status_vector_int; + end if; + end process; + +end top_level; diff --git a/designs/leon3-xilinx-ac701/systest.c b/designs/leon3-xilinx-ac701/systest.c new file mode 100644 index 00000000..6291e344 --- /dev/null +++ b/designs/leon3-xilinx-ac701/systest.c @@ -0,0 +1,14 @@ + + +main() + +{ + + report_start(); + + base_test(); + + //greth_test(0x800c0000); + + report_end(); +} diff --git a/designs/leon3-xilinx-ac701/testbench.vhd b/designs/leon3-xilinx-ac701/testbench.vhd new file mode 100644 index 00000000..b9da49f0 --- /dev/null +++ b/designs/leon3-xilinx-ac701/testbench.vhd @@ -0,0 +1,530 @@ +----------------------------------------------------------------------------- +-- LEON3 Demonstration design test bench +-- Copyright (C) 2013 Gaisler Research +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ + + +library ieee; +use ieee.std_logic_1164.all; +library gaisler; +use gaisler.libdcom.all; +use gaisler.sim.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library techmap; +use techmap.gencomp.all; +use work.debug.all; + +use work.config.all; + +entity testbench is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console + pclow : integer := CFG_PCLOW; + testahb : boolean := true; + USE_MIG_INTERFACE_MODEL : boolean := false + + ); +end; + +architecture behav of testbench is + +-- DDR3 Simulation parameters +constant SIM_BYPASS_INIT_CAL : string := "FAST"; + -- # = "OFF" - Complete memory init & + -- calibration sequence + -- # = "SKIP" - Not supported + -- # = "FAST" - Complete memory init & use + -- abbreviated calib sequence + +constant SIMULATION : string := "TRUE"; + -- Should be TRUE during design simulations and + -- FALSE during implementations + + +constant promfile : string := "prom.srec"; -- rom contents +constant ramfile : string := "ram.srec"; -- ram contents + +signal clk : std_logic := '0'; +signal Rst : std_logic := '0'; + +signal GND : std_ulogic := '0'; +signal VCC : std_ulogic := '1'; +signal NC : std_ulogic := 'Z'; + +signal txd1 , rxd1 , dsurx : std_logic; +signal txd2 , rxd2 , dsutx : std_logic; +signal ctsn1 , rtsn1 , dsuctsn : std_ulogic; +signal ctsn2 , rtsn2 , dsurtsn : std_ulogic; + +signal phy_gtxclk : std_logic := '0'; +signal phy_txer : std_ulogic; +signal phy_txd : std_logic_vector(7 downto 0); +signal phy_txctl_txen : std_ulogic; +signal phy_txclk : std_ulogic; +signal phy_rxer : std_ulogic; +signal phy_rxd : std_logic_vector(7 downto 0); +signal phy_rxctl_rxdv : std_ulogic; +signal phy_rxclk : std_ulogic; +signal phy_reset : std_ulogic; +signal phy_mdio : std_logic; +signal phy_mdc : std_ulogic; +signal phy_crs : std_ulogic; +signal phy_col : std_ulogic; +signal phy_int : std_ulogic; +signal phy_rxdl : std_logic_vector(7 downto 0); +signal phy_txdl : std_logic_vector(7 downto 0); + +signal clk27 : std_ulogic := '0'; +signal clk200p : std_ulogic := '0'; +signal clk200n : std_ulogic := '1'; +signal clk33 : std_ulogic := '0'; +signal clkethp : std_ulogic := '0'; +signal clkethn : std_ulogic := '1'; +signal txp1 : std_logic; +signal txn : std_logic; +signal rxp : std_logic := '1'; +signal rxn : std_logic := '0'; + + +signal iic_scl : std_ulogic; +signal iic_sda : std_ulogic; +signal ddc_scl : std_ulogic; +signal ddc_sda : std_ulogic; +signal dvi_iic_scl : std_logic; +signal dvi_iic_sda : std_logic; + +signal tft_lcd_data : std_logic_vector(11 downto 0); +signal tft_lcd_clk_p : std_ulogic; +signal tft_lcd_clk_n : std_ulogic; +signal tft_lcd_hsync : std_ulogic; +signal tft_lcd_vsync : std_ulogic; +signal tft_lcd_de : std_ulogic; +signal tft_lcd_reset_b : std_ulogic; + +-- DDR3 memory +signal ddr3_dq : std_logic_vector(63 downto 0); +signal ddr3_dqs_p : std_logic_vector(7 downto 0); +signal ddr3_dqs_n : std_logic_vector(7 downto 0); +signal ddr3_addr : std_logic_vector(13 downto 0); +signal ddr3_ba : std_logic_vector(2 downto 0); +signal ddr3_ras_n : std_logic; +signal ddr3_cas_n : std_logic; +signal ddr3_we_n : std_logic; +signal ddr3_reset_n : std_logic; +signal ddr3_ck_p : std_logic_vector(0 downto 0); +signal ddr3_ck_n : std_logic_vector(0 downto 0); +signal ddr3_cke : std_logic_vector(0 downto 0); +signal ddr3_cs_n : std_logic_vector(0 downto 0); +signal ddr3_dm : std_logic_vector(7 downto 0); +signal ddr3_odt : std_logic_vector(0 downto 0); + +-- SPI flash +signal spi_sel_n : std_logic; +signal spi_clk : std_ulogic; +signal spi_miso : std_ulogic := '0'; +signal spi_simo : std_ulogic; + +signal dsurst : std_ulogic; +signal errorn : std_logic; + +signal switch : std_logic_vector(3 downto 0); -- I/O port +signal button : std_logic_vector(3 downto 0); -- I/O port +signal led : std_logic_vector(3 downto 0); -- I/O port +constant lresp : boolean := false; + +signal tdqs_n : std_logic; + +signal gmii_tx_clk : std_logic; +signal gmii_rx_clk : std_logic; +signal gmii_txd : std_logic_vector(7 downto 0); +signal gmii_tx_en : std_logic; +signal gmii_tx_er : std_logic; +signal gmii_rxd : std_logic_vector(7 downto 0); +signal gmii_rx_dv : std_logic; +signal gmii_rx_er : std_logic; + +component leon3mp is + generic ( + fabtech : integer := CFG_FABTECH; + memtech : integer := CFG_MEMTECH; + padtech : integer := CFG_PADTECH; + clktech : integer := CFG_CLKTECH; + disas : integer := CFG_DISAS; -- Enable disassembly to console + dbguart : integer := CFG_DUART; -- Print UART on console + pclow : integer := CFG_PCLOW; + testahb : boolean := false; + SIM_BYPASS_INIT_CAL : string := "OFF"; + SIMULATION : string := "FALSE"; + USE_MIG_INTERFACE_MODEL : boolean := false + ); + port ( + reset : in std_ulogic; + clk200p : in std_ulogic; -- 200 MHz clock + clk200n : in std_ulogic; -- 200 MHz clock +-- spi_sel_n : inout std_ulogic; +-- spi_clk : out std_ulogic; +-- spi_miso : in std_ulogic; + ddr3_dq : inout std_logic_vector(63 downto 0); + ddr3_dqs_p : inout std_logic_vector(7 downto 0); + ddr3_dqs_n : inout std_logic_vector(7 downto 0); + ddr3_addr : out std_logic_vector(13 downto 0); + ddr3_ba : out std_logic_vector(2 downto 0); + ddr3_ras_n : out std_logic; + ddr3_cas_n : out std_logic; + ddr3_we_n : out std_logic; + ddr3_reset_n : out std_logic; + ddr3_ck_p : out std_logic_vector(0 downto 0); + ddr3_ck_n : out std_logic_vector(0 downto 0); + ddr3_cke : out std_logic_vector(0 downto 0); + ddr3_cs_n : out std_logic_vector(0 downto 0); + ddr3_dm : out std_logic_vector(7 downto 0); + ddr3_odt : out std_logic_vector(0 downto 0); + dsurx : in std_ulogic; + dsutx : out std_ulogic; + dsuctsn : in std_ulogic; + dsurtsn : out std_ulogic; + button : in std_logic_vector(3 downto 0); + switch : inout std_logic_vector(3 downto 0); + led : out std_logic_vector(3 downto 0); + iic_scl : inout std_ulogic; + iic_sda : inout std_ulogic; + gtrefclk_p : in std_logic; + gtrefclk_n : in std_logic; + phy_txclk : out std_logic; + phy_txd : out std_logic_vector(3 downto 0); + phy_txctl_txen : out std_ulogic; + phy_rxd : in std_logic_vector(3 downto 0); + phy_rxctl_rxdv : in std_ulogic; + phy_rxclk : in std_ulogic; + phy_reset : out std_ulogic; + phy_mdio : inout std_logic; + phy_mdc : out std_ulogic; + sfp_clock_mux : out std_logic_vector(1 downto 0) + ); +end component; + +begin + + -- clock and reset + clk200p <= not clk200p after 2.5 ns; + clk200n <= not clk200n after 2.5 ns; + clkethp <= not clkethp after 4 ns; + clkethn <= not clkethp after 4 ns; + + rst <= not dsurst; + rxd1 <= 'H'; ctsn1 <= '0'; + rxd2 <= 'H'; ctsn2 <= '0'; + button <= "0000"; + switch(2 downto 0) <= "000"; + + cpu : leon3mp + generic map ( + fabtech => fabtech, + memtech => memtech, + padtech => padtech, + clktech => clktech, + disas => disas, + dbguart => dbguart, + pclow => pclow, + testahb => testahb, + SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL, + SIMULATION => SIMULATION, + USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL + ) + port map ( + reset => rst, + clk200p => clk200p, + clk200n => clk200n, +-- spi_sel_n => spi_sel_n, +-- spi_clk => spi_clk, +-- spi_miso => spi_miso, + ddr3_dq => ddr3_dq, + ddr3_dqs_p => ddr3_dqs_p, + ddr3_dqs_n => ddr3_dqs_n, + ddr3_addr => ddr3_addr, + ddr3_ba => ddr3_ba, + ddr3_ras_n => ddr3_ras_n, + ddr3_cas_n => ddr3_cas_n, + ddr3_we_n => ddr3_we_n, + ddr3_reset_n => ddr3_reset_n, + ddr3_ck_p => ddr3_ck_p, + ddr3_ck_n => ddr3_ck_n, + ddr3_cke => ddr3_cke, + ddr3_cs_n => ddr3_cs_n, + ddr3_dm => ddr3_dm, + ddr3_odt => ddr3_odt, + dsurx => dsurx, + dsutx => dsutx, + dsuctsn => dsuctsn, + dsurtsn => dsurtsn, + button => button, + switch => switch, + led => led, + iic_scl => iic_scl, + iic_sda => iic_sda, + gtrefclk_p => clkethp, + gtrefclk_n => clkethn, + phy_txclk => phy_gtxclk, + phy_txd => phy_txd(3 downto 0), + phy_txctl_txen => phy_txctl_txen, + phy_rxd => phy_rxd(3 downto 0), + phy_rxctl_rxdv => phy_rxctl_rxdv, + phy_rxclk => phy_rxclk'delayed(1 ns), + phy_reset => phy_reset, + phy_mdio => phy_mdio, + phy_mdc => phy_mdc, + sfp_clock_mux => OPEN + ); + +-- spi_gen_model : if (CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1) generate +-- spi0 : spi_flash +-- generic map ( +-- ftype => 3, +-- debug => 0, +-- readcmd => 16#0B#, +-- dummybyte => 0, +-- dualoutput => 0) +-- port map ( +-- sck => spi_clk, +-- di => spi_simo, +-- do => spi_miso, +-- csn => spi_sel_n, +-- sd_cmd_timeout => '0', +-- sd_data_timeout => '0'); +-- end generate; + + -- Memory Models instantiations + gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate + ddr3mem : if (CFG_MIG_SERIES7 = 1) generate + u1 : ddr3ram + generic map ( + width => 64, + abits => 14, + colbits => 10, + rowbits => 10, + implbanks => 1, + fname => ramfile, + lddelay => (0 ns), + ldguard => 1, + speedbin => 9, --DDR3-1600K + density => 3, + pagesize => 1, + changeendian => 8) + port map ( + ck => ddr3_ck_p(0), + ckn => ddr3_ck_n(0), + cke => ddr3_cke(0), + csn => ddr3_cs_n(0), + odt => ddr3_odt(0), + rasn => ddr3_ras_n, + casn => ddr3_cas_n, + wen => ddr3_we_n, + dm => ddr3_dm, + ba => ddr3_ba, + a => ddr3_addr, + resetn => ddr3_reset_n, + dq => ddr3_dq, + dqs => ddr3_dqs_p, + dqsn => ddr3_dqs_n, + doload => led(3) + ); + end generate ddr3mem; + end generate gen_mem_model; + + mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate + ddr3_dq <= (others => 'Z'); + ddr3_dqs_p <= (others => 'Z'); + ddr3_dqs_n <= (others => 'Z'); + end generate mig_mem_model; + + errorn <= led(1); + errorn <= 'H'; -- ERROR pull-up + + phy0 : if (CFG_GRETH = 1) generate + + phy_mdio <= 'H'; + phy_int <= '0'; + p0: phy + generic map ( + address => 7, + extended_regs => 1, + aneg => 1, + base100_t4 => 1, + base100_x_fd => 1, + base100_x_hd => 1, + fd_10 => 1, + hd_10 => 1, + base100_t2_fd => 1, + base100_t2_hd => 1, + base1000_x_fd => 1, + base1000_x_hd => 1, + base1000_t_fd => 1, + base1000_t_hd => 1, + rmii => 0, + rgmii => 1 + ) + port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd, + phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd, + phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk); + + end generate; + + iuerr : process + begin + wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation + wait on led(3); -- DDR3 Memory Init ready + wait for 5000 ns; + wait for 100 us; + if to_x01(errorn) = '1' then wait on errorn; end if; + assert (to_x01(errorn) = '1') + report "*** IU in error mode, simulation halted ***" + severity failure ; -- this should be a failure + end process; + + --data <= buskeep(data) after 5 ns; + + dsucom : process + procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is + variable w32 : std_logic_vector(31 downto 0); + variable c8 : std_logic_vector(7 downto 0); + constant txp : time := 320 * 1 ns; + begin + dsutx <= '1'; + dsurst <= '0'; + switch(3) <= '0'; + wait for 2500 ns; + wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation + dsurst <= '1'; + switch(3) <= '1'; + if (USE_MIG_INTERFACE_MODEL /= true) then + wait on led(3); -- Wait for DDR3 Memory Init ready + end if; + report "Start DSU transfer"; + wait for 5000 ns; + txc(dsutx, 16#55#, txp); -- sync uart + + -- Reads from memory and DSU register to mimic GRMON during simulation + l1 : loop + txc(dsutx, 16#80#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp); + rxi(dsurx, w32, txp, lresp); + --report "DSU read memory " & tost(w32); + txc(dsutx, 16#80#, txp); + txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); + rxi(dsurx, w32, txp, lresp); + --report "DSU Break and Single Step register" & tost(w32); + end loop l1; + + wait; + + -- ** This is only kept for reference -- + + -- do test read and writes to DDR3 to check status + -- Write + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); + txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp); + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp); + txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp); + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp); + txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp); + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp); + txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp); + txc(dsutx, 16#80#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp); + rxi(dsurx, w32, txp, lresp); + txc(dsutx, 16#80#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp); + rxi(dsurx, w32, txp, lresp); + report "* Read " & tost(w32); + txc(dsutx, 16#a0#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp); + rxi(dsurx, w32, txp, lresp); + txc(dsutx, 16#a0#, txp); + txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp); + rxi(dsurx, w32, txp, lresp); + wait; + + -- Register 0x90000000 (DSU Control Register) + -- Data 0x0000202e (b0010 0000 0010 1110) + -- [0] - Trace Enable + -- [1] - Break On Error + -- [2] - Break on IU watchpoint + -- [3] - Break on s/w break points + -- + -- [4] - (Break on trap) + -- [5] - Break on error traps + -- [6] - Debug mode (Read mode only) + -- [7] - DSUEN (read mode) + -- + -- [8] - DSUBRE (read mode) + -- [9] - Processor mode error (clears error) + -- [10] - processor halt (returns 1 if processor halted) + -- [11] - power down mode (return 1 if processor in power down mode) + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); + txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp); + wait; + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); + txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp); + + wait for 25000 ns; + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp); + txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp); + + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp); + txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp); + + txc(dsutx, 16#c0#, txp); + txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp); + txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp); + + txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp); + txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp); + + txc(dsutx, 16#80#, txp); + txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp); + + wait; + + end; + + begin + dsuctsn <= '0'; + dsucfg(dsutx, dsurx); + wait; + end process; +end ; + diff --git a/designs/leon3-xilinx-ac701/tkconfig.h b/designs/leon3-xilinx-ac701/tkconfig.h new file mode 100644 index 00000000..3402ae11 --- /dev/null +++ b/designs/leon3-xilinx-ac701/tkconfig.h @@ -0,0 +1,1138 @@ +#if defined CONFIG_SYN_INFERRED +#define CONFIG_SYN_TECH inferred +#elif defined CONFIG_SYN_UMC +#define CONFIG_SYN_TECH umc +#elif defined CONFIG_SYN_RHUMC +#define CONFIG_SYN_TECH rhumc +#elif defined CONFIG_SYN_DARE +#define CONFIG_SYN_TECH dare +#elif defined CONFIG_SYN_SAED32 +#define CONFIG_SYN_TECH saed32 +#elif defined CONFIG_SYN_ATC18 +#define CONFIG_SYN_TECH atc18s +#elif defined CONFIG_SYN_ATC18RHA +#define CONFIG_SYN_TECH atc18rha +#elif defined CONFIG_SYN_AXCEL +#define CONFIG_SYN_TECH axcel +#elif defined CONFIG_SYN_AXDSP +#define CONFIG_SYN_TECH axdsp +#elif defined CONFIG_SYN_PROASICPLUS +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_ALTERA +#define CONFIG_SYN_TECH altera +#elif defined CONFIG_SYN_STRATIX +#define CONFIG_SYN_TECH stratix1 +#elif defined CONFIG_SYN_STRATIXII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_STRATIXIII +#define CONFIG_SYN_TECH stratix3 +#elif defined CONFIG_SYN_STRATIXIV +#define CONFIG_SYN_TECH stratix4 +#elif defined CONFIG_SYN_CYCLONEII +#define CONFIG_SYN_TECH stratix2 +#elif defined CONFIG_SYN_CYCLONEIII +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_CYCLONEIV +#define CONFIG_SYN_TECH cyclone3 +#elif defined CONFIG_SYN_EASIC45 +#define CONFIG_SYN_TECH easic45 +#elif defined CONFIG_SYN_EASIC90 +#define CONFIG_SYN_TECH easic90 +#elif defined CONFIG_SYN_IHP25 +#define CONFIG_SYN_TECH ihp25 +#elif defined CONFIG_SYN_IHP25RH +#define CONFIG_SYN_TECH ihp25rh +#elif defined CONFIG_SYN_CMOS9SF +#define CONFIG_SYN_TECH cmos9sf +#elif defined CONFIG_SYN_LATTICE +#define CONFIG_SYN_TECH lattice +#elif defined CONFIG_SYN_ECLIPSE +#define CONFIG_SYN_TECH eclipse +#elif defined CONFIG_SYN_PEREGRINE +#define CONFIG_SYN_TECH peregrine +#elif defined CONFIG_SYN_PROASIC +#define CONFIG_SYN_TECH proasic +#elif defined CONFIG_SYN_PROASIC3 +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_PROASIC3E +#define CONFIG_SYN_TECH apa3e +#elif defined CONFIG_SYN_PROASIC3L +#define CONFIG_SYN_TECH apa3l +#elif defined CONFIG_SYN_IGLOO +#define CONFIG_SYN_TECH apa3 +#elif defined CONFIG_SYN_FUSION +#define CONFIG_SYN_TECH actfus +#elif defined CONFIG_SYN_SPARTAN2 +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEX +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_VIRTEXE +#define CONFIG_SYN_TECH virtex +#elif defined CONFIG_SYN_SPARTAN3 +#define CONFIG_SYN_TECH spartan3 +#elif defined CONFIG_SYN_SPARTAN3E +#define CONFIG_SYN_TECH spartan3e +#elif defined CONFIG_SYN_SPARTAN6 +#define CONFIG_SYN_TECH spartan6 +#elif defined CONFIG_SYN_VIRTEX2 +#define CONFIG_SYN_TECH virtex2 +#elif defined CONFIG_SYN_VIRTEX4 +#define CONFIG_SYN_TECH virtex4 +#elif defined CONFIG_SYN_VIRTEX5 +#define CONFIG_SYN_TECH virtex5 +#elif defined CONFIG_SYN_VIRTEX6 +#define CONFIG_SYN_TECH virtex6 +#elif defined CONFIG_SYN_VIRTEX7 +#define CONFIG_SYN_TECH virtex7 +#elif defined CONFIG_SYN_KINTEX7 +#define CONFIG_SYN_TECH kintex7 +#elif defined CONFIG_SYN_ARTIX7 +#define CONFIG_SYN_TECH artix7 +#elif defined CONFIG_SYN_ZYNQ7000 +#define CONFIG_SYN_TECH zynq7000 +#elif defined CONFIG_SYN_ARTIX77 +#define CONFIG_SYN_TECH artix7 +#elif defined CONFIG_SYN_ZYNQ7000 +#define CONFIG_SYN_TECH zynq7000 +#elif defined CONFIG_SYN_RH_LIB18T +#define CONFIG_SYN_TECH rhlib18t +#elif defined CONFIG_SYN_SMIC13 +#define CONFIG_SYN_TECH smic013 +#elif defined CONFIG_SYN_UT025CRH +#define CONFIG_SYN_TECH ut25 +#elif defined CONFIG_SYN_UT130HBD +#define CONFIG_SYN_TECH ut130 +#elif defined CONFIG_SYN_UT90NHBD +#define CONFIG_SYN_TECH ut90 +#elif defined CONFIG_SYN_TSMC90 +#define CONFIG_SYN_TECH tsmc90 +#elif defined CONFIG_SYN_TM65GPLUS +#define CONFIG_SYN_TECH tm65gplus +#elif defined CONFIG_SYN_CUSTOM1 +#define CONFIG_SYN_TECH custom1 +#else +#error "unknown target technology" +#endif + +#if defined CONFIG_SYN_INFER_RAM +#define CFG_RAM_TECH inferred +#elif defined CONFIG_MEM_UMC +#define CFG_RAM_TECH umc +#elif defined CONFIG_MEM_RHUMC +#define CFG_RAM_TECH rhumc +#elif defined CONFIG_MEM_DARE +#define CFG_RAM_TECH dare +#elif defined CONFIG_MEM_SAED32 +#define CFG_RAM_TECH saed32 +#elif defined CONFIG_MEM_VIRAGE +#define CFG_RAM_TECH memvirage +#elif defined CONFIG_MEM_ARTISAN +#define CFG_RAM_TECH memartisan +#elif defined CONFIG_MEM_CUSTOM1 +#define CFG_RAM_TECH custom1 +#elif defined CONFIG_MEM_VIRAGE90 +#define CFG_RAM_TECH memvirage90 +#elif defined CONFIG_MEM_INFERRED +#define CFG_RAM_TECH inferred +#else +#define CFG_RAM_TECH CONFIG_SYN_TECH +#endif + +#if defined CONFIG_SYN_INFER_PADS +#define CFG_PAD_TECH inferred +#else +#define CFG_PAD_TECH CONFIG_SYN_TECH +#endif + +#ifndef CONFIG_SYN_NO_ASYNC +#define CONFIG_SYN_NO_ASYNC 0 +#endif + +#ifndef CONFIG_SYN_SCAN +#define CONFIG_SYN_SCAN 0 +#endif + + +#if defined CONFIG_CLK_ALTDLL +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_HCLKBUF +#define CFG_CLK_TECH axcel +#elif defined CONFIG_CLK_LATDLL +#define CFG_CLK_TECH lattice +#elif defined CONFIG_CLK_PRO3PLL +#define CFG_CLK_TECH apa3 +#elif defined CONFIG_CLK_PRO3EPLL +#define CFG_CLK_TECH apa3e +#elif defined CONFIG_CLK_PRO3LPLL +#define CFG_CLK_TECH apa3l +#elif defined CONFIG_CLK_FUSPLL +#define CFG_CLK_TECH actfus +#elif defined CONFIG_CLK_CLKDLL +#define CFG_CLK_TECH virtex +#elif defined CONFIG_CLK_CLKPLLE2 +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_DCM +#define CFG_CLK_TECH CONFIG_SYN_TECH +#elif defined CONFIG_CLK_LIB18T +#define CFG_CLK_TECH rhlib18t +#elif defined CONFIG_CLK_RHUMC +#define CFG_CLK_TECH rhumc +#elif defined CONFIG_CLK_SAED32 +#define CFG_CLK_TECH saed32 +#elif defined CONFIG_CLK_DARE +#define CFG_CLK_TECH dare +#elif defined CONFIG_CLK_EASIC45 +#define CFG_CLK_TECH easic45 +#elif defined CONFIG_CLK_UT130HBD +#define CFG_CLK_TECH ut130 +#else +#define CFG_CLK_TECH inferred +#endif + +#ifndef CONFIG_CLK_MUL +#define CONFIG_CLK_MUL 2 +#endif + +#ifndef CONFIG_CLK_DIV +#define CONFIG_CLK_DIV 2 +#endif + +#ifndef CONFIG_OCLK_DIV +#define CONFIG_OCLK_DIV 1 +#endif + +#ifndef CONFIG_OCLKB_DIV +#define CONFIG_OCLKB_DIV 0 +#endif + +#ifndef CONFIG_OCLKC_DIV +#define CONFIG_OCLKC_DIV 0 +#endif + +#ifndef CONFIG_PCI_CLKDLL +#define CONFIG_PCI_CLKDLL 0 +#endif + +#ifndef CONFIG_PCI_SYSCLK +#define CONFIG_PCI_SYSCLK 0 +#endif + +#ifndef CONFIG_CLK_NOFB +#define CONFIG_CLK_NOFB 0 +#endif +#ifndef CONFIG_LEON3 +#define CONFIG_LEON3 0 +#endif + +#ifndef CONFIG_PROC_NUM +#define CONFIG_PROC_NUM 1 +#endif + +#ifndef CONFIG_IU_NWINDOWS +#define CONFIG_IU_NWINDOWS 8 +#endif + +#ifndef CONFIG_IU_RSTADDR +#define CONFIG_IU_RSTADDR 8 +#endif + +#ifndef CONFIG_IU_LDELAY +#define CONFIG_IU_LDELAY 1 +#endif + +#ifndef CONFIG_IU_WATCHPOINTS +#define CONFIG_IU_WATCHPOINTS 0 +#endif + +#ifdef CONFIG_IU_V8MULDIV +#ifdef CONFIG_IU_MUL_LATENCY_4 +#define CFG_IU_V8 1 +#elif defined CONFIG_IU_MUL_LATENCY_5 +#define CFG_IU_V8 2 +#elif defined CONFIG_IU_MUL_LATENCY_2 +#define CFG_IU_V8 16#32# +#endif +#else +#define CFG_IU_V8 0 +#endif + +#ifdef CONFIG_IU_MUL_MODGEN +#define CFG_IU_MUL_STRUCT 1 +#elif defined CONFIG_IU_MUL_TECHSPEC +#define CFG_IU_MUL_STRUCT 2 +#elif defined CONFIG_IU_MUL_DW +#define CFG_IU_MUL_STRUCT 3 +#else +#define CFG_IU_MUL_STRUCT 0 +#endif + +#ifndef CONFIG_PWD +#define CONFIG_PWD 0 +#endif + +#ifndef CONFIG_IU_MUL_MAC +#define CONFIG_IU_MUL_MAC 0 +#endif + +#ifndef CONFIG_IU_BP +#define CONFIG_IU_BP 0 +#endif + +#ifndef CONFIG_NOTAG +#define CONFIG_NOTAG 0 +#endif + +#ifndef CONFIG_IU_SVT +#define CONFIG_IU_SVT 0 +#endif + +#if defined CONFIG_FPU_GRFPC1 +#define CONFIG_FPU_GRFPC 1 +#elif defined CONFIG_FPU_GRFPC2 +#define CONFIG_FPU_GRFPC 2 +#else +#define CONFIG_FPU_GRFPC 0 +#endif + +#if defined CONFIG_FPU_GRFPU_INFMUL +#define CONFIG_FPU_GRFPU_MUL 0 +#elif defined CONFIG_FPU_GRFPU_DWMUL +#define CONFIG_FPU_GRFPU_MUL 1 +#elif defined CONFIG_FPU_GRFPU_MODGEN +#define CONFIG_FPU_GRFPU_MUL 2 +#elif defined CONFIG_FPU_GRFPU_TECHSPEC +#define CONFIG_FPU_GRFPU_MUL 3 +#else +#define CONFIG_FPU_GRFPU_MUL 0 +#endif + +#if defined CONFIG_FPU_GRFPU_SH +#define CONFIG_FPU_GRFPU_SHARED 1 +#else +#define CONFIG_FPU_GRFPU_SHARED 0 +#endif + +#if defined CONFIG_FPU_GRFPU +#define CONFIG_FPU (1+CONFIG_FPU_GRFPU_MUL) +#elif defined CONFIG_FPU_MEIKO +#define CONFIG_FPU 15 +#elif defined CONFIG_FPU_GRFPULITE +#define CONFIG_FPU (8+CONFIG_FPU_GRFPC) +#else +#define CONFIG_FPU 0 +#endif + +#ifndef CONFIG_FPU_NETLIST +#define CONFIG_FPU_NETLIST 0 +#endif + +#ifndef CONFIG_ICACHE_ENABLE +#define CONFIG_ICACHE_ENABLE 0 +#endif + +#if defined CONFIG_ICACHE_ASSO1 +#define CFG_IU_ISETS 1 +#elif defined CONFIG_ICACHE_ASSO2 +#define CFG_IU_ISETS 2 +#elif defined CONFIG_ICACHE_ASSO3 +#define CFG_IU_ISETS 3 +#elif defined CONFIG_ICACHE_ASSO4 +#define CFG_IU_ISETS 4 +#else +#define CFG_IU_ISETS 1 +#endif + +#if defined CONFIG_ICACHE_SZ1 +#define CFG_ICACHE_SZ 1 +#elif defined CONFIG_ICACHE_SZ2 +#define CFG_ICACHE_SZ 2 +#elif defined CONFIG_ICACHE_SZ4 +#define CFG_ICACHE_SZ 4 +#elif defined CONFIG_ICACHE_SZ8 +#define CFG_ICACHE_SZ 8 +#elif defined CONFIG_ICACHE_SZ16 +#define CFG_ICACHE_SZ 16 +#elif defined CONFIG_ICACHE_SZ32 +#define CFG_ICACHE_SZ 32 +#elif defined CONFIG_ICACHE_SZ64 +#define CFG_ICACHE_SZ 64 +#elif defined CONFIG_ICACHE_SZ128 +#define CFG_ICACHE_SZ 128 +#elif defined CONFIG_ICACHE_SZ256 +#define CFG_ICACHE_SZ 256 +#else +#define CFG_ICACHE_SZ 1 +#endif + +#ifdef CONFIG_ICACHE_LZ16 +#define CFG_ILINE_SZ 4 +#else +#define CFG_ILINE_SZ 8 +#endif + +#if defined CONFIG_ICACHE_ALGODIR +#define CFG_ICACHE_ALGORND 3 +#elif defined CONFIG_ICACHE_ALGORND +#define CFG_ICACHE_ALGORND 2 +#elif defined CONFIG_ICACHE_ALGOLRR +#define CFG_ICACHE_ALGORND 1 +#else +#define CFG_ICACHE_ALGORND 0 +#endif + +#ifndef CONFIG_ICACHE_LOCK +#define CONFIG_ICACHE_LOCK 0 +#endif + +#ifndef CONFIG_ICACHE_LRAM +#define CONFIG_ICACHE_LRAM 0 +#endif + +#ifndef CONFIG_ICACHE_LRSTART +#define CONFIG_ICACHE_LRSTART 8E +#endif + +#if defined CONFIG_ICACHE_LRAM_SZ2 +#define CFG_ILRAM_SIZE 2 +#elif defined CONFIG_ICACHE_LRAM_SZ4 +#define CFG_ILRAM_SIZE 4 +#elif defined CONFIG_ICACHE_LRAM_SZ8 +#define CFG_ILRAM_SIZE 8 +#elif defined CONFIG_ICACHE_LRAM_SZ16 +#define CFG_ILRAM_SIZE 16 +#elif defined CONFIG_ICACHE_LRAM_SZ32 +#define CFG_ILRAM_SIZE 32 +#elif defined CONFIG_ICACHE_LRAM_SZ64 +#define CFG_ILRAM_SIZE 64 +#elif defined CONFIG_ICACHE_LRAM_SZ128 +#define CFG_ILRAM_SIZE 128 +#elif defined CONFIG_ICACHE_LRAM_SZ256 +#define CFG_ILRAM_SIZE 256 +#else +#define CFG_ILRAM_SIZE 1 +#endif + + +#ifndef CONFIG_DCACHE_ENABLE +#define CONFIG_DCACHE_ENABLE 0 +#endif + +#if defined CONFIG_DCACHE_ASSO1 +#define CFG_IU_DSETS 1 +#elif defined CONFIG_DCACHE_ASSO2 +#define CFG_IU_DSETS 2 +#elif defined CONFIG_DCACHE_ASSO3 +#define CFG_IU_DSETS 3 +#elif defined CONFIG_DCACHE_ASSO4 +#define CFG_IU_DSETS 4 +#else +#define CFG_IU_DSETS 1 +#endif + +#if defined CONFIG_DCACHE_SZ1 +#define CFG_DCACHE_SZ 1 +#elif defined CONFIG_DCACHE_SZ2 +#define CFG_DCACHE_SZ 2 +#elif defined CONFIG_DCACHE_SZ4 +#define CFG_DCACHE_SZ 4 +#elif defined CONFIG_DCACHE_SZ8 +#define CFG_DCACHE_SZ 8 +#elif defined CONFIG_DCACHE_SZ16 +#define CFG_DCACHE_SZ 16 +#elif defined CONFIG_DCACHE_SZ32 +#define CFG_DCACHE_SZ 32 +#elif defined CONFIG_DCACHE_SZ64 +#define CFG_DCACHE_SZ 64 +#elif defined CONFIG_DCACHE_SZ128 +#define CFG_DCACHE_SZ 128 +#elif defined CONFIG_DCACHE_SZ256 +#define CFG_DCACHE_SZ 256 +#else +#define CFG_DCACHE_SZ 1 +#endif + +#ifdef CONFIG_DCACHE_LZ16 +#define CFG_DLINE_SZ 4 +#else +#define CFG_DLINE_SZ 8 +#endif + +#if defined CONFIG_DCACHE_ALGODIR +#define CFG_DCACHE_ALGORND 3 +#elif defined CONFIG_DCACHE_ALGORND +#define CFG_DCACHE_ALGORND 2 +#elif defined CONFIG_DCACHE_ALGOLRR +#define CFG_DCACHE_ALGORND 1 +#else +#define CFG_DCACHE_ALGORND 0 +#endif + +#ifndef CONFIG_DCACHE_LOCK +#define CONFIG_DCACHE_LOCK 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP +#define CONFIG_DCACHE_SNOOP 0 +#endif + +#ifndef CONFIG_DCACHE_SNOOP_SEPTAG +#define CONFIG_DCACHE_SNOOP_SEPTAG 0 +#endif + +#ifndef CONFIG_CACHE_FIXED +#define CONFIG_CACHE_FIXED 0 +#endif + +#ifndef CONFIG_DCACHE_LRAM +#define CONFIG_DCACHE_LRAM 0 +#endif + +#ifndef CONFIG_DCACHE_LRSTART +#define CONFIG_DCACHE_LRSTART 8F +#endif + +#if defined CONFIG_DCACHE_LRAM_SZ2 +#define CFG_DLRAM_SIZE 2 +#elif defined CONFIG_DCACHE_LRAM_SZ4 +#define CFG_DLRAM_SIZE 4 +#elif defined CONFIG_DCACHE_LRAM_SZ8 +#define CFG_DLRAM_SIZE 8 +#elif defined CONFIG_DCACHE_LRAM_SZ16 +#define CFG_DLRAM_SIZE 16 +#elif defined CONFIG_DCACHE_LRAM_SZ32 +#define CFG_DLRAM_SIZE 32 +#elif defined CONFIG_DCACHE_LRAM_SZ64 +#define CFG_DLRAM_SIZE 64 +#elif defined CONFIG_DCACHE_LRAM_SZ128 +#define CFG_DLRAM_SIZE 128 +#elif defined CONFIG_DCACHE_LRAM_SZ256 +#define CFG_DLRAM_SIZE 256 +#else +#define CFG_DLRAM_SIZE 1 +#endif + +#if defined CONFIG_MMU_PAGE_4K +#define CONFIG_MMU_PAGE 0 +#elif defined CONFIG_MMU_PAGE_8K +#define CONFIG_MMU_PAGE 1 +#elif defined CONFIG_MMU_PAGE_16K +#define CONFIG_MMU_PAGE 2 +#elif defined CONFIG_MMU_PAGE_32K +#define CONFIG_MMU_PAGE 3 +#elif defined CONFIG_MMU_PAGE_PROG +#define CONFIG_MMU_PAGE 4 +#else +#define CONFIG_MMU_PAGE 0 +#endif + +#ifdef CONFIG_MMU_ENABLE +#define CONFIG_MMUEN 1 + +#ifdef CONFIG_MMU_SPLIT +#define CONFIG_TLB_TYPE 0 +#endif +#ifdef CONFIG_MMU_COMBINED +#define CONFIG_TLB_TYPE 1 +#endif + +#ifdef CONFIG_MMU_REPARRAY +#define CONFIG_TLB_REP 0 +#endif +#ifdef CONFIG_MMU_REPINCREMENT +#define CONFIG_TLB_REP 1 +#endif + +#ifdef CONFIG_MMU_I2 +#define CONFIG_ITLBNUM 2 +#endif +#ifdef CONFIG_MMU_I4 +#define CONFIG_ITLBNUM 4 +#endif +#ifdef CONFIG_MMU_I8 +#define CONFIG_ITLBNUM 8 +#endif +#ifdef CONFIG_MMU_I16 +#define CONFIG_ITLBNUM 16 +#endif +#ifdef CONFIG_MMU_I32 +#define CONFIG_ITLBNUM 32 +#endif +#ifdef CONFIG_MMU_I64 +#define CONFIG_ITLBNUM 64 +#endif + + +#define CONFIG_DTLBNUM 2 +#ifdef CONFIG_MMU_D2 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 2 +#endif +#ifdef CONFIG_MMU_D4 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 4 +#endif +#ifdef CONFIG_MMU_D8 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 8 +#endif +#ifdef CONFIG_MMU_D16 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 16 +#endif +#ifdef CONFIG_MMU_D32 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 32 +#endif +#ifdef CONFIG_MMU_D64 +#undef CONFIG_DTLBNUM +#define CONFIG_DTLBNUM 64 +#endif +#ifdef CONFIG_MMU_FASTWB +#define CFG_MMU_FASTWB 1 +#else +#define CFG_MMU_FASTWB 0 +#endif + +#else +#define CONFIG_MMUEN 0 +#define CONFIG_ITLBNUM 2 +#define CONFIG_DTLBNUM 2 +#define CONFIG_TLB_TYPE 1 +#define CONFIG_TLB_REP 1 +#define CFG_MMU_FASTWB 0 +#endif + +#ifndef CONFIG_DSU_ENABLE +#define CONFIG_DSU_ENABLE 0 +#endif + +#if defined CONFIG_DSU_ITRACESZ1 +#define CFG_DSU_ITB 1 +#elif CONFIG_DSU_ITRACESZ2 +#define CFG_DSU_ITB 2 +#elif CONFIG_DSU_ITRACESZ4 +#define CFG_DSU_ITB 4 +#elif CONFIG_DSU_ITRACESZ8 +#define CFG_DSU_ITB 8 +#elif CONFIG_DSU_ITRACESZ16 +#define CFG_DSU_ITB 16 +#else +#define CFG_DSU_ITB 0 +#endif + +#if defined CONFIG_DSU_ATRACESZ1 +#define CFG_DSU_ATB 1 +#elif CONFIG_DSU_ATRACESZ2 +#define CFG_DSU_ATB 2 +#elif CONFIG_DSU_ATRACESZ4 +#define CFG_DSU_ATB 4 +#elif CONFIG_DSU_ATRACESZ8 +#define CFG_DSU_ATB 8 +#elif CONFIG_DSU_ATRACESZ16 +#define CFG_DSU_ATB 16 +#else +#define CFG_DSU_ATB 0 +#endif + +#ifndef CONFIG_LEON3FT_EN +#define CONFIG_LEON3FT_EN 0 +#endif + +#if defined CONFIG_IUFT_PAR +#define CONFIG_IUFT_EN 1 +#elif defined CONFIG_IUFT_DMR +#define CONFIG_IUFT_EN 2 +#elif defined CONFIG_IUFT_BCH +#define CONFIG_IUFT_EN 3 +#elif defined CONFIG_IUFT_TMR +#define CONFIG_IUFT_EN 4 +#else +#define CONFIG_IUFT_EN 0 +#endif +#ifndef CONFIG_RF_ERRINJ +#define CONFIG_RF_ERRINJ 0 +#endif + +#if defined CONFIG_FPUFT_PAR +#define CONFIG_FPUFT 1 +#elif defined CONFIG_FPUFT_DMR +#define CONFIG_FPUFT 2 +#elif defined CONFIG_FPUFT_TMR +#define CONFIG_FPUFT 4 +#else +#define CONFIG_FPUFT 0 +#endif + +#ifndef CONFIG_CACHE_FT_EN +#define CONFIG_CACHE_FT_EN 0 +#endif +#ifndef CONFIG_CACHE_ERRINJ +#define CONFIG_CACHE_ERRINJ 0 +#endif + +#ifndef CONFIG_LEON3_NETLIST +#define CONFIG_LEON3_NETLIST 0 +#endif + +#ifdef CONFIG_DEBUG_PC32 +#define CFG_DEBUG_PC32 0 +#else +#define CFG_DEBUG_PC32 2 +#endif +#ifndef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 0 +#endif +#ifndef CONFIG_IU_DISAS_NET +#define CONFIG_IU_DISAS_NET 0 +#endif + + +#ifndef CONFIG_AHB_SPLIT +#define CONFIG_AHB_SPLIT 0 +#endif + +#ifndef CONFIG_AHB_RROBIN +#define CONFIG_AHB_RROBIN 0 +#endif + +#ifndef CONFIG_AHB_FPNPEN +#define CONFIG_AHB_FPNPEN 0 +#endif + +#ifndef CONFIG_AHB_IOADDR +#define CONFIG_AHB_IOADDR FFF +#endif + +#ifndef CONFIG_APB_HADDR +#define CONFIG_APB_HADDR 800 +#endif + +#ifndef CONFIG_AHB_MON +#define CONFIG_AHB_MON 0 +#endif + +#ifndef CONFIG_AHB_MONERR +#define CONFIG_AHB_MONERR 0 +#endif + +#ifndef CONFIG_AHB_MONWAR +#define CONFIG_AHB_MONWAR 0 +#endif + +#ifndef CONFIG_AHB_DTRACE +#define CONFIG_AHB_DTRACE 0 +#endif + +#ifndef CONFIG_DSU_UART +#define CONFIG_DSU_UART 0 +#endif + + +#ifndef CONFIG_DSU_JTAG +#define CONFIG_DSU_JTAG 0 +#endif + +#ifndef CONFIG_DSU_ETH +#define CONFIG_DSU_ETH 0 +#endif + +#ifndef CONFIG_DSU_IPMSB +#define CONFIG_DSU_IPMSB C0A8 +#endif + +#ifndef CONFIG_DSU_IPLSB +#define CONFIG_DSU_IPLSB 0033 +#endif + +#ifndef CONFIG_DSU_ETHMSB +#define CONFIG_DSU_ETHMSB 020000 +#endif + +#ifndef CONFIG_DSU_ETHLSB +#define CONFIG_DSU_ETHLSB 000009 +#endif + +#if defined CONFIG_DSU_ETHSZ1 +#define CFG_DSU_ETHB 1 +#elif CONFIG_DSU_ETHSZ2 +#define CFG_DSU_ETHB 2 +#elif CONFIG_DSU_ETHSZ4 +#define CFG_DSU_ETHB 4 +#elif CONFIG_DSU_ETHSZ8 +#define CFG_DSU_ETHB 8 +#elif CONFIG_DSU_ETHSZ16 +#define CFG_DSU_ETHB 16 +#elif CONFIG_DSU_ETHSZ32 +#define CFG_DSU_ETHB 32 +#else +#define CFG_DSU_ETHB 1 +#endif + +#ifndef CONFIG_DSU_ETH_PROG +#define CONFIG_DSU_ETH_PROG 0 +#endif + +#ifndef CONFIG_DSU_ETH_DIS +#define CONFIG_DSU_ETH_DIS 0 +#endif + +#ifndef CONFIG_MCTRL_LEON2 +#define CONFIG_MCTRL_LEON2 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM +#define CONFIG_MCTRL_SDRAM 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_SEPBUS +#define CONFIG_MCTRL_SDRAM_SEPBUS 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_INVCLK +#define CONFIG_MCTRL_SDRAM_INVCLK 0 +#endif + +#ifndef CONFIG_MCTRL_SDRAM_BUS64 +#define CONFIG_MCTRL_SDRAM_BUS64 0 +#endif + +#ifndef CONFIG_MCTRL_8BIT +#define CONFIG_MCTRL_8BIT 0 +#endif + +#ifndef CONFIG_MCTRL_16BIT +#define CONFIG_MCTRL_16BIT 0 +#endif + +#ifndef CONFIG_MCTRL_5CS +#define CONFIG_MCTRL_5CS 0 +#endif + +#ifndef CONFIG_MCTRL_EDAC +#define CONFIG_MCTRL_EDAC 0 +#endif + +#ifndef CONFIG_MCTRL_PAGE +#define CONFIG_MCTRL_PAGE 0 +#endif + +#ifndef CONFIG_MCTRL_PROGPAGE +#define CONFIG_MCTRL_PROGPAGE 0 +#endif + + +#ifndef CONFIG_MIG_DDR3 +#define CONFIG_MIG_DDR3 0 +#endif + +#ifndef CONFIG_MIG_DDR2 +#define CONFIG_MIG_DDR2 0 +#endif + +#ifndef CONFIG_MIG_RANKS +#define CONFIG_MIG_RANKS 1 +#endif + +#ifndef CONFIG_MIG_COLBITS +#define CONFIG_MIG_COLBITS 10 +#endif + +#ifndef CONFIG_MIG_ROWBITS +#define CONFIG_MIG_ROWBITS 13 +#endif + +#ifndef CONFIG_MIG_BANKBITS +#define CONFIG_MIG_BANKBITS 2 +#endif + +#ifndef CONFIG_MIG_HMASK +#define CONFIG_MIG_HMASK F00 +#endif + +#ifndef CONFIG_MIG_SERIES7 +#define CONFIG_MIG_SERIES7 0 +#endif +#ifndef CONFIG_MIG_SERIES7_MODEL +#define CONFIG_MIG_SERIES7_MODEL 0 +#endif +#ifndef CONFIG_AHBSTAT_ENABLE +#define CONFIG_AHBSTAT_ENABLE 0 +#endif + +#ifndef CONFIG_AHBSTAT_NFTSLV +#define CONFIG_AHBSTAT_NFTSLV 1 +#endif + +#ifndef CONFIG_AHBROM_ENABLE +#define CONFIG_AHBROM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBROM_START +#define CONFIG_AHBROM_START 000 +#endif + +#ifndef CONFIG_AHBROM_PIPE +#define CONFIG_AHBROM_PIPE 0 +#endif + +#if (CONFIG_AHBROM_START == 0) && (CONFIG_AHBROM_ENABLE == 1) +#define CONFIG_ROM_START 100 +#else +#define CONFIG_ROM_START 000 +#endif + + +#ifndef CONFIG_AHBRAM_ENABLE +#define CONFIG_AHBRAM_ENABLE 0 +#endif + +#ifndef CONFIG_AHBRAM_START +#define CONFIG_AHBRAM_START A00 +#endif + +#if defined CONFIG_AHBRAM_SZ1 +#define CFG_AHBRAMSZ 1 +#elif CONFIG_AHBRAM_SZ2 +#define CFG_AHBRAMSZ 2 +#elif CONFIG_AHBRAM_SZ4 +#define CFG_AHBRAMSZ 4 +#elif CONFIG_AHBRAM_SZ8 +#define CFG_AHBRAMSZ 8 +#elif CONFIG_AHBRAM_SZ16 +#define CFG_AHBRAMSZ 16 +#elif CONFIG_AHBRAM_SZ32 +#define CFG_AHBRAMSZ 32 +#elif CONFIG_AHBRAM_SZ64 +#define CFG_AHBRAMSZ 64 +#elif CONFIG_AHBRAM_SZ128 +#define CFG_AHBRAMSZ 128 +#elif CONFIG_AHBRAM_SZ256 +#define CFG_AHBRAMSZ 256 +#elif CONFIG_AHBRAM_SZ512 +#define CFG_AHBRAMSZ 512 +#elif CONFIG_AHBRAM_SZ1024 +#define CFG_AHBRAMSZ 1024 +#elif CONFIG_AHBRAM_SZ2048 +#define CFG_AHBRAMSZ 2048 +#elif CONFIG_AHBRAM_SZ4096 +#define CFG_AHBRAMSZ 4096 +#else +#define CFG_AHBRAMSZ 1 +#endif + +#ifndef CONFIG_AHBRAM_PIPE +#define CONFIG_AHBRAM_PIPE 0 +#endif +#ifndef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 0 +#endif + +#ifndef CONFIG_GRETH_GIGA +#define CONFIG_GRETH_GIGA 0 +#endif + +#if defined CONFIG_GRETH_FIFO4 +#define CFG_GRETH_FIFO 4 +#elif defined CONFIG_GRETH_FIFO8 +#define CFG_GRETH_FIFO 8 +#elif defined CONFIG_GRETH_FIFO16 +#define CFG_GRETH_FIFO 16 +#elif defined CONFIG_GRETH_FIFO32 +#define CFG_GRETH_FIFO 32 +#elif defined CONFIG_GRETH_FIFO64 +#define CFG_GRETH_FIFO 64 +#else +#define CFG_GRETH_FIFO 8 +#endif + +#ifndef CONFIG_GRETH_FT +#define CONFIG_GRETH_FT 0 +#endif + +#ifndef CONFIG_GRETH_EDCLFT +#define CONFIG_GRETH_EDCLFT 0 +#endif +#ifndef CONFIG_UART1_ENABLE +#define CONFIG_UART1_ENABLE 0 +#endif + +#if defined CONFIG_UA1_FIFO1 +#define CFG_UA1_FIFO 1 +#elif defined CONFIG_UA1_FIFO2 +#define CFG_UA1_FIFO 2 +#elif defined CONFIG_UA1_FIFO4 +#define CFG_UA1_FIFO 4 +#elif defined CONFIG_UA1_FIFO8 +#define CFG_UA1_FIFO 8 +#elif defined CONFIG_UA1_FIFO16 +#define CFG_UA1_FIFO 16 +#elif defined CONFIG_UA1_FIFO32 +#define CFG_UA1_FIFO 32 +#else +#define CFG_UA1_FIFO 1 +#endif + +#ifndef CONFIG_IRQ3_ENABLE +#define CONFIG_IRQ3_ENABLE 0 +#endif +#ifndef CONFIG_IRQ3_NSEC +#define CONFIG_IRQ3_NSEC 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif +#ifndef CONFIG_GPT_ENABLE +#define CONFIG_GPT_ENABLE 0 +#endif + +#ifndef CONFIG_GPT_NTIM +#define CONFIG_GPT_NTIM 1 +#endif + +#ifndef CONFIG_GPT_SW +#define CONFIG_GPT_SW 8 +#endif + +#ifndef CONFIG_GPT_TW +#define CONFIG_GPT_TW 8 +#endif + +#ifndef CONFIG_GPT_IRQ +#define CONFIG_GPT_IRQ 8 +#endif + +#ifndef CONFIG_GPT_SEPIRQ +#define CONFIG_GPT_SEPIRQ 0 +#endif + +#ifndef CONFIG_GPT_WDOGEN +#define CONFIG_GPT_WDOGEN 0 +#endif + +#ifndef CONFIG_GPT_WDOG +#define CONFIG_GPT_WDOG 0 +#endif + +#ifndef CONFIG_GRGPIO_ENABLE +#define CONFIG_GRGPIO_ENABLE 0 +#endif +#ifndef CONFIG_GRGPIO_IMASK +#define CONFIG_GRGPIO_IMASK 0000 +#endif +#ifndef CONFIG_GRGPIO_WIDTH +#define CONFIG_GRGPIO_WIDTH 1 +#endif + +#ifndef CONFIG_I2C_ENABLE +#define CONFIG_I2C_ENABLE 0 +#endif +#ifndef CONFIG_VGA_ENABLE +#define CONFIG_VGA_ENABLE 0 +#endif +#ifndef CONFIG_SVGA_ENABLE +#define CONFIG_SVGA_ENABLE 0 +#endif +#ifndef CONFIG_KBD_ENABLE +#define CONFIG_KBD_ENABLE 0 +#endif + + +#ifndef CONFIG_SPIMCTRL +#define CONFIG_SPIMCTRL 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SDCARD +#define CONFIG_SPIMCTRL_SDCARD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_READCMD +#define CONFIG_SPIMCTRL_READCMD 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUMMYBYTE +#define CONFIG_SPIMCTRL_DUMMYBYTE 0 +#endif + +#ifndef CONFIG_SPIMCTRL_DUALOUTPUT +#define CONFIG_SPIMCTRL_DUALOUTPUT 0 +#endif + +#ifndef CONFIG_SPIMCTRL_SCALER +#define CONFIG_SPIMCTRL_SCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_ASCALER +#define CONFIG_SPIMCTRL_ASCALER 1 +#endif + +#ifndef CONFIG_SPIMCTRL_PWRUPCNT +#define CONFIG_SPIMCTRL_PWRUPCNT 0 +#endif + +#ifndef CONFIG_SPIMCTRL_OFFSET +#define CONFIG_SPIMCTRL_OFFSET 0 +#endif +#ifndef CONFIG_SPICTRL_ENABLE +#define CONFIG_SPICTRL_ENABLE 0 +#endif +#ifndef CONFIG_SPICTRL_NUM +#define CONFIG_SPICTRL_NUM 1 +#endif +#ifndef CONFIG_SPICTRL_SLVS +#define CONFIG_SPICTRL_SLVS 1 +#endif +#ifndef CONFIG_SPICTRL_FIFO +#define CONFIG_SPICTRL_FIFO 1 +#endif +#ifndef CONFIG_SPICTRL_SLVREG +#define CONFIG_SPICTRL_SLVREG 0 +#endif +#ifndef CONFIG_SPICTRL_ODMODE +#define CONFIG_SPICTRL_ODMODE 0 +#endif +#ifndef CONFIG_SPICTRL_AM +#define CONFIG_SPICTRL_AM 0 +#endif +#ifndef CONFIG_SPICTRL_ASEL +#define CONFIG_SPICTRL_ASEL 0 +#endif +#ifndef CONFIG_SPICTRL_TWEN +#define CONFIG_SPICTRL_TWEN 0 +#endif +#ifndef CONFIG_SPICTRL_MAXWLEN +#define CONFIG_SPICTRL_MAXWLEN 0 +#endif +#ifndef CONFIG_SPICTRL_SYNCRAM +#define CONFIG_SPICTRL_SYNCRAM 0 +#endif +#if defined(CONFIG_SPICTRL_DMRFT) +#define CONFIG_SPICTRL_FT 1 +#elif defined(CONFIG_SPICTRL_TMRFT) +#define CONFIG_SPICTRL_FT 2 +#else +#define CONFIG_SPICTRL_FT 0 +#endif + +#ifndef CONFIG_DEBUG_UART +#define CONFIG_DEBUG_UART 0 +#endif diff --git a/designs/leon3-xilinx-kc705/.config b/designs/leon3-xilinx-kc705/.config index 139670dc..19943067 100644 --- a/designs/leon3-xilinx-kc705/.config +++ b/designs/leon3-xilinx-kc705/.config @@ -168,7 +168,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -204,15 +203,15 @@ CONFIG_MMU_PAGE_4K=y # CONFIG_DSU_ENABLE=y CONFIG_DSU_ITRACE=y -CONFIG_DSU_ITRACESZ1=y +# CONFIG_DSU_ITRACESZ1 is not set # CONFIG_DSU_ITRACESZ2 is not set -# CONFIG_DSU_ITRACESZ4 is not set +CONFIG_DSU_ITRACESZ4=y # CONFIG_DSU_ITRACESZ8 is not set # CONFIG_DSU_ITRACESZ16 is not set CONFIG_DSU_ATRACE=y -CONFIG_DSU_ATRACESZ1=y +# CONFIG_DSU_ATRACESZ1 is not set # CONFIG_DSU_ATRACESZ2 is not set -# CONFIG_DSU_ATRACESZ4 is not set +CONFIG_DSU_ATRACESZ4=y # CONFIG_DSU_ATRACESZ8 is not set # CONFIG_DSU_ATRACESZ16 is not set @@ -224,7 +223,8 @@ CONFIG_DSU_ATRACESZ1=y # # VHDL debug settings # -# CONFIG_IU_DISAS is not set +CONFIG_IU_DISAS=y +# CONFIG_IU_DISAS_NET is not set CONFIG_DEBUG_PC32=y # @@ -255,7 +255,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000000 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-kc705/Makefile b/designs/leon3-xilinx-kc705/Makefile index 06d16f68..5b069825 100644 --- a/designs/leon3-xilinx-kc705/Makefile +++ b/designs/leon3-xilinx-kc705/Makefile @@ -19,33 +19,23 @@ TOP=leon3mp SIMTOP=testbench # Uncomment for Modelsim or change to specify your simulator -GRLIB_SIMULATOR=ModelSim +#GRLIB_SIMULATOR=ModelSim # Options used during compilation VCOMOPT=-explicit -O0 -VLOGOPT= +define+x1Gb +define+sg125 +define+x8 -suppress 2902 # GRLIB Options -VSIMOPT= -gdisas=1 +VSIMOPT= -gdisas=0 # GRETH options ifeq ($(CONFIG_GRETH_ENABLE),y) -VSIMOPT+= -gEXAMPLE_SIMULATION=1 -L secureip_ver -L xilinxcorelib_ver -L unisims_ver +VSIMOPT+= -L secureip_ver -L xilinxcorelib_ver -L unisims_ver endif # - MIG - -# -# DEBUG - Print debug information from external DDR3 memory (1/0) -# ifeq ($(CONFIG_MIG_SERIES7),y) -ifeq ("$(GRLIB_SIMULATOR)","ALDEC") -VSIMOPT+= -do "do riviera_preload_ddr3_dimm.do; run -all" -else -VSIMOPT+= -do "do preload_ddr3_dimm.do; run -all" -endif -VSIMOPT+= -t fs -novopt -gDEBUG=0 +VSIMOPT+= -t fs -novopt VSIMOPT+= -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl -GRLIB_XIL_Vivado_sim_verilog_define=x1Gb sg125 x8 ifndef CONFIG_MIG_SERIES_7_MODEL VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false else @@ -60,6 +50,13 @@ else VSIMOPT+=-novopt +notimingchecks endif +# Run simulation in batch mode +VSIMOPT+= -c + +# Simulation scripts +#VSIMOPT+= -do "run 1300us; do wave.do; run 200us" +VSIMOPT+= -do "run -all" + # Toplevel VSIMOPT+= $(SIMTOP) @@ -67,11 +64,10 @@ VSIMOPT+= $(SIMTOP) ### Testbench, design and libraries to compile and not to compile -VHDLSYNFILES= config.vhd ahbrom.vhd leon3mp.vhd ddr_dummy.vhd +VHDLSYNFILES= config.vhd ahbram_sim.vhd ahbrom.vhd leon3mp.vhd ddr_dummy.vhd VHDLSIMFILES=testbench.vhd -TECHLIBS = secureip unisim -EXTRA_SOFT = gen_hex_dim +TECHLIBS = secureip unisim LIBSKIP = pci pci/pcif core1553bbc core1553brm core1553brt gr1553 corePCIF \ tmtc openchip ihp spw gsi cypress hynix \ diff --git a/designs/leon3-xilinx-kc705/README.txt b/designs/leon3-xilinx-kc705/README.txt index dd37db6e..d16c0c3d 100644 --- a/designs/leon3-xilinx-kc705/README.txt +++ b/designs/leon3-xilinx-kc705/README.txt @@ -12,6 +12,9 @@ experimental. Currently the design configuration should be left as-is. Note: You must have both Vivado 2013.3 and Xilinx ISE 14.7 in your path for the make targets to work. +Note: Issues on the Ethernet interface have been observed when using +the GRETH 10/100 Mbit MAC with this design. + Simulation and synthesis ------------------------ @@ -44,8 +47,7 @@ To simulate using Aldec Riviera use the following make targets: make soft make riviera-launch -Synthesis will ONLY work with Vivado 2013.02 installed or newer, and -the XILINX variable properly set in the shell. To synthesize the design, do +To synthesize the design, do make vivado @@ -113,13 +115,9 @@ USE_MIG_INTERFACE_MODEL - Use MIG simulation model for faster simulation run tim disas - Enable processor disassembly to console -DEBUG - Enable extra debug information when using Micron DDR3 models - Design specifics ---------------- -* Synthesis should be done using Vivado 2013.02 or newer - * The DDR3 controller is implemented with Xilinx MIG Series7 2.0 and runs of the 200 MHz clock. The DDR3 memory runs at 400 MHz (DDR3-800). grmon-2.0.30-74 or later is needed to detect the diff --git a/designs/leon3-xilinx-kc705/ahbram_sim.vhd b/designs/leon3-xilinx-kc705/ahbram_sim.vhd new file mode 100644 index 00000000..f4f6fb62 --- /dev/null +++ b/designs/leon3-xilinx-kc705/ahbram_sim.vhd @@ -0,0 +1,361 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: ahbram +-- File: ahbram.vhd +-- Author: Jiri Gaisler - Gaisler Research +-- Modified: Jan Andersson - Aeroflex Gaisler +-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write. +-- Added Sx-Record read function +------------------------------------------------------------------------------ + +-- pragma translate_off + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; +use IEEE.Numeric_Std.all; + +library grlib; +use grlib.config_types.all; +use grlib.config.all; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +use grlib.stdio.all; + +library techmap; +use techmap.gencomp.all; + +entity ahbram_sim is + generic ( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#fff#; + tech : integer := DEFMEMTECH; + kbytes : integer := 1; + pipe : integer := 0; + maccsz : integer := AHBDW; + fname : string := "ram.dat" + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type + ); +end; + +architecture rtl of ahbram_sim is + +constant abits : integer := log2ext(kbytes) + 8 - maccsz/64; + +constant dw : integer := maccsz; + +constant hconfig : ahb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0), + 4 => ahb_membar(haddr, '1', '1', hmask), + others => zero32); + + +type reg_type is record + hwrite : std_ulogic; + hready : std_ulogic; + hsel : std_ulogic; + addr : std_logic_vector(abits-1+log2(dw/8) downto 0); + size : std_logic_vector(2 downto 0); + prdata : std_logic_vector((dw-1)*pipe downto 0); + pwrite : std_ulogic; + pready : std_ulogic; +end record; + +constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; +constant RES : reg_type := + (hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'), + size => (others => '0'), prdata => (others => '0'), pwrite => '0', + pready => '1'); + + +signal r, c : reg_type; +signal ramsel : std_logic_vector(dw/8-1 downto 0); +signal write : std_logic_vector(dw/8-1 downto 0); +signal ramaddr : std_logic_vector(abits-1 downto 0); +signal ramdata : std_logic_vector(dw-1 downto 0); +signal hwdata : std_logic_vector(dw-1 downto 0); + +type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range); +signal ram : ram_type; +signal read_address : std_logic_vector(ramaddr'range); + +begin + + comb : process (ahbsi, r, rst, ramdata) + variable bs : std_logic_vector(dw/8-1 downto 0); + variable v : reg_type; + variable haddr : std_logic_vector(abits-1 downto 0); + variable hrdata : std_logic_vector(dw-1 downto 0); + variable seldata : std_logic_vector(dw-1 downto 0); + variable raddr : std_logic_vector(3 downto 2); + variable adsel : std_logic; + begin + v := r; v.hready := '1'; bs := (others => '0'); + v.pready := r.hready; + if pipe=0 then + adsel := r.hwrite or not r.hready; + else + adsel := r.hwrite or r.pwrite; + v.hready := r.hready or not r.pwrite; + end if; + if adsel = '1' then + haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8)); + else + haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8)); + bs := (others => '0'); + end if; + raddr := (others => '0'); + + v.pwrite := '0'; + if pipe/=0 and (r.hready='1' or r.pwrite='0') then + v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0); + end if; + if ahbsi.hready = '1' then + if pipe=0 then + v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0); + end if; + v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1); + v.size := ahbsi.hsize(2 downto 0); + v.hwrite := ahbsi.hwrite and v.hsel; + if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then + v.hready := '0'; + v.pwrite := r.hwrite; + end if; + end if; + + if r.hwrite = '1' then + case r.size is + when HSIZE_BYTE => + bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1'; + when HSIZE_HWORD => + for i in 0 to dw/16-1 loop + if i = conv_integer(r.addr(log2(dw/16) downto 1)) then + bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1'); + end if; + end loop; -- i + when HSIZE_WORD => + if dw = 32 then bs := (others => '1'); + else + for i in 0 to dw/32-1 loop + if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then + bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1'); + end if; + end loop; -- i + end if; + when HSIZE_DWORD => + if dw = 32 then null; + elsif dw = 64 then bs := (others => '1'); + else + for i in 0 to dw/64-1 loop + if i = conv_integer(r.addr(3)) then + bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1'); + end if; + end loop; -- i + end if; + when HSIZE_4WORD => + if dw < 128 then null; + elsif dw = 128 then bs := (others => '1'); + else + for i in 0 to dw/64-1 loop + if i = conv_integer(r.addr(3)) then + bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1'); + end if; + end loop; -- i + end if; + when others => --HSIZE_8WORD + if dw < 256 then null; + else bs := (others => '1'); end if; + end case; + v.hready := not (v.hsel and not ahbsi.hwrite); + v.hwrite := v.hwrite and v.hready; + end if; + + -- Duplicate read data on word basis, unless CORE_ACDM is enabled + if CORE_ACDM = 0 then + if dw = 32 then + seldata := ramdata; + elsif dw = 64 then + if r.size = HSIZE_DWORD then seldata := ramdata; else + if r.addr(2) = '0' then + seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2); + else + seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); + end if; + seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0); + end if; + elsif dw = 128 then + if r.size = HSIZE_4WORD then + seldata := ramdata; + elsif r.size = HSIZE_DWORD then + if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2); + else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if; + seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0); + else + raddr := r.addr(3 downto 2); + case raddr is + when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4); + when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4); + when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4); + when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0); + end case; + seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) & + seldata(dw/4-1 downto 0) & + seldata(dw/4-1 downto 0); + end if; + else + seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size); + end if; + else + seldata := ramdata; + end if; + + if pipe = 0 then + v.prdata := (others => '0'); + hrdata := seldata; + else + v.prdata := seldata; + hrdata := r.prdata; + end if; + + + if (not RESET_ALL) and (rst = '0') then + v.hwrite := RES.hwrite; v.hready := RES.hready; + end if; + write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop; + ramaddr <= haddr; c <= v; + + ahbso.hrdata <= ahbdrivedata(hrdata); + ahbso.hready <= r.hready; + + end process; + + ahbso.hresp <= "00"; + ahbso.hsplit <= (others => '0'); + ahbso.hirq <= (others => '0'); + ahbso.hconfig <= hconfig; + ahbso.hindex <= hindex; + + -- Select correct write data + hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2), + conv_std_logic_vector(log2(dw/8), 3)); + +-- aram : syncrambw generic map (tech, abits, dw, scantest) port map ( +-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin); + RamProc: process(clk) is + + variable L1 : line; + variable FIRST : boolean := true; + variable ADR : std_logic_vector(19 downto 0); + variable BUF : std_logic_vector(31 downto 0); + variable CH : character; + variable ai : integer := 0; + variable len : integer := 0; + file TCF : text open read_mode is fname; + variable rectype : std_logic_vector(3 downto 0); + variable recaddr : std_logic_vector(31 downto 0); + variable reclen : std_logic_vector(7 downto 0); + variable recdata : std_logic_vector(0 to 16*8-1); + + begin + if rising_edge(clk) then + if conv_integer(write) > 0 then + for i in 0 to dw/8-1 loop + if (write(i) = '1') then + ram(to_integer(unsigned(ramaddr)))(i*8+7 downto 0) <= hwdata(i*8+7 downto 0); + end if; + end loop; + end if; + read_address <= ramaddr; + end if; + + if (rst = '0') and (FIRST = true) then + ram <= (others => (others => '0')); + + L1:= new string'(""); + while not endfile(TCF) loop + readline(TCF,L1); + if (L1'length /= 0) then --' + while (not (L1'length=0)) and (L1(L1'left) = ' ') loop + std.textio.read(L1,CH); + end loop; + + if L1'length > 0 then --' + read(L1, ch); + if (ch = 'S') or (ch = 's') then + hread(L1, rectype); + hread(L1, reclen); + len := conv_integer(reclen)-1; + recaddr := (others => '0'); + case rectype is + when "0001" => + hread(L1, recaddr(15 downto 0)); + when "0010" => + hread(L1, recaddr(23 downto 0)); + when "0011" => + hread(L1, recaddr); + when others => next; + end case; + hread(L1, recdata); + + recaddr(31 downto abits+2) := (others => '0'); + ai := conv_integer(recaddr)/4; + for i in 0 to 3 loop + ram(ai+i) <= recdata((i*32) to (i*32+31)); + end loop; + + if ai = 0 then + ai := 1; + end if; + end if; + end if; + end if; + end loop; + + FIRST := false; + + end if; + + end process RamProc; + + ramdata <= ram(to_integer(unsigned(read_address))); + + reg : process (clk) + begin + if rising_edge(clk) then + r <= c; + if RESET_ALL and rst = '0' then + r <= RES; + end if; + end if; + end process; + + bootmsg : report_version + generic map ("ahbram" & tost(hindex) & + ": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes"); +end; + +-- pragma translate_on diff --git a/designs/leon3-xilinx-kc705/config.h b/designs/leon3-xilinx-kc705/config.h index 920f8d86..4510aa2f 100644 --- a/designs/leon3-xilinx-kc705/config.h +++ b/designs/leon3-xilinx-kc705/config.h @@ -163,7 +163,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -197,15 +196,15 @@ */ #define CONFIG_DSU_ENABLE 1 #define CONFIG_DSU_ITRACE 1 -#define CONFIG_DSU_ITRACESZ1 1 +#undef CONFIG_DSU_ITRACESZ1 #undef CONFIG_DSU_ITRACESZ2 -#undef CONFIG_DSU_ITRACESZ4 +#define CONFIG_DSU_ITRACESZ4 1 #undef CONFIG_DSU_ITRACESZ8 #undef CONFIG_DSU_ITRACESZ16 #define CONFIG_DSU_ATRACE 1 -#define CONFIG_DSU_ATRACESZ1 1 +#undef CONFIG_DSU_ATRACESZ1 #undef CONFIG_DSU_ATRACESZ2 -#undef CONFIG_DSU_ATRACESZ4 +#define CONFIG_DSU_ATRACESZ4 1 #undef CONFIG_DSU_ATRACESZ8 #undef CONFIG_DSU_ATRACESZ16 /* @@ -215,7 +214,8 @@ /* * VHDL debug settings */ -#undef CONFIG_IU_DISAS +#define CONFIG_IU_DISAS 1 +#undef CONFIG_IU_DISAS_NET #define CONFIG_DEBUG_PC32 1 /* * AMBA configuration @@ -244,7 +244,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000000 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-kc705/config.help b/designs/leon3-xilinx-kc705/config.help index fd2babca..c114477f 100644 --- a/designs/leon3-xilinx-kc705/config.help +++ b/designs/leon3-xilinx-kc705/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-kc705/config.vhd b/designs/leon3-xilinx-kc705/config.vhd index 17bc2064..2ac3456e 100644 --- a/designs/leon3-xilinx-kc705/config.vhd +++ b/designs/leon3-xilinx-kc705/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -71,8 +71,8 @@ package config is constant CFG_TLB_REP : integer := 0; constant CFG_MMU_PAGE : integer := 0; constant CFG_DSU : integer := 1; - constant CFG_ITBSZ : integer := 1; - constant CFG_ATBSZ : integer := 1; + constant CFG_ITBSZ : integer := 4; + constant CFG_ATBSZ : integer := 4; constant CFG_LEON3FT_EN : integer := 0; constant CFG_IUFT_EN : integer := 0; constant CFG_FPUFT_EN : integer := 0; @@ -80,7 +80,7 @@ package config is constant CFG_CACHE_FT_EN : integer := 0; constant CFG_CACHE_ERRINJ : integer := 0; constant CFG_LEON3_NETLIST: integer := 0; - constant CFG_DISAS : integer := 0 + 0; + constant CFG_DISAS : integer := 1 + 0; constant CFG_PCLOW : integer := 0; -- AMBA settings constant CFG_DEFMST : integer := (0); diff --git a/designs/leon3-xilinx-kc705/config.vhd.h b/designs/leon3-xilinx-kc705/config.vhd.h index 5517bad0..60fcd11e 100644 --- a/designs/leon3-xilinx-kc705/config.vhd.h +++ b/designs/leon3-xilinx-kc705/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-kc705/lconfig.tk b/designs/leon3-xilinx-kc705/lconfig.tk index 79447933..e587d7a9 100755 --- a/designs/leon3-xilinx-kc705/lconfig.tk +++ b/designs/leon3-xilinx-kc705/lconfig.tk @@ -2092,24 +2092,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2181,20 +2180,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2327,9 +2323,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3210,7 +3203,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3260,12 +3253,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3296,12 +3288,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5241,7 +5232,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5447,6 +5437,7 @@ set CONFIG_LEON3FT_PRESENT 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_MODULES 4 proc writeconfig {file1 file2} { set cfg [open $file1 w] @@ -5891,7 +5882,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6035,10 +6025,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6114,6 +6103,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-kc705/leon3mp.vhd b/designs/leon3-xilinx-kc705/leon3mp.vhd index 7a2475c2..8c61fc0b 100644 --- a/designs/leon3-xilinx-kc705/leon3mp.vhd +++ b/designs/leon3-xilinx-kc705/leon3mp.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -176,6 +176,27 @@ component ddr_dummy ); end component ; +-- pragma translate_off +component ahbram_sim + generic ( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#fff#; + tech : integer := DEFMEMTECH; + kbytes : integer := 1; + pipe : integer := 0; + maccsz : integer := AHBDW; + fname : string := "ram.dat" + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type + ); +end component ; +-- pragma translate_on + component IBUFDS_GTE2 port ( O : out std_ulogic; @@ -244,7 +265,8 @@ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal vahbmo : ahb_mst_out_type; signal ui_clk : std_ulogic; -signal clkm, rstn, rstraw, sdclkl : std_ulogic; +signal clkm : std_ulogic := '0'; +signal rstn, rstraw, sdclkl : std_ulogic; signal clk_200 : std_ulogic; signal clk25, clk40, clk65 : std_ulogic; @@ -527,6 +549,7 @@ begin ---------------------------------------------------------------------- mig_gen : if (CFG_MIG_SERIES7 = 1) generate + gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate ddrc : ahb2mig_series7 generic map( hindex => 4, haddr => 16#400#, hmask => 16#C00#, pindex => 4, paddr => 4, @@ -566,6 +589,56 @@ begin clkgenmigref0 : clkgen generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000) port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open); + end generate gen_mig; + + gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate + -- pragma translate_off + + mig_ahbram : ahbram_sim + generic map ( + hindex => 4, + haddr => 16#400#, + hmask => 16#C00#, + tech => 0, + kbytes => 1000, + pipe => 0, + maccsz => AHBDW, + fname => "ram.srec" + ) + port map( + rst => rstn, + clk => clkm, + ahbsi => ahbsi, + ahbso => ahbso(4) + ); + + ddr3_dq <= (others => 'Z'); + ddr3_dqs_p <= (others => 'Z'); + ddr3_dqs_n <= (others => 'Z'); + ddr3_addr <= (others => '0'); + ddr3_ba <= (others => '0'); + ddr3_ras_n <= '0'; + ddr3_cas_n <= '0'; + ddr3_we_n <= '0'; + ddr3_reset_n <= '1'; + ddr3_ck_p <= (others => '0'); + ddr3_ck_n <= (others => '0'); + ddr3_cke <= (others => '0'); + ddr3_cs_n <= (others => '0'); + ddr3_dm <= (others => '0'); + ddr3_odt <= (others => '0'); + + --calib_done : out std_logic; + calib_done <= '1'; + + --ui_clk : out std_logic; + clkm <= not clkm after 5.0 ns; + + --ui_clk_sync_rst : out std_logic + -- n/a + -- pragma translate_on + + end generate gen_mig_model; end generate; @@ -615,7 +688,7 @@ begin hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 14, memtech => memtech, mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO, - nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7, + nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G, ramdebug => 2) @@ -701,8 +774,10 @@ begin end process; -- RGMII Interface - rgmii0 : rgmii generic map (11, 16#010# , 16#ff0#, fabtech, CFG_GRETH1G, 1, 1, 1) - port map (rstn, gtx_clk90, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11)); + rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech, + gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1, + pirq => 11, use90degtxclk => 1) + port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11)); egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1) port map (phy_gtxclk, rgmiio.tx_clk); @@ -747,7 +822,7 @@ begin clkgen_gtrefclk : clkgen generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000) - port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, gtx_clk90, io_ref, open, open, cgi2, cgo2, open, open, open); + port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open); end generate; @@ -761,7 +836,7 @@ begin ---------------------------------------------------------------------- --i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master - i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 11, filter => 9) + i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 9, filter => 9) port map (rstn, clkm, apbi, apbo(9), i2ci, i2co); i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v) diff --git a/designs/leon3-xilinx-kc705/mig_interface_model.v b/designs/leon3-xilinx-kc705/mig_interface_model.v index 9496c788..873977b9 100644 --- a/designs/leon3-xilinx-kc705/mig_interface_model.v +++ b/designs/leon3-xilinx-kc705/mig_interface_model.v @@ -4,20 +4,6 @@ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2012, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Entity: mig_interface_model -- File: mig_interface_model.v diff --git a/designs/leon3-xilinx-kc705/preload_ddr3_dimm.do b/designs/leon3-xilinx-kc705/preload_ddr3_dimm.do deleted file mode 100644 index c4ab1091..00000000 --- a/designs/leon3-xilinx-kc705/preload_ddr3_dimm.do +++ /dev/null @@ -1,52 +0,0 @@ -# Procedure to load memory from file -proc reload_mem {} { - # Load memory with system test and display memory - if {[examine /testbench/led(3)] == 1} { - if {[examine sim:/config@work/CFG_MIG_SERIES7] == 1} { - echo "Loading DDR3 memory with System Test" - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == FALSE} { - mem load -startaddress 0 -format hex -infile sdram_dimm1.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(0)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm2.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(1)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm3.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(2)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm4.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(3)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm5.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(4)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm6.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(5)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm7.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(6)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm8.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(7)/u1/memory - - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(0)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(1)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(2)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(3)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(4)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(5)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(6)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(7)/u1/address - - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(0)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(1)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(2)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(3)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(4)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(5)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(6)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(7)/u1/memory_used 1111111111111111 - } - - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == TRUE} { - echo "MIG Model found" - mem load -startaddress 0 -format hex -infile sdram_dimm_merge.hex -filltype value -filldata 1'b0 sim:/testbench/cpu/mig_gen/ddrc/gen_mig_model/MCB_model_inst/Mem - } - - #do wave.do - } - } -} - -set init_path /testbench/led(3); - -when -label when1 "$init_path'event and $init_path ='1'" { - reload_mem -} - -#run 2 ms diff --git a/designs/leon3-xilinx-kc705/ram.srec b/designs/leon3-xilinx-kc705/ram.srec index a896a74b..a9e939c2 100755 --- a/designs/leon3-xilinx-kc705/ram.srec +++ b/designs/leon3-xilinx-kc705/ram.srec @@ -1,11 +1,11 @@ S00B000072616D2E73726563D9 -S31540000000881000000910006C81C1234401000000E3 +S31540000000881000000910007E81C1209C010000007C S31540000010A1480000A75000001080203EAC102001EF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006C81C5229801000000DB -S31540000050A14800002910006981C523500100000015 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100644 index 6206a2bb..00000000 --- a/designs/leon3-xilinx-kc705/riviera_preload_ddr3_dimm.do +++ /dev/null @@ -1,55 +0,0 @@ -# Procedure to load memory from file -proc reload_mem {} { - # Load memory with system test and display memory - if {[examine /testbench/led(3)] == 1} { - if {[examine sim:/work.config/CFG_MIG_SERIES7] == 1} { - echo "Loading DDR3 memory with System Test" - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == false} { - mem load -startaddress 0 -format hex -infile sdram_dimm1.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__0/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm2.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__1/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm3.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__2/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm4.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__3/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm5.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__4/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm6.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__5/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm7.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__6/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm8.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__7/u1/memory - - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__0/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__1/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__2/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__3/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__4/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__5/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__6/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__7/u1/address - - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__0/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__1/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__2/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__3/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__4/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__5/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__6/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__7/u1/memory_used 1111111111111111 - } - - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == true} { - echo "MIG Model found" - mem load -startaddress 0 -endaddress 65535 -format hex -infile sdram_dimm_merge.hex -filltype value -filldata 1'b0 sim:/testbench/cpu/mig_gen/ddrc/gen_mig_model/MCB_model_inst/Mem - } - - #do wave.do - } - } -} - -set init_path /testbench/led(3); - -when -label when1 {$init_path and $init_path =1} { - echo "MIG Init Complete" - reload_mem -} - -#do wave.awc - -#run 2 ms \ No newline at end of file diff --git a/designs/leon3-xilinx-kc705/sgmii_kc705.vhd b/designs/leon3-xilinx-kc705/sgmii_kc705.vhd index ee72c584..9d5fffb0 100644 --- a/designs/leon3-xilinx-kc705/sgmii_kc705.vhd +++ b/designs/leon3-xilinx-kc705/sgmii_kc705.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-kc705/systest.c b/designs/leon3-xilinx-kc705/systest.c index 5710f893..fc7ee878 100644 --- a/designs/leon3-xilinx-kc705/systest.c +++ b/designs/leon3-xilinx-kc705/systest.c @@ -6,28 +6,28 @@ main() /* variables and pointers to test RGMII interface */ int i; - unsigned long rgmiistatus; - unsigned long rgmiibuf[256]; - unsigned long* rgmiistatusp = (unsigned long*) 0x80001000; - unsigned long* rgmiiop = (unsigned long*) 0x80001400; - unsigned long* rgmiiip = (unsigned long*) 0x80001800; + volatile unsigned long rgmiistatus; + volatile unsigned long rgmiibuf[256]; + volatile unsigned long* rgmiistatusp = (unsigned long*) 0x80001000; + volatile unsigned long* rgmiiop = (unsigned long*) 0x80001400; + volatile unsigned long* rgmiiip = (unsigned long*) 0x80001800; report_start(); base_test(); -// greth_test(0x800c0000); -// -// /* Read RGMII status and buffers */ -// rgmiistatus = *rgmiistatusp; -// -// for (i = 0; i < 256; i++) { -// rgmiibuf[i] = *(rgmiiop + i); -// } -// -// for (i = 0; i < 256; i++) { -// rgmiibuf[i] = *(rgmiiip + i); -// } + //greth_test(0x800c0000); + + /* Read RGMII status and buffers */ + rgmiistatus = *rgmiistatusp; + + for (i = 0; i < 16; i++) { + rgmiibuf[i] = *(rgmiiop + i); + } + + for (i = 0; i < 16; i++) { + rgmiibuf[i] = *(rgmiiip + i); + } report_end(); } diff --git a/designs/leon3-xilinx-kc705/testbench.vhd b/designs/leon3-xilinx-kc705/testbench.vhd index 222d04e0..ffa108a9 100644 --- a/designs/leon3-xilinx-kc705/testbench.vhd +++ b/designs/leon3-xilinx-kc705/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -31,8 +31,6 @@ library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; -library micron; -use micron.all; library techmap; use techmap.gencomp.all; use work.debug.all; @@ -70,8 +68,7 @@ constant SIMULATION : string := "TRUE"; constant promfile : string := "prom.srec"; -- rom contents -constant sramfile : string := "ram.srec"; -- ram contents -constant sdramfile : string := "ram.srec"; -- sdram contents +constant ramfile : string := "ram.srec"; -- ram contents signal clk : std_logic := '0'; signal Rst : std_logic := '0'; @@ -245,35 +242,6 @@ component leon3mp is ); end component; -component ddr3_model - generic( - ADDR_BITS : integer := 14; - BA_BITS : integer := 3; - DM_BITS : integer := 1; - DQ_BITS : integer := 8; - DQS_BITS : integer := 1 - ); - port( - rst_n : in std_logic; - ck : in std_logic; - ck_n : in std_logic; - cke : in std_logic; - cs_n : in std_logic; - ras_n : in std_logic; - cas_n : in std_logic; - we_n : in std_logic; - dm_tdqs : inout std_logic; - ba : in std_logic_vector(2 downto 0); - addr : in std_logic_vector(13 downto 0); - dq : inout std_logic_vector(7 downto 0); - dqs : inout std_logic; - dqs_n : inout std_logic; - tdqs_n : out std_logic_vector(0 to 0); - odt : in std_logic - ); -end component; - - begin -- clock and reset @@ -362,36 +330,38 @@ begin -- Memory Models instantiations gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate ddr3mem : if (CFG_MIG_SERIES7 = 1) generate - gen_mem: for i in 0 to 7 generate - - - u1: ddr3_model - generic map( - ADDR_BITS => 14, - BA_BITS => 3, - DM_BITS => 1, - DQ_BITS => 8, - DQS_BITS => 1 - ) - port map ( - rst_n => ddr3_reset_n, - ck => ddr3_ck_p(0), - ck_n => ddr3_ck_n(0), - cke => ddr3_cke(0), - cs_n => ddr3_cs_n(0), - ras_n => ddr3_ras_n, - cas_n => ddr3_cas_n, - we_n => ddr3_we_n, - dm_tdqs => ddr3_dm(i), - ba => ddr3_ba, - addr => ddr3_addr, - dq => ddr3_dq((8*i+7) downto (8*i)), - dqs => ddr3_dqs_p(i), - dqs_n => ddr3_dqs_n(i), - tdqs_n => open, - odt => ddr3_odt(0) - ); - end generate gen_mem; + u1 : ddr3ram + generic map ( + width => 64, + abits => 14, + colbits => 10, + rowbits => 10, + implbanks => 1, + fname => ramfile, + lddelay => (0 ns), + ldguard => 1, + speedbin => 9, --DDR3-1600K + density => 3, + pagesize => 1, + changeendian => 8) + port map ( + ck => ddr3_ck_p(0), + ckn => ddr3_ck_n(0), + cke => ddr3_cke(0), + csn => ddr3_cs_n(0), + odt => ddr3_odt(0), + rasn => ddr3_ras_n, + casn => ddr3_cas_n, + wen => ddr3_we_n, + dm => ddr3_dm, + ba => ddr3_ba, + a => ddr3_addr, + resetn => ddr3_reset_n, + dq => ddr3_dq, + dqs => ddr3_dqs_p, + dqsn => ddr3_dqs_n, + doload => led(3) + ); end generate ddr3mem; end generate gen_mem_model; @@ -409,7 +379,24 @@ begin phy_mdio <= 'H'; phy_int <= '0'; p0: phy - generic map (address => 7) + generic map ( + address => 7, + extended_regs => 1, + aneg => 1, + base100_t4 => 1, + base100_x_fd => 1, + base100_x_hd => 1, + fd_10 => 1, + hd_10 => 1, + base100_t2_fd => 1, + base100_t2_hd => 1, + base1000_x_fd => 1, + base1000_x_hd => 1, + base1000_t_fd => 1, + base1000_t_hd => 1, + rmii => 0, + rgmii => 1 + ) port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd, phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd, phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk); diff --git a/designs/leon3-xilinx-kc705/tkconfig.h b/designs/leon3-xilinx-kc705/tkconfig.h index 88886af0..3402ae11 100644 --- a/designs/leon3-xilinx-kc705/tkconfig.h +++ b/designs/leon3-xilinx-kc705/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-ml403/.config b/designs/leon3-xilinx-ml403/.config index 65d7f9f2..af3b6284 100644 --- a/designs/leon3-xilinx-ml403/.config +++ b/designs/leon3-xilinx-ml403/.config @@ -161,7 +161,6 @@ CONFIG_DCACHE_ALGOLRR=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 # CONFIG_DCACHE_LRAM is not set diff --git a/designs/leon3-xilinx-ml403/config.h b/designs/leon3-xilinx-ml403/config.h index 8eab77b4..09795e63 100644 --- a/designs/leon3-xilinx-ml403/config.h +++ b/designs/leon3-xilinx-ml403/config.h @@ -156,7 +156,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 #undef CONFIG_DCACHE_LRAM diff --git a/designs/leon3-xilinx-ml403/config.help b/designs/leon3-xilinx-ml403/config.help index a0e9426d..34fd050e 100644 --- a/designs/leon3-xilinx-ml403/config.help +++ b/designs/leon3-xilinx-ml403/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-ml403/config.vhd b/designs/leon3-xilinx-ml403/config.vhd index c4dacebf..4187400b 100644 --- a/designs/leon3-xilinx-ml403/config.vhd +++ b/designs/leon3-xilinx-ml403/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 1; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-ml403/config.vhd.h b/designs/leon3-xilinx-ml403/config.vhd.h index fa62d520..423b834d 100644 --- a/designs/leon3-xilinx-ml403/config.vhd.h +++ b/designs/leon3-xilinx-ml403/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-ml403/lconfig.tk b/designs/leon3-xilinx-ml403/lconfig.tk index c2c19c3a..eba4627d 100755 --- a/designs/leon3-xilinx-ml403/lconfig.tk +++ b/designs/leon3-xilinx-ml403/lconfig.tk @@ -2080,24 +2080,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2169,20 +2168,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2315,9 +2311,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3128,7 +3121,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3178,12 +3171,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3214,12 +3206,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4741,7 +4732,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4904,6 +4894,7 @@ set CONFIG_SVGA_ENABLE 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5360,7 +5351,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5483,10 +5473,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5568,6 +5557,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-ml403/leon3mp.vhd b/designs/leon3-xilinx-ml403/leon3mp.vhd index ea381488..7e8fd47d 100644 --- a/designs/leon3-xilinx-ml403/leon3mp.vhd +++ b/designs/leon3-xilinx-ml403/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml403/testbench.vhd b/designs/leon3-xilinx-ml403/testbench.vhd index afc6e174..2ade1862 100644 --- a/designs/leon3-xilinx-ml403/testbench.vhd +++ b/designs/leon3-xilinx-ml403/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -177,7 +177,7 @@ begin datazz <= "HHHH"; - u0 : cy7c1354 generic map (fname => sramfile) + u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns) port map( Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data, Addr => sram_flash_addr(17 downto 0), Mode => sram_mode, @@ -192,21 +192,29 @@ begin sram_zz <= '0'; - u1 : mt46v16m16 - generic map (index => 1, fname => sdramfile, bbits => 32) - PORT MAP( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); - - u2 : mt46v16m16 - generic map (index => 0, fname => sdramfile, bbits => 32) - PORT MAP( - Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(3 downto 2)); + -- u1 : mt46v16m16 + -- generic map (index => 1, fname => sdramfile, bbits => 32) + -- PORT MAP( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); + + -- u2 : mt46v16m16 + -- generic map (index => 0, fname => sdramfile, bbits => 32) + -- PORT MAP( + -- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(3 downto 2)); + + ddr0 : ddrram + generic map(width => 32, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 2) + port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); prom0 : for i in 0 to (romwidth/8)-1 generate sr0 : sram generic map (index => i, abits => romdepth, fname => promfile) diff --git a/designs/leon3-xilinx-ml403/tkconfig.h b/designs/leon3-xilinx-ml403/tkconfig.h index c6f545f6..5f5ae86a 100644 --- a/designs/leon3-xilinx-ml403/tkconfig.h +++ b/designs/leon3-xilinx-ml403/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-ml40x/.config b/designs/leon3-xilinx-ml40x/.config index e176f9ba..115baf82 100644 --- a/designs/leon3-xilinx-ml40x/.config +++ b/designs/leon3-xilinx-ml40x/.config @@ -173,7 +173,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -259,7 +258,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=00002F # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-ml40x/config.h b/designs/leon3-xilinx-ml40x/config.h index 8b361d74..5e303192 100644 --- a/designs/leon3-xilinx-ml40x/config.h +++ b/designs/leon3-xilinx-ml40x/config.h @@ -167,7 +167,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -247,7 +246,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 00002F #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-ml40x/config.help b/designs/leon3-xilinx-ml40x/config.help index bb7bdf10..960dd587 100644 --- a/designs/leon3-xilinx-ml40x/config.help +++ b/designs/leon3-xilinx-ml40x/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-ml40x/config.vhd b/designs/leon3-xilinx-ml40x/config.vhd index aca7aa72..d11ec59b 100644 --- a/designs/leon3-xilinx-ml40x/config.vhd +++ b/designs/leon3-xilinx-ml40x/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-ml40x/config.vhd.h b/designs/leon3-xilinx-ml40x/config.vhd.h index 692a6c9c..ef4b8a97 100644 --- a/designs/leon3-xilinx-ml40x/config.vhd.h +++ b/designs/leon3-xilinx-ml40x/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-ml40x/lconfig.tk b/designs/leon3-xilinx-ml40x/lconfig.tk index 6d1edfc3..7b2186f0 100755 --- a/designs/leon3-xilinx-ml40x/lconfig.tk +++ b/designs/leon3-xilinx-ml40x/lconfig.tk @@ -2188,24 +2188,23 @@ proc menu7 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 7 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 7 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 7 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 7 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 7 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 7 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 7 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 7 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 7 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 7 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 7 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 7 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 7 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2277,20 +2276,17 @@ proc update_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu7.config.f.x15 normal {n l y}} else {configure_entry .menu7.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x17 normal {n l y}} else {configure_entry .menu7.config.f.x17 disabled {y n l}} + configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x18.l configure -state normal; } else {.menu7.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x17.l configure -state normal; } else {.menu7.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu7.config.f.x19 normal {n l y}} else {configure_entry .menu7.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x20 normal {x l}} else {configure_entry .menu7.config.f.x20 disabled {x l}} + configure_entry .menu7.config.f.x18 normal {n l y}} else {configure_entry .menu7.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x19 normal {x l}} else {configure_entry .menu7.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x21.l configure -state normal; } else {.menu7.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x20.l configure -state normal; } else {.menu7.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x20.l configure -state disabled} } @@ -2423,9 +2419,6 @@ proc update_define_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3236,7 +3229,7 @@ proc menu13 {w title} { hex $w.config.f 13 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 13 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 13 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3286,12 +3279,11 @@ proc update_menu13 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x6.l configure -state normal; } else {.menu13.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x7.l configure -state normal; } else {.menu13.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu13.config.f.x8 normal {n l y}} else {configure_entry .menu13.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu13.config.f.x9 normal {n l y}} else {configure_entry .menu13.config.f.x9 disabled {y n l}} } @@ -3322,12 +3314,11 @@ proc update_define_menu13 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4951,7 +4942,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5115,6 +5105,7 @@ set CONFIG_GRACECTRL 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5576,7 +5567,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5699,10 +5689,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5784,6 +5773,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_31 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-ml40x/leon3mp.vhd b/designs/leon3-xilinx-ml40x/leon3mp.vhd index 864ec14c..d4fa4f16 100644 --- a/designs/leon3-xilinx-ml40x/leon3mp.vhd +++ b/designs/leon3-xilinx-ml40x/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml40x/testbench.vhd b/designs/leon3-xilinx-ml40x/testbench.vhd index 9535ea91..343844a9 100644 --- a/designs/leon3-xilinx-ml40x/testbench.vhd +++ b/designs/leon3-xilinx-ml40x/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -189,7 +189,7 @@ begin datazz <= "HHHH"; - u0 : cy7c1354 generic map (fname => sramfile) + u0 : cy7c1354 generic map (fname => sramfile, tWEH => 0.0 ns, tAH => 0.0 ns) port map( Dq(35 downto 32) => datazz, Dq(31 downto 0) => sram_flash_data, Addr => sram_flash_addr(17 downto 0), Mode => sram_mode, @@ -204,21 +204,29 @@ begin sram_zz <= '0'; - u1 : mt46v16m16 - generic map (index => 1, fname => sdramfile, bbits => 32) - PORT MAP( - Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(1 downto 0)); + -- u1 : mt46v16m16 + -- generic map (index => 1, fname => sdramfile, bbits => 32) + -- PORT MAP( + -- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(1 downto 0)); - u2 : mt46v16m16 - generic map (index => 0, fname => sdramfile, bbits => 32) - PORT MAP( - Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0), - Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, - Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, - Dm => ddr_dm(3 downto 2)); + -- u2 : mt46v16m16 + -- generic map (index => 0, fname => sdramfile, bbits => 32) + -- PORT MAP( + -- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0), + -- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke, + -- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web, + -- Dm => ddr_dm(3 downto 2)); + + ddr0 : ddrram + generic map(width => 32, abits => 13, colbits => 9, rowbits => 13, + implbanks => 1, fname => sdramfile, density => 2) + port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb, + rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, + dqs => ddr_dqs); prom0 : for i in 0 to (romwidth/8)-1 generate sr0 : sram generic map (index => i, abits => romdepth, fname => promfile) diff --git a/designs/leon3-xilinx-ml40x/tkconfig.h b/designs/leon3-xilinx-ml40x/tkconfig.h index dd1f68ef..80313522 100644 --- a/designs/leon3-xilinx-ml40x/tkconfig.h +++ b/designs/leon3-xilinx-ml40x/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-ml501/.config b/designs/leon3-xilinx-ml501/.config index b878a564..fded0a8e 100644 --- a/designs/leon3-xilinx-ml501/.config +++ b/designs/leon3-xilinx-ml501/.config @@ -167,7 +167,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -253,7 +252,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000030 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-ml501/ahb2mig_ml50x.vhd b/designs/leon3-xilinx-ml501/ahb2mig_ml50x.vhd index fc328732..a0c2e95f 100644 --- a/designs/leon3-xilinx-ml501/ahb2mig_ml50x.vhd +++ b/designs/leon3-xilinx-ml501/ahb2mig_ml50x.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml501/config.h b/designs/leon3-xilinx-ml501/config.h index 2feb797a..68bba22e 100644 --- a/designs/leon3-xilinx-ml501/config.h +++ b/designs/leon3-xilinx-ml501/config.h @@ -162,7 +162,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -242,7 +241,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000030 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-ml501/config.help b/designs/leon3-xilinx-ml501/config.help index 278b8deb..955da70b 100644 --- a/designs/leon3-xilinx-ml501/config.help +++ b/designs/leon3-xilinx-ml501/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-ml501/config.vhd b/designs/leon3-xilinx-ml501/config.vhd index dfc2aac1..499e085d 100644 --- a/designs/leon3-xilinx-ml501/config.vhd +++ b/designs/leon3-xilinx-ml501/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-ml501/config.vhd.h b/designs/leon3-xilinx-ml501/config.vhd.h index 5a39fe49..06233b7c 100644 --- a/designs/leon3-xilinx-ml501/config.vhd.h +++ b/designs/leon3-xilinx-ml501/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-ml501/lconfig.tk b/designs/leon3-xilinx-ml501/lconfig.tk index cb615b0d..dc390626 100755 --- a/designs/leon3-xilinx-ml501/lconfig.tk +++ b/designs/leon3-xilinx-ml501/lconfig.tk @@ -2081,24 +2081,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2170,20 +2169,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2316,9 +2312,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3129,7 +3122,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3179,12 +3172,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3215,12 +3207,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4938,7 +4929,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5123,6 +5113,7 @@ set CONFIG_GRACECTRL 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5579,7 +5570,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5702,10 +5692,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5821,6 +5810,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-ml501/leon3mp.vhd b/designs/leon3-xilinx-ml501/leon3mp.vhd index af98b2eb..135a6fc4 100644 --- a/designs/leon3-xilinx-ml501/leon3mp.vhd +++ b/designs/leon3-xilinx-ml501/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml501/svga2ch7301c.vhd b/designs/leon3-xilinx-ml501/svga2ch7301c.vhd index e0fa9171..02906add 100644 --- a/designs/leon3-xilinx-ml501/svga2ch7301c.vhd +++ b/designs/leon3-xilinx-ml501/svga2ch7301c.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml501/testbench.vhd b/designs/leon3-xilinx-ml501/testbench.vhd index 4697c63e..3c63b417 100644 --- a/designs/leon3-xilinx-ml501/testbench.vhd +++ b/designs/leon3-xilinx-ml501/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -32,8 +32,6 @@ library micron; use micron.components.all; library cypress; use cypress.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.ml50x.all; @@ -203,17 +201,25 @@ begin -- end generate; ddr2ranks: for j in 0 to CS_NUM-1 generate - ddr2chips: for i in 0 to 3 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2) - port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2), - LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1), - UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2), - WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(j), - BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(j), - CLK => ddr_clk(j), CLKB => ddr_clkb(j), UDM => ddr_dm(i*2+1)); - end generate; + -- ddr2chips: for i in 0 to 3 generate + -- u1 : HY5PS121621F + -- generic map (TimingCheckFlag => true, PUSCheckFlag => false, + -- index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2) + -- port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2), + -- LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1), + -- UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2), + -- WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(j), + -- BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(j), + -- CLK => ddr_clk(j), CLKB => ddr_clkb(j), UDM => ddr_dm(i*2+1)); + -- end generate; + ddr0 : ddr2ram + generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>0, density => 2, + lddelay => 100 us * CFG_MIG_DDR2) + port map (ck => ddr_clk(j), ckn => ddr_clkb(j), cke => ddr_cke(j), csn => ddr_csb(j), + odt => ddr_odt(j), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2, + dqs => ddr_dqsp, dqsn =>ddr_dqsn); end generate; nodqdel : if (CFG_MIG_DDR2 = 1) generate diff --git a/designs/leon3-xilinx-ml501/tkconfig.h b/designs/leon3-xilinx-ml501/tkconfig.h index 05f894d3..6fa1c902 100644 --- a/designs/leon3-xilinx-ml501/tkconfig.h +++ b/designs/leon3-xilinx-ml501/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-ml50x/.config b/designs/leon3-xilinx-ml50x/.config index 1cae28aa..b19d3c5c 100644 --- a/designs/leon3-xilinx-ml50x/.config +++ b/designs/leon3-xilinx-ml50x/.config @@ -175,7 +175,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -261,7 +260,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=000505 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd b/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd index fc328732..a0c2e95f 100644 --- a/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd +++ b/designs/leon3-xilinx-ml50x/ahb2mig_ml50x.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml50x/config.h b/designs/leon3-xilinx-ml50x/config.h index b81ee850..92cf197d 100644 --- a/designs/leon3-xilinx-ml50x/config.h +++ b/designs/leon3-xilinx-ml50x/config.h @@ -169,7 +169,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -249,7 +248,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 000505 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-ml50x/config.help b/designs/leon3-xilinx-ml50x/config.help index 300efd31..98b6951f 100644 --- a/designs/leon3-xilinx-ml50x/config.help +++ b/designs/leon3-xilinx-ml50x/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-ml50x/config.vhd b/designs/leon3-xilinx-ml50x/config.vhd index 72c9af61..bff5881c 100644 --- a/designs/leon3-xilinx-ml50x/config.vhd +++ b/designs/leon3-xilinx-ml50x/config.vhd @@ -64,7 +64,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-ml50x/config.vhd.h b/designs/leon3-xilinx-ml50x/config.vhd.h index aba10fbb..cdd5eca5 100644 --- a/designs/leon3-xilinx-ml50x/config.vhd.h +++ b/designs/leon3-xilinx-ml50x/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-ml50x/grlib_config.vhd b/designs/leon3-xilinx-ml50x/grlib_config.vhd index 0e5a2140..661591a5 100644 --- a/designs/leon3-xilinx-ml50x/grlib_config.vhd +++ b/designs/leon3-xilinx-ml50x/grlib_config.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml50x/lconfig.tk b/designs/leon3-xilinx-ml50x/lconfig.tk index f64a7f56..f49ff846 100755 --- a/designs/leon3-xilinx-ml50x/lconfig.tk +++ b/designs/leon3-xilinx-ml50x/lconfig.tk @@ -2195,24 +2195,23 @@ proc menu7 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 7 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 7 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 7 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 7 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 7 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 7 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 7 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 7 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 7 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 7 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 7 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 7 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 7 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2284,20 +2283,17 @@ proc update_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu7.config.f.x15 normal {n l y}} else {configure_entry .menu7.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x17 normal {n l y}} else {configure_entry .menu7.config.f.x17 disabled {y n l}} + configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x18.l configure -state normal; } else {.menu7.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x17.l configure -state normal; } else {.menu7.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu7.config.f.x19 normal {n l y}} else {configure_entry .menu7.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x20 normal {x l}} else {configure_entry .menu7.config.f.x20 disabled {x l}} + configure_entry .menu7.config.f.x18 normal {n l y}} else {configure_entry .menu7.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x19 normal {x l}} else {configure_entry .menu7.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x21.l configure -state normal; } else {.menu7.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x20.l configure -state normal; } else {.menu7.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x20.l configure -state disabled} } @@ -2430,9 +2426,6 @@ proc update_define_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3243,7 +3236,7 @@ proc menu13 {w title} { hex $w.config.f 13 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 13 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 13 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 13 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3293,12 +3286,11 @@ proc update_menu13 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x6.l configure -state normal; } else {.menu13.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu13.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu13.config.f.x7.l configure -state normal; } else {.menu13.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu13.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu13.config.f.x8 normal {n l y}} else {configure_entry .menu13.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu13.config.f.x9 normal {n l y}} else {configure_entry .menu13.config.f.x9 disabled {y n l}} } @@ -3329,12 +3321,11 @@ proc update_define_menu13 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5232,7 +5223,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5429,6 +5419,7 @@ set tmpvar_34 "(not set)" set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5892,7 +5883,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6015,10 +6005,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6134,6 +6123,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_31 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-ml50x/leon3mp.vhd b/designs/leon3-xilinx-ml50x/leon3mp.vhd index 691ec26c..c51bfa06 100644 --- a/designs/leon3-xilinx-ml50x/leon3mp.vhd +++ b/designs/leon3-xilinx-ml50x/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml50x/svga2ch7301c.vhd b/designs/leon3-xilinx-ml50x/svga2ch7301c.vhd index e0fa9171..02906add 100644 --- a/designs/leon3-xilinx-ml50x/svga2ch7301c.vhd +++ b/designs/leon3-xilinx-ml50x/svga2ch7301c.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml50x/testbench.vhd b/designs/leon3-xilinx-ml50x/testbench.vhd index b3002e83..5c482b54 100644 --- a/designs/leon3-xilinx-ml50x/testbench.vhd +++ b/designs/leon3-xilinx-ml50x/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -32,8 +32,6 @@ library micron; use micron.components.all; library cypress; use cypress.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -- configuration @@ -204,17 +202,14 @@ begin cor_pci_exp_rxn, ep_sys_clk_p, ep_sys_clk_n, cor_sys_reset_n ); - ddr2mem: for i in 0 to 3 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => 3-i, fname => sdramfile, fdelay => 100*CFG_MIG_DDR2) - port map (DQ => ddr_dq2(i*16+15 downto i*16), LDQS => ddr_dqsp(i*2), - LDQSB => ddr_dqsn(i*2), UDQS => ddr_dqsp(i*2+1), - UDQSB => ddr_dqsn(i*2+1), LDM => ddr_dm(i*2), - WEB => ddr_web, CASB => ddr_casb, RASB => ddr_rasb, CSB => ddr_csb(0), - BA => ddr_ba(1 downto 0), ADDR => ddr_ad(12 downto 0), CKE => ddr_cke(0), - CLK => ddr_clk(0), CLKB => ddr_clkb(0), UDM => ddr_dm(i*2+1)); - end generate; + ddr0 : ddr2ram + generic map(width => 64, abits => 13, babits =>2, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>1, density => 2, + lddelay => 100 us * CFG_MIG_DDR2) + port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke(0), csn => ddr_csb(0), + odt => ddr_odt(0), rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web, + dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2, + dqs => ddr_dqsp, dqsn =>ddr_dqsn); nodqdel : if (CFG_MIG_DDR2 = 1) generate ddr2delay : delay_wire @@ -224,7 +219,7 @@ begin dqdel : if (CFG_MIG_DDR2 = 0) generate ddr2delay : delay_wire - generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 2.5) + generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 5.5) port map(a => ddr_dq, b => ddr_dq2); end generate; diff --git a/designs/leon3-xilinx-ml50x/tkconfig.h b/designs/leon3-xilinx-ml50x/tkconfig.h index e646d9c5..26d43fe6 100644 --- a/designs/leon3-xilinx-ml50x/tkconfig.h +++ b/designs/leon3-xilinx-ml50x/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-ml510/leon3mp.vhd b/designs/leon3-xilinx-ml510/leon3mp.vhd index b2c8b96c..87c54556 100644 --- a/designs/leon3-xilinx-ml510/leon3mp.vhd +++ b/designs/leon3-xilinx-ml510/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml510/svga2ch7301c.vhd b/designs/leon3-xilinx-ml510/svga2ch7301c.vhd index e0fa9171..02906add 100644 --- a/designs/leon3-xilinx-ml510/svga2ch7301c.vhd +++ b/designs/leon3-xilinx-ml510/svga2ch7301c.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml510/testbench.vhd b/designs/leon3-xilinx-ml510/testbench.vhd index 0c80ddf6..e86cf6be 100644 --- a/designs/leon3-xilinx-ml510/testbench.vhd +++ b/designs/leon3-xilinx-ml510/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,8 +30,6 @@ library techmap; use techmap.gencomp.all; library cypress; use cypress.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -- configuration @@ -298,50 +296,74 @@ begin ); - ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH, - fname => sdramfile, fdelay => 0) - port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)), - LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), - LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), - UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), - UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), - LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), - WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b, - RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0), - BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0), - CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p, - CLKB => dimm0_ddr2_pll_clkin_n, - UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH))); - end generate; - - ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH, - fname => sdramfile, fdelay => 0) - port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)), - LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), - LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), - UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), - UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), - LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), - WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b, - RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0), - BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0), - CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p, - CLKB => dimm1_ddr2_pll_clkin_n, - UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH))); - end generate; + -- ddr2mem0: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate + -- u1 : HY5PS121621F + -- generic map (TimingCheckFlag => true, PUSCheckFlag => false, + -- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH, + -- fname => sdramfile, fdelay => 0) + -- port map (DQ => dimm0_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)), + -- LDQS => dimm0_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- LDQSB => dimm0_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- UDQS => dimm0_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- UDQSB => dimm0_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- LDM => dimm0_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- WEB => dimm0_ddr2_we_b, CASB => dimm0_ddr2_cas_b, + -- RASB => dimm0_ddr2_ras_b, CSB => dimm0_ddr2_s_b(0), + -- BA => dimm0_ddr2_ba(1 downto 0), ADDR => dimm0_ddr2_a(12 downto 0), + -- CKE => dimm0_ddr2_cke(0), CLK => dimm0_ddr2_pll_clkin_p, + -- CLKB => dimm0_ddr2_pll_clkin_n, + -- UDM => dimm0_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH))); + -- end generate; + + ddr2mem0 : ddr2ram + generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 14, babits => 3, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>1, density => 2) + port map (ck => dimm0_ddr2_pll_clkin_p, ckn => dimm0_ddr2_pll_clkin_n, + cke => dimm0_ddr2_cke(0), csn => dimm0_ddr2_s_b(0), + odt => gnd, rasn => dimm0_ddr2_ras_b, + casn => dimm0_ddr2_cas_b, wen => dimm0_ddr2_we_b, + dm => dimm0_ddr2_dqm(7 downto 8-CFG_DDR2SP_DATAWIDTH/8), ba => dimm0_ddr2_ba, + a => dimm0_ddr2_a, dq => dimm0_ddr2_dq2(63 downto 64-CFG_DDR2SP_DATAWIDTH), + dqs => dimm0_ddr2_dqs_p(7 downto 8-CFG_DDR2SP_DATAWIDTH/8), + dqsn =>dimm0_ddr2_dqs_n(7 downto 8-CFG_DDR2SP_DATAWIDTH/8)); + + -- ddr2mem1: for i in 0 to (1 + 2*(CFG_DDR2SP_DATAWIDTH/64)) generate + -- u1 : HY5PS121621F + -- generic map (TimingCheckFlag => true, PUSCheckFlag => false, + -- index => (1 + 2*(CFG_DDR2SP_DATAWIDTH/64))-i, bbits => CFG_DDR2SP_DATAWIDTH, + -- fname => sdramfile, fdelay => 0) + -- port map (DQ => dimm1_ddr2_dq2(i*16+15+32*(32/CFG_DDR2SP_DATAWIDTH) downto i*16+32*(32/CFG_DDR2SP_DATAWIDTH)), + -- LDQS => dimm1_ddr2_dqs_p(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- LDQSB => dimm1_ddr2_dqs_n(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- UDQS => dimm1_ddr2_dqs_p(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- UDQSB => dimm1_ddr2_dqs_n(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- LDM => dimm1_ddr2_dqm(i*2+4*(32/CFG_DDR2SP_DATAWIDTH)), + -- WEB => dimm1_ddr2_we_b, CASB => dimm1_ddr2_cas_b, + -- RASB => dimm1_ddr2_ras_b, CSB => dimm1_ddr2_s_b(0), + -- BA => dimm1_ddr2_ba(1 downto 0), ADDR => dimm1_ddr2_a(12 downto 0), + -- CKE => dimm1_ddr2_cke(0), CLK => dimm1_ddr2_pll_clkin_p, + -- CLKB => dimm1_ddr2_pll_clkin_n, + -- UDM => dimm1_ddr2_dqm(i*2+1+4*(32/CFG_DDR2SP_DATAWIDTH))); + -- end generate; + + ddr2mem1 : ddr2ram + generic map(width => CFG_DDR2SP_DATAWIDTH, abits => 13, babits =>2, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>1, density => 2) + port map (ck => dimm1_ddr2_pll_clkin_p, ckn => dimm1_ddr2_pll_clkin_n, + cke => dimm1_ddr2_cke(0), csn => dimm1_ddr2_s_b(0), + odt => gnd, rasn => dimm1_ddr2_ras_b, + casn => dimm1_ddr2_cas_b, wen => dimm1_ddr2_we_b, + dm => dimm1_ddr2_dqm(CFG_DDR2SP_DATAWIDTH/8-1 downto 0), ba => dimm1_ddr2_ba(1 downto 0), + a => dimm1_ddr2_a(12 downto 0), dq => dimm1_ddr2_dq2(CFG_DDR2SP_DATAWIDTH-1 downto 0), + dqs => dimm1_ddr2_dqs_p(CFG_DDR2SP_DATAWIDTH/8-1 downto 0), + dqsn =>dimm1_ddr2_dqs_n(CFG_DDR2SP_DATAWIDTH/8-1 downto 0)); ddr2delay0 : delay_wire - generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 2.5) + generic map(data_width => dimm0_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5) port map(a => dimm0_ddr2_dq, b => dimm0_ddr2_dq2); ddr2delay1 : delay_wire - generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 2.5) + generic map(data_width => dimm1_ddr2_dq'length, delay_atob => 0.0, delay_btoa => 5.5) port map(a => dimm1_ddr2_dq, b => dimm1_ddr2_dq2); prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile) diff --git a/designs/leon3-xilinx-ml605/.config b/designs/leon3-xilinx-ml605/.config index 5187accd..13a5404b 100755 --- a/designs/leon3-xilinx-ml605/.config +++ b/designs/leon3-xilinx-ml605/.config @@ -152,7 +152,6 @@ CONFIG_DCACHE_LZ16=y CONFIG_DCACHE_ALGOLRU=y # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -232,7 +231,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020789 CONFIG_DSU_ETHLSB=000123 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-ml605/Makefile b/designs/leon3-xilinx-ml605/Makefile index 500cff31..97fff99c 100644 --- a/designs/leon3-xilinx-ml605/Makefile +++ b/designs/leon3-xilinx-ml605/Makefile @@ -153,16 +153,14 @@ SDCFILE=default.sdc BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut CLEAN=soft-clean migclean pcieclean TECHLIBS = secureip unisim -VLOGOPT= +define+x1Gb +define+sg187E +define+x16 -O0 +VLOGOPT= -O0 VCOMOPT= -explicit -O0 ifeq ("$(GRLIB_SIMULATOR)","ALDEC") -VSIMOPT= +access +w -gdisas=1 -gDEBUG=0 -do riviera_preload_ddr3_dimm.do -t ps -novopt +notimingchecks -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl $(SIMTOP) +VSIMOPT= +access +w -t ps -novopt +notimingchecks -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl $(SIMTOP) else -VSIMOPT= -gdisas=1 -gDEBUG=0 -do preload_ddr3_dimm.do -t ps -novopt +notimingchecks -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl $(SIMTOP) +VSIMOPT= -t ps -novopt +notimingchecks -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl $(SIMTOP) endif -EXTRA_SOFT = gen_hex_dim16 - LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ tmtc openchip ihp usbhc spw gsi cypress hynix \ spansion diff --git a/designs/leon3-xilinx-ml605/README.txt b/designs/leon3-xilinx-ml605/README.txt index 0f45b611..0e4bacb2 100644 --- a/designs/leon3-xilinx-ml605/README.txt +++ b/designs/leon3-xilinx-ml605/README.txt @@ -59,7 +59,7 @@ controller from Xilinx use the make targets: This will ONLY work with ISE-14 installed, and the XILINX variable properly set in the shell. To build the design, do - make planAhead + make planahead and then diff --git a/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd b/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd index 63670692..b25057d3 100644 --- a/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd +++ b/designs/leon3-xilinx-ml605/ahb2mig_ml605.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml605/config.h b/designs/leon3-xilinx-ml605/config.h index 8a775d86..62155427 100644 --- a/designs/leon3-xilinx-ml605/config.h +++ b/designs/leon3-xilinx-ml605/config.h @@ -147,7 +147,6 @@ #define CONFIG_DCACHE_ALGOLRU 1 #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -221,7 +220,6 @@ #define CONFIG_DSU_ETHMSB 020789 #define CONFIG_DSU_ETHLSB 000123 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-ml605/config.help b/designs/leon3-xilinx-ml605/config.help index b4b10880..a299a799 100644 --- a/designs/leon3-xilinx-ml605/config.help +++ b/designs/leon3-xilinx-ml605/config.help @@ -348,19 +348,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -368,10 +369,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-ml605/config.vhd b/designs/leon3-xilinx-ml605/config.vhd index 39769980..c5bd105b 100644 --- a/designs/leon3-xilinx-ml605/config.vhd +++ b/designs/leon3-xilinx-ml605/config.vhd @@ -50,7 +50,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-ml605/config.vhd.h b/designs/leon3-xilinx-ml605/config.vhd.h index 2ee2753a..9c7c37d1 100644 --- a/designs/leon3-xilinx-ml605/config.vhd.h +++ b/designs/leon3-xilinx-ml605/config.vhd.h @@ -35,7 +35,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-ml605/grlib_config.vhd b/designs/leon3-xilinx-ml605/grlib_config.vhd index c594ac71..0a6a748c 100644 --- a/designs/leon3-xilinx-ml605/grlib_config.vhd +++ b/designs/leon3-xilinx-ml605/grlib_config.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml605/lconfig.tk b/designs/leon3-xilinx-ml605/lconfig.tk index a07a0aa9..37d6b0ff 100755 --- a/designs/leon3-xilinx-ml605/lconfig.tk +++ b/designs/leon3-xilinx-ml605/lconfig.tk @@ -1996,24 +1996,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2085,20 +2084,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2231,9 +2227,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3114,7 +3107,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3164,12 +3157,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3200,12 +3192,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -4841,7 +4832,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5026,6 +5016,7 @@ set CONFIG_DEBUG_UART 0 set CONFIG_LEON3FT_PRESENT 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_BOARD_ML505 4 set CONFIG_MODULES 4 proc writeconfig {file1 file2} { @@ -5432,7 +5423,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5576,10 +5566,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5636,6 +5625,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-ml605/leon3mp.vhd b/designs/leon3-xilinx-ml605/leon3mp.vhd index aaf5cccd..7b290454 100644 --- a/designs/leon3-xilinx-ml605/leon3mp.vhd +++ b/designs/leon3-xilinx-ml605/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml605/preload_ddr3_dimm.do b/designs/leon3-xilinx-ml605/preload_ddr3_dimm.do deleted file mode 100644 index 66e20fde..00000000 --- a/designs/leon3-xilinx-ml605/preload_ddr3_dimm.do +++ /dev/null @@ -1,40 +0,0 @@ -# Procedure to load memory from file -proc reload_mem {} { - # Load memory with system test and display memory - if {[examine /testbench/led(3)] == 1} { - #if {[examine sim:/config@work/CFG_MIG_SERIES7] == 1} { - echo "Loading DDR3 memory with System Test" - #if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == FALSE} { - mem load -startaddress 0 -format hex -infile sdram_dimm_merge3.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem(0)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm_merge4.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem(1)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm_merge1.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem(2)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm_merge2.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem(3)/u1/memory - - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem(0)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem(1)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem(2)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem(3)/u1/address - - change sim:/testbench/gen_mem(0)/u1/memory_used 11111111111111111111111111111111 - change sim:/testbench/gen_mem(1)/u1/memory_used 11111111111111111111111111111111 - change sim:/testbench/gen_mem(2)/u1/memory_used 11111111111111111111111111111111 - change sim:/testbench/gen_mem(3)/u1/memory_used 11111111111111111111111111111111 - #} - - #if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == TRUE} { - # echo "MIG Model found" - # mem load -startaddress 0 -format hex -infile sdram_dimm_merge.hex -filltype value -filldata 1'b0 sim:/testbench/cpu/mig_gen/ddrc/gen_mig_model/MCB_model_inst/Mem - #} - - #do wave.do - #} - } -} - -set init_path /testbench/led(3); - -when -label when1 "$init_path'event and $init_path ='1'" { - reload_mem -} - -#run 2 ms diff --git a/designs/leon3-xilinx-ml605/riviera_preload_ddr3_dimm.do b/designs/leon3-xilinx-ml605/riviera_preload_ddr3_dimm.do deleted file mode 100644 index 5291153c..00000000 --- a/designs/leon3-xilinx-ml605/riviera_preload_ddr3_dimm.do +++ /dev/null @@ -1,40 +0,0 @@ -# Procedure to load memory from file -proc reload_mem {} { - # Load memory with system test and display memory - if {[examine /testbench/led(3)] == 1} { - #if {[examine sim:/config@work/CFG_MIG_SERIES7] == 1} { - echo "Loading DDR3 memory with System Test" - #if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == FALSE} { - mem load -startaddress 0 -format hex -infile sdram_dimm_merge3.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem__0/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm_merge4.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem__1/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm_merge1.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem__2/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm_merge2.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem__3/u1/memory - - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem__0/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem__1/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem__2/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem__3/u1/address - - change sim:/testbench/gen_mem__0/u1/memory_used 11111111111111111111111111111111 - change sim:/testbench/gen_mem__1/u1/memory_used 11111111111111111111111111111111 - change sim:/testbench/gen_mem__2/u1/memory_used 11111111111111111111111111111111 - change sim:/testbench/gen_mem__3/u1/memory_used 11111111111111111111111111111111 - #} - - #if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == TRUE} { - # echo "MIG Model found" - # mem load -startaddress 0 -format hex -infile sdram_dimm_merge.hex -filltype value -filldata 1'b0 sim:/testbench/cpu/mig_gen/ddrc/gen_mig_model/MCB_model_inst/Mem - #} - - #do wave.do - #} - } -} - -set init_path /testbench/led(3); - -when -label when1 {$init_path and $init_path =1} { - reload_mem -} - -#run 2 ms \ No newline at end of file diff --git a/designs/leon3-xilinx-ml605/svga2ch7301c.vhd b/designs/leon3-xilinx-ml605/svga2ch7301c.vhd index 87876f8d..143d9e63 100644 --- a/designs/leon3-xilinx-ml605/svga2ch7301c.vhd +++ b/designs/leon3-xilinx-ml605/svga2ch7301c.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-ml605/testbench.vhd b/designs/leon3-xilinx-ml605/testbench.vhd index 991f72b5..4ffabc2e 100644 --- a/designs/leon3-xilinx-ml605/testbench.vhd +++ b/designs/leon3-xilinx-ml605/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -28,8 +28,6 @@ use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.all; use work.debug.all; use work.config.all; @@ -59,7 +57,7 @@ constant SIM_BYPASS_INIT_CAL : string := "FAST"; constant promfile : string := "prom.srec"; -- rom contents - constant sdramfile : string := "ram.srec"; -- sdram contents + constant ramfile : string := "ram.srec"; -- sdram contents constant lresp : boolean := false; constant ct : integer := clkperiod/2; @@ -151,28 +149,6 @@ signal clk_33 : std_ulogic := '0'; signal brdyn : std_ulogic; -component ddr3_model is - port ( - rst_n : in std_logic; - ck : in std_logic; - ck_n : in std_logic; - cke : in std_logic; - cs_n : in std_logic; - ras_n : in std_logic; - cas_n : in std_logic; - we_n : in std_logic; - dm_tdqs : inout std_logic_vector(1 downto 0); - ba : in std_logic_vector(2 downto 0); - addr : in std_logic_vector(12 downto 0); - dq : inout std_logic_vector(15 downto 0); - dqs : inout std_logic_vector(1 downto 0); - dqs_n : inout std_logic_vector(1 downto 0); - tdqs_n : out std_logic_vector(1 downto 0); - odt : in std_logic - ); -end component ddr3_model; - - ---------------------pcie---------------------------------------------- signal cor_sys_reset_n : std_logic := '1'; signal ep_sys_clk_p : std_logic; @@ -287,31 +263,40 @@ begin led => led ); - gen_mem: for i in 0 to 3 generate - u1: ddr3_model port map - ( - rst_n => ddr3_reset_n, - ck => ddr3_ck_p(0), - ck_n => ddr3_ck_n(0), - cke => ddr3_cke(0), - cs_n => ddr3_cs_n(0), - ras_n => ddr3_ras_n, - cas_n => ddr3_cas_n, - we_n => ddr3_we_n, - dm_tdqs => ddr3_dm((2*(i+1)-1) downto (i*2)), - ba => ddr3_ba, - addr => ddr3_addr, - dq => ddr3_dq((16*i+15) downto (16*i)), - dqs => ddr3_dqs_p((2*(i+1)-1) downto (i*2)), - dqs_n => ddr3_dqs_n((2*(i+1)-1) downto (i*2)), - tdqs_n => ddr3_tdqs_n((2*(i+1)-1) downto (i*2)), - odt => ddr3_odt(0)); - end generate gen_mem; - --- prom0 : sram --- generic map (index => 6, abits => 24, fname => promfile) --- port map (address(23 downto 0), data(31 downto 24), romsn, writen, oen); + u1 : ddr3ram + generic map ( + width => 64, + abits => 13, + colbits => 10, + rowbits => 13, + implbanks => 1, + fname => ramfile, + lddelay => (0 ns), + ldguard => 1, + speedbin => 9, --DDR3-1600K + density => 3, + pagesize => 1, + changeendian => 32) + port map ( + ck => ddr3_ck_p(0), + ckn => ddr3_ck_n(0), + cke => ddr3_cke(0), + csn => ddr3_cs_n(0), + odt => ddr3_odt(0), + rasn => ddr3_ras_n, + casn => ddr3_cas_n, + wen => ddr3_we_n, + dm => ddr3_dm, + ba => ddr3_ba, + a => ddr3_addr, + resetn => ddr3_reset_n, + dq => ddr3_dq, + dqs => ddr3_dqs_p, + dqsn => ddr3_dqs_n, + doload => led(3) + ); + address(0) <= '0'; prom0 : for i in 0 to 1 generate sr0 : sram generic map (index => i+4, abits => 24, fname => promfile) diff --git a/designs/leon3-xilinx-ml605/tkconfig.h b/designs/leon3-xilinx-ml605/tkconfig.h index 300e9810..c9afc030 100644 --- a/designs/leon3-xilinx-ml605/tkconfig.h +++ b/designs/leon3-xilinx-ml605/tkconfig.h @@ -407,10 +407,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-sp601/README.txt b/designs/leon3-xilinx-sp601/README.txt index 0a1bc02b..f8775bf9 100644 --- a/designs/leon3-xilinx-sp601/README.txt +++ b/designs/leon3-xilinx-sp601/README.txt @@ -24,13 +24,13 @@ library, do as follows: This will ONLY work with correct version of ISE installed, and the XILINX variable properly set in the shell. For ISE13 it is recommened to use the 'ise' make target -and for ISE14 to use the 'planAhead' target. To synthesize the design, do +and for ISE14 to use the 'planahead' target. To synthesize the design, do make ise (ISE13) or - make planAhead (ISE14) + make planahead (ISE14) and then diff --git a/designs/leon3-xilinx-sp601/ahb2mig_sp601.vhd b/designs/leon3-xilinx-sp601/ahb2mig_sp601.vhd index dafb640e..9815811b 100644 --- a/designs/leon3-xilinx-sp601/ahb2mig_sp601.vhd +++ b/designs/leon3-xilinx-sp601/ahb2mig_sp601.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -52,10 +52,12 @@ entity ahb2mig_sp601 is mcb3_dram_cke : out std_logic; mcb3_dram_dm : out std_logic; mcb3_dram_udqs : inout std_logic; + mcb3_dram_udqs_n : inout std_logic; mcb3_rzq : inout std_logic; mcb3_zio : inout std_logic; mcb3_dram_udm : out std_logic; mcb3_dram_dqs : inout std_logic; + mcb3_dram_dqs_n : inout std_logic; mcb3_dram_ck : out std_logic; mcb3_dram_ck_n : out std_logic; @@ -411,6 +413,7 @@ begin mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_dm => mcb3_dram_dm, mcb3_dram_udqs => mcb3_dram_udqs, + mcb3_dram_udqs_n => mcb3_dram_udqs_n, mcb3_rzq => mcb3_rzq, mcb3_zio => mcb3_zio, mcb3_dram_udm => mcb3_dram_udm, @@ -421,6 +424,7 @@ begin c3_clk0 => open, c3_rst0 => open, mcb3_dram_dqs => mcb3_dram_dqs, + mcb3_dram_dqs_n => mcb3_dram_dqs_n, mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, c3_p0_cmd_clk => clk_amba, diff --git a/designs/leon3-xilinx-sp601/config.help b/designs/leon3-xilinx-sp601/config.help index 458bbd81..81b3d19a 100644 --- a/designs/leon3-xilinx-sp601/config.help +++ b/designs/leon3-xilinx-sp601/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-sp601/config.vhd b/designs/leon3-xilinx-sp601/config.vhd index 8970fc05..42c50ae7 100644 --- a/designs/leon3-xilinx-sp601/config.vhd +++ b/designs/leon3-xilinx-sp601/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-sp601/config.vhd.h b/designs/leon3-xilinx-sp601/config.vhd.h index 368a9909..4937ee54 100644 --- a/designs/leon3-xilinx-sp601/config.vhd.h +++ b/designs/leon3-xilinx-sp601/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-sp601/lconfig.tk b/designs/leon3-xilinx-sp601/lconfig.tk index 15c1f1df..4899f30e 100755 --- a/designs/leon3-xilinx-sp601/lconfig.tk +++ b/designs/leon3-xilinx-sp601/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5144,7 +5135,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5345,6 +5335,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5801,7 +5792,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5924,10 +5914,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6039,6 +6028,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-sp601/leon3mp.ucf b/designs/leon3-xilinx-sp601/leon3mp.ucf index d9a0c5b1..5f5c2dcb 100644 --- a/designs/leon3-xilinx-sp601/leon3mp.ucf +++ b/designs/leon3-xilinx-sp601/leon3mp.ucf @@ -130,11 +130,12 @@ NET "ddr_cke" LOC = "H7" ; NET "ddr_dm(0)" LOC = "K3" ; # NET "ddr_dqs(0)" LOC = "L4" ; -#NET "ddr_dqsn(0)" LOC = "L3" ; +NET "ddr_dqsn(0)" LOC = "L3" ; NET "ddr_odt" LOC = "K6" ; NET "ddr_ras" LOC = "L5" ; NET "ddr_dm(1)" LOC = "K4" ; NET "ddr_dqs(1)" LOC = "P2" ; +NET "ddr_dqsn(1)" LOC = "P1" ; NET "ddr_we" LOC = "E3" ; # The specific pin below for RZQ is required for xc6slx16-csg324 diff --git a/designs/leon3-xilinx-sp601/leon3mp.vhd b/designs/leon3-xilinx-sp601/leon3mp.vhd index 6ce85449..2e6e8351 100644 --- a/designs/leon3-xilinx-sp601/leon3mp.vhd +++ b/designs/leon3-xilinx-sp601/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -82,7 +82,7 @@ entity leon3mp is ddr_cas : out std_ulogic; -- cas ddr_dm : out std_logic_vector(1 downto 0); -- dm ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs --- ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn + ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn ddr_ad : out std_logic_vector(12 downto 0); -- address ddr_ba : out std_logic_vector(2 downto 0); -- bank address ddr_dq : inout std_logic_vector(15 downto 0); -- data @@ -124,7 +124,6 @@ end; architecture rtl of leon3mp is signal vcc : std_logic; signal gnd : std_logic; - signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn signal ddr_clk_fb_out : std_logic; signal ddr_clk_fb : std_logic; @@ -221,8 +220,6 @@ begin port map (reset, clkm, lock, rstn, rstraw); clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk); --- clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v) --- port map (clk200_p, clk200_n, lclk200); -- clock generator clkgen0 : clkgen @@ -347,6 +344,8 @@ begin ---------------------------------------------------------------------- ddr2sp0 : if (CFG_DDR2SP /= 0) generate + clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v) + port map (clk200_p, clk200_n, lclk200); ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech, hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1, pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8, @@ -380,10 +379,12 @@ begin mcb3_dram_cke => ddr_cke, mcb3_dram_dm => ddr_dm(0), mcb3_dram_udqs => ddr_dqs(1), + mcb3_dram_udqs_n => ddr_dqsn(1), mcb3_rzq => ddr_rzq, mcb3_zio => ddr_zio, mcb3_dram_udm => ddr_dm(1), mcb3_dram_dqs => ddr_dqs(0), + mcb3_dram_dqs_n => ddr_dqsn(0), mcb3_dram_ck => ddr_clk, mcb3_dram_ck_n => ddr_clkb, ahbsi => ahbsi, diff --git a/designs/leon3-xilinx-sp601/testbench.vhd b/designs/leon3-xilinx-sp601/testbench.vhd index 29b9ada8..5e929a4d 100644 --- a/designs/leon3-xilinx-sp601/testbench.vhd +++ b/designs/leon3-xilinx-sp601/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,15 +30,10 @@ library techmap; use techmap.gencomp.all; library micron; use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -library hynix; -use hynix.components.all; - entity testbench is generic ( fabtech : integer := CFG_FABTECH; @@ -176,6 +171,7 @@ begin ddr_cas => ddr_cas, ddr_dm => ddr_dm, ddr_dqs => ddr_dqs, + ddr_dqsn => ddr_dqsn, ddr_ad => ddr_ad, ddr_ba => ddr_ba, ddr_dq => ddr_dq, @@ -215,35 +211,28 @@ begin migddr2mem : if (CFG_MIG_DDR2 = 1) generate - ddr2mem0 : for i in 0 to 0 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => i, bbits => 16, fname => sdramfile, - fdelay => 150) - port map (DQ => ddr_dq(i*16+15 downto i*16), - LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2), - UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1), - LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas, - RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0), - ADDR => ddr_ad(12 downto 0), CKE => ddr_cke, - CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1)); - end generate; + ddr2mem0: ddr2ram + generic map (width => 16, abits => 13, babits => 3, + colbits => 10, rowbits => 13, implbanks => 1, + fname => sdramfile, lddelay => (220 us), + speedbin => 1) + port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, + odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, + dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn); end generate; ddr2mem : if (CFG_DDR2SP /= 0) generate - ddr2mem0 : for i in 0 to 0 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => i, bbits => 16, fname => sdramfile) - port map (DQ => ddr_dq2(i*16+15 downto i*16), - LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2), - UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1), - LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas, - RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba(1 downto 0), - ADDR => ddr_ad(12 downto 0), CKE => ddr_cke, - CLK => ddr_clk, CLKB => ddr_clkb, UDM => ddr_dm(i*2+1)); - end generate; + ddr2mem0: ddr2ram + generic map (width => 16, abits => 13, babits => 3, + colbits => 10, rowbits => 13, implbanks => 1, + fname => sdramfile, lddelay => (0 us), + speedbin => 1) + port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, + odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, + dq => ddr_dq2, dqs => ddr_dqs, dqsn => ddr_dqsn); ddr2delay0 : delay_wire - generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 10.0) + generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 9.0) port map(a => ddr_dq, b => ddr_dq2); end generate; diff --git a/designs/leon3-xilinx-sp601/tkconfig.h b/designs/leon3-xilinx-sp601/tkconfig.h index 2a5a32c5..d5a3e41a 100644 --- a/designs/leon3-xilinx-sp601/tkconfig.h +++ b/designs/leon3-xilinx-sp601/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-sp605/.config b/designs/leon3-xilinx-sp605/.config index d9b5acd8..041f4c54 100644 --- a/designs/leon3-xilinx-sp605/.config +++ b/designs/leon3-xilinx-sp605/.config @@ -169,7 +169,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -255,7 +254,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020605 CONFIG_DSU_ETHLSB=000987 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-sp605/README.txt b/designs/leon3-xilinx-sp605/README.txt index 8883bd87..a0d7381b 100644 --- a/designs/leon3-xilinx-sp605/README.txt +++ b/designs/leon3-xilinx-sp605/README.txt @@ -23,13 +23,13 @@ library, do as follows: This will ONLY work with correct version of ISE installed, and the XILINX variable properly set in the shell. For ISE13 it is recommened to use the 'ise' make target -and for ISE14 to use the 'planAhead' target. To synthesize the design, do +and for ISE14 to use the 'planahead' target. To synthesize the design, do make ise (ISE13) or - make planAhead (ISE14) + make planahead (ISE14) and then @@ -66,8 +66,6 @@ Design specifics make distclean vsim Modelsim v6.6e or newer is required to build the secure IP models. - Note that the regular leon3 test bench cannot be run in simulation - as the DDR3 model lacks data pre-load. * The application UART1 is connected to the USB/UART connector diff --git a/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd b/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd index 0f4164e3..46cb9a77 100644 --- a/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd +++ b/designs/leon3-xilinx-sp605/ahb2mig_sp605.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-sp605/config.h b/designs/leon3-xilinx-sp605/config.h index d4842f43..298d5ca4 100644 --- a/designs/leon3-xilinx-sp605/config.h +++ b/designs/leon3-xilinx-sp605/config.h @@ -164,7 +164,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -244,7 +243,6 @@ #define CONFIG_DSU_ETHMSB 020605 #define CONFIG_DSU_ETHLSB 000987 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-sp605/config.help b/designs/leon3-xilinx-sp605/config.help index f8aed7da..fec1c3de 100644 --- a/designs/leon3-xilinx-sp605/config.help +++ b/designs/leon3-xilinx-sp605/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-sp605/config.vhd b/designs/leon3-xilinx-sp605/config.vhd index 026f0eda..f61c9447 100644 --- a/designs/leon3-xilinx-sp605/config.vhd +++ b/designs/leon3-xilinx-sp605/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-sp605/config.vhd.h b/designs/leon3-xilinx-sp605/config.vhd.h index 88b23ced..28a4a0f7 100644 --- a/designs/leon3-xilinx-sp605/config.vhd.h +++ b/designs/leon3-xilinx-sp605/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-sp605/lconfig.tk b/designs/leon3-xilinx-sp605/lconfig.tk index b0de92b4..a339ab26 100755 --- a/designs/leon3-xilinx-sp605/lconfig.tk +++ b/designs/leon3-xilinx-sp605/lconfig.tk @@ -2093,24 +2093,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2182,20 +2181,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2328,9 +2324,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3210,7 +3203,7 @@ proc menu12 {w title} { hex $w.config.f 12 5 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 6 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 7 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 8 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 8 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3260,12 +3253,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x5.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x5.l configure -state normal; } else {.menu12.config.f.x5.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x5.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x7 normal {n l y}} else {configure_entry .menu12.config.f.x7 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} } @@ -3296,12 +3288,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5414,7 +5405,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5629,6 +5619,7 @@ set CONFIG_LEON3FT_PRESENT 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_BOARD_ML505 4 set CONFIG_MODULES 4 proc writeconfig {file1 file2} { @@ -6074,7 +6065,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6216,10 +6206,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -6290,6 +6279,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-sp605/leon3mp.vhd b/designs/leon3-xilinx-sp605/leon3mp.vhd index a746ae1a..43fd669b 100644 --- a/designs/leon3-xilinx-sp605/leon3mp.vhd +++ b/designs/leon3-xilinx-sp605/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-sp605/prom.h b/designs/leon3-xilinx-sp605/prom.h index b976d020..e283ab8b 100644 --- a/designs/leon3-xilinx-sp605/prom.h +++ b/designs/leon3-xilinx-sp605/prom.h @@ -1,4 +1,4 @@ -#define MCFG1 0x10380033 +#define MCFG1 0x10380133 #define MCFG2 0xe6B86e60 #define MCFG3 0x000ff000 #define ASDCFG 0x80000000 diff --git a/designs/leon3-xilinx-sp605/prom.srec b/designs/leon3-xilinx-sp605/prom.srec index e0372044..a2497cbf 100755 --- a/designs/leon3-xilinx-sp605/prom.srec +++ b/designs/leon3-xilinx-sp605/prom.srec @@ -24,7 +24,7 @@ S1130150010000000100000089A008420100000025 S113016001000000010000000100000010800005F3 S11301700100000001000000000000000000000079 S1130180874440008730E01C8688E00F1280001509 -S11301900320000005040E008410A033C420400096 +S11301900320000005040E008410A133C420400095 S11301A00539AE1B8410A260C4206004050003FC62 S11301B0C420600882103860C40040008530A00C60 S11301C0030000048210600980A040021280000530 diff --git a/designs/leon3-xilinx-sp605/svga2ch7301c.vhd b/designs/leon3-xilinx-sp605/svga2ch7301c.vhd index 4f9a1eac..804921c7 100644 --- a/designs/leon3-xilinx-sp605/svga2ch7301c.vhd +++ b/designs/leon3-xilinx-sp605/svga2ch7301c.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-sp605/testbench.vhd b/designs/leon3-xilinx-sp605/testbench.vhd index 66ac1845..1b00f50b 100644 --- a/designs/leon3-xilinx-sp605/testbench.vhd +++ b/designs/leon3-xilinx-sp605/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -29,9 +29,6 @@ use gaisler.sim.all; library techmap; use techmap.gencomp.all; use work.debug.all; -library hynix; -use hynix.components.all; -library micron; use work.config.all; -- configuration @@ -371,14 +368,19 @@ end generate; end generate; address(0) <= '0'; - u1 : entity micron.ddr3 - port map ( rst_n => ddr_reset_n, dq => ddr_dq, - tdqs_n => ddr3_tdqs_n, - dqs => ddr_dqs, dqs_n => ddr_dqsn, - dm_tdqs => ddr_dm, we_n => ddr_we, cas_n => ddr_cas, - ras_n => ddr_ras, cs_n => ddr_csb, ba => ddr_ba, - addr => ddr_ad(12 downto 0), cke => ddr_cke, - ck => ddr_clk, ck_n => ddr_clkb, odt => ddr_odt) ; + u1 : ddr3ram + generic map ( + width => 16, abits => 13, fname => sdramfile, + speedbin => 3, + ldguard => 1 + ) + port map ( + ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb, odt => ddr_odt, + rasn => ddr_ras, casn => ddr_cas, wen => ddr_we, + dm => ddr_dm, ba => ddr_ba, a => ddr_ad, resetn => ddr_reset_n, + dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn, + doload => led(2) + ); errorn <= led(1); errorn <= 'H'; -- ERROR pull-up diff --git a/designs/leon3-xilinx-sp605/tkconfig.h b/designs/leon3-xilinx-sp605/tkconfig.h index 5a8d1bef..20e75fe6 100644 --- a/designs/leon3-xilinx-sp605/tkconfig.h +++ b/designs/leon3-xilinx-sp605/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-sp605/vga_clkgen.vhd b/designs/leon3-xilinx-sp605/vga_clkgen.vhd index b1ee2d14..b96a3b45 100644 --- a/designs/leon3-xilinx-sp605/vga_clkgen.vhd +++ b/designs/leon3-xilinx-sp605/vga_clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-vc707/.config b/designs/leon3-xilinx-vc707/.config index c99548a8..09377259 100644 --- a/designs/leon3-xilinx-vc707/.config +++ b/designs/leon3-xilinx-vc707/.config @@ -102,19 +102,19 @@ CONFIG_LEON3_CUSTOM=y CONFIG_IU_NWINDOWS=8 CONFIG_IU_V8MULDIV=y # CONFIG_IU_MUL_LATENCY_2 is not set -CONFIG_IU_MUL_LATENCY_4=y -# CONFIG_IU_MUL_LATENCY_5 is not set +# CONFIG_IU_MUL_LATENCY_4 is not set +CONFIG_IU_MUL_LATENCY_5=y # CONFIG_IU_MUL_MAC is not set CONFIG_IU_MUL_INFERRED=y # CONFIG_IU_MUL_MODGEN is not set # CONFIG_IU_MUL_TECHSPEC is not set # CONFIG_IU_MUL_DW is not set CONFIG_IU_BP=y -# CONFIG_IU_SVT is not set +CONFIG_IU_SVT=y # CONFIG_NOTAG is not set CONFIG_IU_LDELAY=1 CONFIG_IU_WATCHPOINTS=2 -# CONFIG_PWD is not set +CONFIG_PWD=y CONFIG_IU_RSTADDR=00000 # @@ -127,9 +127,9 @@ CONFIG_IU_RSTADDR=00000 # CONFIG_ICACHE_ENABLE=y # CONFIG_ICACHE_ASSO1 is not set -# CONFIG_ICACHE_ASSO2 is not set +CONFIG_ICACHE_ASSO2=y # CONFIG_ICACHE_ASSO3 is not set -CONFIG_ICACHE_ASSO4=y +# CONFIG_ICACHE_ASSO4 is not set # CONFIG_ICACHE_SZ1 is not set # CONFIG_ICACHE_SZ2 is not set CONFIG_ICACHE_SZ4=y @@ -139,18 +139,18 @@ CONFIG_ICACHE_SZ4=y # CONFIG_ICACHE_SZ64 is not set # CONFIG_ICACHE_SZ128 is not set # CONFIG_ICACHE_SZ256 is not set -# CONFIG_ICACHE_LZ16 is not set -CONFIG_ICACHE_LZ32=y -# CONFIG_ICACHE_ALGORND is not set -CONFIG_ICACHE_ALGODIR=y +CONFIG_ICACHE_LZ16=y +# CONFIG_ICACHE_LZ32 is not set +CONFIG_ICACHE_ALGORND=y +# CONFIG_ICACHE_ALGODIR is not set # CONFIG_ICACHE_ALGOLRR is not set # CONFIG_ICACHE_ALGOLRU is not set -CONFIG_ICACHE_LOCK=y +# CONFIG_ICACHE_LOCK is not set CONFIG_DCACHE_ENABLE=y # CONFIG_DCACHE_ASSO1 is not set -# CONFIG_DCACHE_ASSO2 is not set +CONFIG_DCACHE_ASSO2=y # CONFIG_DCACHE_ASSO3 is not set -CONFIG_DCACHE_ASSO4=y +# CONFIG_DCACHE_ASSO4 is not set # CONFIG_DCACHE_SZ1 is not set # CONFIG_DCACHE_SZ2 is not set CONFIG_DCACHE_SZ4=y @@ -160,15 +160,14 @@ CONFIG_DCACHE_SZ4=y # CONFIG_DCACHE_SZ64 is not set # CONFIG_DCACHE_SZ128 is not set # CONFIG_DCACHE_SZ256 is not set -# CONFIG_DCACHE_LZ16 is not set -CONFIG_DCACHE_LZ32=y -# CONFIG_DCACHE_ALGORND is not set -CONFIG_DCACHE_ALGODIR=y +CONFIG_DCACHE_LZ16=y +# CONFIG_DCACHE_LZ32 is not set +CONFIG_DCACHE_ALGORND=y +# CONFIG_DCACHE_ALGODIR is not set # CONFIG_DCACHE_ALGOLRR is not set # CONFIG_DCACHE_ALGOLRU is not set -CONFIG_DCACHE_LOCK=y +# CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 @@ -245,6 +244,17 @@ CONFIG_APB_HADDR=800 CONFIG_DSU_UART=y CONFIG_DSU_JTAG=y # CONFIG_GRUSB_DCL is not set +CONFIG_DSU_ETH=y +# CONFIG_DSU_ETHSZ1 is not set +# CONFIG_DSU_ETHSZ2 is not set +# CONFIG_DSU_ETHSZ4 is not set +# CONFIG_DSU_ETHSZ8 is not set +CONFIG_DSU_ETHSZ16=y +CONFIG_DSU_IPMSB=C0A8 +CONFIG_DSU_IPLSB=0033 +CONFIG_DSU_ETHMSB=020000 +CONFIG_DSU_ETHLSB=000000 +# CONFIG_DSU_ETH_PROG is not set # # Peripherals @@ -272,7 +282,7 @@ CONFIG_MCTRL_16BIT=y # MIG Series 7 memory controller # CONFIG_MIG_SERIES7=y -# CONFIG_MIG_SERIES_7_MODEL is not set +CONFIG_MIG_SERIES_7_MODEL=y # CONFIG_AHBSTAT_ENABLE is not set # @@ -299,7 +309,14 @@ CONFIG_AHBRAM_START=A00 # # Ethernet # -# CONFIG_GRETH_ENABLE is not set +CONFIG_GRETH_ENABLE=y +# CONFIG_GRETH_GIGA is not set +# CONFIG_GRETH_FIFO4 is not set +CONFIG_GRETH_FIFO8=y +# CONFIG_GRETH_FIFO16 is not set +# CONFIG_GRETH_FIFO32 is not set +# CONFIG_GRETH_FIFO64 is not set +# CONFIG_GRETH_FT is not set # # USB 2.0 Host Controller diff --git a/designs/leon3-xilinx-vc707/Makefile b/designs/leon3-xilinx-vc707/Makefile index 347e7871..d45943a1 100644 --- a/designs/leon3-xilinx-vc707/Makefile +++ b/designs/leon3-xilinx-vc707/Makefile @@ -19,14 +19,13 @@ TOP=leon3mp SIMTOP=testbench # Uncomment for Modelsim or change to specify your simulator -GRLIB_SIMULATOR=ModelSim +#GRLIB_SIMULATOR=ModelSim # Options used during compilation VCOMOPT=-explicit -O0 -VLOGOPT= +define+x1Gb +define+sg125 +define+x8 -suppress 2902 # GRLIB Options -VSIMOPT= -gdisas=1 +#VSIMOPT= -gdisas=1 # GRETH options ifeq ($(CONFIG_GRETH_ENABLE),y) @@ -34,20 +33,11 @@ VSIMOPT+= -L gig_ethernet_pcs_pma_v14_0 -L secureip_ver -L xilinxcorelib_ver -L endif # - MIG - -# -# DEBUG - Print debug information from external DDR3 memory (1/0) -# ifeq ($(CONFIG_MIG_SERIES7),y) -ifeq ("$(GRLIB_SIMULATOR)","ALDEC") -VSIMOPT+= -do "do riviera_preload_ddr3_dimm.do; run -all" -else -VSIMOPT+= -do "do preload_ddr3_dimm.do; run -all" -endif -VSIMOPT+= -t fs -novopt -gDEBUG=0 +VSIMOPT+= -t fs -novopt VSIMOPT+= -L secureip_ver -L xilinxcorelib_ver -L unisims_ver glbl -GRLIB_XIL_Vivado_sim_verilog_define=x1Gb sg125 x8 ifndef CONFIG_MIG_SERIES_7_MODEL -VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false -gSIM_BYPASS_INIT_CAL=FAST -gSIMULATION=TRUE -gcheck_strict_timing=0 +VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=false -gSIM_BYPASS_INIT_CAL=FAST -gSIMULATION=TRUE else VSIMOPT+= -gUSE_MIG_INTERFACE_MODEL=true -t ps endif @@ -60,6 +50,12 @@ else VSIMOPT+= -novopt +notimingchecks endif +# Run simulation in batch mode +#VSIMOPT+= -c + +# Simulation scripts +VSIMOPT+= -do "run -all" + # Toplevel VSIMOPT+= $(SIMTOP) @@ -67,11 +63,10 @@ VSIMOPT+= $(SIMTOP) ### Testbench, design and libraries to compile and not to compile -VHDLSYNFILES= config.vhd ahbrom.vhd leon3mp.vhd ddr_dummy.vhd sgmii_vc707.vhd +VHDLSYNFILES= config.vhd ahbram_sim.vhd ahbrom.vhd leon3mp.vhd ddr_dummy.vhd sgmii_vc707.vhd VHDLSIMFILES=testbench.vhd -TECHLIBS = secureip unisim -EXTRA_SOFT = gen_hex_dim +TECHLIBS = secureip unisim LIBSKIP = pci pci/pcif core1553bbc core1553brm core1553brt gr1553 corePCIF \ tmtc openchip ihp spw gsi cypress hynix \ @@ -79,7 +74,7 @@ LIBSKIP = pci pci/pcif core1553bbc core1553brm core1553brt gr1553 corePCIF \ DIRSKIP = b1553 pci pci/pcif leon2 leon2ft crypto satcan pci ambatest \ spacewire ascs slink \ leon4 leon4v0 l2cache pwm gr1553b iommu ac97 secureip -FILESKIP = grcan.vhd ddr2.v mobile_ddr.v +FILESKIP = grcan.vhd ddr2.v mobile_ddr.v sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/leon3-xilinx-vc707/README.txt b/designs/leon3-xilinx-vc707/README.txt index 44c0c796..07e13385 100644 --- a/designs/leon3-xilinx-vc707/README.txt +++ b/designs/leon3-xilinx-vc707/README.txt @@ -9,7 +9,7 @@ additional information. Note: The Vivado flow and parts of this design are still experimental. Currently the design configuration should be left as-is. -Note: You must have both Vivado 2013.2 and Xilinx ISE 14.6 in your +Note: You must have both Vivado 2013.3 and Xilinx ISE 14.6 in your path for the make targets to work. Simulation and synthesis @@ -46,8 +46,7 @@ To simulate using Aldec Riviera use the following make targets: make soft make riviera-launch -Synthesis will ONLY work with Vivado 2013.03 installed or newer, and -the XILINX variable properly set in the shell. To synthesize the design, do +To synthesize the design, do make vivado diff --git a/designs/leon3-xilinx-vc707/ahbram_sim.vhd b/designs/leon3-xilinx-vc707/ahbram_sim.vhd new file mode 100644 index 00000000..f4f6fb62 --- /dev/null +++ b/designs/leon3-xilinx-vc707/ahbram_sim.vhd @@ -0,0 +1,361 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: ahbram +-- File: ahbram.vhd +-- Author: Jiri Gaisler - Gaisler Research +-- Modified: Jan Andersson - Aeroflex Gaisler +-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write. +-- Added Sx-Record read function +------------------------------------------------------------------------------ + +-- pragma translate_off + +library ieee; +use ieee.std_logic_1164.all; +use std.textio.all; +use IEEE.Numeric_Std.all; + +library grlib; +use grlib.config_types.all; +use grlib.config.all; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +use grlib.stdio.all; + +library techmap; +use techmap.gencomp.all; + +entity ahbram_sim is + generic ( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#fff#; + tech : integer := DEFMEMTECH; + kbytes : integer := 1; + pipe : integer := 0; + maccsz : integer := AHBDW; + fname : string := "ram.dat" + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type + ); +end; + +architecture rtl of ahbram_sim is + +constant abits : integer := log2ext(kbytes) + 8 - maccsz/64; + +constant dw : integer := maccsz; + +constant hconfig : ahb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0), + 4 => ahb_membar(haddr, '1', '1', hmask), + others => zero32); + + +type reg_type is record + hwrite : std_ulogic; + hready : std_ulogic; + hsel : std_ulogic; + addr : std_logic_vector(abits-1+log2(dw/8) downto 0); + size : std_logic_vector(2 downto 0); + prdata : std_logic_vector((dw-1)*pipe downto 0); + pwrite : std_ulogic; + pready : std_ulogic; +end record; + +constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; +constant RES : reg_type := + (hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'), + size => (others => '0'), prdata => (others => '0'), pwrite => '0', + pready => '1'); + + +signal r, c : reg_type; +signal ramsel : std_logic_vector(dw/8-1 downto 0); +signal write : std_logic_vector(dw/8-1 downto 0); +signal ramaddr : std_logic_vector(abits-1 downto 0); +signal ramdata : std_logic_vector(dw-1 downto 0); +signal hwdata : std_logic_vector(dw-1 downto 0); + +type ram_type is array (0 to (2**ramaddr'length)-1) of std_logic_vector(ramdata'range); +signal ram : ram_type; +signal read_address : std_logic_vector(ramaddr'range); + +begin + + comb : process (ahbsi, r, rst, ramdata) + variable bs : std_logic_vector(dw/8-1 downto 0); + variable v : reg_type; + variable haddr : std_logic_vector(abits-1 downto 0); + variable hrdata : std_logic_vector(dw-1 downto 0); + variable seldata : std_logic_vector(dw-1 downto 0); + variable raddr : std_logic_vector(3 downto 2); + variable adsel : std_logic; + begin + v := r; v.hready := '1'; bs := (others => '0'); + v.pready := r.hready; + if pipe=0 then + adsel := r.hwrite or not r.hready; + else + adsel := r.hwrite or r.pwrite; + v.hready := r.hready or not r.pwrite; + end if; + if adsel = '1' then + haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8)); + else + haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8)); + bs := (others => '0'); + end if; + raddr := (others => '0'); + + v.pwrite := '0'; + if pipe/=0 and (r.hready='1' or r.pwrite='0') then + v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0); + end if; + if ahbsi.hready = '1' then + if pipe=0 then + v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0); + end if; + v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1); + v.size := ahbsi.hsize(2 downto 0); + v.hwrite := ahbsi.hwrite and v.hsel; + if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then + v.hready := '0'; + v.pwrite := r.hwrite; + end if; + end if; + + if r.hwrite = '1' then + case r.size is + when HSIZE_BYTE => + bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1'; + when HSIZE_HWORD => + for i in 0 to dw/16-1 loop + if i = conv_integer(r.addr(log2(dw/16) downto 1)) then + bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1'); + end if; + end loop; -- i + when HSIZE_WORD => + if dw = 32 then bs := (others => '1'); + else + for i in 0 to dw/32-1 loop + if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then + bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1'); + end if; + end loop; -- i + end if; + when HSIZE_DWORD => + if dw = 32 then null; + elsif dw = 64 then bs := (others => '1'); + else + for i in 0 to dw/64-1 loop + if i = conv_integer(r.addr(3)) then + bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1'); + end if; + end loop; -- i + end if; + when HSIZE_4WORD => + if dw < 128 then null; + elsif dw = 128 then bs := (others => '1'); + else + for i in 0 to dw/64-1 loop + if i = conv_integer(r.addr(3)) then + bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1'); + end if; + end loop; -- i + end if; + when others => --HSIZE_8WORD + if dw < 256 then null; + else bs := (others => '1'); end if; + end case; + v.hready := not (v.hsel and not ahbsi.hwrite); + v.hwrite := v.hwrite and v.hready; + end if; + + -- Duplicate read data on word basis, unless CORE_ACDM is enabled + if CORE_ACDM = 0 then + if dw = 32 then + seldata := ramdata; + elsif dw = 64 then + if r.size = HSIZE_DWORD then seldata := ramdata; else + if r.addr(2) = '0' then + seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2); + else + seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); + end if; + seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0); + end if; + elsif dw = 128 then + if r.size = HSIZE_4WORD then + seldata := ramdata; + elsif r.size = HSIZE_DWORD then + if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2); + else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if; + seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0); + else + raddr := r.addr(3 downto 2); + case raddr is + when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4); + when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4); + when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4); + when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0); + end case; + seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) & + seldata(dw/4-1 downto 0) & + seldata(dw/4-1 downto 0); + end if; + else + seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size); + end if; + else + seldata := ramdata; + end if; + + if pipe = 0 then + v.prdata := (others => '0'); + hrdata := seldata; + else + v.prdata := seldata; + hrdata := r.prdata; + end if; + + + if (not RESET_ALL) and (rst = '0') then + v.hwrite := RES.hwrite; v.hready := RES.hready; + end if; + write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop; + ramaddr <= haddr; c <= v; + + ahbso.hrdata <= ahbdrivedata(hrdata); + ahbso.hready <= r.hready; + + end process; + + ahbso.hresp <= "00"; + ahbso.hsplit <= (others => '0'); + ahbso.hirq <= (others => '0'); + ahbso.hconfig <= hconfig; + ahbso.hindex <= hindex; + + -- Select correct write data + hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2), + conv_std_logic_vector(log2(dw/8), 3)); + +-- aram : syncrambw generic map (tech, abits, dw, scantest) port map ( +-- clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin); + RamProc: process(clk) is + + variable L1 : line; + variable FIRST : boolean := true; + variable ADR : std_logic_vector(19 downto 0); + variable BUF : std_logic_vector(31 downto 0); + variable CH : character; + variable ai : integer := 0; + variable len : integer := 0; + file TCF : text open read_mode is fname; + variable rectype : std_logic_vector(3 downto 0); + variable recaddr : std_logic_vector(31 downto 0); + variable reclen : std_logic_vector(7 downto 0); + variable recdata : std_logic_vector(0 to 16*8-1); + + begin + if rising_edge(clk) then + if conv_integer(write) > 0 then + for i in 0 to dw/8-1 loop + if (write(i) = '1') then + ram(to_integer(unsigned(ramaddr)))(i*8+7 downto 0) <= hwdata(i*8+7 downto 0); + end if; + end loop; + end if; + read_address <= ramaddr; + end if; + + if (rst = '0') and (FIRST = true) then + ram <= (others => (others => '0')); + + L1:= new string'(""); + while not endfile(TCF) loop + readline(TCF,L1); + if (L1'length /= 0) then --' + while (not (L1'length=0)) and (L1(L1'left) = ' ') loop + std.textio.read(L1,CH); + end loop; + + if L1'length > 0 then --' + read(L1, ch); + if (ch = 'S') or (ch = 's') then + hread(L1, rectype); + hread(L1, reclen); + len := conv_integer(reclen)-1; + recaddr := (others => '0'); + case rectype is + when "0001" => + hread(L1, recaddr(15 downto 0)); + when "0010" => + hread(L1, recaddr(23 downto 0)); + when "0011" => + hread(L1, recaddr); + when others => next; + end case; + hread(L1, recdata); + + recaddr(31 downto abits+2) := (others => '0'); + ai := conv_integer(recaddr)/4; + for i in 0 to 3 loop + ram(ai+i) <= recdata((i*32) to (i*32+31)); + end loop; + + if ai = 0 then + ai := 1; + end if; + end if; + end if; + end if; + end loop; + + FIRST := false; + + end if; + + end process RamProc; + + ramdata <= ram(to_integer(unsigned(read_address))); + + reg : process (clk) + begin + if rising_edge(clk) then + r <= c; + if RESET_ALL and rst = '0' then + r <= RES; + end if; + end if; + end process; + + bootmsg : report_version + generic map ("ahbram" & tost(hindex) & + ": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes"); +end; + +-- pragma translate_on diff --git a/designs/leon3-xilinx-vc707/config.h b/designs/leon3-xilinx-vc707/config.h index 346af880..a5c8f894 100644 --- a/designs/leon3-xilinx-vc707/config.h +++ b/designs/leon3-xilinx-vc707/config.h @@ -99,19 +99,19 @@ #define CONFIG_IU_NWINDOWS (8) #define CONFIG_IU_V8MULDIV 1 #undef CONFIG_IU_MUL_LATENCY_2 -#define CONFIG_IU_MUL_LATENCY_4 1 -#undef CONFIG_IU_MUL_LATENCY_5 +#undef CONFIG_IU_MUL_LATENCY_4 +#define CONFIG_IU_MUL_LATENCY_5 1 #undef CONFIG_IU_MUL_MAC #define CONFIG_IU_MUL_INFERRED 1 #undef CONFIG_IU_MUL_MODGEN #undef CONFIG_IU_MUL_TECHSPEC #undef CONFIG_IU_MUL_DW #define CONFIG_IU_BP 1 -#undef CONFIG_IU_SVT +#define CONFIG_IU_SVT 1 #undef CONFIG_NOTAG #define CONFIG_IU_LDELAY (1) #define CONFIG_IU_WATCHPOINTS (2) -#undef CONFIG_PWD +#define CONFIG_PWD 1 #define CONFIG_IU_RSTADDR 00000 /* * Floating-point unit @@ -122,9 +122,9 @@ */ #define CONFIG_ICACHE_ENABLE 1 #undef CONFIG_ICACHE_ASSO1 -#undef CONFIG_ICACHE_ASSO2 +#define CONFIG_ICACHE_ASSO2 1 #undef CONFIG_ICACHE_ASSO3 -#define CONFIG_ICACHE_ASSO4 1 +#undef CONFIG_ICACHE_ASSO4 #undef CONFIG_ICACHE_SZ1 #undef CONFIG_ICACHE_SZ2 #define CONFIG_ICACHE_SZ4 1 @@ -134,18 +134,18 @@ #undef CONFIG_ICACHE_SZ64 #undef CONFIG_ICACHE_SZ128 #undef CONFIG_ICACHE_SZ256 -#undef CONFIG_ICACHE_LZ16 -#define CONFIG_ICACHE_LZ32 1 -#undef CONFIG_ICACHE_ALGORND -#define CONFIG_ICACHE_ALGODIR 1 +#define CONFIG_ICACHE_LZ16 1 +#undef CONFIG_ICACHE_LZ32 +#define CONFIG_ICACHE_ALGORND 1 +#undef CONFIG_ICACHE_ALGODIR #undef CONFIG_ICACHE_ALGOLRR #undef CONFIG_ICACHE_ALGOLRU -#define CONFIG_ICACHE_LOCK 1 +#undef CONFIG_ICACHE_LOCK #define CONFIG_DCACHE_ENABLE 1 #undef CONFIG_DCACHE_ASSO1 -#undef CONFIG_DCACHE_ASSO2 +#define CONFIG_DCACHE_ASSO2 1 #undef CONFIG_DCACHE_ASSO3 -#define CONFIG_DCACHE_ASSO4 1 +#undef CONFIG_DCACHE_ASSO4 #undef CONFIG_DCACHE_SZ1 #undef CONFIG_DCACHE_SZ2 #define CONFIG_DCACHE_SZ4 1 @@ -155,15 +155,14 @@ #undef CONFIG_DCACHE_SZ64 #undef CONFIG_DCACHE_SZ128 #undef CONFIG_DCACHE_SZ256 -#undef CONFIG_DCACHE_LZ16 -#define CONFIG_DCACHE_LZ32 1 -#undef CONFIG_DCACHE_ALGORND -#define CONFIG_DCACHE_ALGODIR 1 +#define CONFIG_DCACHE_LZ16 1 +#undef CONFIG_DCACHE_LZ32 +#define CONFIG_DCACHE_ALGORND 1 +#undef CONFIG_DCACHE_ALGODIR #undef CONFIG_DCACHE_ALGOLRR #undef CONFIG_DCACHE_ALGOLRU -#define CONFIG_DCACHE_LOCK 1 +#undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* @@ -234,6 +233,17 @@ #define CONFIG_DSU_UART 1 #define CONFIG_DSU_JTAG 1 #undef CONFIG_GRUSB_DCL +#define CONFIG_DSU_ETH 1 +#undef CONFIG_DSU_ETHSZ1 +#undef CONFIG_DSU_ETHSZ2 +#undef CONFIG_DSU_ETHSZ4 +#undef CONFIG_DSU_ETHSZ8 +#define CONFIG_DSU_ETHSZ16 1 +#define CONFIG_DSU_IPMSB C0A8 +#define CONFIG_DSU_IPLSB 0033 +#define CONFIG_DSU_ETHMSB 020000 +#define CONFIG_DSU_ETHLSB 000000 +#undef CONFIG_DSU_ETH_PROG /* * Peripherals */ @@ -256,7 +266,7 @@ * MIG Series 7 memory controller */ #define CONFIG_MIG_SERIES7 1 -#undef CONFIG_MIG_SERIES_7_MODEL +#define CONFIG_MIG_SERIES_7_MODEL 1 #undef CONFIG_AHBSTAT_ENABLE /* * On-chip RAM/ROM @@ -281,7 +291,14 @@ /* * Ethernet */ -#undef CONFIG_GRETH_ENABLE +#define CONFIG_GRETH_ENABLE 1 +#undef CONFIG_GRETH_GIGA +#undef CONFIG_GRETH_FIFO4 +#define CONFIG_GRETH_FIFO8 1 +#undef CONFIG_GRETH_FIFO16 +#undef CONFIG_GRETH_FIFO32 +#undef CONFIG_GRETH_FIFO64 +#undef CONFIG_GRETH_FT /* * USB 2.0 Host Controller */ diff --git a/designs/leon3-xilinx-vc707/config.help b/designs/leon3-xilinx-vc707/config.help index 97a03801..ca870e76 100644 --- a/designs/leon3-xilinx-vc707/config.help +++ b/designs/leon3-xilinx-vc707/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-vc707/config.vhd b/designs/leon3-xilinx-vc707/config.vhd index 77309cf3..0cf107f3 100644 --- a/designs/leon3-xilinx-vc707/config.vhd +++ b/designs/leon3-xilinx-vc707/config.vhd @@ -33,33 +33,33 @@ package config is constant CFG_LEON3 : integer := 1; constant CFG_NCPU : integer := (1); constant CFG_NWIN : integer := (8); - constant CFG_V8 : integer := 1 + 4*0; + constant CFG_V8 : integer := 2 + 4*0; constant CFG_MAC : integer := 0; constant CFG_BP : integer := 1; - constant CFG_SVT : integer := 0; + constant CFG_SVT : integer := 1; constant CFG_RSTADDR : integer := 16#00000#; constant CFG_LDDEL : integer := (1); constant CFG_NOTAG : integer := 0; constant CFG_NWP : integer := (2); - constant CFG_PWD : integer := 0*2; + constant CFG_PWD : integer := 1*2; constant CFG_FPU : integer := 0 + 16*0 + 32*0; constant CFG_GRFPUSH : integer := 0; constant CFG_ICEN : integer := 1; - constant CFG_ISETS : integer := 4; + constant CFG_ISETS : integer := 2; constant CFG_ISETSZ : integer := 4; - constant CFG_ILINE : integer := 8; - constant CFG_IREPL : integer := 3; - constant CFG_ILOCK : integer := 1; + constant CFG_ILINE : integer := 4; + constant CFG_IREPL : integer := 2; + constant CFG_ILOCK : integer := 0; constant CFG_ILRAMEN : integer := 0; constant CFG_ILRAMADDR: integer := 16#8E#; constant CFG_ILRAMSZ : integer := 1; constant CFG_DCEN : integer := 1; - constant CFG_DSETS : integer := 4; + constant CFG_DSETS : integer := 2; constant CFG_DSETSZ : integer := 4; - constant CFG_DLINE : integer := 8; - constant CFG_DREPL : integer := 3; - constant CFG_DLOCK : integer := 1; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DLINE : integer := 4; + constant CFG_DREPL : integer := 2; + constant CFG_DLOCK : integer := 0; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; @@ -102,12 +102,12 @@ package config is constant CFG_GRUSB_DCL_UIFACE : integer := 1; constant CFG_GRUSB_DCL_DW : integer := 8; -- Ethernet DSU - constant CFG_DSU_ETH : integer := 0 + 0 + 0; - constant CFG_ETH_BUF : integer := 1; + constant CFG_DSU_ETH : integer := 1 + 0 + 0; + constant CFG_ETH_BUF : integer := 16; constant CFG_ETH_IPM : integer := 16#C0A8#; constant CFG_ETH_IPL : integer := 16#0033#; constant CFG_ETH_ENM : integer := 16#020000#; - constant CFG_ETH_ENL : integer := 16#000009#; + constant CFG_ETH_ENL : integer := 16#000000#; -- LEON2 memory controller constant CFG_MCTRL_LEON2 : integer := 1; constant CFG_MCTRL_RAM8BIT : integer := 1; @@ -144,7 +144,7 @@ package config is constant CFG_AHBRADDR : integer := 16#A00#; constant CFG_AHBRPIPE : integer := 0; -- Gaisler Ethernet core - constant CFG_GRETH : integer := 0; + constant CFG_GRETH : integer := 1; constant CFG_GRETH1G : integer := 0; constant CFG_ETH_FIFO : integer := 8; diff --git a/designs/leon3-xilinx-vc707/config.vhd.h b/designs/leon3-xilinx-vc707/config.vhd.h index b7402209..e287663e 100644 --- a/designs/leon3-xilinx-vc707/config.vhd.h +++ b/designs/leon3-xilinx-vc707/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-vc707/lconfig.tk b/designs/leon3-xilinx-vc707/lconfig.tk index 5c0bcb86..f767d4f0 100755 --- a/designs/leon3-xilinx-vc707/lconfig.tk +++ b/designs/leon3-xilinx-vc707/lconfig.tk @@ -2096,24 +2096,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2185,20 +2184,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2331,9 +2327,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3222,7 +3215,7 @@ proc menu12 {w title} { hex $w.config.f 12 8 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 9 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 10 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 11 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 11 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3274,12 +3267,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x8.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x8.l configure -state normal; } else {.menu12.config.f.x8.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x8.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x9.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x9.l configure -state normal; } else {.menu12.config.f.x9.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x9.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x10 normal {n l y}} else {configure_entry .menu12.config.f.x10 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x11 normal {n l y}} else {configure_entry .menu12.config.f.x11 disabled {y n l}} } @@ -3317,12 +3309,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -6253,7 +6244,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -6590,6 +6580,7 @@ set CONFIG_LEON3FT_PRESENT 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_MODULES 4 proc writeconfig {file1 file2} { set cfg [open $file1 w] @@ -7034,7 +7025,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -7185,10 +7175,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controller " write_comment $cfg $autocfg "Leon2 memory controller " @@ -7264,6 +7253,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_31 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-vc707/leon3mp.vhd b/designs/leon3-xilinx-vc707/leon3mp.vhd index 68f0efde..ec135e87 100644 --- a/designs/leon3-xilinx-vc707/leon3mp.vhd +++ b/designs/leon3-xilinx-vc707/leon3mp.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -133,7 +133,11 @@ component sgmii_vc707 pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; - autonegotiation : integer := 1 + abits : integer := 8; + autonegotiation : integer := 1; + pirq : integer := 0; + debugmem : integer := 0; + tech : integer := 0 ); port( sgmiii : in eth_sgmii_in_type; @@ -141,7 +145,6 @@ component sgmii_vc707 gmiii : out eth_in_type; gmiio : in eth_out_type; reset : in std_logic; -- Asynchronous reset for entire core. - button : in std_logic; apb_clk : in std_logic; apb_rstn : in std_logic; apbi : in apb_slv_in_type; @@ -213,6 +216,28 @@ component ddr_dummy ); end component ; +-- pragma translate_off +component ahbram_sim + generic ( + hindex : integer := 0; + haddr : integer := 0; + hmask : integer := 16#fff#; + tech : integer := DEFMEMTECH; + kbytes : integer := 1; + pipe : integer := 0; + maccsz : integer := AHBDW; + fname : string := "ram.dat" + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type + ); +end component ; +-- pragma translate_on + + --constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_GRUSBHC+CFG_GRUSBDC+CFG_GRUSB_DCL; constant maxahbm : integer := 16; --constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2+CFG_GRUSBDC; @@ -237,7 +262,8 @@ signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); signal vahbmo : ahb_mst_out_type; signal ui_clk : std_ulogic; -signal clkm, rstn, rstraw, sdclkl : std_ulogic; +signal clkm : std_ulogic := '0'; +signal rstn, rstraw, sdclkl : std_ulogic; signal clk_200 : std_ulogic; signal clk25, clk40, clk65 : std_ulogic; @@ -262,7 +288,6 @@ signal sgmiii : eth_sgmii_in_type; signal sgmiio : eth_sgmii_out_type; signal sgmiirst : std_logic; -signal buttonsgmi : std_logic; signal ethernet_phy_int : std_logic; @@ -349,7 +374,7 @@ begin rst1 : rstgen -- reset generator generic map (acthigh => 1) - port map (rst, clkm, '1', migrstn, open); + port map (rst, clkm, lock, migrstn, open); ---------------------------------------------------------------------- --- AHB CONTROLLER -------------------------------------------------- @@ -527,6 +552,7 @@ begin ---------------------------------------------------------------------- mig_gen : if (CFG_MIG_SERIES7 = 1) generate + gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate ddrc : ahb2mig_series7 generic map( hindex => 4, haddr => 16#400#, hmask => 16#C00#, pindex => 4, paddr => 4, @@ -566,6 +592,56 @@ begin clkgenmigref0 : clkgen generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000) port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open); + end generate gen_mig; + + gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate + -- pragma translate_off + + mig_ahbram : ahbram_sim + generic map ( + hindex => 4, + haddr => 16#400#, + hmask => 16#C00#, + tech => 0, + kbytes => 1000, + pipe => 0, + maccsz => AHBDW, + fname => "ram.srec" + ) + port map( + rst => rstn, + clk => clkm, + ahbsi => ahbsi, + ahbso => ahbso(4) + ); + + ddr3_dq <= (others => 'Z'); + ddr3_dqs_p <= (others => 'Z'); + ddr3_dqs_n <= (others => 'Z'); + ddr3_addr <= (others => '0'); + ddr3_ba <= (others => '0'); + ddr3_ras_n <= '0'; + ddr3_cas_n <= '0'; + ddr3_we_n <= '0'; + ddr3_reset_n <= '1'; + ddr3_ck_p <= (others => '0'); + ddr3_ck_n <= (others => '0'); + ddr3_cke <= (others => '0'); + ddr3_cs_n <= (others => '0'); + ddr3_dm <= (others => '0'); + ddr3_odt <= (others => '0'); + + --calib_done : out std_logic; + calib_done <= '1'; + + --ui_clk : out std_logic; + clkm <= not clkm after 5.0 ns; + + --ui_clk_sync_rst : out std_logic + -- n/a + -- pragma translate_on + + end generate gen_mig_model; end generate; @@ -613,12 +689,12 @@ begin e1 : grethm generic map( hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG, - pindex => 14, paddr => 14, pirq => 12, memtech => memtech, + pindex => 14, paddr => 16#800#, pmask => 16#f00#, pirq => 12, memtech => memtech, mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO, nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7, macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1, ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, - giga => CFG_GRETH1G) + giga => CFG_GRETH1G, ramdebug => 0, gmiimode => 1) port map( rst => rstn, clk => clkm, ahbmi => ahbmi, ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio); @@ -627,10 +703,14 @@ begin sgmii0 : sgmii_vc707 generic map( - pindex => 11, - paddr => 11, - pmask => 16#fff#, - autonegotiation => autonegotiation + pindex => 11, + paddr => 16#010#, + pmask => 16#ff0#, + abits => 8, + autonegotiation => autonegotiation, + pirq => 11, + debugmem => 1, + tech => fabtech ) port map( sgmiii => sgmiii, @@ -638,16 +718,12 @@ begin gmiii => gmiii, gmiio => gmiio, reset => sgmiirst, - button => buttonsgmi, apb_clk => clkm, apb_rstn => rstn, apbi => apbi, apbo => apbo(11) ); - pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v) port map (button(2), buttonsgmi); - - emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v) port map (emdio, sgmiio.mdio_o, sgmiio.mdio_oe, sgmiii.mdio_i); @@ -666,7 +742,7 @@ begin txn <= sgmiio.txn; sgmiii.rxp <= rxp; sgmiii.rxn <= rxn; - + end generate; noeth0 : if CFG_GRETH = 0 generate @@ -829,7 +905,7 @@ begin ---------------------------------------------------------------------- apb0 : apbctrl -- AHB/APB bridge - generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16) + generic map (hindex => 1, haddr => CFG_APBADDR, hmask => 16#F00#, nslaves => 16) port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); irqctrl : if CFG_IRQ3_ENABLE /= 0 generate diff --git a/designs/leon3-xilinx-vc707/mig_interface_model.v b/designs/leon3-xilinx-vc707/mig_interface_model.v index 809240af..9caa34c5 100644 --- a/designs/leon3-xilinx-vc707/mig_interface_model.v +++ b/designs/leon3-xilinx-vc707/mig_interface_model.v @@ -4,20 +4,6 @@ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2012, Aeroflex Gaisler --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- -- Entity: mig_interface_model -- File: mig_interface_model.v diff --git a/designs/leon3-xilinx-vc707/preload_ddr3_dimm.do b/designs/leon3-xilinx-vc707/preload_ddr3_dimm.do deleted file mode 100644 index c4ab1091..00000000 --- a/designs/leon3-xilinx-vc707/preload_ddr3_dimm.do +++ /dev/null @@ -1,52 +0,0 @@ -# Procedure to load memory from file -proc reload_mem {} { - # Load memory with system test and display memory - if {[examine /testbench/led(3)] == 1} { - if {[examine sim:/config@work/CFG_MIG_SERIES7] == 1} { - echo "Loading DDR3 memory with System Test" - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == FALSE} { - mem load -startaddress 0 -format hex -infile sdram_dimm1.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(0)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm2.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(1)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm3.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(2)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm4.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(3)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm5.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(4)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm6.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(5)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm7.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(6)/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm8.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(7)/u1/memory - - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(0)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(1)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(2)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(3)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(4)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(5)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(6)/u1/address - mem load -startaddress 0 -format hex -filltype incr -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem(7)/u1/address - - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(0)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(1)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(2)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(3)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(4)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(5)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(6)/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem(7)/u1/memory_used 1111111111111111 - } - - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == TRUE} { - echo "MIG Model found" - mem load -startaddress 0 -format hex -infile sdram_dimm_merge.hex -filltype value -filldata 1'b0 sim:/testbench/cpu/mig_gen/ddrc/gen_mig_model/MCB_model_inst/Mem - } - - #do wave.do - } - } -} - -set init_path /testbench/led(3); - -when -label when1 "$init_path'event and $init_path ='1'" { - reload_mem -} - -#run 2 ms diff --git a/designs/leon3-xilinx-vc707/ram.srec b/designs/leon3-xilinx-vc707/ram.srec index a896a74b..75f5a4c3 100755 --- a/designs/leon3-xilinx-vc707/ram.srec +++ b/designs/leon3-xilinx-vc707/ram.srec @@ -1,11 +1,11 @@ S00B000072616D2E73726563D9 -S31540000000881000000910006C81C1234401000000E3 +S31540000000881000000910007E81C1209C010000007C S31540000010A1480000A75000001080203EAC102001EF S3154000002091D0200001000000010000000100000006 S3154000003091D02000010000000100000001000000F6 -S31540000040A14800002910006C81C5229801000000DB -S31540000050A14800002910006981C523500100000015 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100644 index 6206a2bb..00000000 --- a/designs/leon3-xilinx-vc707/riviera_preload_ddr3_dimm.do +++ /dev/null @@ -1,55 +0,0 @@ -# Procedure to load memory from file -proc reload_mem {} { - # Load memory with system test and display memory - if {[examine /testbench/led(3)] == 1} { - if {[examine sim:/work.config/CFG_MIG_SERIES7] == 1} { - echo "Loading DDR3 memory with System Test" - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == false} { - mem load -startaddress 0 -format hex -infile sdram_dimm1.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__0/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm2.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__1/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm3.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__2/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm4.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__3/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm5.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__4/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm6.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__5/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm7.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__6/u1/memory - mem load -startaddress 0 -format hex -infile sdram_dimm8.hex -filltype value -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__7/u1/memory - - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__0/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__1/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__2/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__3/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__4/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__5/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__6/u1/address - mem load -startaddress 0 -format hex -filltype inc -filldata 1'b0 sim:/testbench/gen_mem_model/ddr3mem/gen_mem__7/u1/address - - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__0/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__1/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__2/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__3/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__4/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__5/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__6/u1/memory_used 1111111111111111 - change sim:/testbench/gen_mem_model/ddr3mem/gen_mem__7/u1/memory_used 1111111111111111 - } - - if {[examine /testbench/USE_MIG_INTERFACE_MODEL] == true} { - echo "MIG Model found" - mem load -startaddress 0 -endaddress 65535 -format hex -infile sdram_dimm_merge.hex -filltype value -filldata 1'b0 sim:/testbench/cpu/mig_gen/ddrc/gen_mig_model/MCB_model_inst/Mem - } - - #do wave.do - } - } -} - -set init_path /testbench/led(3); - -when -label when1 {$init_path and $init_path =1} { - echo "MIG Init Complete" - reload_mem -} - -#do wave.awc - -#run 2 ms \ No newline at end of file diff --git a/designs/leon3-xilinx-vc707/sgmii_vc707.vhd b/designs/leon3-xilinx-vc707/sgmii_vc707.vhd index 6b695dc3..77e4253e 100644 --- a/designs/leon3-xilinx-vc707/sgmii_vc707.vhd +++ b/designs/leon3-xilinx-vc707/sgmii_vc707.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -68,22 +68,34 @@ -- -------------------------------------------------------------------------------- - -library unisim; -use unisim.vcomponents.all; - library ieee; use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library gaisler; +use gaisler.net.all; +use gaisler.misc.all; library grlib; +use grlib.config_types.all; +use grlib.config.all; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; -library gaisler; -use gaisler.misc.all; -use gaisler.net.all; +library techmap; +use techmap.gencomp.all; +use techmap.allclkgen.all; + +library techmap; +use techmap.gencomp.all; +use techmap.allclkgen.all; + +library eth; +use eth.grethpkg.all; +library unisim; +use unisim.vcomponents.all; -------------------------------------------------------------------------------- -- The entity declaration for the example design @@ -94,7 +106,12 @@ entity sgmii_vc707 is pindex : integer := 0; paddr : integer := 0; pmask : integer := 16#fff#; - autonegotiation : integer := 1 + abits : integer := 8; + autonegotiation : integer := 1; + pirq : integer := 0; + debugmem : integer := 0; + tech : integer := 0; + simulation : integer := 0 ); port( -- Tranceiver Interface @@ -105,7 +122,6 @@ entity sgmii_vc707 is gmiio : in eth_out_type; -- Asynchronous reset for entire core. reset : in std_logic; - button : in std_logic; -- APB Status bus apb_clk : in std_logic; apb_rstn : in std_logic; @@ -170,15 +186,15 @@ architecture top_level of sgmii_vc707 is -- Speed Control ---------------- speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds - speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed + speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed -- General IO's --------------- status_vector : out std_logic_vector(15 downto 0); -- Core status. - reset : in std_logic; -- Asynchronous reset for entire core. + reset : in std_logic; -- Asynchronous reset for entire core. signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input. gt0_qplloutclk_in : in std_logic; -- Input from PMD to indicate presence of optical input. - gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input. + gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input. ); @@ -277,6 +293,19 @@ component IBUFDS_GTE2 ); end component; +----- component BUFHCE ----- +component BUFHCE + generic ( + CE_TYPE : string := "SYNC"; + INIT_OUT : integer := 0 + ); + port ( + O : out std_ulogic; + CE : in std_ulogic; + I : in std_ulogic + ); +end component; + ----- component BUFGMUX ----- component BUFGMUX generic ( @@ -290,10 +319,79 @@ component BUFGMUX ); end component; +----- component ODDR ----- +component ODDR + generic ( + DDR_CLK_EDGE : string := "OPPOSITE_EDGE"; + INIT : bit := '0'; + SRTYPE : string := "SYNC" + ); + port ( + Q : out std_ulogic; + C : in std_ulogic; + CE : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + R : in std_ulogic := 'L'; + S : in std_ulogic := 'L' + ); +end component; + +constant REVISION : integer := 1; + constant pconfig : apb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, 0, 0), + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); + type sgmiiregs is record + irq : std_logic_vector(31 downto 0); -- interrupt + mask : std_logic_vector(31 downto 0); -- interrupt enable + configuration_vector : std_logic_vector( 4 downto 0); + an_adv_config_vector : std_logic_vector(15 downto 0); + end record; + + -- APB and RGMII control register + constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; + + constant RES_configuration_vector : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(autonegotiation,1)) & "0000"; + + constant RES : sgmiiregs := + ( irq => (others => '0'), mask => (others => '0'), + configuration_vector => RES_configuration_vector, an_adv_config_vector => "0001100000000001"); + + type rxregs is record + gmii_rxd : std_logic_vector(7 downto 0); + gmii_rxd_int : std_logic_vector(7 downto 0); + gmii_rx_dv : std_logic; + gmii_rx_er : std_logic; + count : integer; + gmii_dv : std_logic; + keepalive : integer; + end record; + + constant RESRX : rxregs := + ( gmii_rxd => (others => '0'), gmii_rxd_int => (others => '0'), + gmii_rx_dv => '0', gmii_rx_er => '0', + count => 0, gmii_dv => '0', keepalive => 0 + ); + + type txregs is record + gmii_txd : std_logic_vector(7 downto 0); + gmii_txd_int : std_logic_vector(7 downto 0); + gmii_tx_en : std_logic; + gmii_tx_en_int : std_logic; + gmii_tx_er : std_logic; + count : integer; + cnt_en : std_logic; + keepalive : integer; + end record; + + constant RESTX : txregs := + ( gmii_txd => (others => '0'), gmii_txd_int => (others => '0'), + gmii_tx_en => '0', gmii_tx_en_int => '0', gmii_tx_er => '0', + count => 0, cnt_en => '0', keepalive => 0 + ); + ------------------------------------------------------------------------------ -- internal signals used in this top level example design. ------------------------------------------------------------------------------ @@ -332,16 +430,17 @@ constant pconfig : apb_config_type := ( signal gmii_rx_dv : std_logic; signal gmii_rx_er : std_logic; signal gmii_isolate : std_logic; - signal gmii_txd_int : std_logic_vector(7 downto 0); - signal gmii_tx_en_int : std_logic; - signal gmii_tx_er_int : std_logic; + + -- Internal GMII signals from Xilinx SGMII block signal gmii_rxd_int : std_logic_vector(7 downto 0); signal gmii_rx_dv_int : std_logic; signal gmii_rx_er_int : std_logic; -- Extra registers to ease IOB placement - signal status_vector_int : std_logic_vector(15 downto 0); - signal status_vector_apb : std_logic_vector(15 downto 0); + signal status_vector_int : std_logic_vector(15 downto 0); + signal status_vector_apb : std_logic_vector(15 downto 0); + signal status_vector_apb1 : std_logic_vector(31 downto 0); + signal status_vector_apb2 : std_logic_vector(31 downto 0); -- These attributes will stop timing errors being reported in back annotated -- SDF simulation. @@ -360,15 +459,39 @@ constant pconfig : apb_config_type := ( signal an_restart_config : std_logic; signal link_timer_value : std_logic_vector(8 downto 0); - signal status_vector : std_logic_vector(15 downto 0); signal synchronization_done : std_logic; signal linkup : std_logic; signal signal_detect : std_logic; + -- Route gtrefclk through an IBUFG. + signal gtrefclk_buf_i : std_logic; + attribute clock_signal : string; attribute clock_signal of sgmii_clk : signal is "yes"; attribute clock_signal of sgmii_clk_int : signal is "yes"; + signal r, rin : sgmiiregs; + signal rrx,rinrx : rxregs; + signal rtx, rintx : txregs; + + signal cnt_en : std_logic; + + signal usr2rstn : std_logic; + + -- debug signal + signal WMemRgmiioData : std_logic_vector(15 downto 0); + signal RMemRgmiioData : std_logic_vector(15 downto 0); + signal RMemRgmiioAddr : std_logic_vector(9 downto 0); + signal WMemRgmiioAddr : std_logic_vector(9 downto 0); + signal WMemRgmiioWrEn : std_logic; + signal WMemRgmiiiData : std_logic_vector(15 downto 0); + signal RMemRgmiiiData : std_logic_vector(15 downto 0); + signal RMemRgmiiiAddr : std_logic_vector(9 downto 0); + signal WMemRgmiiiAddr : std_logic_vector(9 downto 0); + signal WMemRgmiiiWrEn : std_logic; + signal RMemRgmiiiRead : std_logic; + signal RMemRgmiioRead : std_logic; + begin ----------------------------------------------------------------------------- @@ -376,10 +499,9 @@ begin ----------------------------------------------------------------------------- -- Remove AN during simulation i.e. "00000" - configuration_vector <= "10000" when (autonegotiation = 1 or button = '1') else "00000"; + configuration_vector <= "10000" when (autonegotiation = 1) else "00000"; - --an_adv_config_vector <= x"4001"; - --an_adv_config_vector <= "0000000000100001"; + -- Configuration for Xilinx SGMII IP. See doc for SGMII IP for more information an_adv_config_vector <= "0001100000000001"; an_restart_config <= '0'; link_timer_value <= "000110010"; @@ -389,30 +511,28 @@ begin linkup <= status_vector_int(0); signal_detect <= '1'; - apbo.pindex <= pindex; - apbo.pconfig <= pconfig; - apbo.pirq <= (others => '0'); - apbo.prdata(31 downto 16) <= (others => '0'); - apbo.prdata(15 downto 0) <= status_vector_apb; - gmiii.gtx_clk <= userclk2; gmiii.tx_clk <= userclk2; gmiii.rx_clk <= userclk2; - gmii_txd <= gmiio.txd; - gmii_tx_en <= gmiio.tx_en; - gmii_tx_er <= gmiio.tx_er; + gmiii.rmii_clk <= userclk2; gmiii.rxd <= gmii_rxd; gmiii.rx_dv <= gmii_rx_dv; gmiii.rx_er <= gmii_rx_er; + gmiii.rx_en <= gmii_rx_dv or sgmii_clk_en; + --gmiii.tx_dv <= '1'; + gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1'; + + -- GMII output controlled via generics gmiii.edclsepahb <= '0'; gmiii.edcldisable <= '0'; gmiii.phyrstaddr <= (others => '0'); gmiii.edcladdr <= (others => '0'); - gmiii.rmii_clk <= sgmii_clk; + -- Not used gmiii.rx_col <= '0'; gmiii.rx_crs <= '0'; + gmiii.tx_clk_90 <= '0'; sgmiio.mdio_o <= gmiio.mdio_o; sgmiio.mdio_oe <= gmiio.mdio_oe; @@ -425,108 +545,129 @@ begin -- Transceiver Clock Management ----------------------------------------------------------------------------- - -- Clock circuitry for the GT Transceiver uses a differential input clock. - -- gtrefclk is routed to the tranceiver. - ibufds_gtrefclk : IBUFDS_GTE2 - port map ( - I => sgmiii.clkp, - IB => sgmiii.clkn, - CEB => '0', - O => gtrefclk, - ODIV2 => open - ); - - -- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is - -- routed to an MMCM module where it is used to create phase and frequency - -- related 62.5MHz and 125MHz clock sources - mmcm_adv_inst : MMCME2_ADV - generic map - (BANDWIDTH => "OPTIMIZED", - --CLKOUT4_CASCADE => FALSE, - COMPENSATION => "ZHOLD", --- STARTUP_WAIT => FALSE, - DIVCLK_DIVIDE => 1, - CLKFBOUT_MULT_F => 16.000, - CLKFBOUT_PHASE => 0.000, - --CLKFBOUT_USE_FINE_PS => FALSE, - CLKOUT0_DIVIDE_F => 8.000, - CLKOUT0_PHASE => 0.000, - CLKOUT0_DUTY_CYCLE => 0.5, - --CLKOUT0_USE_FINE_PS => FALSE, - CLKOUT1_DIVIDE => 16, - CLKOUT1_PHASE => 0.000, - CLKOUT1_DUTY_CYCLE => 0.5, - --CLKOUT1_USE_FINE_PS => FALSE, - CLKIN1_PERIOD => 16.0, - REF_JITTER1 => 0.010) - port map - -- Output clocks - (CLKFBOUT => clkfbout, - CLKFBOUTB => open, - CLKOUT0 => clkout0, - CLKOUT0B => open, - CLKOUT1 => clkout1, - CLKOUT1B => open, - CLKOUT2 => open, - CLKOUT2B => open, - CLKOUT3 => open, - CLKOUT3B => open, - CLKOUT4 => open, - CLKOUT5 => open, - CLKOUT6 => open, - -- Input clock control - CLKFBIN => clkfbout, - CLKIN1 => txoutclk, - CLKIN2 => '0', - -- Tied to always select the primary input clock - CLKINSEL => '1', - -- Ports for dynamic reconfiguration - DADDR => (others => '0'), - DCLK => '0', - DEN => '0', - DI => (others => '0'), - DO => open, - DRDY => open, - DWE => '0', - -- Ports for dynamic phase shift - PSCLK => '0', - PSEN => '0', - PSINCDEC => '0', - PSDONE => open, - -- Other control and status signals - LOCKED => mmcm_locked, - CLKINSTOPPED => open, - CLKFBSTOPPED => open, - PWRDWN => '0', - RST => mmcm_reset); - - mmcm_reset <= reset or (not resetdone); - - -- This 62.5MHz clock is placed onto global clock routing and is then used - -- for tranceiver TXUSRCLK/RXUSRCLK. - bufg_userclk: BUFG - port map ( - I => clkout1, - O => userclk - ); - - -- This 125MHz clock is placed onto global clock routing and is then used - -- to clock all Ethernet core logic. - bufg_userclk2: BUFG - port map ( - I => clkout0, - O => userclk2 - ); - - - -- This 62.5MHz clock is placed onto global clock routing and is then used - -- for tranceiver TXUSRCLK/RXUSRCLK. - bufg_rxuserclk: BUFG - port map ( - I => rxoutclk, - O => rxuserclk - ); + sgmii1 : if simulation = 1 generate + + end generate; + + sgmii0 : if simulation = 0 generate + + -- Clock circuitry for the GT Transceiver uses a differential input clock. + -- gtrefclk is routed to the tranceiver. + ibufds_gtrefclk : IBUFDS_GTE2 + port map ( + I => sgmiii.clkp, + IB => sgmiii.clkn, + CEB => '0', + O => gtrefclk_buf_i, + ODIV2 => open + ); + + bufhce_gtrefclk : BUFHCE + port map ( + I => gtrefclk_buf_i, + CE => '1', + O => gtrefclk + ); + + -- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is + -- routed to an MMCM module where it is used to create phase and frequency + -- related 62.5MHz and 125MHz clock sources + mmcm_adv_inst : MMCME2_ADV + generic map + (BANDWIDTH => "OPTIMIZED", + --CLKOUT4_CASCADE => FALSE, + COMPENSATION => "ZHOLD", + -- STARTUP_WAIT => FALSE, + DIVCLK_DIVIDE => 1, + CLKFBOUT_MULT_F => 16.000, + CLKFBOUT_PHASE => 0.000, + --CLKFBOUT_USE_FINE_PS => FALSE, + CLKOUT0_DIVIDE_F => 8.000, + CLKOUT0_PHASE => 0.000, + CLKOUT0_DUTY_CYCLE => 0.5, + --CLKOUT0_USE_FINE_PS => FALSE, + CLKOUT1_DIVIDE => 16, + CLKOUT1_PHASE => 0.000, + CLKOUT1_DUTY_CYCLE => 0.5, + --CLKOUT1_USE_FINE_PS => FALSE, + CLKIN1_PERIOD => 16.0, + REF_JITTER1 => 0.010) + port map + -- Output clocks + (CLKFBOUT => clkfbout, + CLKFBOUTB => open, + CLKOUT0 => clkout0, + CLKOUT0B => open, + CLKOUT1 => clkout1, + CLKOUT1B => open, + CLKOUT2 => open, + CLKOUT2B => open, + CLKOUT3 => open, + CLKOUT3B => open, + CLKOUT4 => open, + CLKOUT5 => open, + CLKOUT6 => open, + -- Input clock control + CLKFBIN => clkfbout, + CLKIN1 => txoutclk, + CLKIN2 => '0', + -- Tied to always select the primary input clock + CLKINSEL => '1', + -- Ports for dynamic reconfiguration + DADDR => (others => '0'), + DCLK => '0', + DEN => '0', + DI => (others => '0'), + DO => open, + DRDY => open, + DWE => '0', + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + -- Other control and status signals + LOCKED => mmcm_locked, + CLKINSTOPPED => open, + CLKFBSTOPPED => open, + PWRDWN => '0', + RST => mmcm_reset); + + mmcm_reset <= reset or (not resetdone); + + -- This 62.5MHz clock is placed onto global clock routing and is then used + -- for tranceiver TXUSRCLK/RXUSRCLK. + bufg_userclk: BUFG + port map ( + I => clkout1, + O => userclk + ); + + -- This 125MHz clock is placed onto global clock routing and is then used + -- to clock all Ethernet core logic. + bufg_userclk2: BUFG + port map ( + I => clkout0, + O => userclk2 + ); + + + -- This 62.5MHz clock is placed onto global clock routing and is then used + -- for tranceiver TXUSRCLK/RXUSRCLK. + bufg_rxuserclk: BUFG + port map ( + I => rxoutclk, + O => rxuserclk + ); + end generate; + + ----------------------------------------------------------------------------- + -- Sync Reset for user clock + ----------------------------------------------------------------------------- + userclk2_rst : rstgen + generic map(syncin => 1, syncrst => 1) + port map(apb_rstn, userclk2, '1', usr2rstn, open); ----------------------------------------------------------------------------- -- Transceiver PMA reset circuitry @@ -544,6 +685,106 @@ begin pma_reset <= pma_reset_pipe(3); + ------------------------------------------------------------------------------ + -- GMII (Aeroflex Gaisler) to GMII (Xilinx) style + ------------------------------------------------------------------------------ + + -- 10/100Mbit TX Loic + process (usr2rstn,rtx,gmiio) + variable v : txregs; + begin + v := rtx; + v.cnt_en := '0'; + v.gmii_tx_en_int := gmiio.tx_en; + + if (gmiio.tx_en = '1' and rtx.gmii_tx_en_int = '0') then + v.count := 0; + elsif (v.count >= 9) and gmiio.speed = '1' then + v.count := 0; + elsif (v.count >= 99) and gmiio.speed = '0' then + v.count := 0; + else + v.count := rtx.count + 1; + end if; + + case v.count is + when 0 => + v.gmii_txd_int(3 downto 0) := gmiio.txd(3 downto 0); + v.cnt_en := '1'; + + when 5 => + if gmiio.speed = '1' then + v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0); + v.cnt_en := '1'; + end if; + + when 50=> + if gmiio.speed = '0' then + v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0); + v.cnt_en := '1'; + end if; + + + when 9 => + if gmiio.speed = '1' then + v.gmii_txd := v.gmii_txd_int; + v.gmii_tx_en := '1'; + v.gmii_tx_er := gmiio.tx_er; + if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if; + if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if; + end if; + + when 99 => + if gmiio.speed = '0' then + v.gmii_txd := v.gmii_txd_int; + v.gmii_tx_en := '1'; + v.gmii_tx_er := gmiio.tx_er; + if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if; + if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if; + end if; + + when others => + null; + + end case; + + if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '1') then + v.keepalive := 2; + end if; + + if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '0' and rtx.keepalive = 0) then + v := RESTX; + end if; + + -- reset operation + if (not RESET_ALL) and (usr2rstn = '0') then + v := RESTX; + end if; + + -- update registers + rintx <= v; + end process; + + txegs : process(userclk2) + begin + if rising_edge(userclk2) then + rtx <= rintx; + if RESET_ALL and usr2rstn = '0' then + rtx <= RESTX; + end if; + end if; + end process; + + -- 1000Mbit TX Logic (Bypass) + -- n/a + + -- TX Mux Select + cnt_en <= '1' when (gmiio.gbit = '1') else rtx.cnt_en; + + gmii_txd <= gmiio.txd when (gmiio.gbit = '1') else rtx.gmii_txd; + gmii_tx_en <= gmiio.tx_en when (gmiio.gbit = '1') else rtx.gmii_tx_en; + gmii_tx_er <= gmiio.tx_er when (gmiio.gbit = '1') else rtx.gmii_tx_er; + ------------------------------------------------------------------------------ -- Instantiate the Core Block (core wrapper). ------------------------------------------------------------------------------ @@ -553,7 +794,6 @@ begin core_wrapper : sgmii port map ( - gtrefclk => gtrefclk, txp => sgmiio.txp, txn => sgmiio.txn, @@ -576,9 +816,9 @@ begin gmii_txd => gmii_txd, gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, - gmii_rxd => gmii_rxd, - gmii_rx_dv => gmii_rx_dv, - gmii_rx_er => gmii_rx_er, + gmii_rxd => gmii_rxd_int, + gmii_rx_dv => gmii_rx_dv_int, + gmii_rx_er => gmii_rx_er_int, gmii_isolate => gmii_isolate, configuration_vector => configuration_vector, an_interrupt => an_interrupt, @@ -591,39 +831,87 @@ begin signal_detect => signal_detect, gt0_qplloutclk_in => '0', gt0_qplloutrefclk_in => '0' - ); - + ); - ----------------------------------------------------------------------------- - -- SGMII clock logic - ----------------------------------------------------------------------------- + ------------------------------------------------------------------------------ + -- GMII (Xilinx) to GMII (Aeroflex Gailers) style + ------------------------------------------------------------------------------ - process (userclk2) + ---- 10/100Mbit RX Loic + process (usr2rstn,rrx,gmii_rx_dv_int,gmii_rxd_int,gmii_rx_er_int,sgmii_clk_en) + variable v : rxregs; begin - if userclk2'event and userclk2 = '1' then - sgmii_clk_int <= sgmii_clk_r; + v := rrx; + + if (gmii_rx_dv_int = '1' and sgmii_clk_en = '1') then + v.count := 0; + v.gmii_rxd_int := gmii_rxd_int; + v.gmii_dv := '1'; + v.keepalive := 1; + elsif (v.count >= 9) and gmiio.speed = '1' then + v.count := 0; + v.keepalive := rrx.keepalive - 1; + elsif (v.count >= 99) and gmiio.speed = '0' then + v.count := 0; + v.keepalive := rrx.keepalive - 1; + else + v.count := rrx.count + 1; end if; - end process; - bufgmux_sgmiiclk: BUFGMUX - generic map ("ASYNC") - port map ( - O => sgmii_clk, - I0 => userclk2, - I1 => sgmii_clk_int, - S => speed_is_10_100 - ); + case v.count is + when 0 => + v.gmii_rxd := v.gmii_rxd_int(3 downto 0) & v.gmii_rxd_int(3 downto 0); + v.gmii_rx_dv := v.gmii_dv; + when 5 => + if gmiio.speed = '1' then + v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4); + v.gmii_rx_dv := v.gmii_dv; + v.gmii_dv := '0'; + end if; + when 50 => + if gmiio.speed = '0' then + v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4); + v.gmii_rx_dv := v.gmii_dv; + v.gmii_dv := '0'; + end if; + when others => + v.gmii_rxd := v.gmii_rxd; + v.gmii_rx_dv := '0'; + end case; + + v.gmii_rx_er := gmii_rx_er_int; + + if (rrx.keepalive = 0 and gmii_rx_dv_int = '0') then + v := RESRX; + end if; - ----------------------------------------------------------------------------- - -- Extra registers to ease IOB placement - ----------------------------------------------------------------------------- - process (userclk2) - begin - if userclk2'event and userclk2 = '1' then - status_vector <= status_vector_int; + -- reset operation + if (not RESET_ALL) and (usr2rstn = '0') then + v := RESRX; end if; + + -- update registers + rinrx <= v; + end process; + + rx100regs : process(userclk2) + begin + if rising_edge(userclk2) then + rrx <= rinrx; + if RESET_ALL and usr2rstn = '0' then + rrx <= RESRX; + end if; + end if; end process; + ---- 1000Mbit RX Logic (Bypass) + -- n/a + + ---- RX Mux Select + gmii_rxd <= gmii_rxd_int when (gmiio.gbit = '1') else rinrx.gmii_rxd; + gmii_rx_dv <= gmii_rx_dv_int when (gmiio.gbit = '1') else rinrx.gmii_rx_dv; + gmii_rx_er <= gmii_rx_er_int when (gmiio.gbit = '1') else rinrx.gmii_rx_er; + ----------------------------------------------------------------------------- -- Extra registers to ease CDC placement ----------------------------------------------------------------------------- @@ -634,4 +922,205 @@ begin end if; end process; + --------------------------------------------------------------------------------------- + -- APB Section + --------------------------------------------------------------------------------------- + + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + + -- Extra registers to ease CDC placement + process (apb_clk) + begin + if apb_clk'event and apb_clk = '1' then + status_vector_apb1 <= (others => '0'); + status_vector_apb2 <= (others => '0'); + if autonegotiation = 1 then status_vector_apb2(17) <= '1'; else status_vector_apb2(17) <= '0'; end if; + if debugmem = 1 then status_vector_apb2(16) <= '1'; else status_vector_apb2(16) <= '0'; end if; + -- Register to detect a speed change + status_vector_apb1(15 downto 0) <= status_vector_apb; + status_vector_apb2 <= status_vector_apb1; + end if; + end process; + + rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead ) + variable rdata : std_logic_vector(31 downto 0); + variable paddress : std_logic_vector(7 downto 2); + variable v : sgmiiregs; + begin + + v := r; + paddress := (others => '0'); + paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2); + rdata := (others => '0'); + + -- read/write registers + + if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then + case paddress(7 downto 2) is + when "000000" => + rdata(31 downto 0) := status_vector_apb2; + when "000001" => + rdata(31 downto 0) := r.irq; + v.irq := (others => '0'); -- Interrupt is clear on read + when "000010" => + rdata(31 downto 0) := r.mask; + when "000011" => + rdata(4 downto 0) := r.configuration_vector; + when "000100" => + rdata(15 downto 0) := r.an_adv_config_vector; + when others => + null; + end case; + end if; + + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case paddress(7 downto 2) is + when "000000" => + null; + when "000001" => + null; + when "000010" => + v.mask := apbi.pwdata(31 downto 0); + when "000011" => + v.configuration_vector := apbi.pwdata(4 downto 0); + when "000100" => + v.an_adv_config_vector := apbi.pwdata(15 downto 0); + when others => + null; + end case; + end if; + + -- Check interrupts + for i in 0 to status_vector_apb2'length-1 loop + if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then + v.irq(i) := '1'; + end if; + end loop; + + -- reset operation + if (not RESET_ALL) and (apb_rstn = '0') then + v := RES; + end if; + + -- update registers + rin <= v; + + -- drive outputs + if apbi.psel(pindex) = '0' then + apbo.prdata <= (others => '0'); + elsif RMemRgmiiiRead = '1' then + apbo.prdata(31 downto 16) <= (others => '0'); + apbo.prdata(15 downto 0) <= RMemRgmiiiData; + elsif RMemRgmiioRead = '1' then + apbo.prdata(31 downto 16) <= (others => '0'); + apbo.prdata(15 downto 0) <= RMemRgmiioData; + else + apbo.prdata <= rdata; + end if; + + apbo.pirq <= (others => '0'); + apbo.pirq(pirq) <= orv(v.irq); + + end process; + + regs : process(apb_clk) + begin + if rising_edge(apb_clk) then + r <= rin; + if RESET_ALL and apb_rstn = '0' then + r <= RES; + end if; + end if; + end process; + + --------------------------------------------------------------------------------------- + -- Debug Mem + --------------------------------------------------------------------------------------- + + debugmem1 : if (debugmem /= 0) generate + + -- Write GMII IN data + process (userclk2) + begin -- process + if rising_edge(userclk2) then + WMemRgmiioData(15 downto 0) <= '0' & '0' & '0' & '0' & "00" & gmii_tx_er & gmii_tx_en & gmii_txd; + if (gmii_tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then + WMemRgmiioAddr <= WMemRgmiioAddr + 1; + WMemRgmiioWrEn <= '1'; + else + if (gmii_tx_en = '0') then + WMemRgmiioAddr <= (others => '1'); + else + WMemRgmiioAddr <= WMemRgmiioAddr; + end if; + WMemRgmiioWrEn <= '0'; + end if; + + if usr2rstn = '0' then + WMemRgmiioAddr <= (others => '0'); + WMemRgmiioWrEn <= '0'; + end if; + + end if; + end process; + + -- Read + RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex); + RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2); + + gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map( + apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData, + userclk2, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData); + + -- Write GMII IN data + process (userclk2) + begin -- process + if rising_edge(userclk2) then + + if (gmii_rx_dv = '1') then + WMemRgmiiiData(15 downto 0) <= '0' & sgmii_clk_en & '0' & '0' & "00" & gmii_rx_er & gmii_rx_dv & gmii_rxd; + elsif (gmii_rx_dv_int = '0') then + WMemRgmiiiData(15 downto 0) <= (others => '0'); + else + WMemRgmiiiData <= WMemRgmiiiData; + end if; + + if (gmii_rx_dv = '1') and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then + WMemRgmiiiAddr <= WMemRgmiiiAddr + 1; + WMemRgmiiiWrEn <= '1'; + else + if (gmii_rx_dv_int = '0') then + WMemRgmiiiAddr <= (others => '1'); + WMemRgmiiiWrEn <= '0'; + else + WMemRgmiiiAddr <= WMemRgmiiiAddr; + WMemRgmiiiWrEn <= '0'; + end if; + end if; + + if usr2rstn = '0' then + WMemRgmiiiAddr <= (others => '0'); + WMemRgmiiiWrEn <= '0'; + end if; + + end if; + end process; + + -- Read + RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex); + RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2); + + rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map( + apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData, + userclk2, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData); + + end generate; + +-- pragma translate_off + bootmsg : report_version + generic map ("sgmii" & tost(pindex) & + ": SGMII rev " & tost(REVISION) & ", irq " & tost(pirq)); +-- pragma translate_on + end top_level; diff --git a/designs/leon3-xilinx-vc707/systest.c b/designs/leon3-xilinx-vc707/systest.c index f1a41326..42712e36 100644 --- a/designs/leon3-xilinx-vc707/systest.c +++ b/designs/leon3-xilinx-vc707/systest.c @@ -16,5 +16,6 @@ memory = *memptr; report_start(); base_test(); + //greth_test(0x80080000); report_end(); } diff --git a/designs/leon3-xilinx-vc707/testbench.vhd b/designs/leon3-xilinx-vc707/testbench.vhd index b62a3dd3..97fc63cc 100644 --- a/designs/leon3-xilinx-vc707/testbench.vhd +++ b/designs/leon3-xilinx-vc707/testbench.vhd @@ -3,7 +3,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,8 +30,6 @@ library grlib; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; -library micron; -use micron.all; library techmap; use techmap.gencomp.all; use work.debug.all; @@ -69,11 +67,10 @@ constant SIMULATION : string := "TRUE"; constant promfile : string := "prom.srec"; -- rom contents -constant sramfile : string := "ram.srec"; -- ram contents -constant sdramfile : string := "ram.srec"; -- sdram contents +constant ramfile : string := "ram.srec"; -- ram contents signal clk : std_logic := '0'; -signal Rst : std_logic := '0'; +signal rst : std_logic := '0'; signal address : std_logic_vector(25 downto 0); signal data : std_logic_vector(15 downto 0); @@ -200,6 +197,8 @@ signal ddo : grusb_dcl_debug_data; signal phy_mdio : std_logic; signal phy_mdc : std_ulogic; +signal txp_eth, txn_eth : std_logic; + component leon3mp is generic ( fabtech : integer := CFG_FABTECH; @@ -275,35 +274,6 @@ component leon3mp is ); end component; -component ddr3_model - generic( - ADDR_BITS : integer := 14; - BA_BITS : integer := 3; - DM_BITS : integer := 1; - DQ_BITS : integer := 8; - DQS_BITS : integer := 1 - ); - port( - rst_n : in std_logic; - ck : in std_logic; - ck_n : in std_logic; - cke : in std_logic; - cs_n : in std_logic; - ras_n : in std_logic; - cas_n : in std_logic; - we_n : in std_logic; - dm_tdqs : inout std_logic; - ba : in std_logic_vector(2 downto 0); - addr : in std_logic_vector(13 downto 0); - dq : inout std_logic_vector(7 downto 0); - dqs : inout std_logic; - dqs_n : inout std_logic; - tdqs_n : out std_logic_vector(0 to 0); - odt : in std_logic - ); -end component; - - begin -- clock and reset @@ -376,10 +346,10 @@ begin usb_resetn => usb_resetn, gtrefclk_p => clkethp, gtrefclk_n => clkethn, - txp => OPEN, - txn => OPEN, - rxp => '1', - rxn => '1', + txp => txp_eth, + txn => txn_eth, + rxp => txp_eth, + rxn => txn_eth, emdio => phy_mdio, emdc => phy_mdc, eint => '0', @@ -396,7 +366,24 @@ begin phy_mdio <= 'H'; p0: phy - generic map (address => 7) + generic map ( + address => 7, + extended_regs => 1, + aneg => 1, + base100_t4 => 1, + base100_x_fd => 1, + base100_x_hd => 1, + fd_10 => 1, + hd_10 => 1, + base100_t2_fd => 1, + base100_t2_hd => 1, + base1000_x_fd => 1, + base1000_x_hd => 1, + base1000_t_fd => 1, + base1000_t_hd => 1, + rmii => 0, + rgmii => 1 + ) port map(dsurst, phy_mdio, OPEN , OPEN , OPEN , OPEN , OPEN , OPEN , OPEN , "00000000", '0', '0', phy_mdc, clkethp); @@ -410,39 +397,41 @@ begin writen, oen); end generate; - -- Memory Models instantiations + -- Memory model instantiation gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate ddr3mem : if (CFG_MIG_SERIES7 = 1) generate - gen_mem: for i in 0 to 7 generate - - - u1: ddr3_model - generic map( - ADDR_BITS => 14, - BA_BITS => 3, - DM_BITS => 1, - DQ_BITS => 8, - DQS_BITS => 1 - ) - port map ( - rst_n => ddr3_reset_n, - ck => ddr3_ck_p(0), - ck_n => ddr3_ck_n(0), - cke => ddr3_cke(0), - cs_n => ddr3_cs_n(0), - ras_n => ddr3_ras_n, - cas_n => ddr3_cas_n, - we_n => ddr3_we_n, - dm_tdqs => ddr3_dm(i), - ba => ddr3_ba, - addr => ddr3_addr, - dq => ddr3_dq((8*i+7) downto (8*i)), - dqs => ddr3_dqs_p(i), - dqs_n => ddr3_dqs_n(i), - tdqs_n => open, - odt => ddr3_odt(0) - ); - end generate gen_mem; + u1 : ddr3ram + generic map ( + width => 64, + abits => 14, + colbits => 10, + rowbits => 10, + implbanks => 1, + fname => ramfile, + lddelay => (0 ns), + ldguard => 1, + speedbin => 9, --DDR3-1600K + density => 3, + pagesize => 1, + changeendian => 8) + port map ( + ck => ddr3_ck_p(0), + ckn => ddr3_ck_n(0), + cke => ddr3_cke(0), + csn => ddr3_cs_n(0), + odt => ddr3_odt(0), + rasn => ddr3_ras_n, + casn => ddr3_cas_n, + wen => ddr3_we_n, + dm => ddr3_dm, + ba => ddr3_ba, + a => ddr3_addr, + resetn => ddr3_reset_n, + dq => ddr3_dq, + dqs => ddr3_dqs_p, + dqsn => ddr3_dqs_n, + doload => led(3) + ); end generate ddr3mem; end generate gen_mem_model; @@ -526,7 +515,9 @@ begin dsurst <= '0'; switch(4) <= '0'; wait for 2500 ns; - wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation + if (USE_MIG_INTERFACE_MODEL /= true) then + wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation + end if; dsurst <= '1'; switch(4) <= '1'; if (USE_MIG_INTERFACE_MODEL /= true) then diff --git a/designs/leon3-xilinx-vc707/tkconfig.h b/designs/leon3-xilinx-vc707/tkconfig.h index acc3c28d..da767a93 100644 --- a/designs/leon3-xilinx-vc707/tkconfig.h +++ b/designs/leon3-xilinx-vc707/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-xilinx-xc3sd-1800/.config b/designs/leon3-xilinx-xc3sd-1800/.config index 638a90a5..286dfc4e 100755 --- a/designs/leon3-xilinx-xc3sd-1800/.config +++ b/designs/leon3-xilinx-xc3sd-1800/.config @@ -168,7 +168,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -# CONFIG_DCACHE_SNOOP_FAST is not set # CONFIG_DCACHE_SNOOP_SEPTAG is not set CONFIG_CACHE_FIXED=0 @@ -254,7 +253,6 @@ CONFIG_DSU_IPLSB=0033 CONFIG_DSU_ETHMSB=020000 CONFIG_DSU_ETHLSB=001234 # CONFIG_DSU_ETH_PROG is not set -# CONFIG_DSU_ETH_DIS is not set # # Peripherals diff --git a/designs/leon3-xilinx-xc3sd-1800/Makefile b/designs/leon3-xilinx-xc3sd-1800/Makefile index c9730164..59aa720a 100644 --- a/designs/leon3-xilinx-xc3sd-1800/Makefile +++ b/designs/leon3-xilinx-xc3sd-1800/Makefile @@ -24,7 +24,7 @@ LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan pci leon3ft ambatest can \ usb grusbhc spacewire ascs slink hcan \ leon4 leon4v0 l2cache pwm gr1553b iommu -FILESKIP = grcan.vhd i2cmst.vhd +FILESKIP = grcan.vhd i2cmst.vhd sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/leon3-xilinx-xc3sd-1800/config.h b/designs/leon3-xilinx-xc3sd-1800/config.h index e49bc8f3..aa417488 100644 --- a/designs/leon3-xilinx-xc3sd-1800/config.h +++ b/designs/leon3-xilinx-xc3sd-1800/config.h @@ -163,7 +163,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#undef CONFIG_DCACHE_SNOOP_FAST #undef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_CACHE_FIXED 0 /* @@ -243,7 +242,6 @@ #define CONFIG_DSU_ETHMSB 020000 #define CONFIG_DSU_ETHLSB 001234 #undef CONFIG_DSU_ETH_PROG -#undef CONFIG_DSU_ETH_DIS /* * Peripherals */ diff --git a/designs/leon3-xilinx-xc3sd-1800/config.help b/designs/leon3-xilinx-xc3sd-1800/config.help index bd263df7..5dfe05eb 100644 --- a/designs/leon3-xilinx-xc3sd-1800/config.help +++ b/designs/leon3-xilinx-xc3sd-1800/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-xilinx-xc3sd-1800/config.vhd b/designs/leon3-xilinx-xc3sd-1800/config.vhd index b24c30bc..e895e9b8 100644 --- a/designs/leon3-xilinx-xc3sd-1800/config.vhd +++ b/designs/leon3-xilinx-xc3sd-1800/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 4; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 0 + 4*0; + constant CFG_DSNOOP : integer := 1*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-xilinx-xc3sd-1800/config.vhd.h b/designs/leon3-xilinx-xc3sd-1800/config.vhd.h index 507e9ab3..3cde0380 100644 --- a/designs/leon3-xilinx-xc3sd-1800/config.vhd.h +++ b/designs/leon3-xilinx-xc3sd-1800/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-xilinx-xc3sd-1800/lconfig.tk b/designs/leon3-xilinx-xc3sd-1800/lconfig.tk index a9ddd922..7485c2ba 100755 --- a/designs/leon3-xilinx-xc3sd-1800/lconfig.tk +++ b/designs/leon3-xilinx-xc3sd-1800/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5117,7 +5108,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5313,6 +5303,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -5770,7 +5761,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -5893,10 +5883,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "Leon2 memory controller " @@ -5996,6 +5985,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_30 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3-xilinx-xc3sd-1800/leon3mp.vhd b/designs/leon3-xilinx-xc3sd-1800/leon3mp.vhd index 00a5429c..cec2efac 100644 --- a/designs/leon3-xilinx-xc3sd-1800/leon3mp.vhd +++ b/designs/leon3-xilinx-xc3sd-1800/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-xilinx-xc3sd-1800/testbench.vhd b/designs/leon3-xilinx-xc3sd-1800/testbench.vhd index 30e865bf..06cba0b7 100644 --- a/designs/leon3-xilinx-xc3sd-1800/testbench.vhd +++ b/designs/leon3-xilinx-xc3sd-1800/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,15 +30,10 @@ library techmap; use techmap.gencomp.all; library micron; use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -library hynix; -use hynix.components.all; - entity testbench is generic ( fabtech : integer := CFG_FABTECH; @@ -218,18 +213,26 @@ begin ); ddr2mem : if (CFG_DDR2SP /= 0) generate - ddr2mem0 : for i in 0 to 1 generate - u1 : HY5PS121621F - generic map (TimingCheckFlag => true, PUSCheckFlag => false, - index => 1-i, bbits => 32, fname => sdramfile) - port map (DQ => ddr_dq2(i*16+15 downto i*16), - LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2), - UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1), - LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas, - RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba, - ADDR => ddr_ad(12 downto 0), CKE => ddr_cke, - CLK => ddr_clk(i), CLKB => ddr_clkb(i), UDM => ddr_dm(i*2+1)); - end generate; + -- ddr2mem0 : for i in 0 to 1 generate + -- u1 : HY5PS121621F + -- generic map (TimingCheckFlag => true, PUSCheckFlag => false, + -- index => 1-i, bbits => 32, fname => sdramfile) + -- port map (DQ => ddr_dq2(i*16+15 downto i*16), + -- LDQS => ddr_dqs(i*2), LDQSB => ddr_dqsn(i*2), + -- UDQS => ddr_dqs(i*2+1), UDQSB => ddr_dqsn(i*2+1), + -- LDM => ddr_dm(i*2), WEB => ddr_we, CASB => ddr_cas, + -- RASB => ddr_ras, CSB => ddr_csb, BA => ddr_ba, + -- ADDR => ddr_ad(12 downto 0), CKE => ddr_cke, + -- CLK => ddr_clk(i), CLKB => ddr_clkb(i), UDM => ddr_dm(i*2+1)); + -- end generate; + + ddr0 : ddr2ram + generic map(width => 32, abits => 13, babits =>2, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>1, density => 2) + port map (ck => ddr_clk(0), ckn => ddr_clkb(0), cke => ddr_cke, csn => ddr_csb, + odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we, + dm => ddr_dm, ba => ddr_ba(1 downto 0), a => ddr_ad(12 downto 0), dq => ddr_dq2, + dqs => ddr_dqs); ddr2delay0 : delay_wire generic map(data_width => ddr_dq'length, delay_atob => 0.0, delay_btoa => 1.0) diff --git a/designs/leon3-xilinx-xc3sd-1800/tkconfig.h b/designs/leon3-xilinx-xc3sd-1800/tkconfig.h index 509d19d9..569e6672 100644 --- a/designs/leon3-xilinx-xc3sd-1800/tkconfig.h +++ b/designs/leon3-xilinx-xc3sd-1800/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-ztex-ufm-111/README.txt b/designs/leon3-ztex-ufm-111/README.txt index 790245bf..e4d737e1 100644 --- a/designs/leon3-ztex-ufm-111/README.txt +++ b/designs/leon3-ztex-ufm-111/README.txt @@ -32,13 +32,13 @@ library, do as follows: This will ONLY work with correct version of ISE installed, and the XILINX variable properly set in the shell. For ISE13 it is recommened to use the 'ise' make target -and for ISE14 to use the 'planAhead' target. To synthesize the design, do +and for ISE14 to use the 'planahead' target. To synthesize the design, do make ise (ISE13) or - make planAhead (ISE14) + make planahead (ISE14) The FPGA can be programmed via JTAG using: diff --git a/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd b/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd index 4af0d1e3..0f635415 100644 --- a/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd +++ b/designs/leon3-ztex-ufm-111/ahb2mig_ztex.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-ztex-ufm-111/config.help b/designs/leon3-ztex-ufm-111/config.help index 55dfa04b..f45c4ca2 100644 --- a/designs/leon3-ztex-ufm-111/config.help +++ b/designs/leon3-ztex-ufm-111/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-ztex-ufm-111/config.vhd b/designs/leon3-ztex-ufm-111/config.vhd index 3aaccec3..28ac9c0a 100644 --- a/designs/leon3-ztex-ufm-111/config.vhd +++ b/designs/leon3-ztex-ufm-111/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-ztex-ufm-111/config.vhd.h b/designs/leon3-ztex-ufm-111/config.vhd.h index 64fe0a01..25e8c292 100644 --- a/designs/leon3-ztex-ufm-111/config.vhd.h +++ b/designs/leon3-ztex-ufm-111/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-ztex-ufm-111/lconfig.tk b/designs/leon3-ztex-ufm-111/lconfig.tk index c522a273..c62b5f0e 100755 --- a/designs/leon3-ztex-ufm-111/lconfig.tk +++ b/designs/leon3-ztex-ufm-111/lconfig.tk @@ -2186,24 +2186,23 @@ proc menu7 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 7 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 7 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 7 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 7 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 7 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 7 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 7 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 7 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 7 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 7 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 7 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 7 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 7 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2275,20 +2274,17 @@ proc update_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu7.config.f.x15 normal {n l y}} else {configure_entry .menu7.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x17 normal {n l y}} else {configure_entry .menu7.config.f.x17 disabled {y n l}} + configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x18.l configure -state normal; } else {.menu7.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x17.l configure -state normal; } else {.menu7.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu7.config.f.x19 normal {n l y}} else {configure_entry .menu7.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x20 normal {x l}} else {configure_entry .menu7.config.f.x20 disabled {x l}} + configure_entry .menu7.config.f.x18 normal {n l y}} else {configure_entry .menu7.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x19 normal {x l}} else {configure_entry .menu7.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x21.l configure -state normal; } else {.menu7.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x20.l configure -state normal; } else {.menu7.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x20.l configure -state disabled} } @@ -2421,9 +2417,6 @@ proc update_define_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4332,7 +4325,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4471,6 +4463,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4931,7 +4924,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-ztex-ufm-111/leon3mp.vhd b/designs/leon3-ztex-ufm-111/leon3mp.vhd index d69aa3b7..93546df8 100644 --- a/designs/leon3-ztex-ufm-111/leon3mp.vhd +++ b/designs/leon3-ztex-ufm-111/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-ztex-ufm-111/testbench.vhd b/designs/leon3-ztex-ufm-111/testbench.vhd index 56ea0208..c11c1dd8 100644 --- a/designs/leon3-ztex-ufm-111/testbench.vhd +++ b/designs/leon3-ztex-ufm-111/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,8 +30,6 @@ library techmap; use techmap.gencomp.all; library micron; use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; @@ -62,16 +60,14 @@ architecture behav of testbench is signal errorn : std_logic; signal mcb3_dram_dq : std_logic_vector(15 downto 0); signal mcb3_rzq : std_logic; - signal mcb3_dram_udqs : std_logic; - signal mcb3_dram_dqs : std_logic; + signal mcb3_dram_dqs : std_logic_vector(1 downto 0); signal mcb3_dram_a : std_logic_vector(12 downto 0); signal mcb3_dram_ba : std_logic_vector(1 downto 0); signal mcb3_dram_cke : std_logic; signal mcb3_dram_ras_n : std_logic; signal mcb3_dram_cas_n : std_logic; signal mcb3_dram_we_n : std_logic; - signal mcb3_dram_dm : std_logic; - signal mcb3_dram_udm : std_logic; + signal mcb3_dram_dm : std_logic_vector(1 downto 0); signal mcb3_dram_ck : std_logic; signal mcb3_dram_ck_n : std_logic; signal dsubre : std_ulogic; -- Debug Unit break (connect to button) @@ -89,7 +85,7 @@ architecture behav of testbench is begin -- clock and reset - clk48 <= not clk48 after 10.05 ns; + clk48 <= not clk48 after 10.417 ns; reset <= '1', '0' after 300 ns; dsubre <= '0'; @@ -107,16 +103,16 @@ begin -- DDR SDRAM mcb3_dram_dq => mcb3_dram_dq, mcb3_rzq => mcb3_rzq, - mcb3_dram_udqs => mcb3_dram_udqs, - mcb3_dram_dqs => mcb3_dram_dqs, + mcb3_dram_udqs => mcb3_dram_dqs(1), + mcb3_dram_dqs => mcb3_dram_dqs(0), mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, - mcb3_dram_dm => mcb3_dram_dm, - mcb3_dram_udm => mcb3_dram_udm, + mcb3_dram_dm => mcb3_dram_dm(0), + mcb3_dram_udm => mcb3_dram_dm(1), mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, -- Debug support unit @@ -137,32 +133,13 @@ begin migddr2mem : if (CFG_MIG_DDR2 = 1) generate - ddr0 : mt46v16m16 - generic map ( - tCK => 5.000 ns, - tCH => 2.250 ns, -- 0.45*tCK - tCL => 2.250 ns, -- 0.45*tCK - tDH => 0.500 ns, - tDS => 0.500 ns, - tIH => 0.900 ns, - tIS => 0.900 ns, - tMRD => 10.000 ns, - tRAS => 40.000 ns, - tRAP => 15.000 ns, - tRC => 55.000 ns, - tRFC => 70.000 ns, - tRCD => 15.000 ns, - tRP => 15.000 ns, - tRRD => 10.000 ns, - tWR => 15.000 ns, - index => -1, fname => sdramfile, cols_bits => 10, fdelay => 15, - chktiming => false) - port map( - Dq => mcb3_dram_dq, Dqs(1) => mcb3_dram_udqs, Dqs(0) => mcb3_dram_dqs, - Addr => mcb3_dram_a, Ba => mcb3_dram_ba, Clk => mcb3_dram_ck, - Clk_n => mcb3_dram_ck_n, Cke => mcb3_dram_cke, Cs_n => csb, - Ras_n => mcb3_dram_ras_n, Cas_n => mcb3_dram_cas_n, We_n => mcb3_dram_we_n, - Dm(1) => mcb3_dram_udm, Dm(0) => mcb3_dram_dm); + ddr0 : ddrram + generic map(width => 16, abits => 13, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>4, lddelay => 15 us) + port map (ck => mcb3_dram_ck, cke => mcb3_dram_cke, csn => csb, + rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n, + dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a, + dq => mcb3_dram_dq, dqs => mcb3_dram_dqs); end generate; --spimem0: if CFG_SPIMCTRL = 1 generate diff --git a/designs/leon3-ztex-ufm-111/tkconfig.h b/designs/leon3-ztex-ufm-111/tkconfig.h index c44ec8b1..d7aa9833 100644 --- a/designs/leon3-ztex-ufm-111/tkconfig.h +++ b/designs/leon3-ztex-ufm-111/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3-ztex-ufm-115/.config b/designs/leon3-ztex-ufm-115/.config index 6d65a69a..527b4980 100644 --- a/designs/leon3-ztex-ufm-115/.config +++ b/designs/leon3-ztex-ufm-115/.config @@ -176,7 +176,6 @@ CONFIG_DCACHE_ALGORND=y # CONFIG_DCACHE_ALGOLRU is not set # CONFIG_DCACHE_LOCK is not set CONFIG_DCACHE_SNOOP=y -CONFIG_DCACHE_SNOOP_FAST=y CONFIG_DCACHE_SNOOP_SEPTAG=y CONFIG_CACHE_FIXED=0 diff --git a/designs/leon3-ztex-ufm-115/README.txt b/designs/leon3-ztex-ufm-115/README.txt index 25949e57..3ad90061 100644 --- a/designs/leon3-ztex-ufm-115/README.txt +++ b/designs/leon3-ztex-ufm-115/README.txt @@ -32,13 +32,13 @@ library, do as follows: This will ONLY work with correct version of ISE installed, and the XILINX variable properly set in the shell. For ISE13 it is recommened to use the 'ise' make target -and for ISE14 to use the 'planAhead' target. To synthesize the design, do +and for ISE14 to use the 'planahead' target. To synthesize the design, do make ise (ISE13) or - make planAhead (ISE14) + make planahead (ISE14) The FPGA can be programmed via JTAG using: diff --git a/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd b/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd index a7f4a46f..03bb99a0 100644 --- a/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd +++ b/designs/leon3-ztex-ufm-115/ahb2mig_ztex.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-ztex-ufm-115/config.h b/designs/leon3-ztex-ufm-115/config.h index 98b0b120..e881eb06 100644 --- a/designs/leon3-ztex-ufm-115/config.h +++ b/designs/leon3-ztex-ufm-115/config.h @@ -170,7 +170,6 @@ #undef CONFIG_DCACHE_ALGOLRU #undef CONFIG_DCACHE_LOCK #define CONFIG_DCACHE_SNOOP 1 -#define CONFIG_DCACHE_SNOOP_FAST 1 #define CONFIG_DCACHE_SNOOP_SEPTAG 1 #define CONFIG_CACHE_FIXED 0 /* diff --git a/designs/leon3-ztex-ufm-115/config.help b/designs/leon3-ztex-ufm-115/config.help index 55dfa04b..f45c4ca2 100644 --- a/designs/leon3-ztex-ufm-115/config.help +++ b/designs/leon3-ztex-ufm-115/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3-ztex-ufm-115/config.vhd b/designs/leon3-ztex-ufm-115/config.vhd index 5bc26dbc..e47fdbe4 100644 --- a/designs/leon3-ztex-ufm-115/config.vhd +++ b/designs/leon3-ztex-ufm-115/config.vhd @@ -59,7 +59,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 2; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 1 + 1 + 4*1; + constant CFG_DSNOOP : integer := 1*2 + 4*1; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3-ztex-ufm-115/config.vhd.h b/designs/leon3-ztex-ufm-115/config.vhd.h index 64fe0a01..25e8c292 100644 --- a/designs/leon3-ztex-ufm-115/config.vhd.h +++ b/designs/leon3-ztex-ufm-115/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3-ztex-ufm-115/lconfig.tk b/designs/leon3-ztex-ufm-115/lconfig.tk index c55d18c5..db406802 100755 --- a/designs/leon3-ztex-ufm-115/lconfig.tk +++ b/designs/leon3-ztex-ufm-115/lconfig.tk @@ -2189,24 +2189,23 @@ proc menu7 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 7 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 7 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 7 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 7 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 7 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 7 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 7 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 7 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 7 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_19 - minimenu $w.config.f 7 20 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 7 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 7 19 "Local data RAM size (kbytes)" tmpvar_19 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_19 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_19 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_19 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_19 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_19 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_19 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_19 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_19 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_19 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 7 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2278,20 +2277,17 @@ proc update_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu7.config.f.x15 normal {n l y}} else {configure_entry .menu7.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu7.config.f.x17 normal {n l y}} else {configure_entry .menu7.config.f.x17 disabled {y n l}} + configure_entry .menu7.config.f.x16 normal {n l y}} else {configure_entry .menu7.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x18.l configure -state normal; } else {.menu7.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu7.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x17.l configure -state normal; } else {.menu7.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu7.config.f.x19 normal {n l y}} else {configure_entry .menu7.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x20 normal {x l}} else {configure_entry .menu7.config.f.x20 disabled {x l}} + configure_entry .menu7.config.f.x18 normal {n l y}} else {configure_entry .menu7.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu7.config.f.x19 normal {x l}} else {configure_entry .menu7.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x21.l configure -state normal; } else {.menu7.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu7.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu7.config.f.x20.l configure -state normal; } else {.menu7.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu7.config.f.x20.l configure -state disabled} } @@ -2424,9 +2420,6 @@ proc update_define_menu7 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -4336,7 +4329,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -4475,6 +4467,7 @@ set CONFIG_SPICTRL_TMRFT 0 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -4936,7 +4929,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_18 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } diff --git a/designs/leon3-ztex-ufm-115/leon3mp.vhd b/designs/leon3-ztex-ufm-115/leon3mp.vhd index 68440e83..12ab3a25 100644 --- a/designs/leon3-ztex-ufm-115/leon3mp.vhd +++ b/designs/leon3-ztex-ufm-115/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3-ztex-ufm-115/testbench.vhd b/designs/leon3-ztex-ufm-115/testbench.vhd index a971e5ed..b9d2d4ed 100644 --- a/designs/leon3-ztex-ufm-115/testbench.vhd +++ b/designs/leon3-ztex-ufm-115/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -28,18 +28,10 @@ use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; -library micron; -use micron.components.all; -library hynix; -use hynix.components.all; use work.debug.all; use work.config.all; -library hynix; -use hynix.components.all; -use hynix.HY5PS121621F_PACK.all; - entity testbench is generic ( fabtech : integer := CFG_FABTECH; @@ -64,17 +56,15 @@ architecture behav of testbench is signal mcb3_dram_dq : std_logic_vector(15 downto 0); signal mcb3_rzq : std_logic; signal mcb3_zio : std_logic; - signal mcb3_dram_udqs : std_logic; - signal mcb3_dram_udqs_n : std_logic; - signal mcb3_dram_dqs : std_logic; - signal mcb3_dram_dqs_n : std_logic; + signal mcb3_dram_dqs : std_logic_vector(1 downto 0); + signal mcb3_dram_dqs_n : std_logic_vector(1 downto 0); signal mcb3_dram_a : std_logic_vector(12 downto 0); signal mcb3_dram_ba : std_logic_vector(2 downto 0); signal mcb3_dram_cke : std_logic; signal mcb3_dram_ras_n : std_logic; signal mcb3_dram_cas_n : std_logic; signal mcb3_dram_we_n : std_logic; - signal mcb3_dram_dm : std_logic; + signal mcb3_dram_dm : std_logic_vector(1 downto 0); signal mcb3_dram_udm : std_logic; signal mcb3_dram_ck : std_logic; signal mcb3_dram_ck_n : std_logic; @@ -94,7 +84,7 @@ architecture behav of testbench is begin -- clock and reset - clk48 <= not clk48 after 10.05 ns; + clk48 <= not clk48 after 10.417 ns; reset <= '1', '0' after 300 ns; dsubre <= '0'; @@ -113,18 +103,18 @@ begin mcb3_dram_dq => mcb3_dram_dq, mcb3_rzq => mcb3_rzq, mcb3_zio => mcb3_zio, - mcb3_dram_udqs => mcb3_dram_udqs, - mcb3_dram_udqs_n => mcb3_dram_udqs_n, - mcb3_dram_dqs => mcb3_dram_dqs, - mcb3_dram_dqs_n => mcb3_dram_dqs_n, + mcb3_dram_udqs => mcb3_dram_dqs(1), + mcb3_dram_udqs_n => mcb3_dram_dqs_n(1), + mcb3_dram_dqs => mcb3_dram_dqs(0), + mcb3_dram_dqs_n => mcb3_dram_dqs_n(0), mcb3_dram_a => mcb3_dram_a, mcb3_dram_ba => mcb3_dram_ba, mcb3_dram_cke => mcb3_dram_cke, mcb3_dram_ras_n => mcb3_dram_ras_n, mcb3_dram_cas_n => mcb3_dram_cas_n, mcb3_dram_we_n => mcb3_dram_we_n, - mcb3_dram_dm => mcb3_dram_dm, - mcb3_dram_udm => mcb3_dram_udm, + mcb3_dram_dm => mcb3_dram_dm(0), + mcb3_dram_udm => mcb3_dram_dm(1), mcb3_dram_ck => mcb3_dram_ck, mcb3_dram_ck_n => mcb3_dram_ck_n, -- Debug support unit @@ -145,18 +135,14 @@ begin migddr2mem : if (CFG_MIG_DDR2 = 1) generate - u0 : HY5PS121621F - generic map (TimingCheckFlag => false, PUSCheckFlag => false, - index => 0, bbits => 16, fname => sdramfile, - fdelay => 115, part_number => B800) - port map (DQ => mcb3_dram_dq, - LDQS => mcb3_dram_dqs, LDQSB => mcb3_dram_dqs_n, - UDQS => mcb3_dram_udqs, UDQSB => mcb3_dram_udqs_n, - LDM => mcb3_dram_dm, WEB => mcb3_dram_we_n, - CASB => mcb3_dram_cas_n, RASB => mcb3_dram_ras_n, - CSB => csb, BA => mcb3_dram_ba(1 downto 0), ADDR => mcb3_dram_a, - CKE => mcb3_dram_cke, CLK => mcb3_dram_ck, - CLKB => mcb3_dram_ck_n, UDM => mcb3_dram_udm); + ddr0 : ddr2ram + generic map(width => 16, abits => 13, babits => 3, colbits => 10, rowbits => 13, + implbanks => 1, fname => sdramfile, speedbin=>9, density => 2, + lddelay => 115 us) + port map (ck => mcb3_dram_ck, ckn => mcb3_dram_ck_n, cke => mcb3_dram_cke, csn => csb, + odt => '0', rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n, + dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a(12 downto 0), + dq => mcb3_dram_dq, dqs => mcb3_dram_dqs, dqsn => mcb3_dram_dqs_n); end generate; --spimem0: if CFG_SPIMCTRL = 1 generate diff --git a/designs/leon3-ztex-ufm-115/tkconfig.h b/designs/leon3-ztex-ufm-115/tkconfig.h index c44ec8b1..d7aa9833 100644 --- a/designs/leon3-ztex-ufm-115/tkconfig.h +++ b/designs/leon3-ztex-ufm-115/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/leon3mp/config.help b/designs/leon3mp/config.help index 088f5249..acc4dd0f 100644 --- a/designs/leon3mp/config.help +++ b/designs/leon3mp/config.help @@ -440,19 +440,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -460,10 +461,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/designs/leon3mp/config.vhd b/designs/leon3mp/config.vhd index b5ea5626..f6cf0f3f 100644 --- a/designs/leon3mp/config.vhd +++ b/designs/leon3mp/config.vhd @@ -58,7 +58,7 @@ package config is constant CFG_DLINE : integer := 8; constant CFG_DREPL : integer := 0; constant CFG_DLOCK : integer := 0; - constant CFG_DSNOOP : integer := 0 + 0 + 4*0; + constant CFG_DSNOOP : integer := 0*2 + 4*0; constant CFG_DFIXED : integer := 16#0#; constant CFG_DLRAMEN : integer := 0; constant CFG_DLRAMADDR: integer := 16#8F#; diff --git a/designs/leon3mp/config.vhd.h b/designs/leon3mp/config.vhd.h index 21647e25..527910bf 100644 --- a/designs/leon3mp/config.vhd.h +++ b/designs/leon3mp/config.vhd.h @@ -46,7 +46,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/designs/leon3mp/lconfig.tk b/designs/leon3mp/lconfig.tk index 1e5e4ad7..76878003 100755 --- a/designs/leon3mp/lconfig.tk +++ b/designs/leon3mp/lconfig.tk @@ -2082,24 +2082,23 @@ proc menu6 {w title} { menusplit $w $w.config.f.x13.x.menu 4 bool $w.config.f 6 14 "Cache locking " CONFIG_DCACHE_LOCK bool $w.config.f 6 15 "AHB snooping " CONFIG_DCACHE_SNOOP - bool $w.config.f 6 16 "Fast snooping " CONFIG_DCACHE_SNOOP_FAST - bool $w.config.f 6 17 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG - hex $w.config.f 6 18 "Fixed cacheability map " CONFIG_CACHE_FIXED - bool $w.config.f 6 19 "Enable local data RAM " CONFIG_DCACHE_LRAM + bool $w.config.f 6 16 "Separate snoop tags " CONFIG_DCACHE_SNOOP_SEPTAG + hex $w.config.f 6 17 "Fixed cacheability map " CONFIG_CACHE_FIXED + bool $w.config.f 6 18 "Enable local data RAM " CONFIG_DCACHE_LRAM global tmpvar_18 - minimenu $w.config.f 6 20 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 - menu $w.config.f.x20.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" - $w.config.f.x20.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" - $w.config.f.x20.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" - menusplit $w $w.config.f.x20.x.menu 9 - hex $w.config.f 6 21 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART + minimenu $w.config.f 6 19 "Local data RAM size (kbytes)" tmpvar_18 CONFIG_DCACHE_LRAM_SZ1 + menu $w.config.f.x19.x.menu -tearoffcommand "menutitle \"Local data RAM size (kbytes)\"" + $w.config.f.x19.x.menu add radiobutton -label "1" -variable tmpvar_18 -value "1" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "2" -variable tmpvar_18 -value "2" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "4" -variable tmpvar_18 -value "4" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "8" -variable tmpvar_18 -value "8" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "16" -variable tmpvar_18 -value "16" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "32" -variable tmpvar_18 -value "32" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "64" -variable tmpvar_18 -value "64" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "128" -variable tmpvar_18 -value "128" -command "update_active" + $w.config.f.x19.x.menu add radiobutton -label "256" -variable tmpvar_18 -value "256" -command "update_active" + menusplit $w $w.config.f.x19.x.menu 9 + hex $w.config.f 6 20 " Local data RAM start address (8 MSB) " CONFIG_DCACHE_LRSTART @@ -2171,20 +2170,17 @@ proc update_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { configure_entry .menu6.config.f.x15 normal {n l y}} else {configure_entry .menu6.config.f.x15 disabled {y n l}} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - configure_entry .menu6.config.f.x17 normal {n l y}} else {configure_entry .menu6.config.f.x17 disabled {y n l}} + configure_entry .menu6.config.f.x16 normal {n l y}} else {configure_entry .menu6.config.f.x16 disabled {y n l}} global CONFIG_CACHE_FIXED - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x18.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x18.l configure -state normal; } else {.menu6.config.f.x18.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x18.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {.menu6.config.f.x17.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x17.l configure -state normal; } else {.menu6.config.f.x17.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x17.l configure -state disabled} global CONFIG_DCACHE_LRAM if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then { - configure_entry .menu6.config.f.x19 normal {n l y}} else {configure_entry .menu6.config.f.x19 disabled {y n l}} - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x20 normal {x l}} else {configure_entry .menu6.config.f.x20 disabled {x l}} + configure_entry .menu6.config.f.x18 normal {n l y}} else {configure_entry .menu6.config.f.x18 disabled {y n l}} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {configure_entry .menu6.config.f.x19 normal {x l}} else {configure_entry .menu6.config.f.x19 disabled {x l}} global CONFIG_DCACHE_LRSTART - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x21.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x21.l configure -state normal; } else {.menu6.config.f.x21.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x21.l configure -state disabled} + if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_LRAM == 1)} then {.menu6.config.f.x20.x configure -state normal -foreground [ cget .ref -foreground ]; .menu6.config.f.x20.l configure -state normal; } else {.menu6.config.f.x20.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu6.config.f.x20.l configure -state disabled} } @@ -2317,9 +2313,6 @@ proc update_define_menu6 {} { global CONFIG_DCACHE_SNOOP if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then { set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP&15]} else {set CONFIG_DCACHE_SNOOP [expr $CONFIG_DCACHE_SNOOP|16]} - global CONFIG_DCACHE_SNOOP_FAST - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { - set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST&15]} else {set CONFIG_DCACHE_SNOOP_FAST [expr $CONFIG_DCACHE_SNOOP_FAST|16]} global CONFIG_DCACHE_SNOOP_SEPTAG if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then { set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG&15]} else {set CONFIG_DCACHE_SNOOP_SEPTAG [expr $CONFIG_DCACHE_SNOOP_SEPTAG|16]} @@ -3130,7 +3123,7 @@ proc menu12 {w title} { hex $w.config.f 12 6 "MSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHMSB hex $w.config.f 12 7 "LSB 24 bits of ethern number (hex) " CONFIG_DSU_ETHLSB bool $w.config.f 12 8 "Programmable 4-bit LSB of MAC/IP address" CONFIG_DSU_ETH_PROG - bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS + bool $w.config.f 12 9 "EDCL disable pin " CONFIG_DSU_ETH_DIS @@ -3180,12 +3173,11 @@ proc update_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x6.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x6.l configure -state normal; } else {.menu12.config.f.x6.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x6.l configure -state disabled} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {.menu12.config.f.x7.x configure -state normal -foreground [ cget .ref -foreground ]; .menu12.config.f.x7.l configure -state normal; } else {.menu12.config.f.x7.x configure -state disabled -foreground [ cget .ref -disabledforeground ]; .menu12.config.f.x7.l configure -state disabled} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { configure_entry .menu12.config.f.x8 normal {n l y}} else {configure_entry .menu12.config.f.x8 disabled {y n l}} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { configure_entry .menu12.config.f.x9 normal {n l y}} else {configure_entry .menu12.config.f.x9 disabled {y n l}} } @@ -3216,12 +3208,11 @@ proc update_define_menu12 {} { if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHMSB "$CONFIG_DSU_ETHMSB" 020000} global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {validate_hex CONFIG_DSU_ETHLSB "$CONFIG_DSU_ETHLSB" 000000} - global CONFIG_GRETH_GIGA global CONFIG_DSU_ETH_PROG - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then { set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG&15]} else {set CONFIG_DSU_ETH_PROG [expr $CONFIG_DSU_ETH_PROG|16]} global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then { + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then { set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS&15]} else {set CONFIG_DSU_ETH_DIS [expr $CONFIG_DSU_ETH_DIS|16]} } @@ -5324,7 +5315,6 @@ set CONFIG_DCACHE_ALGOLRR 0 set CONFIG_DCACHE_ALGOLRU 0 set CONFIG_DCACHE_LOCK 0 set CONFIG_DCACHE_SNOOP 0 -set CONFIG_DCACHE_SNOOP_FAST 0 set CONFIG_DCACHE_SNOOP_SEPTAG 0 set CONFIG_CACHE_FIXED 0 set CONFIG_DCACHE_LRAM 0 @@ -5580,6 +5570,7 @@ set CONFIG_GRGPIO_IMASK 0000 set CONFIG_DEBUG_UART 0 set CONFIG_SYN_ARTISAN 4 set CONFIG_PCI_ENABLE 4 +set CONFIG_DCACHE_SNOOP_FAST 4 set CONFIG_HAS_SHARED_GRFPU 4 set CONFIG_FPU_GRFPU_SH 4 set CONFIG_LEON3FT_PRESENT 4 @@ -6037,7 +6028,6 @@ proc writeconfig {file1 file2} { if { $tmpvar_17 == "LRU" } then { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 1 [list $notmod] 2 } else { write_tristate $cfg $autocfg CONFIG_DCACHE_ALGOLRU 0 [list $notmod] 2 }} if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_ASSO1 != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LOCK $CONFIG_DCACHE_LOCK [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP $CONFIG_DCACHE_SNOOP [list $notmod] 2 } - if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_FAST $CONFIG_DCACHE_SNOOP_FAST [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_DCACHE_ENABLE == 1) && ($CONFIG_DCACHE_SNOOP == 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_SNOOP_SEPTAG $CONFIG_DCACHE_SNOOP_SEPTAG [list $notmod] 2 } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_ICACHE_ENABLE == 1 || $CONFIG_DCACHE_ENABLE == 1)} then {write_hex $cfg $autocfg CONFIG_CACHE_FIXED $CONFIG_CACHE_FIXED $notmod } if {($CONFIG_LEON3 == 1) && ($CONFIG_LEON3_CUSTOM == 1) && ($CONFIG_MMU_ENABLE != 1)} then {write_tristate $cfg $autocfg CONFIG_DCACHE_LRAM $CONFIG_DCACHE_LRAM [list $notmod] 2 } @@ -6160,10 +6150,9 @@ proc writeconfig {file1 file2} { global CONFIG_DSU_ETHLSB if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_hex $cfg $autocfg CONFIG_DSU_ETHLSB $CONFIG_DSU_ETHLSB $notmod } global CONFIG_DSU_ETH_PROG - global CONFIG_GRETH_GIGA - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_PROG $CONFIG_DSU_ETH_PROG [list $notmod] 2 } global CONFIG_DSU_ETH_DIS - if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_GRETH_GIGA == 0)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } + if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_DSU_ETH == 1) && ($CONFIG_DSU_ETH_PROG == 1)} then {write_tristate $cfg $autocfg CONFIG_DSU_ETH_DIS $CONFIG_DSU_ETH_DIS [list $notmod] 2 } write_comment $cfg $autocfg "Peripherals " write_comment $cfg $autocfg "Memory controllers " write_comment $cfg $autocfg "8/32-bit PROM/SRAM controller " @@ -6266,6 +6255,7 @@ proc writeconfig {file1 file2} { if {($CONFIG_AHBRAM_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_AHBRAM_PIPE $CONFIG_AHBRAM_PIPE [list $notmod] 2 } write_comment $cfg $autocfg "Ethernet " write_tristate $cfg $autocfg CONFIG_GRETH_ENABLE $CONFIG_GRETH_ENABLE [list $notmod] 2 + global CONFIG_GRETH_GIGA if {($CONFIG_GRETH_ENABLE == 1)} then {write_tristate $cfg $autocfg CONFIG_GRETH_GIGA $CONFIG_GRETH_GIGA [list $notmod] 2 } global tmpvar_32 if {($CONFIG_GRETH_ENABLE == 1) && ($CONFIG_GRETH_GIGA == 0)} then { diff --git a/designs/leon3mp/leon3mp.vhd b/designs/leon3mp/leon3mp.vhd index 91f79d2e..5b255842 100644 --- a/designs/leon3mp/leon3mp.vhd +++ b/designs/leon3mp/leon3mp.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3mp/testbench.vhd b/designs/leon3mp/testbench.vhd index 492f72bd..ce11a660 100644 --- a/designs/leon3mp/testbench.vhd +++ b/designs/leon3mp/testbench.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/designs/leon3mp/tkconfig.h b/designs/leon3mp/tkconfig.h index a800c20b..2f1ffa8f 100644 --- a/designs/leon3mp/tkconfig.h +++ b/designs/leon3mp/tkconfig.h @@ -475,10 +475,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/designs/netcard/Makefile b/designs/netcard/Makefile index b746e66d..c9fdd484 100644 --- a/designs/netcard/Makefile +++ b/designs/netcard/Makefile @@ -22,7 +22,7 @@ DIRSKIP = b1553 pci/pcif leon2 leon2ft crypto satcan ddr usb leon3ft \ usbhc leon3 can i2c satcan ascs spi memctrl hcan slink \ leon4 leon4v0 leon3v3 clk2x srmmu irqmp -FILESKIP = i2cmst.vhd +FILESKIP = i2cmst.vhd sgmii.vhd include $(GRLIB)/bin/Makefile include $(GRLIB)/software/leon3/Makefile diff --git a/designs/netcard/netcard.vhd b/designs/netcard/netcard.vhd index 28cbb52c..c9ad13b6 100644 --- a/designs/netcard/netcard.vhd +++ b/designs/netcard/netcard.vhd @@ -4,7 +4,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/doc/Changelog.txt b/doc/Changelog.txt index 6d4fb22e..518c3f87 100644 --- a/doc/Changelog.txt +++ b/doc/Changelog.txt @@ -1,3 +1,77 @@ +----------------------- Release 1.3.7-b4144 ---------------------------- + +2014-04-16 Change default assignment of GRLIB_SIMULATOR to ModelSim + +2014-04-15 DDR3RAM sim model: Improve memory usage + +2014-04-11 RGMII: First revision of documentation for the RGMII IP + +2014-04-11 SAED32-TECHMAP: Fixed Bidir mapping and corrected erroneous + instantiation of technology memory. + +2014-04-11 LEON3-ASIC: Fixed simulation for SAED32 technology library + and modified design to work with base_test and greth_test + in systest + +2014-04-10 Xilinx techmap: Assign SIM_COLLISION_CHECK generic in techmap + layer instead of patching UNSIM sources. + +2014-04-10 Disable install-unisim and install-secureip targets when + GRLIB_SIMULATOR is set to Xilinx. + +2014-04-10 Updated PlanAhead script generation to allow ISim simulation + +2014-04-08 Updated the leon3-digilent-xc7z020 design to working condition + +2014-04-04 10/100Mbit mode fix for RGMII and SGMII on Xilinx designs + - Fixed 10/100Mbit mode in RGMII for ref designs KC705, + AC701 and GR-XC6 + - Fixed 10/100Mbit mode in SGMII for ref designs VC707 + +2013-04-04 PlanAhead flow updated to improve overall timing + +2013-04-04 GRETH/GRETH_GBIT updated to support unchanged clock speed for + lower bit rates + +2013-03-25 Remove lib/openchip + +2013-03-25 Add template design for Xilinx AC701 board (leon3-xilinx-ac701) + +2013-03-21 Set Unisim pad delays to zero to match ISE simulation model + behavior. + +2013-03-18 GPTIMER/GRTIMER: Merge GRTIMER functionality into GPTIMER. + +2014-03-06 DSU3: Add dsu3_mb to allow AHB trace of second AHB bus + +2014-03-05 LEON3v3: Rearranged and updated IP core documentation. + +2014-03-05 LEON3v3: Removed fast snooping option from xconfig menus, + default to always on. + +2014-03-05 LEON3v3: Added safeguard to generate error in simulation if FT + features are accidentally enabled on non-FT version of LEON3. + +2014-03-01 LEON3v3: Improve performance for d-cache in frozen state by + only fetching missing data instead of full d-cache line. + +2014-02-17 GPTIMER: Add WDOGDIS and WDOGNMI fields, see GRIP for details. + +2014-02-16 systest: Add -qnoambapp option if LDFLAGS variable is + undefined. If -qnoambapp leads to errors then these can be + fixed by defining LDFLAGS or installing a recent BCC version. + +2014-02-09 MUL32/DIV32: Add support for grlib_async_reset_enable. + +2014-01-18 Update documentation to warn for use of -use_new_parser yes + with Xilinx XST. + +2014-01-13 Remove planAhead make target, use only planahead. + +2014-01-03 Added generic DDR1, DDR2, DDR3 SDRAM simulation models + under lib/gaisler/sim.vhd. Updated most template designs + to use new models. + ----------------------- Release 1.3.4-b4140 ---------------------------- 2013-12-19 Fixed Xilinx planAhead flow for Spartan6 designs diff --git a/doc/grip.pdf b/doc/grip.pdf index 684e2aa5..5da63252 100644 Binary files a/doc/grip.pdf and b/doc/grip.pdf differ diff --git a/doc/grlib.pdf b/doc/grlib.pdf index 0aecf102..5ae7333e 100644 Binary files a/doc/grlib.pdf and b/doc/grlib.pdf differ diff --git a/doc/guide.pdf b/doc/guide.pdf index 8a8f7b34..cddb8edc 100644 Binary files a/doc/guide.pdf and b/doc/guide.pdf differ diff --git a/lib/esa/memoryctrl/memoryctrl.vhd b/lib/esa/memoryctrl/memoryctrl.vhd index 4da151d4..1fc596ec 100644 --- a/lib/esa/memoryctrl/memoryctrl.vhd +++ b/lib/esa/memoryctrl/memoryctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/eth/comp/ethcomp.vhd b/lib/eth/comp/ethcomp.vhd index dea62025..05a6549c 100644 --- a/lib/eth/comp/ethcomp.vhd +++ b/lib/eth/comp/ethcomp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -46,7 +46,8 @@ package ethcomp is edclsepahbg : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer + maxsize : integer; + gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -118,10 +119,12 @@ package ethcomp is rmii_clk : in std_ulogic; tx_clk : in std_ulogic; rx_clk : in std_ulogic; + tx_dv : in std_ulogic; rxd : in std_logic_vector(3 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; + rx_en : in std_ulogic; rx_crs : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); @@ -169,7 +172,9 @@ package ethcomp is multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - mdiohold : integer := 1); + mdiohold : integer := 1; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -239,12 +244,14 @@ package ethcomp is --ethernet input signals gtx_clk : in std_ulogic; tx_clk : in std_ulogic; + tx_dv : in std_ulogic; rx_clk : in std_ulogic; rxd : in std_logic_vector(7 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; rx_crs : in std_ulogic; + rx_en : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); mdint : in std_ulogic; @@ -285,11 +292,13 @@ package ethcomp is ipaddrl : integer := 16#0035#; phyrstadr : integer range 0 to 31 := 0; rmii : integer range 0 to 1 := 0; - oepol : integer range 0 to 1 := 0; - scanen : integer range 0 to 1 := 0; + oepol : integer range 0 to 1 := 0; + scanen : integer range 0 to 1 := 0; mdint_pol : integer range 0 to 1 := 0; enable_mdint : integer range 0 to 1 := 0; - multicast : integer range 0 to 1 := 0); + multicast : integer range 0 to 1 := 0; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -309,24 +318,26 @@ package ethcomp is hprot : out std_logic_vector(3 downto 0); hwdata : out std_logic_vector(31 downto 0); --apb slv in - psel : in std_ulogic; - penable : in std_ulogic; - paddr : in std_logic_vector(31 downto 0); - pwrite : in std_ulogic; - pwdata : in std_logic_vector(31 downto 0); + psel : in std_ulogic; + penable : in std_ulogic; + paddr : in std_logic_vector(31 downto 0); + pwrite : in std_ulogic; + pwdata : in std_logic_vector(31 downto 0); --apb slv out - prdata : out std_logic_vector(31 downto 0); + prdata : out std_logic_vector(31 downto 0); --irq irq : out std_logic; --ethernet input signals rmii_clk : in std_ulogic; tx_clk : in std_ulogic; + tx_dv : in std_ulogic; rx_clk : in std_ulogic; rxd : in std_logic_vector(3 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; rx_crs : in std_ulogic; + rx_en : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); mdint : in std_ulogic; @@ -375,7 +386,9 @@ package ethcomp is enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; - ramdebug : integer range 0 to 2 := 0); + ramdebug : integer range 0 to 2 := 0; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; diff --git a/lib/eth/core/eth_ahb_mst.vhd b/lib/eth/core/eth_ahb_mst.vhd index be4d65e5..94f33b91 100644 --- a/lib/eth/core/eth_ahb_mst.vhd +++ b/lib/eth/core/eth_ahb_mst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/eth/core/eth_edcl_ahb_mst.vhd b/lib/eth/core/eth_edcl_ahb_mst.vhd index da54b2c1..4fb6bc60 100644 --- a/lib/eth/core/eth_edcl_ahb_mst.vhd +++ b/lib/eth/core/eth_edcl_ahb_mst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/eth/core/eth_rstgen.vhd b/lib/eth/core/eth_rstgen.vhd index 498fb3c9..da7903cd 100644 --- a/lib/eth/core/eth_rstgen.vhd +++ b/lib/eth/core/eth_rstgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/eth/core/greth_pkg.vhd b/lib/eth/core/greth_pkg.vhd index d95a7491..d85f95ea 100644 --- a/lib/eth/core/greth_pkg.vhd +++ b/lib/eth/core/greth_pkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -26,7 +26,7 @@ package grethpkg is --gigabit sync types type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0); type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0); - + constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00"; constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10"; constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11"; @@ -34,7 +34,7 @@ package grethpkg is constant HBURST_INCR: std_logic_vector(2 downto 0) := "001"; constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010"; - + constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00"; constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01"; constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10"; @@ -45,7 +45,7 @@ package grethpkg is conv_std_logic_vector(1500, 16); constant minpload : std_logic_vector(10 downto 0) := conv_std_logic_vector(60, 11); - + type ahb_fifo_in_type is record renable : std_ulogic; raddress : std_logic_vector(4 downto 0); @@ -55,7 +55,7 @@ package grethpkg is end record; type ahb_fifo_out_type is record - data : std_logic_vector(31 downto 0); + data : std_logic_vector(31 downto 0); end record; type nchar_fifo_in_type is record @@ -124,13 +124,13 @@ package grethpkg is grant : std_ulogic; data : std_logic_vector(31 downto 0); ready : std_ulogic; - error : std_ulogic; - retry : std_ulogic; + error : std_ulogic; + retry : std_ulogic; end record; type eth_rx_ahb_in_type is record req : std_ulogic; - write : std_ulogic; + write : std_ulogic; addr : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0); end record; @@ -145,7 +145,7 @@ package grethpkg is type eth_rx_gbit_ahb_in_type is record req : std_ulogic; - write : std_ulogic; + write : std_ulogic; addr : std_logic_vector(31 downto 0); data : std_logic_vector(31 downto 0); size : std_logic_vector(1 downto 0); @@ -156,6 +156,7 @@ package grethpkg is start : std_ulogic; read_ack : std_ulogic; data : std_logic_vector(31 downto 0); + datavalid : std_ulogic; valid : std_ulogic; len : std_logic_vector(10 downto 0); rx_col : std_ulogic; @@ -163,8 +164,8 @@ package grethpkg is end record; type gbit_tx_host_type is record - txd : std_logic_vector(3 downto 0); - tx_en : std_ulogic; + txd : std_logic_vector(3 downto 0); + tx_en : std_ulogic; done : std_ulogic; read : std_ulogic; restart : std_ulogic; @@ -195,11 +196,12 @@ package grethpkg is rx_er : std_ulogic; rx_col : std_ulogic; rx_crs : std_ulogic; + rx_en : std_ulogic; end record; type gbit_gtx_host_type is record - txd : std_logic_vector(7 downto 0); - tx_en : std_ulogic; + txd : std_logic_vector(7 downto 0); + tx_en : std_ulogic; tx_er : std_ulogic; done : std_ulogic; restart : std_ulogic; @@ -228,6 +230,7 @@ package grethpkg is readack : std_ulogic; speed : std_ulogic; data : std_logic_vector(31 downto 0); + datavalid : std_ulogic; valid : std_ulogic; len : std_logic_vector(10 downto 0); end record; @@ -264,6 +267,7 @@ package grethpkg is rx_crs : std_ulogic; rx_er : std_ulogic; enable : std_ulogic; + rx_en : std_ulogic; end record; component greth_rx is @@ -271,28 +275,32 @@ package grethpkg is nsync : integer range 1 to 2 := 2; rmii : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; - maxsize : integer); + maxsize : integer; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; rxi : in host_rx_type; rxo : out rx_host_type - ); + ); end component; component greth_tx is generic( - ifg_gap : integer := 24; + ifg_gap : integer := 24; attempt_limit : integer := 16; backoff_limit : integer := 10; nsync : integer range 1 to 2 := 2; - rmii : integer range 0 to 1 := 0); + rmii : integer range 0 to 1 := 0; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; txi : in host_tx_type; txo : out tx_host_type - ); + ); end component; component eth_rstgen is @@ -308,20 +316,22 @@ package grethpkg is component greth_gbit_tx is generic( - ifg_gap : integer := 24; + ifg_gap : integer := 24; attempt_limit : integer := 16; backoff_limit : integer := 10; - nsync : integer range 1 to 2 := 2); + nsync : integer range 1 to 2 := 2; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; txi : in gbit_host_tx_type; - txo : out gbit_tx_host_type); + txo : out gbit_tx_host_type); end component; component greth_gbit_gtx is generic( - ifg_gap : integer := 24; + ifg_gap : integer := 24; attempt_limit : integer := 16; backoff_limit : integer := 10; nsync : integer range 1 to 2 := 2); @@ -336,12 +346,14 @@ package grethpkg is component greth_gbit_rx is generic( multicast : integer range 0 to 1 := 0; - nsync : integer range 1 to 2 := 2); + nsync : integer range 1 to 2 := 2; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; rxi : in gbit_host_rx_type; - rxo : out gbit_rx_host_type); + rxo : out gbit_rx_host_type); end component; component eth_ahb_mst is @@ -379,7 +391,7 @@ package grethpkg is tmsto : out eth_tx_ahb_out_type ); end component; - + function mirror(din : in std_logic_vector) return std_logic_vector; function crc32_4(d : in std_logic_vector(3 downto 0); @@ -396,11 +408,11 @@ package grethpkg is bcnt : in std_logic_vector(10 downto 0); usesz : in std_ulogic) return std_ulogic; - + function getfifosize(edcl, fifosize, ebufsize : in integer) return integer; function setburstlength(fifosize : in integer) return integer; - + function calccrc(d : in std_logic_vector(3 downto 0); crc : in std_logic_vector(31 downto 0)) return std_logic_vector; @@ -409,11 +421,11 @@ package grethpkg is function crcadder(d1 : in std_logic_vector(15 downto 0); d2 : in std_logic_vector(17 downto 0)) return std_logic_vector; - + end package; package body grethpkg is - + function mirror(din : in std_logic_vector) return std_logic_vector is variable do : std_logic_vector(din'range); @@ -532,7 +544,7 @@ package body grethpkg is return fifosize; end if; end function; - + function calccrc(d : in std_logic_vector(3 downto 0); crc : in std_logic_vector(31 downto 0)) return std_logic_vector is @@ -576,6 +588,50 @@ package body grethpkg is return ncrc; end function; + + function calccrc_8(data : in std_logic_vector( 7 downto 0); + crc : in std_logic_vector(31 downto 0)) + return std_logic_vector is + variable ncrc : std_logic_vector(31 downto 0); + variable d : std_logic_vector(7 downto 0); + begin + d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3); + d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7); + ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30); + ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31); + ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31); + ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31); + ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30); + ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31); + ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31); + ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31); + ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28); + ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29); + ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29); + ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28); + ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30); + ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31); + ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31); + ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31); + ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29); + ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30); + ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31); + ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31); + ncrc(20) := d(4) xor crc(12) xor crc(28); + ncrc(21) := d(5) xor crc(13) xor crc(29); + ncrc(22) := d(0) xor crc(14) xor crc(24); + ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30); + ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31); + ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27); + ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30); + ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31); + ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30); + ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31); + ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31); + ncrc(31) := d(5) xor crc(23) xor crc(29); + return ncrc; + end function; + --16-bit one's complement adder function crcadder(d1 : in std_logic_vector(15 downto 0); d2 : in std_logic_vector(17 downto 0)) @@ -588,5 +644,5 @@ package body grethpkg is sum := vd1 + vd2; return sum; end function; - + end package body; diff --git a/lib/eth/core/greth_rx.vhd b/lib/eth/core/greth_rx.vhd index 4c03dcea..86b1b3a9 100644 --- a/lib/eth/core/greth_rx.vhd +++ b/lib/eth/core/greth_rx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -35,7 +35,8 @@ entity greth_rx is nsync : integer range 1 to 2 := 2; rmii : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; - maxsize : integer := 1500 + maxsize : integer := 1500; + gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -351,9 +352,23 @@ begin end process; - rxregs : process(clk) is - begin - if rising_edge(clk) then r <= rin; end if; - end process; + gmiimode0 : if gmiimode = 0 generate + rxregs0 : process(clk) is + begin + if rising_edge(clk) then + r <= rin; + end if; + end process; + end generate; + + gmiimode1 : if gmiimode = 1 generate + rxregs1 : process(clk) is + begin + if rising_edge(clk) then + if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if; + end if; + end process; + end generate; + end architecture; diff --git a/lib/eth/core/greth_tx.vhd b/lib/eth/core/greth_tx.vhd index f5b36c35..1aa9b506 100644 --- a/lib/eth/core/greth_tx.vhd +++ b/lib/eth/core/greth_tx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -35,7 +35,9 @@ entity greth_tx is attempt_limit : integer := 16; backoff_limit : integer := 10; nsync : integer range 1 to 2 := 2; - rmii : integer range 0 to 1 := 0); + rmii : integer range 0 to 1 := 0; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -489,18 +491,39 @@ begin txo.status <= r.status; end process; - txregs : process(clk) is - begin - if rising_edge(clk) then - r <= rin; - if rst = '0' then - r.icnt <= (others => '0'); r.delay_val <= (others => '0'); - r.cnt <= (others => '0'); - else - r.icnt <= rin.icnt; r.delay_val <= rin.delay_val; - r.cnt <= rin.cnt; + + gmiimode0 : if gmiimode = 0 generate + txregs0 : process(clk) is + begin + if rising_edge(clk) then + r <= rin; + if rst = '0' then + r.icnt <= (others => '0'); r.delay_val <= (others => '0'); + r.cnt <= (others => '0'); + else + r.icnt <= rin.icnt; r.delay_val <= rin.delay_val; + r.cnt <= rin.cnt; + end if; end if; - end if; - end process; - + end process; + end generate; + + gmiimode1 : if gmiimode = 1 generate + txregs0 : process(clk) is + begin + if rising_edge(clk) then + if txi.datavalid = '1' then r <= rin; end if; + if rst = '0' then + r.icnt <= (others => '0'); r.delay_val <= (others => '0'); + r.cnt <= (others => '0'); + else + if txi.datavalid = '1' then + r.icnt <= rin.icnt; r.delay_val <= rin.delay_val; + r.cnt <= rin.cnt; + end if; + end if; + end if; + end process; + end generate; + end architecture; diff --git a/lib/eth/core/grethc.vhd b/lib/eth/core/grethc.vhd index 20e454ec..d223b0ce 100644 --- a/lib/eth/core/grethc.vhd +++ b/lib/eth/core/grethc.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -17,10 +17,10 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- --- Entity: grethc --- File: grethc.vhd --- Author: Marko Isomaki --- Description: Ethernet Media Access Controller with Ethernet Debug +-- Entity: grethc +-- File: grethc.vhd +-- Author: Marko Isomaki +-- Description: Ethernet Media Access Controller with Ethernet Debug -- Communication Link ------------------------------------------------------------------------------ library ieee; @@ -48,15 +48,17 @@ entity grethc is ipaddrl : integer := 16#0035#; phyrstadr : integer range 0 to 32 := 0; rmii : integer range 0 to 1 := 0; - oepol : integer range 0 to 1 := 0; - scanen : integer range 0 to 1 := 0; + oepol : integer range 0 to 1 := 0; + scanen : integer range 0 to 1 := 0; mdint_pol : integer range 0 to 1 := 0; enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer := 1500); + maxsize : integer := 1500; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -91,13 +93,13 @@ entity grethc is ehprot : out std_logic_vector(3 downto 0); ehwdata : out std_logic_vector(31 downto 0); --apb slv in - psel : in std_ulogic; - penable : in std_ulogic; - paddr : in std_logic_vector(31 downto 0); - pwrite : in std_ulogic; - pwdata : in std_logic_vector(31 downto 0); + psel : in std_ulogic; + penable : in std_ulogic; + paddr : in std_logic_vector(31 downto 0); + pwrite : in std_ulogic; + pwdata : in std_logic_vector(31 downto 0); --apb slv out - prdata : out std_logic_vector(31 downto 0); + prdata : out std_logic_vector(31 downto 0); --irq irq : out std_logic; --rx ahb fifo @@ -127,10 +129,12 @@ entity grethc is rmii_clk : in std_ulogic; tx_clk : in std_ulogic; rx_clk : in std_ulogic; - rxd : in std_logic_vector(3 downto 0); + tx_dv : in std_ulogic; + rxd : in std_logic_vector(3 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; + rx_en : in std_ulogic; rx_crs : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); @@ -241,7 +245,7 @@ architecture rtl of grethc is ta, ta2, ta3, data, dataend); type ctrl_reg_type is record - txen : std_ulogic; + txen : std_ulogic; rxen : std_ulogic; tx_irqen : std_ulogic; rx_irqen : std_ulogic; @@ -2079,7 +2083,7 @@ begin -- SIGNAL ASSIGNMENTS --------------------------------------------------------- ------------------------------------------------------------------------------- rin <= v; - prdata <= vprdata; + prdata <= vprdata; irq <= vpirq; --rx ahb fifo @@ -2123,6 +2127,7 @@ begin rxi.rx_dv <= rx_dv; rxi.rx_crs <= rx_crs; rxi.rx_er <= rx_er; + rxi.rx_en <= rx_en; txi.rx_col <= rx_col; txi.rx_crs <= rx_crs; @@ -2133,6 +2138,7 @@ begin txi.data <= r.txdata; txi.valid <= r.txvalid; txi.len <= r.txlength; + txi.datavalid <= tx_dv; mdc <= r.mdioclk; mdio_o <= r.mdioo; @@ -2176,7 +2182,7 @@ begin ehwdata <= ahbmo2.hwdata; speed <= r.ctrl.speed; - reset <= irst; + reset <= irst; regs : process(clk) is begin @@ -2192,7 +2198,9 @@ begin attempt_limit => attempt_limit, backoff_limit => backoff_limit, nsync => nsync, - rmii => rmii) + rmii => rmii, + gmiimode => gmiimode + ) port map( rst => arst, clk => tx_clk, @@ -2207,7 +2215,9 @@ begin attempt_limit => attempt_limit, backoff_limit => backoff_limit, nsync => nsync, - rmii => rmii) + rmii => rmii, + gmiimode => gmiimode + ) port map( rst => arst, clk => rmii_clk, @@ -2224,7 +2234,9 @@ begin nsync => nsync, rmii => rmii, multicast => multicast, - maxsize => maxsize) + maxsize => maxsize, + gmiimode => gmiimode + ) port map( rst => arst, clk => rx_clk, @@ -2238,7 +2250,8 @@ begin nsync => nsync, rmii => rmii, multicast => multicast, - maxsize => maxsize) + maxsize => maxsize, + gmiimode => gmiimode) port map( rst => arst, clk => rmii_clk, diff --git a/lib/eth/wrapper/greth_gbit_gen.vhd b/lib/eth/wrapper/greth_gbit_gen.vhd index afb0409b..79780757 100644 --- a/lib/eth/wrapper/greth_gbit_gen.vhd +++ b/lib/eth/wrapper/greth_gbit_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -57,7 +57,9 @@ entity greth_gbit_gen is enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; - ramdebug : integer range 0 to 2 := 0); + ramdebug : integer range 0 to 2 := 0; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -104,12 +106,14 @@ entity greth_gbit_gen is --ethernet input signals gtx_clk : in std_ulogic; tx_clk : in std_ulogic; + tx_dv : in std_ulogic; rx_clk : in std_ulogic; rxd : in std_logic_vector(7 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; rx_crs : in std_ulogic; + rx_en : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); mdint : in std_ulogic; @@ -194,7 +198,9 @@ begin enable_mdint => enable_mdint, multicast => multicast, edclsepahbg => edclsepahbg, - ramdebug => ramdebug) + ramdebug => ramdebug, + gmiimode => gmiimode + ) port map( rst => rst, clk => clk, @@ -264,12 +270,14 @@ begin --ethernet input signals gtx_clk => gtx_clk, tx_clk => tx_clk, + tx_dv => tx_dv, rx_clk => rx_clk, rxd => rxd, rx_dv => rx_dv, rx_er => rx_er, rx_col => rx_col, rx_crs => rx_crs, + rx_en => rx_en, mdio_i => mdio_i, phyrstaddr => phyrstaddr, mdint => mdint, diff --git a/lib/eth/wrapper/greth_gen.vhd b/lib/eth/wrapper/greth_gen.vhd index 412f7ab4..51cff84c 100644 --- a/lib/eth/wrapper/greth_gen.vhd +++ b/lib/eth/wrapper/greth_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -58,7 +58,8 @@ entity greth_gen is multicast : integer range 0 to 1 := 0; edclsepahbg : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - maxsize : integer + maxsize : integer; + gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -94,23 +95,25 @@ entity greth_gen is ehprot : out std_logic_vector(3 downto 0); ehwdata : out std_logic_vector(31 downto 0); --apb slv in - psel : in std_ulogic; - penable : in std_ulogic; - paddr : in std_logic_vector(31 downto 0); - pwrite : in std_ulogic; - pwdata : in std_logic_vector(31 downto 0); + psel : in std_ulogic; + penable : in std_ulogic; + paddr : in std_logic_vector(31 downto 0); + pwrite : in std_ulogic; + pwdata : in std_logic_vector(31 downto 0); --apb slv out - prdata : out std_logic_vector(31 downto 0); + prdata : out std_logic_vector(31 downto 0); --irq irq : out std_logic; --ethernet input signals rmii_clk : in std_ulogic; tx_clk : in std_ulogic; + tx_dv : in std_ulogic; rx_clk : in std_ulogic; rxd : in std_logic_vector(3 downto 0); rx_dv : in std_ulogic; rx_er : in std_ulogic; rx_col : in std_ulogic; + rx_en : in std_ulogic; rx_crs : in std_ulogic; mdio_i : in std_ulogic; phyrstaddr : in std_logic_vector(4 downto 0); @@ -204,7 +207,9 @@ begin multicast => multicast, edclsepahbg => edclsepahbg, ramdebug => ramdebug, - maxsize => maxsize) + maxsize => maxsize, + gmiimode => gmiimode + ) port map( rst => rst, clk => clk, @@ -274,11 +279,13 @@ begin --ethernet input signals rmii_clk => rmii_clk, tx_clk => tx_clk, + tx_dv => tx_dv, rx_clk => rx_clk, rxd => rxd(3 downto 0), rx_dv => rx_dv, rx_er => rx_er, rx_col => rx_col, + rx_en => rx_en, rx_crs => rx_crs, mdio_i => mdio_i, phyrstaddr => phyrstaddr, diff --git a/lib/gaisler/ambatest/ahbtbm.vhd b/lib/gaisler/ambatest/ahbtbm.vhd index 573b19ad..d285dcf6 100644 --- a/lib/gaisler/ambatest/ahbtbm.vhd +++ b/lib/gaisler/ambatest/ahbtbm.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ambatest/ahbtbp.vhd b/lib/gaisler/ambatest/ahbtbp.vhd index 141cd5a9..95d44c16 100644 --- a/lib/gaisler/ambatest/ahbtbp.vhd +++ b/lib/gaisler/ambatest/ahbtbp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ambatest/ahbtbs.vhd b/lib/gaisler/ambatest/ahbtbs.vhd index 453dec8b..0ad47c97 100644 --- a/lib/gaisler/ambatest/ahbtbs.vhd +++ b/lib/gaisler/ambatest/ahbtbs.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/arith/arith.vhd b/lib/gaisler/arith/arith.vhd index 81f3b49b..71759140 100644 --- a/lib/gaisler/arith/arith.vhd +++ b/lib/gaisler/arith/arith.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -65,12 +65,15 @@ type mul32_out_type is record end record; component div32 +generic (scantest : integer := 0); port ( rst : in std_ulogic; clk : in std_ulogic; holdn : in std_ulogic; divi : in div32_in_type; - divo : out div32_out_type + divo : out div32_out_type; + testen : in std_ulogic := '0'; + testrst : in std_ulogic := '1' ); end component; @@ -80,14 +83,17 @@ generic ( multype : integer := 0; pipe : integer := 0; mac : integer := 0; - arch : integer range 0 to 3 := 0 + arch : integer range 0 to 3 := 0; + scantest: integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; holdn : in std_ulogic; muli : in mul32_in_type; - mulo : out mul32_out_type + mulo : out mul32_out_type; + testen : in std_ulogic := '0'; + testrst : in std_ulogic := '1' ); end component; diff --git a/lib/gaisler/arith/div32.vhd b/lib/gaisler/arith/div32.vhd index 6545d6a5..e4b9d8c7 100644 --- a/lib/gaisler/arith/div32.vhd +++ b/lib/gaisler/arith/div32.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -40,12 +40,15 @@ library gaisler; use gaisler.arith.all; entity div32 is +generic (scantest : integer := 0); port ( rst : in std_ulogic; clk : in std_ulogic; holdn : in std_ulogic; divi : in div32_in_type; - divo : out div32_out_type + divo : out div32_out_type; + testen : in std_ulogic := '0'; + testrst : in std_ulogic := '1' ); end; @@ -66,6 +69,7 @@ type div_regtype is record end record; constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; +constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1; constant RRES : div_regtype := ( x => (others => '0'), state => (others => '0'), @@ -80,12 +84,17 @@ constant RRES : div_regtype := ( cnt => (others => '0')); +signal arst : std_ulogic; signal r, rin : div_regtype; signal addin1, addin2, addout: std_logic_vector(32 downto 0); signal addsub : std_logic; begin + arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else + rst when ASYNC_RESET else + '1'; + divcomb : process (r, rst, divi, addout) variable v : div_regtype; variable vready, vnready : std_logic; @@ -162,7 +171,7 @@ begin divo.icc <= r.x(63) & r.qzero & r.ovf & '0'; if (divi.flush = '1') then v.state := "000"; end if; - if (not RESET_ALL) and (rst = '0') then + if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then v.state := RRES.state; v.cnt := RRES.cnt; end if; rin <= v; @@ -179,19 +188,31 @@ begin addout <= addin1 + b + addsub; end process; - reg : process(clk) - begin - if rising_edge(clk) then - if (holdn = '1') then r <= rin; end if; - if (rst = '0') then - if RESET_ALL then - r <= RRES; - else - r.state <= RRES.state; r.cnt <= RRES.cnt; + syncrregs : if not ASYNC_RESET generate + reg : process(clk) + begin + if rising_edge(clk) then + if (holdn = '1') then r <= rin; end if; + if (rst = '0') then + if RESET_ALL then + r <= RRES; + else + r.state <= RRES.state; r.cnt <= RRES.cnt; + end if; end if; end if; - end if; - end process; + end process; + end generate syncrregs; + asyncrregs : if ASYNC_RESET generate + reg : process(clk, arst) + begin + if (arst = '0') then + r <= RRES; + elsif rising_edge(clk) then + if (holdn = '1') then r <= rin; end if; + end if; + end process; + end generate asyncrregs; end; diff --git a/lib/gaisler/arith/mul32.vhd b/lib/gaisler/arith/mul32.vhd index 49bb3424..e0a7449d 100644 --- a/lib/gaisler/arith/mul32.vhd +++ b/lib/gaisler/arith/mul32.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -42,14 +42,17 @@ generic ( multype : integer range 0 to 3 := 0; pipe : integer range 0 to 1 := 0; mac : integer range 0 to 1 := 0; - arch : integer range 0 to 3 := 0 + arch : integer range 0 to 3 := 0; + scantest: integer := 0 ); port ( rst : in std_ulogic; clk : in std_ulogic; holdn : in std_ulogic; muli : in mul32_in_type; - mulo : out mul32_out_type + mulo : out mul32_out_type; + testen : in std_ulogic := '0'; + testrst : in std_ulogic := '1' ); end; @@ -81,6 +84,7 @@ type mac_regtype is record end record; constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; +constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1; constant MULRES : mul_regtype := ( acc => (others => '0'), state => (others => '0'), @@ -93,6 +97,7 @@ constant MACRES : mac_regtype := ( msigned => '0', xsigned => '0'); +signal arst : std_ulogic; signal rm, rmin : mul_regtype; signal mm, mmin : mac_regtype; signal ma, mb : std_logic_vector(32 downto 0); @@ -102,7 +107,11 @@ signal vcc : std_logic; begin - vcc <= '1'; + vcc <= '1'; + + arst <= testrst when (ASYNC_RESET and scantest/=0 and testen/='0') else + rst when ASYNC_RESET else + '1'; mulcomb : process(rst, rm, muli, mreg, prod, mm) variable mop1, mop2 : std_logic_vector(32 downto 0); @@ -300,7 +309,7 @@ begin -- drive result and condition codes if (muli.flush = '1') then v.state := "00"; v.start := '0'; end if; - if (not RESET_ALL) and (rst = '0') then + if (not ASYNC_RESET) and (not RESET_ALL) and (rst = '0') then v.nready := MULRES.nready; v.ready := MULRES.ready; v.state := MULRES.state; v.start := MULRES.start; end if; @@ -352,19 +361,35 @@ begin xm1616 : if MULTIPLIER = m16x16 generate m1616 : techmult generic map (tech, arch, 17, 17, pipe+1, pipe) port map (ma(16 downto 0), mb(16 downto 0), clk, holdn, vcc, prod(33 downto 0)); - reg : process(clk) - begin - if rising_edge(clk) then - if (holdn = '1') then - mm <= mmin; - mreg(33 downto 0) <= prod(33 downto 0); - end if; - if RESET_ALL and (rst = '0') then + syncrregs : if not ASYNC_RESET generate + reg : process(clk) + begin + if rising_edge(clk) then + if (holdn = '1') then + mm <= mmin; + mreg(33 downto 0) <= prod(33 downto 0); + end if; + if RESET_ALL and (rst = '0') then + mm <= MACRES; + mreg(33 downto 0) <= (others => '0'); + end if; + end if; + end process; + end generate syncrregs; + asyncrregs : if ASYNC_RESET generate + reg : process(clk, arst) + begin + if (arst = '0') then mm <= MACRES; mreg(33 downto 0) <= (others => '0'); + elsif rising_edge(clk) then + if (holdn = '1') then + mm <= mmin; + mreg(33 downto 0) <= prod(33 downto 0); + end if; end if; - end if; - end process; + end process; + end generate asyncrregs; mreg(49 downto 34) <= (others => '0'); prod(65 downto 34) <= (others => '0'); end generate; @@ -390,21 +415,31 @@ begin mreg <= (others => '0'); end generate; - - reg : process(clk) - begin - if rising_edge(clk) then - if (holdn = '1') then rm <= rmin; end if; - if (rst = '0') then - if RESET_ALL then - rm <= MULRES; - else - rm.nready <= MULRES.nready; rm.ready <= MULRES.ready; - rm.state <= MULRES.state; rm.start <= MULRES.start; + syncrregs : if not ASYNC_RESET generate + reg : process(clk) + begin + if rising_edge(clk) then + if (holdn = '1') then rm <= rmin; end if; + if (rst = '0') then + if RESET_ALL then + rm <= MULRES; + else + rm.nready <= MULRES.nready; rm.ready <= MULRES.ready; + rm.state <= MULRES.state; rm.start <= MULRES.start; + end if; end if; end if; - end if; - end process; + end process; + end generate syncrregs; + asyncrregs : if ASYNC_RESET generate + reg : process(clk, arst) + begin + if (arst = '0') then + rm <= MULRES; + elsif rising_edge(clk) then + if (holdn = '1') then rm <= rmin; end if; + end if; + end process; + end generate asyncrregs; end; - diff --git a/lib/gaisler/can/can.vhd b/lib/gaisler/can/can.vhd index 30f8740b..3109ebef 100644 --- a/lib/gaisler/can/can.vhd +++ b/lib/gaisler/can/can.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/can/can_mc.vhd b/lib/gaisler/can/can_mc.vhd index 34827a7a..d4963194 100644 --- a/lib/gaisler/can/can_mc.vhd +++ b/lib/gaisler/can/can_mc.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/can/can_mod.vhd b/lib/gaisler/can/can_mod.vhd index 5cc254e0..ab2863a5 100644 --- a/lib/gaisler/can/can_mod.vhd +++ b/lib/gaisler/can/can_mod.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/can/can_oc.vhd b/lib/gaisler/can/can_oc.vhd index 427c04c2..64c4f4dc 100644 --- a/lib/gaisler/can/can_oc.vhd +++ b/lib/gaisler/can/can_oc.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/can/can_rd.vhd b/lib/gaisler/can/can_rd.vhd index 946fecb4..a2e9684c 100644 --- a/lib/gaisler/can/can_rd.vhd +++ b/lib/gaisler/can/can_rd.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ahb2avl_async.vhd b/lib/gaisler/ddr/ahb2avl_async.vhd index b4905961..246d7dd1 100644 --- a/lib/gaisler/ddr/ahb2avl_async.vhd +++ b/lib/gaisler/ddr/ahb2avl_async.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -131,6 +131,7 @@ begin generic map ( avldbits => avldbits, avlabits => avlabits, + ahbbits => ahbbits, burstlen => burstlen, nosync => nosync ) diff --git a/lib/gaisler/ddr/ahb2avl_async_be.vhd b/lib/gaisler/ddr/ahb2avl_async_be.vhd index d8cb3d6e..8cb9dd68 100644 --- a/lib/gaisler/ddr/ahb2avl_async_be.vhd +++ b/lib/gaisler/ddr/ahb2avl_async_be.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -27,6 +27,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library grlib; +use grlib.amba.all; use grlib.stdlib.all; library gaisler; use gaisler.ddrpkg.all; @@ -36,6 +37,7 @@ entity ahb2avl_async_be is generic ( avldbits : integer := 32; avlabits : integer := 20; + ahbbits : integer := ahbdw; burstlen : integer := 8; nosync : integer := 0 ); @@ -92,6 +94,7 @@ begin variable slvi: ddravl_slv_in_type; variable rddone: std_ulogic; variable inc_ramaddr: std_ulogic; + variable aendaddr: std_logic_vector(9 downto 0); begin v := r; @@ -104,8 +107,20 @@ begin slvi.write_req := r.wr; slvi.size := std_logic_vector(to_unsigned(avlbl, slvi.size'length)); + -- fix for accesses wider than 32-b word + aendaddr := request.endaddr; --(log2(4*burstlen)-1 downto 2); + if request.hsize(1 downto 0)="11" and request.hio='0' then + aendaddr(2):='1'; + end if; + if ahbbits > 64 and request.hsize(2)='1' then + aendaddr(3 downto 2) := "11"; + if ahbbits > 128 and request.hsize(0)='1' then + aendaddr(4) := '1'; + end if; + end if; v.req1 := request; + v.req1.endaddr := aendaddr; v.req2 := r.req1; v.start1 := start_tog; v.start2 := r.start1; diff --git a/lib/gaisler/ddr/ahb2mig_series7.vhd b/lib/gaisler/ddr/ahb2mig_series7.vhd index d401ba6a..468df104 100644 --- a/lib/gaisler/ddr/ahb2mig_series7.vhd +++ b/lib/gaisler/ddr/ahb2mig_series7.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ahb2mig_series7_pkg.vhd b/lib/gaisler/ddr/ahb2mig_series7_pkg.vhd index 4091443f..49ec109b 100644 --- a/lib/gaisler/ddr/ahb2mig_series7_pkg.vhd +++ b/lib/gaisler/ddr/ahb2mig_series7_pkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr1spax.vhd b/lib/gaisler/ddr/ddr1spax.vhd index 7c30aa71..b8fa4d06 100644 --- a/lib/gaisler/ddr/ddr1spax.vhd +++ b/lib/gaisler/ddr/ddr1spax.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr1spax_ddr.vhd b/lib/gaisler/ddr/ddr1spax_ddr.vhd index 0eca6f7f..26065bc8 100644 --- a/lib/gaisler/ddr/ddr1spax_ddr.vhd +++ b/lib/gaisler/ddr/ddr1spax_ddr.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr2buf.vhd b/lib/gaisler/ddr/ddr2buf.vhd index 47d5c595..be93a04b 100644 --- a/lib/gaisler/ddr/ddr2buf.vhd +++ b/lib/gaisler/ddr/ddr2buf.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr2spa.vhd b/lib/gaisler/ddr/ddr2spa.vhd index 58b6f22d..e932e109 100644 --- a/lib/gaisler/ddr/ddr2spa.vhd +++ b/lib/gaisler/ddr/ddr2spa.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr2spax.vhd b/lib/gaisler/ddr/ddr2spax.vhd index 9c085781..254a76e1 100644 --- a/lib/gaisler/ddr/ddr2spax.vhd +++ b/lib/gaisler/ddr/ddr2spax.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr2spax_ahb.vhd b/lib/gaisler/ddr/ddr2spax_ahb.vhd index eac4cfd4..4c255f71 100644 --- a/lib/gaisler/ddr/ddr2spax_ahb.vhd +++ b/lib/gaisler/ddr/ddr2spax_ahb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddr2spax_ddr.vhd b/lib/gaisler/ddr/ddr2spax_ddr.vhd index cb13de7f..ee4f2f31 100644 --- a/lib/gaisler/ddr/ddr2spax_ddr.vhd +++ b/lib/gaisler/ddr/ddr2spax_ddr.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddrintpkg.vhd b/lib/gaisler/ddr/ddrintpkg.vhd index 91c22ada..a83154da 100644 --- a/lib/gaisler/ddr/ddrintpkg.vhd +++ b/lib/gaisler/ddr/ddrintpkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -273,6 +273,7 @@ package ddrintpkg is generic ( avldbits : integer := 32; avlabits : integer := 20; + ahbbits : integer := ahbdw; burstlen : integer := 8; nosync : integer := 0 ); diff --git a/lib/gaisler/ddr/ddrphy_wrap.vhd b/lib/gaisler/ddr/ddrphy_wrap.vhd index 491e9593..f6e6be7b 100644 --- a/lib/gaisler/ddr/ddrphy_wrap.vhd +++ b/lib/gaisler/ddr/ddrphy_wrap.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -103,6 +103,7 @@ begin sdi.data(127 downto dbits*2) <= (others => '0'); end generate; sdi.cb <= (others => '0'); sdi.regrdata <= (others => '0'); + sdi.writereq <= '0'; end; @@ -311,7 +312,7 @@ begin testen,testrst,scanen,testoen); sdi.regrdata <= (others => '0'); - + sdi.writereq <= '0'; end; @@ -524,7 +525,7 @@ begin testen => testen, testrst => testrst, scanen => scanen, testoen => testoen ); sdi.regrdata <= (others => '0'); - + sdi.writereq <= '0'; end; @@ -930,6 +931,7 @@ begin testen, testrst, scanen, testoen ); + sdi.writereq <= '0'; end; library ieee; @@ -1170,6 +1172,7 @@ begin customclk => customclk, customdin => customdin, customdout => customdout, testen => testen, testrst => testrst, scanen => scanen, testoen => testoen ); + sdi.writereq <= '0'; end; diff --git a/lib/gaisler/ddr/ddrpkg.vhd b/lib/gaisler/ddr/ddrpkg.vhd index 4580b83e..6538fd3d 100644 --- a/lib/gaisler/ddr/ddrpkg.vhd +++ b/lib/gaisler/ddr/ddrpkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/ddr/ddrspa.vhd b/lib/gaisler/ddr/ddrspa.vhd index 697bc01e..48377736 100644 --- a/lib/gaisler/ddr/ddrspa.vhd +++ b/lib/gaisler/ddr/ddrspa.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/dirs.txt b/lib/gaisler/dirs.txt index 0d73b166..2df56391 100644 --- a/lib/gaisler/dirs.txt +++ b/lib/gaisler/dirs.txt @@ -7,7 +7,7 @@ srmmu leon3 leon3v3 leon4 leon4v0 irqmp -l2cache/v2 +l2cache/v2 l2cache/v2-pkg can hcan misc diff --git a/lib/gaisler/gr1553b/gr1553b_pads.vhd b/lib/gaisler/gr1553b/gr1553b_pads.vhd index bba6a76a..d3058481 100644 --- a/lib/gaisler/gr1553b/gr1553b_pads.vhd +++ b/lib/gaisler/gr1553b/gr1553b_pads.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/gr1553b/gr1553b_pkg.vhd b/lib/gaisler/gr1553b/gr1553b_pkg.vhd index ff69f0e9..24d6a967 100644 --- a/lib/gaisler/gr1553b/gr1553b_pkg.vhd +++ b/lib/gaisler/gr1553b/gr1553b_pkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd b/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd index 16ea8d12..a837d4f2 100644 --- a/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd +++ b/lib/gaisler/gr1553b/gr1553b_stdlogic.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/gr1553b/simtrans1553.vhd b/lib/gaisler/gr1553b/simtrans1553.vhd index 6e701362..475d47d0 100644 --- a/lib/gaisler/gr1553b/simtrans1553.vhd +++ b/lib/gaisler/gr1553b/simtrans1553.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/greth/ethernet_mac.vhd b/lib/gaisler/greth/ethernet_mac.vhd index a51228e5..a4366228 100644 --- a/lib/gaisler/greth/ethernet_mac.vhd +++ b/lib/gaisler/greth/ethernet_mac.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/greth/greth.vhd b/lib/gaisler/greth/greth.vhd index 933df86f..ee6cf083 100644 --- a/lib/gaisler/greth/greth.vhd +++ b/lib/gaisler/greth/greth.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -70,7 +70,9 @@ entity greth is multicast : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer := 1518); + maxsize : integer := 1518; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -175,7 +177,9 @@ begin edclsepahbg => 0, ramdebug => ramdebug, mdiohold => mdiohold, - maxsize => maxsize) + maxsize => maxsize, + gmiimode => gmiimode + ) port map( rst => rst, clk => clk, @@ -210,13 +214,13 @@ begin ehprot => open, ehwdata => open, --apb slv in - psel => apbi.psel(pindex), - penable => apbi.penable, - paddr => apbi.paddr, - pwrite => apbi.pwrite, - pwdata => apbi.pwdata, + psel => apbi.psel(pindex), + penable => apbi.penable, + paddr => apbi.paddr, + pwrite => apbi.pwrite, + pwdata => apbi.pwdata, --apb slv out - prdata => apbo.prdata, + prdata => apbo.prdata, --irq irq => irq, --rx ahb fifo @@ -245,12 +249,14 @@ begin --ethernet input signals rmii_clk => ethi.rmii_clk, tx_clk => ethi.tx_clk, + tx_dv => ethi.tx_dv, rx_clk => ethi.rx_clk, rxd => ethi.rxd(3 downto 0), rx_dv => ethi.rx_dv, rx_er => ethi.rx_er, rx_col => ethi.rx_col, rx_crs => ethi.rx_crs, + rx_en => ethi.rx_en, mdio_i => ethi.mdio_i, phyrstaddr => ethi.phyrstaddr, mdint => ethi.mdint, diff --git a/lib/gaisler/greth/greth_gbit.vhd b/lib/gaisler/greth/greth_gbit.vhd index f11d541c..299503be 100644 --- a/lib/gaisler/greth/greth_gbit.vhd +++ b/lib/gaisler/greth/greth_gbit.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -68,7 +68,9 @@ entity greth_gbit is enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - mdiohold : integer := 1); + mdiohold : integer := 1; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -165,7 +167,9 @@ begin multicast => multicast, edclsepahbg => 0, ramdebug => ramdebug, - mdiohold => mdiohold) + mdiohold => mdiohold, + gmiimode => gmiimode + ) port map( rst => rst, clk => clk, @@ -235,12 +239,14 @@ begin --ethernet input signals gtx_clk => ethi.gtx_clk, tx_clk => ethi.tx_clk, + tx_dv => ethi.tx_dv, rx_clk => ethi.rx_clk, rxd => ethi.rxd, rx_dv => ethi.rx_dv, rx_er => ethi.rx_er, rx_col => ethi.rx_col, rx_crs => ethi.rx_crs, + rx_en => ethi.rx_en, mdio_i => ethi.mdio_i, phyrstaddr => ethi.phyrstaddr, mdint => ethi.mdint, diff --git a/lib/gaisler/greth/greth_gbit_mb.vhd b/lib/gaisler/greth/greth_gbit_mb.vhd index 4b697863..4041ff5e 100644 --- a/lib/gaisler/greth/greth_gbit_mb.vhd +++ b/lib/gaisler/greth/greth_gbit_mb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -70,7 +70,9 @@ entity greth_gbit_mb is multicast : integer range 0 to 1 := 0; edclsepahb : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - mdiohold : integer := 1); + mdiohold : integer := 1; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -168,7 +170,9 @@ begin multicast => multicast, edclsepahbg => edclsepahb, ramdebug => ramdebug, - mdiohold => mdiohold) + mdiohold => mdiohold, + gmiimode => gmiimode + ) port map( rst => rst, clk => clk, @@ -238,12 +242,14 @@ begin --ethernet input signals gtx_clk => ethi.gtx_clk, tx_clk => ethi.tx_clk, + tx_dv => ethi.tx_dv, rx_clk => ethi.rx_clk, rxd => ethi.rxd, rx_dv => ethi.rx_dv, rx_er => ethi.rx_er, rx_col => ethi.rx_col, rx_crs => ethi.rx_crs, + rx_en => ethi.rx_en, mdio_i => ethi.mdio_i, phyrstaddr => ethi.phyrstaddr, mdint => ethi.mdint, diff --git a/lib/gaisler/greth/greth_mb.vhd b/lib/gaisler/greth/greth_mb.vhd index a2a7821f..196a984a 100644 --- a/lib/gaisler/greth/greth_mb.vhd +++ b/lib/gaisler/greth/greth_mb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -72,7 +72,9 @@ entity greth_mb is edclsepahb : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer); + maxsize : integer; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -171,15 +173,17 @@ begin ipaddrl => ipaddrl, phyrstadr => phyrstadr, rmii => rmii, - oepol => oepol, - scanen => scanen, + oepol => oepol, + scanen => scanen, mdint_pol => mdint_pol, enable_mdint => enable_mdint, multicast => multicast, edclsepahbg => edclsepahb, ramdebug => ramdebug, mdiohold => mdiohold, - maxsize => maxsize) + maxsize => maxsize, + gmiimode => gmiimode + ) port map( rst => rst, clk => clk, @@ -214,13 +218,13 @@ begin ehprot => ahbmo2.hprot, ehwdata => ehwdata, --apb slv in - psel => apbi.psel(pindex), - penable => apbi.penable, - paddr => apbi.paddr, - pwrite => apbi.pwrite, - pwdata => apbi.pwdata, + psel => apbi.psel(pindex), + penable => apbi.penable, + paddr => apbi.paddr, + pwrite => apbi.pwrite, + pwdata => apbi.pwdata, --apb slv out - prdata => apbo.prdata, + prdata => apbo.prdata, --irq irq => irq, --rx ahb fifo @@ -249,12 +253,14 @@ begin --ethernet input signals rmii_clk => ethi.rmii_clk, tx_clk => ethi.tx_clk, + tx_dv => ethi.tx_dv, rx_clk => ethi.rx_clk, rxd => ethi.rxd(3 downto 0), rx_dv => ethi.rx_dv, rx_er => ethi.rx_er, rx_col => ethi.rx_col, rx_crs => ethi.rx_crs, + rx_en => ethi.rx_en, mdio_i => ethi.mdio_i, phyrstaddr => ethi.phyrstaddr, mdint => ethi.mdint, diff --git a/lib/gaisler/greth/grethm.vhd b/lib/gaisler/greth/grethm.vhd index 6551bb29..ad0121e8 100644 --- a/lib/gaisler/greth/grethm.vhd +++ b/lib/gaisler/greth/grethm.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -68,7 +68,8 @@ entity grethm is multicast : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer := 1500 + maxsize : integer := 1500; + gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -119,7 +120,8 @@ begin multicast => multicast, ramdebug => ramdebug, mdiohold => mdiohold, - maxsize => maxsize + maxsize => maxsize, + gmiimode => gmiimode ) port map ( rst => rst, @@ -164,7 +166,9 @@ begin enable_mdint => enable_mdint, multicast => multicast, ramdebug => ramdebug, - mdiohold => mdiohold) + mdiohold => mdiohold, + gmiimode => gmiimode + ) port map ( rst => rst, clk => clk, diff --git a/lib/gaisler/greth/rgmii.vhd b/lib/gaisler/greth/rgmii.vhd index 1ff7f947..acb5c1f4 100644 --- a/lib/gaisler/greth/rgmii.vhd +++ b/lib/gaisler/greth/rgmii.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -20,7 +20,7 @@ -- Entity: rgmii -- File: rgmii.vhd -- Author: Fredrik Ringhage - Aeroflex Gaisler --- Description: GMII to RGMII interface +-- Description: GMII to RGMII interface ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; @@ -28,8 +28,11 @@ use ieee.numeric_std.all; library gaisler; use gaisler.net.all; +use gaisler.misc.all; library grlib; +use grlib.config_types.all; +use grlib.config.all; use grlib.amba.all; use grlib.stdlib.all; use grlib.devices.all; @@ -38,23 +41,28 @@ library techmap; use techmap.gencomp.all; use techmap.allclkgen.all; +library techmap; +use techmap.gencomp.all; +use techmap.allclkgen.all; + library eth; use eth.grethpkg.all; entity rgmii is generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - tech : integer := 0; - gmii : integer := 0; - extclk : integer := 0; - clkdiv2 : integer := 0; - debugmem : integer := 0 + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + tech : integer := 0; + gmii : integer := 0; + debugmem : integer := 0; + abits : integer := 8; + no_clk_mux : integer := 0; + pirq : integer := 0; + use90degtxclk : integer := 0 ); port ( rstn : in std_ulogic; - clk_tx_g : in std_ulogic; gmiii : out eth_in_type; gmiio : in eth_out_type; rgmiii : in eth_in_type; @@ -64,30 +72,45 @@ entity rgmii is apb_rstn : in std_logic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type - ); end ; architecture rtl of rgmii is -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_RGMII, 0, 0, 0), - 1 => apb_iobar(paddr, pmask)); - - attribute keep : boolean; - attribute syn_keep : boolean; - attribute syn_preserve : boolean; - + constant REVISION : integer := 1; + + constant pconfig : apb_config_type := ( + 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_RGMII, 0, REVISION, pirq), + 1 => apb_iobar(paddr, pmask)); + + type rgmiiregs is record + clk25_wrap : unsigned(5 downto 0); + clk25_first_edge : unsigned(5 downto 0); + clk25_second_edge : unsigned(5 downto 0); + clk2_5_wrap : unsigned(5 downto 0); + clk2_5_first_edge : unsigned(5 downto 0); + clk2_5_second_edge : unsigned(5 downto 0); + irq : std_logic_vector(15 downto 0); -- interrupt + mask : std_logic_vector(15 downto 0); -- interrupt enable + clkedge : std_logic_vector(23 downto 0); + rxctrl_q1_delay : std_logic_vector(1 downto 0); + rxctrl_q2_delay : std_logic_vector(1 downto 0); + rxctrl_q1_sel : std_logic; + end record; + + -- Global signal signal vcc, gnd : std_ulogic; - signal tx_en, tx_ctlp, tx_ctl : std_ulogic; + signal tx_en, tx_ctl : std_ulogic; signal txd : std_logic_vector(7 downto 0); - signal rxd, rxd_int : std_logic_vector(7 downto 0); + signal rxd, rxd_pre, rxd_int, rxd_int0, rxd_int1, rxd_int2,rxd_q1,rxd_q2 : std_logic_vector(7 downto 0); signal rx_clk, nrx_clk : std_ulogic; - signal rx_dv, rx_dv_int, rx_ctl, rx_ctl_int, rx_error : std_logic; - signal clk50i,clk50ni, clk25i, clk25ni, clk125i, clk2_5i, clk2_5ni : std_ulogic; + signal rx_dv, rx_dv_pre, rx_dv_int, rx_dv0 , rx_ctl, rx_ctl_pre, rx_ctl_int, rx_ctl0, rx_error : std_logic; + signal rx_dv_int0, rx_dv_int1, rx_dv_int2 : std_logic; + signal rx_ctl_int0, rx_ctl_int1, rx_ctl_int2 : std_logic; + signal clk25i, clk25ni, clk2_5i, clk2_5ni : std_ulogic; signal txp, txn, tx_clk_ddr, tx_clk, tx_clki, ntx_clk : std_ulogic; signal cnt2_5, cnt25 : unsigned(5 downto 0); - signal rst50n,rsttxclkn,rsttxclk,rsttxclk90n,rsttxclk90 : std_logic; + signal rsttxclkn,rsttxclk : std_logic; -- RGMII Inband status signals signal inbandopt,inbandreq : std_logic; @@ -98,9 +121,48 @@ constant pconfig : apb_config_type := ( signal carrier_ext : std_logic; signal carrier_ext_error : std_logic; signal carrier_sense : std_logic; - + -- Extra registers to ease IOB placement - signal status_vector_apb : std_logic_vector(15 downto 0); + signal status_vector_apb : std_logic_vector(15 downto 0); + signal status_vector_apb1 : std_logic_vector(15 downto 0); + signal status_vector_apb2 : std_logic_vector(15 downto 0); + + -- APB and RGMII control register + constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; + + -- notech default settings + constant RES : rgmiiregs := + ( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6), + clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6), + irq => (others => '0'), mask => (others => '0'), clkedge => "000000100000101100000111", + rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '0'); + + -- Kintex7 settings for KC705 Dev Board + constant RES_kintex7 : rgmiiregs := + ( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6), + clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6), + irq => (others => '0'), mask => (others => '0'), clkedge => "000000100000101100000111", + rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => (others => '0'), rxctrl_q1_sel => '1'); + + -- Spartan6 settings for GR-XC6 Dev Board + constant RES_spartan6 : rgmiiregs := + ( clk25_wrap => to_unsigned(4,6), clk25_first_edge => to_unsigned(1,6), clk25_second_edge => to_unsigned(2,6), + clk2_5_wrap => to_unsigned(49,6), clk2_5_first_edge => to_unsigned(23,6), clk2_5_second_edge => to_unsigned(24,6), + irq => (others => '0'), mask => (others => '0'), clkedge => "000000100011100000111000", + rxctrl_q1_delay => (others => '0'), rxctrl_q2_delay => "01", rxctrl_q1_sel => '1'); + + signal r, rin : rgmiiregs; + + signal clk_tx_90_n : std_logic; + signal sync_gbit : std_logic; + signal sync_speed : std_logic; + signal cnt2_5_en, cnt25_en : std_logic; + signal clkedge_sync : std_logic_vector(23 downto 0); + signal sync_rxctrl_q1_delay : std_logic_vector(1 downto 0); + signal sync_rxctrl_q2_delay : std_logic_vector(1 downto 0); + signal sync_rxctrl_q1_sel : std_logic; + signal cnt_en : std_logic; + signal clk10_100 : std_logic; -- debug signal signal WMemRgmiioData : std_logic_vector(15 downto 0); @@ -116,8 +178,6 @@ constant pconfig : apb_config_type := ( signal RMemRgmiiiRead : std_logic; signal RMemRgmiioRead : std_logic; - signal clk_tx_g_n : std_logic; - begin -- rtl vcc <= '1'; gnd <= '0'; @@ -136,103 +196,172 @@ begin -- rtl -- TX path --------------------------------------------------------------------------------------- - - -- Generate transmit clocks. - tx_clk <= rgmiii.gtx_clk; + useclkmux0 : if no_clk_mux = 0 generate + process (apb_clk) + begin -- process + if rising_edge(apb_clk) then + clk25i <= not clk25i; + if cnt2_5 = "001001" then cnt2_5 <= "000000"; clk2_5i <= not clk2_5i; + else cnt2_5 <= cnt2_5 + 1; end if; + if apb_rstn = '0' then clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= "000000"; end if; + end if; + end process; + + notecclkmux : if (has_clkmux(tech) = 0) generate + tx_clki <= rgmiii.gtx_clk when ((gmii = 1) and (gmiio.gbit = '1')) else + clk25i when gmiio.speed = '1' else clk2_5i; + end generate; + + tecclkmux : if (has_clkmux(tech) = 1) generate + -- Select 2.5 or 25 Mhz clockL + clkmux10_100 : clkmux generic map (tech => tech) port map (clk2_5i,clk25i,gmiio.speed,clk10_100); + clkmux1000 : clkmux generic map (tech => tech) port map (clk10_100,rgmiii.gtx_clk,gmiio.gbit,tx_clki); + end generate; + + clkbuf0: techbuf generic map (buftype => 2, tech => tech) + port map (i => tx_clki, o => tx_clk); + end generate; + + noclkmux0 : if no_clk_mux = 1 generate + -- Generate transmit clocks. + tx_clk <= rgmiii.gtx_clk; + + process (tx_clk) + begin -- process + if rising_edge(tx_clk) then + + if cnt25 >= r.clk25_wrap then + cnt25 <= to_unsigned(0,cnt25'length); + cnt25_en <= '1'; + else + cnt25_en <= '0'; + cnt25 <= cnt25 + 1; + end if; + if (cnt25 >= r.clk25_wrap) then + clk25ni <= clkedge_sync(0); + clk25i <= clkedge_sync(1); + elsif (cnt25 = r.clk25_first_edge) then + clk25ni <= clkedge_sync(2); + clk25i <= clkedge_sync(3); + elsif (cnt25 = r.clk25_second_edge) then + clk25ni <= clkedge_sync(4); + clk25i <= clkedge_sync(5); + end if; + + if cnt2_5 >= r.clk2_5_wrap then + cnt2_5 <= to_unsigned(0,cnt2_5'length); + cnt2_5_en <= '1'; + else + cnt2_5 <= cnt2_5 + 1; + cnt2_5_en <= '0'; + end if; + + if (cnt2_5 >= r.clk2_5_wrap) then + clk2_5ni <= clkedge_sync(8); + clk2_5i <= clkedge_sync(9); + elsif (cnt25 = r.clk2_5_first_edge) then + clk2_5ni <= clkedge_sync(10); + clk2_5i <= clkedge_sync(11); + elsif (cnt2_5 = r.clk2_5_second_edge) then + clk2_5ni <= clkedge_sync(12); + clk2_5i <= clkedge_sync(13); + end if; + + if rsttxclkn = '0' then + cnt2_5_en <= '0'; cnt25_en <= '0'; clk25i <= '0'; clk25ni <= '0'; + clk2_5i <= '0'; clk2_5ni <= '0'; cnt2_5 <= to_unsigned(0,cnt2_5'length); + cnt25 <= to_unsigned(0,cnt25'length); + end if; + + end if; + end process; + end generate; + ntx_clk <= not tx_clk; - - gmiii.gtx_clk <= tx_clk; + gmiii.gtx_clk <= tx_clk; gmiii.tx_clk <= tx_clk; - process (tx_clk) - begin -- process - if rising_edge(tx_clk) then + noclkmux1 : if no_clk_mux = 1 generate + cnt_en <= '1' when ((gmii = 1) and (gmiio.gbit = '1')) else + cnt25_en when gmiio.speed = '1' else cnt2_5_en; + end generate; - if cnt25 = to_unsigned(4,cnt25'length) then - cnt25 <= to_unsigned(0,cnt25'length); - else - cnt25 <= cnt25 + 1; - end if; - if cnt25 = to_unsigned(0,cnt25'length) then - clk25i <= '1'; - elsif cnt25 = to_unsigned(3,cnt25'length) then - clk25i <= '0'; - else - clk25i <= clk25i; - end if; - clk25ni <= not clk25i; - - if cnt2_5 = to_unsigned(49,cnt2_5'length) then - cnt2_5 <= to_unsigned(0,cnt2_5'length); - else - cnt2_5 <= cnt2_5 + 1; - end if; - if cnt2_5 = to_unsigned(0,cnt2_5'length) then - clk2_5i <= '1'; - elsif cnt2_5 = to_unsigned(49,cnt2_5'length) then - clk2_5i <= '0'; - else - clk2_5i <= clk2_5i; - end if; - clk2_5ni <= not clk2_5i; - - if rsttxclkn = '0' then clk25i <= '0'; clk2_5i <= '0'; cnt2_5 <= to_unsigned(0,cnt2_5'length); cnt25 <= to_unsigned(0,cnt25'length); end if; + useclkmux1 : if no_clk_mux = 0 generate + cnt_en <= '1'; + end generate; - end if; - end process; + gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1'; -- Generate RGMII control signal and check data rate process (tx_clk) begin -- process + -- CDC (Only 1 CDC register is used since the signals are semi-static) + sync_gbit <= gmiio.gbit; + sync_speed <= gmiio.speed; + clkedge_sync <= r.clkedge; + if rising_edge(tx_clk) then - if (gmiio.gbit = '1') then + if (gmii = 1) and (sync_gbit = '1') then txd(7 downto 0) <= gmiio.txd(7 downto 0); else - txd(7 downto 4) <= gmiio.txd(3 downto 0); txd(3 downto 0) <= gmiio.txd(3 downto 0); + txd(7 downto 4) <= gmiio.txd(3 downto 0); end if; tx_en <= gmiio.tx_en; tx_ctl <= gmiio.tx_en xor gmiio.tx_er; end if; - - if (gmii = 1) and (gmiio.gbit = '1') then - txp <= '1'; - txn <= '0'; + + if (gmii = 1) and (sync_gbit = '1') then + txp <= clkedge_sync(17); + txn <= clkedge_sync(16); else - if gmiio.speed = '1' then - txp <= clk25i; - txn <= clk25ni; + if sync_speed = '1' then + txp <= clk25ni; + txn <= clk25i; else - txp <= clk2_5i; - txn <= clk2_5ni; + txp <= clk2_5ni; + txn <= clk2_5i; end if; end if; - end process; - clk_tx_rst : eth_rstgen + clk_tx_rst : rstgen + generic map(syncin => 1, syncrst => 1) port map(rstn, tx_clk, vcc, rsttxclkn, open); rsttxclk <= not rsttxclkn; - clk_tx90_rst : eth_rstgen - port map(rstn, clk_tx_g, vcc, rsttxclk90n, open); - rsttxclk90 <= not rsttxclk90n; + -- DDR outputs + rgmii_txd : for i in 0 to 3 generate + ddr_oreg0 : ddr_oreg generic map (tech, arch => 1) + port map (q => rgmiio.txd(i), c1 => tx_clk, c2 => ntx_clk, ce => vcc, + d1 => txd(i), d2 => txd(i+4), r => gnd, s => gnd); + end generate; + rgmii_tx_ctl : ddr_oreg generic map (tech, arch => 1) + port map (q => rgmiio.tx_en, c1 => tx_clk, c2 => ntx_clk, ce => vcc, + d1 => tx_en, d2 => tx_ctl, r => gnd, s => gnd); + + no_clk_mux1 : if no_clk_mux = 1 generate + use90degtxclk1 : if use90degtxclk = 1 generate + clk_tx_90_n <= not rgmiii.tx_clk_90; + rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1) + port map (q => tx_clk_ddr, c1 => rgmiii.tx_clk_90, c2 => clk_tx_90_n, ce => vcc, + d1 => txp, d2 => txn, r => gnd, s => gnd); + end generate; + + use90degtxclk0 : if use90degtxclk = 0 generate + rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1) + port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc, + d1 => txp, d2 => txn, r => gnd, s => gnd); + end generate; + end generate; + + no_clk_mux0 : if no_clk_mux = 0 generate + rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1) + port map (q => tx_clk_ddr, c1 => tx_clk, c2 => ntx_clk, ce => vcc, + d1 => '1', d2 => '0', r => gnd, s => gnd); + end generate; - clk_tx_g_n <= not clk_tx_g; - -- DDR outputs - rgmii_txd : for i in 0 to 3 generate - ddr_oreg0 : ddr_oreg generic map (tech, arch => 1) - port map (q => rgmiio.txd(i), c1 => tx_clk, c2 => ntx_clk, ce => vcc, - d1 => txd(i), d2 => txd(i+4), r => rsttxclk, s => gnd); - end generate; - rgmii_tx_ctl : ddr_oreg generic map (tech, arch => 1) - port map (q => rgmiio.tx_en, c1 => tx_clk, c2 => ntx_clk, ce => vcc, - d1 => tx_en, d2 => tx_ctl, r => rsttxclk, s => gnd); - rgmii_tx_clk : ddr_oreg generic map (tech, arch => 1) - port map (q =>tx_clk_ddr, c1 => clk_tx_g, c2 => clk_tx_g_n, ce => vcc, - d1 => txp, d2 => txn, r => rsttxclk90, s => gnd); - rgmiio.tx_er <= '0'; rgmiio.tx_clk <= tx_clk_ddr; rgmiio.reset <= rstn; @@ -246,6 +375,16 @@ begin -- rtl -- RX path --------------------------------------------------------------------------------------- + -- CDC (RX Control signal) + process (rx_clk) + begin + if rising_edge(rx_clk) then + sync_rxctrl_q1_delay <= r.rxctrl_q1_delay; + sync_rxctrl_q2_delay <= r.rxctrl_q2_delay; + sync_rxctrl_q1_sel <= r.rxctrl_q1_sel; + end if; + end process; + -- Rx Clocks rx_clk <= rgmiii.rx_clk; nrx_clk <= not rgmiii.rx_clk; @@ -253,44 +392,103 @@ begin -- rtl -- DDR inputs rgmii_rxd : for i in 0 to 3 generate ddr_ireg0 : ddr_ireg generic map (tech, arch => 1) - port map (q1 => rxd_int(i), q2 => rxd_int(i+4), c1 => rx_clk, c2 => nrx_clk, + port map (q1 => rxd_pre(i), q2 => rxd_pre(i+4), c1 => rx_clk, c2 => nrx_clk, ce => vcc, d => rgmiii.rxd(i), r => gnd, s => gnd); - V7D : if (tech = virtex7) or (tech = kintex7) generate process (rx_clk) begin if rising_edge(rx_clk) then - rxd(i) <= rxd_int(i+4); + + rxd_int <= rxd_pre; + + rxd_int0(i) <= rxd_int(i); + rxd_int0(i+4) <= rxd_int(i+4); + rxd_int1(i) <= rxd_int0(i); + rxd_int1(i+4) <= rxd_int0(i+4); + rxd_int2(i) <= rxd_int1(i); + rxd_int2(i+4) <= rxd_int1(i+4); end if; end process; - rxd(i+4) <= rxd_int(i); - end generate; - S6D : if (tech = spartan6) generate - rxd(i) <= rxd_int(i); - rxd(i+4) <= rxd_int(i+4); - end generate; + end generate; + rgmii_rxd0 : for i in 0 to 3 generate + process (rx_clk) + begin + if (sync_rxctrl_q1_delay = "00") then + rxd_q1(i) <= rxd_int(i); + elsif (sync_rxctrl_q1_delay = "01") then + rxd_q1(i) <= rxd_int0(i); + elsif (sync_rxctrl_q1_delay = "10") then + rxd_q1(i) <= rxd_int1(i); + else + rxd_q1(i) <= rxd_int2(i); + end if; + end process; end generate; + + rgmii_rxd1 : for i in 4 to 7 generate + process (rx_clk) + begin + if (sync_rxctrl_q2_delay = "00") then + rxd_q2(i) <= rxd_int(i); + elsif (sync_rxctrl_q2_delay = "01") then + rxd_q2(i) <= rxd_int0(i); + elsif (sync_rxctrl_q2_delay = "10") then + rxd_q2(i) <= rxd_int1(i); + else + rxd_q2(i) <= rxd_int2(i); + end if; + end process; + end generate; + + rxd(3 downto 0) <= rxd_q1(3 downto 0) when (sync_rxctrl_q1_sel = '0') else rxd_q2(7 downto 4); + rxd(7 downto 4) <= rxd_q2(7 downto 4) when (sync_rxctrl_q1_sel = '0') else rxd_q1(3 downto 0); + ddr_dv0 : ddr_ireg generic map (tech, arch => 1) - port map (q1 => rx_dv_int, q2 => rx_ctl_int, c1 => rx_clk, c2 => nrx_clk, + port map (q1 => rx_dv_pre, q2 => rx_ctl_pre, c1 => rx_clk, c2 => nrx_clk, ce => vcc, d => rgmiii.rx_dv, r => gnd, s => gnd); - - V7DV : if (tech = virtex7) or (tech = kintex7) generate - process (rx_clk) - begin - if rising_edge(rx_clk) then - rx_dv <= rx_ctl_int; - end if; - end process; - rx_ctl <= rx_dv_int; - end generate; - S6DV : if (tech = spartan6) generate - rx_dv <= rx_dv_int; - rx_ctl <= rx_ctl_int; - end generate; + process (rx_clk) + begin + if rising_edge(rx_clk) then + rx_ctl_int <= rx_ctl_pre; + rx_dv_int <= rx_dv_pre; + + rx_ctl_int0 <= rx_ctl_int; + rx_ctl_int1 <= rx_ctl_int0; + rx_ctl_int2 <= rx_ctl_int1; + rx_dv_int0 <= rx_dv_int; + rx_dv_int1 <= rx_dv_int1; + rx_dv_int2 <= rx_dv_int2; + end if; + end process; + process (rx_clk) + begin + if (sync_rxctrl_q1_delay = "00") then + rx_dv0 <= rx_dv_int; + elsif (sync_rxctrl_q1_delay = "01") then + rx_dv0 <= rx_dv_int0; + elsif (sync_rxctrl_q1_delay = "10") then + rx_dv0 <= rx_dv_int1; + else + rx_dv0 <= rx_dv_int2; + end if; + + if (sync_rxctrl_q2_delay = "00") then + rx_ctl0 <= rx_ctl_int; + elsif (sync_rxctrl_q2_delay = "01") then + rx_ctl0 <= rx_ctl_int0; + elsif (sync_rxctrl_q2_delay = "10") then + rx_ctl0 <= rx_ctl_int1; + else + rx_ctl0 <= rx_ctl_int2; + end if; + end process; + + rx_dv <= rx_dv0 when (sync_rxctrl_q1_sel = '0') else rx_ctl0; + rx_ctl <= rx_ctl0 when (sync_rxctrl_q1_sel = '0') else rx_dv0; -- Decode GMII error signal rx_error <= rx_dv xor rx_ctl; @@ -325,6 +523,7 @@ begin -- rtl gmiii.rx_col <= '0'; gmiii.rx_crs <= rx_dv; gmiii.rmii_clk <= '0'; + gmiii.rx_en <= '1'; -- GMII output controlled via generics gmiii.edclsepahb <= '0'; @@ -335,25 +534,20 @@ begin -- rtl --------------------------------------------------------------------------------------- -- APB Section --------------------------------------------------------------------------------------- - + apbo.pindex <= pindex; apbo.pconfig <= pconfig; - apbo.pirq <= (others => '0'); - apbo.prdata(31 downto 16) <= (others => '0'); - apbo.prdata(15 downto 0) <= (others => '0') when apbi.psel(pindex) = '0' else - RMemRgmiiiData when RMemRgmiiiRead = '1' else - RMemRgmiioData when RMemRgmiioRead = '1' else - status_vector_apb; - - -- Extra registers to ease CDC placement + + -- Extra registers to ease CDC placement process (apb_clk) begin if apb_clk'event and apb_clk = '1' then - status_vector_apb(15 downto 12) <= (others => '0'); - status_vector_apb(11) <= '0'; - status_vector_apb(10) <= '0'; - status_vector_apb(9) <= gmiio.speed; - status_vector_apb(8) <= gmiio.gbit; + if no_clk_mux = 1 then status_vector_apb(15) <= '1'; else status_vector_apb(15) <= '0'; end if; + if debugmem = 1 then status_vector_apb(14) <= '1'; else status_vector_apb(14) <= '0'; end if; + if gmii = 1 then status_vector_apb(13) <= '1'; else status_vector_apb(13) <= '0'; end if; + status_vector_apb(12 downto 10) <= (others => '0'); + status_vector_apb(9) <= gmiio.gbit; + status_vector_apb(8) <= gmiio.speed; status_vector_apb(7) <= carrier_sense; status_vector_apb(6) <= carrier_ext_error; status_vector_apb(5) <= carrier_ext; @@ -362,12 +556,155 @@ begin -- rtl status_vector_apb(2) <= clock_speed(1); status_vector_apb(1) <= clock_speed(0); status_vector_apb(0) <= link_status; + + -- Register to detect a speed change + status_vector_apb1 <= status_vector_apb; + status_vector_apb2 <= status_vector_apb1; end if; - end process; + end process; - debugmem0 : if (debugmem /= 0) generate + rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead ) + variable rdata : std_logic_vector(31 downto 0); + variable paddress : std_logic_vector(7 downto 2); + variable v : rgmiiregs; + begin + + v := r; + paddress := (others => '0'); + paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2); + rdata := (others => '0'); + + -- read/write registers + + if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then + case paddress(7 downto 2) is + when "000000" => + rdata(15 downto 0) := status_vector_apb1; + when "000001" => + rdata(15 downto 0) := r.irq; + v.irq := (others => '0'); -- Interrupt is clear on read + when "000010" => + rdata(15 downto 0) := r.mask; + when "000011" => + rdata(5 downto 0) := std_logic_vector(r.clk25_wrap); + when "000100" => + rdata(5 downto 0) := std_logic_vector(r.clk25_first_edge); + when "000101" => + rdata(5 downto 0) := std_logic_vector(r.clk25_second_edge); + when "000110" => + rdata(5 downto 0) := std_logic_vector(r.clk2_5_wrap); + when "000111" => + rdata(5 downto 0) := std_logic_vector(r.clk2_5_first_edge); + when "001000" => + rdata(5 downto 0) := std_logic_vector(r.clk2_5_second_edge); + when "001001" => + rdata(23 downto 0) := r.clkedge; + when "001010" => + rdata(1 downto 0) := v.rxctrl_q2_delay; + when "001011" => + rdata(1 downto 0) := v.rxctrl_q1_delay; + when "001100" => + rdata(0) := v.rxctrl_q1_sel; + when others => + null; + end case; + end if; - -- Write GMII IN data + if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then + case paddress(7 downto 2) is + when "000000" => + null; + when "000001" => + null; + when "000010" => + v.mask := apbi.pwdata(15 downto 0); + when "000011" => + v.clk25_wrap := unsigned(apbi.pwdata(5 downto 0)); + when "000100" => + v.clk25_first_edge := unsigned(apbi.pwdata(5 downto 0)); + when "000101" => + v.clk25_second_edge := unsigned(apbi.pwdata(5 downto 0)); + when "000110" => + v.clk2_5_wrap := unsigned(apbi.pwdata(5 downto 0)); + when "000111" => + v.clk2_5_first_edge := unsigned(apbi.pwdata(5 downto 0)); + when "001000" => + v.clk2_5_second_edge := unsigned(apbi.pwdata(5 downto 0)); + when "001001" => + v.clkedge := apbi.pwdata(23 downto 0); + when "001010" => + v.rxctrl_q2_delay := apbi.pwdata(1 downto 0); + when "001011" => + v.rxctrl_q1_delay := apbi.pwdata(1 downto 0); + when "001100" => + v.rxctrl_q1_sel := apbi.pwdata(0); + when others => + null; + end case; + end if; + + -- Check interrupts + for i in 0 to status_vector_apb'length-1 loop + if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then + v.irq(i) := '1'; + end if; + end loop; + + -- reset operation + if (not RESET_ALL) and (apb_rstn = '0') then + if (tech = kintex7) then + v := RES_kintex7; + elsif (tech = spartan6) then + v := RES_spartan6; + else + v := RES; + end if; + end if; + + -- update registers + rin <= v; + + -- drive outputs + if apbi.psel(pindex) = '0' then + apbo.prdata <= (others => '0'); + elsif RMemRgmiiiRead = '1' then + apbo.prdata(31 downto 16) <= (others => '0'); + apbo.prdata(15 downto 0) <= RMemRgmiiiData; + elsif RMemRgmiioRead = '1' then + apbo.prdata(31 downto 16) <= (others => '0'); + apbo.prdata(15 downto 0) <= RMemRgmiioData; + else + apbo.prdata <= rdata; + end if; + + apbo.pirq <= (others => '0'); + apbo.pirq(pirq) <= orv(v.irq); + + end process; + + regs : process(apb_clk) + begin + if rising_edge(apb_clk) then + r <= rin; + if RESET_ALL and apb_rstn = '0' then + if (tech = kintex7) then + r <= RES_kintex7; + elsif (tech = spartan6) then + r <= RES_spartan6; + else + r <= RES; + end if; + end if; + end if; + end process; + + --------------------------------------------------------------------------------------- + -- Debug Mem + --------------------------------------------------------------------------------------- + + debugmem1 : if (debugmem /= 0) generate + + -- Write GMII IN data process (tx_clk) begin -- process if rising_edge(tx_clk) then @@ -376,7 +713,7 @@ begin -- rtl WMemRgmiioAddr <= WMemRgmiioAddr + 1; WMemRgmiioWrEn <= '1'; else - if (rx_dv = '0') then + if (tx_en = '0') then WMemRgmiioAddr <= (others => '1'); else WMemRgmiioAddr <= WMemRgmiioAddr; @@ -392,11 +729,7 @@ begin -- rtl gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map( apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData, - tx_clk, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData); - - end generate; - - debugmem1 : if (debugmem /= 0) generate + tx_clk, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData); -- Write GMII IN data process (rx_clk) @@ -406,7 +739,7 @@ begin -- rtl if ((rx_dv = '1') or (rx_ctl = '1')) and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then WMemRgmiiiAddr <= WMemRgmiiiAddr + 1; WMemRgmiiiWrEn <= '1'; - else + else if (rx_dv = '0') then WMemRgmiiiAddr <= (others => '1'); else @@ -423,9 +756,14 @@ begin -- rtl rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map( apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData, - tx_clk, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData); + rx_clk, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData); end generate; +-- pragma translate_off + bootmsg : report_version + generic map ("rgmii" & tost(pindex) & + ": RGMII rev " & tost(REVISION) & ", irq " & tost(pirq)); +-- pragma translate_on end rtl; diff --git a/lib/gaisler/greth/vhdlsyn.txt b/lib/gaisler/greth/vhdlsyn.txt index 14c81cc4..8869b63a 100644 --- a/lib/gaisler/greth/vhdlsyn.txt +++ b/lib/gaisler/greth/vhdlsyn.txt @@ -1 +1 @@ -ethernet_mac.vhd greth.vhd greth_mb.vhd greth_gbit.vhd greth_gbit_mb.vhd grethm.vhd rgmii.vhd +ethernet_mac.vhd greth.vhd greth_mb.vhd greth_gbit.vhd greth_gbit_mb.vhd grethm.vhd rgmii.vhd comma_detect.vhd sgmii.vhd elastic_buffer.vhd diff --git a/lib/gaisler/i2c/i2c.vhd b/lib/gaisler/i2c/i2c.vhd index 696deb6f..074fe3b7 100644 --- a/lib/gaisler/i2c/i2c.vhd +++ b/lib/gaisler/i2c/i2c.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2c2ahb.vhd b/lib/gaisler/i2c/i2c2ahb.vhd index 450c32d6..1a1af5c8 100644 --- a/lib/gaisler/i2c/i2c2ahb.vhd +++ b/lib/gaisler/i2c/i2c2ahb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2c2ahb_apb.vhd b/lib/gaisler/i2c/i2c2ahb_apb.vhd index f6f6eff3..3206d893 100644 --- a/lib/gaisler/i2c/i2c2ahb_apb.vhd +++ b/lib/gaisler/i2c/i2c2ahb_apb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd b/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd index 4b8ca93d..7824b25a 100644 --- a/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd +++ b/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2c2ahb_gen.vhd b/lib/gaisler/i2c/i2c2ahb_gen.vhd index 74a6fe8e..df7d2f6c 100644 --- a/lib/gaisler/i2c/i2c2ahb_gen.vhd +++ b/lib/gaisler/i2c/i2c2ahb_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2c2ahbx.vhd b/lib/gaisler/i2c/i2c2ahbx.vhd index e2c0ecb9..0ddfeb6f 100644 --- a/lib/gaisler/i2c/i2c2ahbx.vhd +++ b/lib/gaisler/i2c/i2c2ahbx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2cmst.vhd b/lib/gaisler/i2c/i2cmst.vhd index 425d2471..ad41bb90 100644 --- a/lib/gaisler/i2c/i2cmst.vhd +++ b/lib/gaisler/i2c/i2cmst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2cmst_gen.vhd b/lib/gaisler/i2c/i2cmst_gen.vhd index 05633c87..fff217de 100644 --- a/lib/gaisler/i2c/i2cmst_gen.vhd +++ b/lib/gaisler/i2c/i2cmst_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/i2c/i2cslv.vhd b/lib/gaisler/i2c/i2cslv.vhd index 8c128b43..a6b1aa5e 100644 --- a/lib/gaisler/i2c/i2cslv.vhd +++ b/lib/gaisler/i2c/i2cslv.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/irqmp/irqmp.vhd b/lib/gaisler/irqmp/irqmp.vhd index 7d3dc01b..a3038f54 100644 --- a/lib/gaisler/irqmp/irqmp.vhd +++ b/lib/gaisler/irqmp/irqmp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/ahbjtag.vhd b/lib/gaisler/jtag/ahbjtag.vhd index ad38e983..6f5d32d8 100644 --- a/lib/gaisler/jtag/ahbjtag.vhd +++ b/lib/gaisler/jtag/ahbjtag.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/ahbjtag_bsd.vhd b/lib/gaisler/jtag/ahbjtag_bsd.vhd index 80963365..1c2d67f5 100644 --- a/lib/gaisler/jtag/ahbjtag_bsd.vhd +++ b/lib/gaisler/jtag/ahbjtag_bsd.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/bscanregs.vhd b/lib/gaisler/jtag/bscanregs.vhd index cd312e53..7fb5ebac 100644 --- a/lib/gaisler/jtag/bscanregs.vhd +++ b/lib/gaisler/jtag/bscanregs.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/bscanregsbd.vhd b/lib/gaisler/jtag/bscanregsbd.vhd index 372846ab..4d1ad18c 100644 --- a/lib/gaisler/jtag/bscanregsbd.vhd +++ b/lib/gaisler/jtag/bscanregsbd.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/jtag.vhd b/lib/gaisler/jtag/jtag.vhd index fafa773e..5faf9518 100644 --- a/lib/gaisler/jtag/jtag.vhd +++ b/lib/gaisler/jtag/jtag.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/jtagcom.vhd b/lib/gaisler/jtag/jtagcom.vhd index dcf2f322..4ac98adf 100644 --- a/lib/gaisler/jtag/jtagcom.vhd +++ b/lib/gaisler/jtag/jtagcom.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -204,6 +204,8 @@ begin else if r.upd2 = '0' then v.state := shft; end if; end if; + when others => + v.state := shft; v.addr := (others => '0'); v.seq := '0'; end case; if (rst = '0') or (r.trst(0) = '1') then diff --git a/lib/gaisler/jtag/jtagcom2.vhd b/lib/gaisler/jtag/jtagcom2.vhd index ffec06a0..81ad1b74 100644 --- a/lib/gaisler/jtag/jtagcom2.vhd +++ b/lib/gaisler/jtag/jtagcom2.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/jtag/jtagtst.vhd b/lib/gaisler/jtag/jtagtst.vhd index 9800ff5c..dd13f230 100644 --- a/lib/gaisler/jtag/jtagtst.vhd +++ b/lib/gaisler/jtag/jtagtst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -67,6 +67,13 @@ package jtagtst is signal tck, tms, tdi : out std_ulogic; signal tdo : in std_ulogic; cp : in integer); + + procedure jwritem(addr : in std_logic_vector; + data : in jdata_vector_type; + hsize : in std_logic_vector(1 downto 0); + signal tck, tms, tdi : out std_ulogic; + signal tdo : in std_ulogic; + cp : in integer); procedure jreadm(addr : in std_logic_vector; data : out jdata_vector_type; @@ -76,6 +83,15 @@ package jtagtst is reread : in boolean := false; assertions : in boolean := false); + procedure jreadm(addr : in std_logic_vector; + hsize : in std_logic_vector(1 downto 0); + data : out jdata_vector_type; + signal tck, tms, tdi : out std_ulogic; + signal tdo : in std_ulogic; + cp : in integer; + reread : in boolean := false; + assertions : in boolean := false); + procedure jwrite(addr, data : in std_logic_vector; signal tck, tms, tdi : out std_ulogic; signal tdo : in std_ulogic; @@ -97,6 +113,15 @@ package jtagtst is reread : in boolean := false; assertions : in boolean := false); + procedure jread(addr : in std_logic_vector; + hsize : in std_logic_vector; + data : out std_logic_vector; + signal tck, tms, tdi : out std_ulogic; + signal tdo : in std_ulogic; + cp : in integer; + reread : in boolean := false; + assertions : in boolean := false); + procedure bscantest(signal tdo : in std_ulogic; signal tck, tms, tdi : out std_ulogic; cp: in integer; @@ -241,6 +266,41 @@ package body jtagtst is end loop; data := dr(31 downto 0); end; + + procedure jread(addr : in std_logic_vector; + hsize : in std_logic_vector; + data : out std_logic_vector; + signal tck, tms, tdi : out std_ulogic; + signal tdo : in std_ulogic; + cp : in integer; + reread : in boolean := false; + assertions : in boolean := false) is + variable tmp : std_logic_vector(32 downto 0); + variable tmp2 : std_logic_vector(34 downto 0); + variable dr : std_logic_vector(32 downto 0); + variable dr2 : std_logic_vector(34 downto 0); + begin + wait for 10 * cp * 1 ns; + shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg + wait for 5 * cp * 1 ns; + tmp2 := '0' & hsize & addr; + shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg + wait for 5 * cp * 1 ns; + shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg + wait for 5 * cp * 1 ns; + tmp := (others => '0'); --tmp(32) := '1'; + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg + assert dr(32) = '1' or not assertions + report "JTAG READ: data read out before AHB access completed" + severity warning; + while dr(32) /= '1' and reread loop + assert not assertions report "Re-reading JTAG data register" severity note; + wait for 5 * cp * 1 ns; + tmp := (others => '0'); + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg + end loop; + data := dr(31 downto 0); + end; procedure jwritem(addr : in std_logic_vector; data : in jdata_vector_type; @@ -268,6 +328,33 @@ package body jtagtst is end loop; tmp := '0' & data(data'right); shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg + end; + + procedure jwritem(addr : in std_logic_vector; + data : in jdata_vector_type; + hsize : in std_logic_vector(1 downto 0); + signal tck, tms, tdi : out std_ulogic; + signal tdo : in std_ulogic; + cp : in integer) is + variable tmp : std_logic_vector(32 downto 0); + variable tmp2 : std_logic_vector(34 downto 0); + variable dr : std_logic_vector(32 downto 0); + variable dr2 : std_logic_vector(34 downto 0); + begin + wait for 10 * cp * 1 ns; + shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg + wait for 5 * cp * 1 ns; + tmp2 := '1' & hsize & addr; + shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg + wait for 5 * cp * 1 ns; + shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg + wait for 5 * cp * 1 ns; + for i in data'left to data'right-1 loop + tmp := '1' & data(i); + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg + end loop; + tmp := '0' & data(data'right); + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- write data reg end; procedure jreadm(addr : in std_logic_vector; @@ -318,6 +405,53 @@ package body jtagtst is data(data'right) := dr(31 downto 0); end; + procedure jreadm(addr : in std_logic_vector; + hsize : in std_logic_vector(1 downto 0); + data : out jdata_vector_type; + signal tck, tms, tdi : out std_ulogic; + signal tdo : in std_ulogic; + cp : in integer; + reread : in boolean := false; + assertions : in boolean := false) is + variable tmp : std_logic_vector(32 downto 0); + variable tmp2 : std_logic_vector(34 downto 0); + variable dr : std_logic_vector(32 downto 0); + variable dr2 : std_logic_vector(34 downto 0); + begin + wait for 10 * cp * 1 ns; + shift(false, 6, B"010000", dr, tck, tms, tdi, tdo, cp); -- inst = addrreg + wait for 5 * cp * 1 ns; + tmp2 := '0' & hsize & addr; + shift(true, 35, tmp2, dr2, tck, tms, tdi, tdo, cp); -- write add reg + wait for 5 * cp * 1 ns; + shift(false, 6, B"110000", dr, tck, tms, tdi, tdo, cp); -- inst = datareg + wait for 5 * cp * 1 ns; + for i in data'left to data'right-1 loop + tmp := (others => '0'); tmp(32) := '1'; + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg + assert dr(32) = '1' or not assertions + report "JTAG READ: data read out before AHB access completed" + severity warning; + while dr(32) /= '1' and reread loop + assert not assertions report "Re-reading JTAG data register" severity note; + tmp := (others => '0'); tmp(32) := '1'; + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg + end loop; + data(i) := dr(31 downto 0); + end loop; + tmp := (others => '0'); + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg + assert dr(32) = '1' or not assertions + report "JTAG READ: data read out before AHB access completed" + severity warning; + while dr(32) /= '1' and reread loop + assert not assertions report "Re-reading JTAG data register" severity note; + tmp := (others => '0'); + shift(true, 33, tmp, dr, tck, tms, tdi, tdo, cp); -- read data reg + end loop; + data(data'right) := dr(31 downto 0); + end; + procedure jtagcom(signal tdo : in std_ulogic; signal tck, tms, tdi : out std_ulogic; cp, start, addr : in integer; @@ -334,7 +468,8 @@ begin tck <= '0'; tms <= '0'; tdi <= '0'; - wait for start * 1 us; + wait for start * 1 us; + print("AHB JTAG TEST"); for i in 1 to 5 loop -- reset clkj('1', '0', dc, tck, tms, tdi, tdo, cp); diff --git a/lib/gaisler/jtag/libjtagcom.vhd b/lib/gaisler/jtag/libjtagcom.vhd index d4f8ddb7..b735160d 100644 --- a/lib/gaisler/jtag/libjtagcom.vhd +++ b/lib/gaisler/jtag/libjtagcom.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/l2cache/l2c.in b/lib/gaisler/l2cache/l2c.in index aac76264..38e1bcb0 100644 --- a/lib/gaisler/l2cache/l2c.in +++ b/lib/gaisler/l2cache/l2c.in @@ -1,7 +1,7 @@ mainmenu_option next_comment comment 'L2 Cache' -# bool 'Enable L2 Cache ' CONFIG_L2_ENABLE + bool 'Enable L2 Cache ' CONFIG_L2_ENABLE # if [ "$CONFIG_GPT_ENABLE" = "y" ]; then choice 'Associativity (ways) ' \ "1 CONFIG_L2_ASSO1 \ diff --git a/lib/gaisler/l2cache/l2c.in.h b/lib/gaisler/l2cache/l2c.in.h index 8cb58ecb..8d09a8e3 100644 --- a/lib/gaisler/l2cache/l2c.in.h +++ b/lib/gaisler/l2cache/l2c.in.h @@ -1,3 +1,6 @@ +#ifndef CONFIG_L2_ENABLE +#define CONFIG_L2_ENABLE 0 +#endif #if defined CONFIG_L2_ASSO1 #define CFG_L2_ASSO 1 diff --git a/lib/gaisler/l2cache/l2c.in.vhd b/lib/gaisler/l2cache/l2c.in.vhd index 84abd3ff..b7c25665 100644 --- a/lib/gaisler/l2cache/l2c.in.vhd +++ b/lib/gaisler/l2cache/l2c.in.vhd @@ -1,4 +1,5 @@ -- L2 Cache + constant CFG_L2_EN : integer := CONFIG_L2_ENABLE; constant CFG_L2_SIZE : integer := CFG_L2_SZ; constant CFG_L2_WAYS : integer := CFG_L2_ASSO; constant CFG_L2_HPROT : integer := CONFIG_L2_HPROT; diff --git a/lib/gaisler/l2cache/v2-pkg/l2cache.vhd b/lib/gaisler/l2cache/v2-pkg/l2cache.vhd new file mode 100644 index 00000000..359842dd --- /dev/null +++ b/lib/gaisler/l2cache/v2-pkg/l2cache.vhd @@ -0,0 +1,87 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Package: l2cache +-- File: libcache.vhd +-- Author: Nils-Johan Wessman - Gaisler Research +-- Description: L2-Cache component declaration +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library techmap; +use techmap.gencomp.all; +library gaisler; + +package l2cache is + +component l2c is + generic ( + hslvidx : integer := 0; + hmstidx : integer := 0; + haddr : integer := 16#F00#; + hmask : integer := 16#F00#; + ioaddr : integer := 16#000#; + cached : integer := 16#0000#; + hirq : integer := 0; + cen : integer range 0 to 1 := 0; + hproten : integer range 0 to 1 := 0; + wp : integer range 0 to 1 := 0; + repl : integer range 0 to 1 := 0; + ways : integer range 1 to 4 := 1; + linesize : integer range 16 to 64 := 32; + waysize : integer range 1 to 512 := 1; + memtech : integer range 0 to NTECH := 0; + bbuswidth : integer := 128; + bioaddr : integer := 16#000#; + biomask : integer := 16#000#; + sbus : integer := 0; + mbus : integer := 1; + stat : integer range 0 to 2 := 0; + scantest : integer := 0; + arch : integer := 0; + mtrr : integer := 0; + edacen : integer range 0 to 1 := 0; + rmw : integer range 0 to 1 := 0; + ft : integer range 0 to 1 := 0; + fttiming : integer range 0 to 1 := 0; + wbmask : integer range 0 to 16#FFFF# := 16#FFFF#; + debug : integer range 0 to 1 := 0); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type; + ahbmi : in ahb_mst_in_type; + ahbmo : out ahb_mst_out_type; + ahbsov: in ahb_slv_out_vector; + sto : out std_logic_vector(2 downto 0); + debugo: out std_logic_vector(255*debug downto 0) + ); +end component; + +end; + +package body l2cache is + +end; diff --git a/lib/gaisler/l2cache/v2-pkg/vhdlsyn.txt b/lib/gaisler/l2cache/v2-pkg/vhdlsyn.txt new file mode 100644 index 00000000..c70dddff --- /dev/null +++ b/lib/gaisler/l2cache/v2-pkg/vhdlsyn.txt @@ -0,0 +1 @@ +l2cache.vhd diff --git a/lib/gaisler/leon3/cpu_disasx.vhd b/lib/gaisler/leon3/cpu_disasx.vhd index 13194b87..47ad599d 100644 --- a/lib/gaisler/leon3/cpu_disasx.vhd +++ b/lib/gaisler/leon3/cpu_disasx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3/leon3.in b/lib/gaisler/leon3/leon3.in index 32b561a5..58e22bb4 100644 --- a/lib/gaisler/leon3/leon3.in +++ b/lib/gaisler/leon3/leon3.in @@ -255,9 +255,6 @@ if [ "$CONFIG_LEON3" = "y" ]; then bool 'Cache locking ' CONFIG_DCACHE_LOCK fi bool 'AHB snooping ' CONFIG_DCACHE_SNOOP - if [ "$CONFIG_DCACHE_SNOOP" = "y" ]; then - bool 'Fast snooping ' CONFIG_DCACHE_SNOOP_FAST - fi if [ "$CONFIG_DCACHE_SNOOP" = "y" ]; then bool 'Separate snoop tags ' CONFIG_DCACHE_SNOOP_SEPTAG fi diff --git a/lib/gaisler/leon3/leon3.in.h b/lib/gaisler/leon3/leon3.in.h index a6f5794a..8a2bf40c 100644 --- a/lib/gaisler/leon3/leon3.in.h +++ b/lib/gaisler/leon3/leon3.in.h @@ -253,10 +253,6 @@ #define CONFIG_DCACHE_SNOOP 0 #endif -#ifndef CONFIG_DCACHE_SNOOP_FAST -#define CONFIG_DCACHE_SNOOP_FAST 0 -#endif - #ifndef CONFIG_DCACHE_SNOOP_SEPTAG #define CONFIG_DCACHE_SNOOP_SEPTAG 0 #endif diff --git a/lib/gaisler/leon3/leon3.in.help b/lib/gaisler/leon3/leon3.in.help index f0c7ba01..7def0f86 100644 --- a/lib/gaisler/leon3/leon3.in.help +++ b/lib/gaisler/leon3/leon3.in.help @@ -287,19 +287,20 @@ CONFIG_DCACHE_LOCK Data cache snooping CONFIG_DCACHE_SNOOP - Say Y here to enable data cache snooping on the AHB bus. Is only - useful if you have additional AHB masters such as the DSU or a - target PCI interface. Note that the target technology must support - dual-port RAMs for this option to be enabled. Dual-port RAMS are - currently supported on Virtex/2, Virage and Actel targets. - -Data cache snooping implementation -CONFIG_DCACHE_SNOOP_FAST - The default snooping implementation is 'slow', which works if you - don't have AHB slaves in cacheable areas capable of zero-waitstates - non-sequential write accesses. Otherwise use 'fast' and suffer a - few kgates extra area. This option is currently only needed in - multi-master systems with the SSRAM or DDR memory controllers. + Say Y here to enable data cache snooping on the AHB bus. + + With snooping, AHB writes by other masters to data that is in the + data cache will be automatically detected and the cache line will + be marked as invalid. This simplifies software design in systems + with DMA units or multiple processors accessing the same memory. + It is a requirement (together with separate snoop tags) to run + Linux on more than one CPU. + + Depending on the separate snoop tags option, snooping will be + implemented using either dual-port (common tags) or two-port + RAMs (separate tags). A workaround if dual port RAMs are + not available for the target technology is to use separate + snoop tags even if it is not needed otherwise. Separate snoop tags CONFIG_DCACHE_SNOOP_SEPTAG @@ -307,10 +308,12 @@ CONFIG_DCACHE_SNOOP_SEPTAG This is necessary when snooping support is wanted in systems with MMU, typically for SMP systems. In this case, the snoop tags will contain the physical tag address while the normal - tags contain the virtual tag address. This option can also be - together with the 'fast snooping' option to enable snooping - support on technologies without dual-port RAMs. In such case, - the snoop tag RAM will be implemented using a two-port RAM. + tags contain the virtual tag address. + + When separate snoop tags are enabled, the tag RAMs will be implemented + using two-port RAMs instead of dual-port RAMs. A workaround if + dual port RAMs are not available for the target technology is + therefore to use separate snoop tags even if it is not needed. Fixed cacheability map CONFIG_CACHE_FIXED diff --git a/lib/gaisler/leon3/leon3.in.vhd b/lib/gaisler/leon3/leon3.in.vhd index bf337d52..fe5daeba 100644 --- a/lib/gaisler/leon3/leon3.in.vhd +++ b/lib/gaisler/leon3/leon3.in.vhd @@ -28,7 +28,7 @@ constant CFG_DLINE : integer := CFG_DLINE_SZ; constant CFG_DREPL : integer := CFG_DCACHE_ALGORND; constant CFG_DLOCK : integer := CONFIG_DCACHE_LOCK; - constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP + CONFIG_DCACHE_SNOOP_FAST + 4*CONFIG_DCACHE_SNOOP_SEPTAG; + constant CFG_DSNOOP : integer := CONFIG_DCACHE_SNOOP*2 + 4*CONFIG_DCACHE_SNOOP_SEPTAG; constant CFG_DFIXED : integer := 16#CONFIG_CACHE_FIXED#; constant CFG_DLRAMEN : integer := CONFIG_DCACHE_LRAM; constant CFG_DLRAMADDR: integer := 16#CONFIG_DCACHE_LRSTART#; diff --git a/lib/gaisler/leon3/leon3.vhd b/lib/gaisler/leon3/leon3.vhd index 3f7b7ef8..2dd713da 100644 --- a/lib/gaisler/leon3/leon3.vhd +++ b/lib/gaisler/leon3/leon3.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -675,6 +675,7 @@ package leon3 is ahbmi : in ahb_mst_in_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; + tahbsi : in ahb_slv_in_type; dbgi : in l3_debug_out_vector(0 to NCPU-1); dbgo : out l3_debug_in_vector(0 to NCPU-1); dsui : in dsu_in_type; @@ -682,6 +683,32 @@ package leon3 is hclken : in std_ulogic ); end component; + + component dsu3_mb + generic ( + hindex : integer := 0; + haddr : integer := 16#900#; + hmask : integer := 16#f00#; + ncpu : integer := 1; + tbits : integer := 30; -- timer bits (instruction trace time tag) + tech : integer := DEFMEMTECH; + irq : integer := 0; + kbytes : integer := 0; + testen : integer := 0 + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbmi : in ahb_mst_in_type; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type; + tahbsi : in ahb_slv_in_type; + dbgi : in l3_debug_out_vector(0 to NCPU-1); + dbgo : out l3_debug_in_vector(0 to NCPU-1); + dsui : in dsu_in_type; + dsuo : out dsu_out_type + ); + end component; type irq_in_vector is array (Natural range <> ) of l3_irq_in_type; type irq_out_vector is array (Natural range <> ) of l3_irq_out_type; diff --git a/lib/gaisler/leon3v3/cachemem.vhd b/lib/gaisler/leon3v3/cachemem.vhd index 4328de64..3aa6268a 100644 --- a/lib/gaisler/leon3v3/cachemem.vhd +++ b/lib/gaisler/leon3v3/cachemem.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/dsu3.vhd b/lib/gaisler/leon3v3/dsu3.vhd index e14b3c3b..cabb09a0 100644 --- a/lib/gaisler/leon3v3/dsu3.vhd +++ b/lib/gaisler/leon3v3/dsu3.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -68,6 +68,6 @@ begin gnd <= '0'; vcc <= '1'; x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen) - port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, dbgi, dbgo, dsui, dsuo, vcc); + port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, ahbsi, dbgi, dbgo, dsui, dsuo, vcc); end; diff --git a/lib/gaisler/leon3v3/dsu3_mb.vhd b/lib/gaisler/leon3v3/dsu3_mb.vhd new file mode 100644 index 00000000..0ea470bd --- /dev/null +++ b/lib/gaisler/leon3v3/dsu3_mb.vhd @@ -0,0 +1,75 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: dsu +-- File: dsu.vhd +-- Author: Jiri Gaisler, Edvin Catovic - Aeroflex Gaisler AB +-- Description: Combined LEON3 debug support with AHB trace unit +-- connected on separate bus. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.amba.all; +use grlib.stdlib.all; +use grlib.devices.all; +library gaisler; +use gaisler.leon3.all; +library techmap; +use techmap.gencomp.all; + +entity dsu3_mb is + generic ( + hindex : integer := 0; + haddr : integer := 16#900#; + hmask : integer := 16#f00#; + ncpu : integer := 1; + tbits : integer := 30; -- timer bits (instruction trace time tag) + tech : integer := DEFMEMTECH; + irq : integer := 0; + kbytes : integer := 0; + testen : integer := 0 + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbmi : in ahb_mst_in_type; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type; + tahbsi : in ahb_slv_in_type; + dbgi : in l3_debug_out_vector(0 to NCPU-1); + dbgo : out l3_debug_in_vector(0 to NCPU-1); + dsui : in dsu_in_type; + dsuo : out dsu_out_type + ); +end; + +architecture rtl of dsu3_mb is + + signal gnd, vcc : std_ulogic; + +begin + + gnd <= '0'; vcc <= '1'; + + x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen) + port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, tahbsi, dbgi, dbgo, dsui, dsuo, vcc); + +end; diff --git a/lib/gaisler/leon3v3/dsu3x.vhd b/lib/gaisler/leon3v3/dsu3x.vhd index 2ceda35f..27f37793 100644 --- a/lib/gaisler/leon3v3/dsu3x.vhd +++ b/lib/gaisler/leon3v3/dsu3x.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -56,6 +56,7 @@ entity dsu3x is ahbmi : in ahb_mst_in_type; ahbsi : in ahb_slv_in_type; ahbso : out ahb_slv_out_type; + tahbsi : in ahb_slv_in_type; dbgi : in l3_debug_out_vector(0 to NCPU-1); dbgo : out l3_debug_in_vector(0 to NCPU-1); dsui : in dsu_in_type; @@ -229,12 +230,12 @@ architecture rtl of dsu3x is signal r, rin : reg_type; signal rh, rhin : hclk_reg_type; - signal ahbsi2 : ahb_slv_in_type; + signal ahbsi2, tahbsi2 : ahb_slv_in_type; signal hrdata2x : std_logic_vector(31 downto 0); begin - comb: process(rst, r, ahbsi, ahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x) + comb: process(rst, r, ahbsi, ahbsi2, tahbsi2, dbgi, dsui, ahbmi, tr, tbo, hclken, rh, hrdata2x) variable v : reg_type; variable iuacc : std_ulogic; @@ -277,7 +278,7 @@ begin -- check for AHB watchpoints bphit1 := '0'; bphit2 := '0'; - if TRACEN and ((ahbsi2.hready and tr.ahbactive) = '1') then + if TRACEN and ((tahbsi2.hready and tr.ahbactive) = '1') then if ((((tr.tbreg1.addr xor tr.haddr(31 downto 2)) and tr.tbreg1.mask) = zero32(29 downto 0)) and (((tr.tbreg1.read and not tr.hwrite) or (tr.tbreg1.write and tr.hwrite)) = '1')) then bphit1 := '1'; end if; @@ -339,15 +340,15 @@ begin -- save AHB transfer parameters - if (ahbsi2.hready = '1' ) then - tv.haddr := ahbsi2.haddr; tv.hwrite := ahbsi2.hwrite; tv.htrans := ahbsi2.htrans; - tv.hsize := ahbsi2.hsize; tv.hburst := ahbsi2.hburst; - tv.hmaster := ahbsi2.hmaster; tv.hmastlock := ahbsi2.hmastlock; + if (tahbsi2.hready = '1' ) then + tv.haddr := tahbsi2.haddr; tv.hwrite := tahbsi2.hwrite; tv.htrans := tahbsi2.htrans; + tv.hsize := tahbsi2.hsize; tv.hburst := tahbsi2.hburst; + tv.hmaster := tahbsi2.hmaster; tv.hmastlock := tahbsi2.hmastlock; end if; - if tr.hsel = '1' then tv.hwdata := ahbsi2.hwdata(31 downto 0); end if; - if ahbsi2.hready = '1' then - tv.hsel := ahbsi2.hsel(hindex); - tv.ahbactive := ahbsi2.htrans(1); + if tr.hsel = '1' then tv.hwdata := tahbsi2.hwdata(31 downto 0); end if; + if tahbsi2.hready = '1' then + tv.hsel := tahbsi2.hsel(hindex); + tv.ahbactive := tahbsi2.htrans(1); end if; end if; @@ -673,34 +674,86 @@ begin end process; comb2gen0 : if (clk2x /= 0) generate - ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hmastlock, hclken, ahbsi2.hmastlock); - ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite); - ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready); - gen3 : for i in ahbsi.haddr'range generate - ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i)); + -- register i/f + gen0 : for i in ahbsi.hsel'range generate + ag0 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i)); end generate; - gen4 : for i in ahbsi.htrans'range generate - ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i)); + + gen1 : for i in ahbsi.haddr'range generate + ag1 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.haddr(i), hclken, ahbsi2.haddr(i)); end generate; --- gen5 : for i in ahbsi.hwdata'range generate - gen5 : for i in 0 to 31 generate - ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i)); + + ag2 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwrite, hclken, ahbsi2.hwrite); + + gen3 : for i in ahbsi.htrans'range generate + ag3 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.htrans(i), hclken, ahbsi2.htrans(i)); + end generate; + + gen4 : for i in ahbsi.hwdata'range generate + ag4 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hwdata(i), hclken, ahbsi2.hwdata(i)); end generate; - gen6 : for i in ahbsi.hsize'range generate - ag6 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsize(i), hclken, ahbsi2.hsize(i)); + + ag5 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hready, hclken, ahbsi2.hready); + + -- not used by register i/f: + ahbsi2.hsize <= (others => '0'); + ahbsi2.hburst <= (others => '0'); + ahbsi2.hprot <= (others => '0'); + ahbsi2.hmaster <= (others => '0'); + ahbsi2.hmastlock <= '0'; + ahbsi2.hmbsel <= (others => '0'); + ahbsi2.hirq <= (others => '0'); + ahbsi2.testen <= '0'; + ahbsi2.testrst <= '0'; + ahbsi2.scanen <= '0'; + ahbsi2.testoen <= '0'; + + -- trace buffer: + gen6 : for i in tahbsi.haddr'range generate + ag6 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.haddr(i), hclken, tahbsi2.haddr(i)); end generate; - gen7 : for i in ahbsi.hburst'range generate - ag7 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hburst(i), hclken, ahbsi2.hburst(i)); + + ag7 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwrite, hclken, tahbsi2.hwrite); + + gen8 : for i in tahbsi.htrans'range generate + ag8 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.htrans(i), hclken, tahbsi2.htrans(i)); end generate; - gen8 : for i in ahbsi.hmaster'range generate - ag8 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hmaster(i), hclken, ahbsi2.hmaster(i)); + + gen9 : for i in tahbsi.hsize'range generate + ag9 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsize(i), hclken, tahbsi2.hsize(i)); end generate; - gen9 : for i in ahbsi.hsel'range generate - ag9 : clkand generic map (tech => 0, ren => 0) port map (ahbsi.hsel(i), hclken, ahbsi2.hsel(i)); + + gen10 : for i in tahbsi.hburst'range generate + a10 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hburst(i), hclken, tahbsi2.hburst(i)); end generate; - gen10 : for i in hrdata2x'range generate - ag10 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i)); + gen11 : for i in tahbsi.hwdata'range generate + ag11 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hwdata(i), hclken, tahbsi2.hwdata(i)); + end generate; + + ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hready, hclken, tahbsi2.hready); + + gen12 : for i in tahbsi.hmaster'range generate + ag12 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmaster(i), hclken, tahbsi2.hmaster(i)); + end generate; + + ag13 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hmastlock, hclken, tahbsi2.hmastlock); + + gen14 : for i in tahbsi.hsel'range generate + ag14 : clkand generic map (tech => 0, ren => 0) port map (tahbsi.hsel(i), hclken, tahbsi2.hsel(i)); + end generate; + + -- not used by trace buffer: + tahbsi2.hprot <= (others => '0'); + tahbsi2.hmbsel <= (others => '0'); + tahbsi2.hirq <= (others => '0'); + tahbsi2.testen <= '0'; + tahbsi2.testrst <= '0'; + tahbsi2.scanen <= '0'; + tahbsi2.testoen <= '0'; + + gen15 : for i in hrdata2x'range generate + ag15 : clkand generic map (tech => 0, ren => 0) port map (r.slv.hrdata(i), rh.oen, hrdata2x(i)); end generate; reg2 : process(hclk) @@ -711,6 +764,7 @@ begin comb2gen1 : if (clk2x = 0) generate ahbsi2 <= ahbsi; rh.irq <= '0'; rh.oen <= '0'; hrdata2x <= (others => '0'); + tahbsi2 <= tahbsi; end generate; reg : process(cpuclk) diff --git a/lib/gaisler/leon3v3/grfpwx.vhd b/lib/gaisler/leon3v3/grfpwx.vhd index cec99816..87854458 100644 --- a/lib/gaisler/leon3v3/grfpwx.vhd +++ b/lib/gaisler/leon3v3/grfpwx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/grfpwxsh.vhd b/lib/gaisler/leon3v3/grfpwxsh.vhd index ca00d8a0..57058dcc 100644 --- a/lib/gaisler/leon3v3/grfpwxsh.vhd +++ b/lib/gaisler/leon3v3/grfpwxsh.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/grlfpwx.vhd b/lib/gaisler/leon3v3/grlfpwx.vhd index dfd40a7c..1ece2506 100644 --- a/lib/gaisler/leon3v3/grlfpwx.vhd +++ b/lib/gaisler/leon3v3/grlfpwx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/iu3.vhd b/lib/gaisler/leon3v3/iu3.vhd index fc402215..9a2bfc42 100644 --- a/lib/gaisler/leon3v3/iu3.vhd +++ b/lib/gaisler/leon3v3/iu3.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/leon3cg.vhd b/lib/gaisler/leon3v3/leon3cg.vhd index cff4d304..18fe5202 100644 --- a/lib/gaisler/leon3v3/leon3cg.vhd +++ b/lib/gaisler/leon3v3/leon3cg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/leon3s.vhd b/lib/gaisler/leon3v3/leon3s.vhd index e424acfe..9a941468 100644 --- a/lib/gaisler/leon3v3/leon3s.vhd +++ b/lib/gaisler/leon3v3/leon3s.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/leon3sh.vhd b/lib/gaisler/leon3v3/leon3sh.vhd index d0523fab..c05db301 100644 --- a/lib/gaisler/leon3v3/leon3sh.vhd +++ b/lib/gaisler/leon3v3/leon3sh.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/leon3x.vhd b/lib/gaisler/leon3v3/leon3x.vhd index 54ee64f4..73d95bad 100644 --- a/lib/gaisler/leon3v3/leon3x.vhd +++ b/lib/gaisler/leon3v3/leon3x.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -128,6 +128,14 @@ constant fpuarch : integer := fpu mod 16; constant fpunet : integer := (fpu mod 32) / 16; constant fpushared : boolean := (fpu / 32) /= 0; +constant FTSUP : integer := 0 + ; + +-- Create an array length mismatch error if the user tries to enable FT +-- features in non-FT release. +constant dummy_ft_consistency_check: + std_logic_vector(FTSUP*(iuft+fpft+cmft) downto (iuft+fpft+cmft)) := "0"; + signal holdn : std_logic; signal rfi : iregfile_in_type; signal rfo : iregfile_out_type; diff --git a/lib/gaisler/leon3v3/libcache.vhd b/lib/gaisler/leon3v3/libcache.vhd index 1e413a00..90e580cb 100644 --- a/lib/gaisler/leon3v3/libcache.vhd +++ b/lib/gaisler/leon3v3/libcache.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -543,7 +543,9 @@ package body libcache is begin cfg := (others => '0'); cfg(31 downto 31) := conv_std_logic_vector(lock, 1); - cfg(30 downto 28) := conv_std_logic_vector(repl+1, 3); + if sets /= 1 then + cfg(30 downto 28) := conv_std_logic_vector(repl+1, 3); + end if; if snoop /= 0 then cfg(27) := '1'; end if; cfg(26 downto 24) := conv_std_logic_vector(sets-1, 3); cfg(23 downto 20) := conv_std_logic_vector(log2(setsize), 4); diff --git a/lib/gaisler/leon3v3/libfpu.vhd b/lib/gaisler/leon3v3/libfpu.vhd index 1ab3610d..0e9c25cd 100644 --- a/lib/gaisler/leon3v3/libfpu.vhd +++ b/lib/gaisler/leon3v3/libfpu.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/libiu.vhd b/lib/gaisler/leon3v3/libiu.vhd index 733a1b5b..d200b52a 100644 --- a/lib/gaisler/leon3v3/libiu.vhd +++ b/lib/gaisler/leon3v3/libiu.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/libleon3.vhd b/lib/gaisler/leon3v3/libleon3.vhd index 5a23b841..1da19a03 100644 --- a/lib/gaisler/leon3v3/libleon3.vhd +++ b/lib/gaisler/leon3v3/libleon3.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/mmu_acache.vhd b/lib/gaisler/leon3v3/mmu_acache.vhd index 35a052f7..c393d4d1 100644 --- a/lib/gaisler/leon3v3/mmu_acache.vhd +++ b/lib/gaisler/leon3v3/mmu_acache.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -237,8 +237,10 @@ begin htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1; hburst := HBURST_INCR; end if; - if (dreq and r.bg and ahbi.hready and not r.retry) = '1' - then dgrant := (not mcdi.lock or r.hlocken) or r.retry2; v.hcache := dec_hcache; end if; + if (dreq and r.bg and ahbi.hready and not r.retry) = '1' then + dgrant := (not mcdi.lock or r.hlocken) or (r.retry2 and (not r.bo(1) and r.bo(0))); + v.hcache := dec_hcache; + end if; end if; if (hclken = '1') or (clk2x = 0) then diff --git a/lib/gaisler/leon3v3/mmu_cache.vhd b/lib/gaisler/leon3v3/mmu_cache.vhd index 09327d1d..18cd085d 100644 --- a/lib/gaisler/leon3v3/mmu_cache.vhd +++ b/lib/gaisler/leon3v3/mmu_cache.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/mmu_dcache.vhd b/lib/gaisler/leon3v3/mmu_dcache.vhd index 6300b9d7..b1a3c01c 100644 --- a/lib/gaisler/leon3v3/mmu_dcache.vhd +++ b/lib/gaisler/leon3v3/mmu_dcache.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -731,7 +731,7 @@ begin newptag := mmudco.wbtransdata.data(TAG_HIGH downto TAG_LOW); end if; end if; - if (dci.read and hcache) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if; + if (dci.read and hcache and andv(r.cctrl.dcs)) = '1' then v.wb.addr(LINE_HIGH downto 0) := (others => '0'); end if; end if; if (eholdn and (not r.nomds)) = '1' then -- avoid false path through nullify case dci.asi(4 downto 0) is @@ -829,7 +829,7 @@ begin end if; when others => if dci.read = '1' then -- read access - v.rburst := hcache; -- and not forcemiss; + v.rburst := hcache and (andv(r.cctrl.dcs) or andv(dci.size)); -- and not forcemiss; if (dlram = 1) and (lramen = '1') then lramrd := '1'; elsif (ilram = 1) and (ilramen = '1') then @@ -837,7 +837,8 @@ begin else v.dstate := asi_idtag; v.holdn := dci.dsuen; v.ilramen := '1'; end if; elsif dci.dsuen = '0' then if not ((hit and valid and not forcemiss) = '1') then -- read miss - v.holdn := '0'; v.dstate := wread; v.ready := '0'; v.cache := hcache; + v.holdn := '0'; v.dstate := wread; v.ready := '0'; + v.cache := hcache and andv(r.cctrl.dcs); if (not M_EN) or ((dci.asi(4 downto 0) = ASI_MMU_BP) or (r.mmctrl1.e = '0')) then -- cache disabled if mmu-enabled but off or BYPASS if ((r.stpend = '0') or ((mcdo.ready and not r.req) = '1')) then @@ -1028,9 +1029,9 @@ begin for i in 0 to 3 loop wlrr(i) := r.lrr; end loop; if (r.stpend = '0') and (r.ready = '0') then if (r.rburst) = '1' then - if (mcdo.grant = '1') and (r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW)) - and not ((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0')) - then + if (mcdo.grant = '1') and ((r.cctrl.dcs = "01") or + ((r.wb.addr(LINE_HIGH downto LINE_LOW) >= bend(LINE_HIGH downto LINE_LOW)) and not + ((r.wb.addr(LINE_HIGH downto LINE_LOW) = bend(LINE_HIGH downto LINE_LOW)) and (mcdo.ready = '0')))) then v.burst := '0'; else v.burst := r.burst; end if; end if; @@ -1042,11 +1043,11 @@ begin mds := '0'; end if; end if; - dwrite := r.cache and r.cctrl.dcs(1); rdatasel := memory; + dwrite := r.cache; rdatasel := memory; mexc := mcdo.mexc; v.bmexc := r.bmexc or mcdo.mexc or dci.flushl; if r.req = '0' then - twrite := r.cache and r.cctrl.dcs(1); tagclear := v.bmexc; + twrite := r.cache; tagclear := v.bmexc; if (((dci.enaddr and not mds) = '1') or (dci.flushl = '1') or ((dci.enaddr and twrite) = '1')) and ((r.cctrl.dcs(0) = '1') or (dlram = 1)) then v.dstate := loadpend; v.holdn := '0'; diff --git a/lib/gaisler/leon3v3/mmu_icache.vhd b/lib/gaisler/leon3v3/mmu_icache.vhd index cb943e74..fb5abcd5 100644 --- a/lib/gaisler/leon3v3/mmu_icache.vhd +++ b/lib/gaisler/leon3v3/mmu_icache.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/proc3.vhd b/lib/gaisler/leon3v3/proc3.vhd index e0fd5a47..a2c774fd 100644 --- a/lib/gaisler/leon3v3/proc3.vhd +++ b/lib/gaisler/leon3v3/proc3.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/regfile_3p_l3.vhd b/lib/gaisler/leon3v3/regfile_3p_l3.vhd index f869218b..fe6f2fc9 100644 --- a/lib/gaisler/leon3v3/regfile_3p_l3.vhd +++ b/lib/gaisler/leon3v3/regfile_3p_l3.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/tbufmem.vhd b/lib/gaisler/leon3v3/tbufmem.vhd index b9129b58..982697d5 100644 --- a/lib/gaisler/leon3v3/tbufmem.vhd +++ b/lib/gaisler/leon3v3/tbufmem.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/leon3v3/vhdlsyn.txt b/lib/gaisler/leon3v3/vhdlsyn.txt index 425f7b9f..4625b031 100644 --- a/lib/gaisler/leon3v3/vhdlsyn.txt +++ b/lib/gaisler/leon3v3/vhdlsyn.txt @@ -2,6 +2,7 @@ tbufmem.vhd dsu3x.vhd dsu3.vhd dsu3_2x.vhd +dsu3_mb.vhd libfpu.vhd libiu.vhd libcache.vhd diff --git a/lib/gaisler/memctrl/memctrl.vhd b/lib/gaisler/memctrl/memctrl.vhd index 60c5bdf8..dbc31e62 100644 --- a/lib/gaisler/memctrl/memctrl.vhd +++ b/lib/gaisler/memctrl/memctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -418,7 +418,8 @@ component ftsdmctrl wprot : integer := 0; sdbits : integer := 32; syncrst : integer := 0; - pageburst : integer := 0 + pageburst : integer := 0; + edac : integer := 0 ); port ( rst : in std_ulogic; @@ -581,4 +582,31 @@ end component; ); end component; + component p8ctrl + generic ( + hindex : integer := 0; + romaddr : integer := 0; + rommask : integer := 16#ff0#; + ramaddr : integer := 0; + iomask : integer := 16#ff0#; + ioaddr : integer := 0; + rammask : integer := 16#ff0#; + romws : integer := 15; + ramws : integer := 15; + prom8en : integer := 0; + rmw : integer := 0; + oepol : integer := 0; + romasel : integer range 0 to 28 := 23 + ); + port ( + rst : in std_ulogic; + clk : in std_ulogic; + ahbsi : in ahb_slv_in_type; + ahbso : out ahb_slv_out_type; + sri : in memory_in_type; + sro : out memory_out_type; + sdo : out sdctrl_out_type + ); + end component; + end; diff --git a/lib/gaisler/memctrl/sdctrl.vhd b/lib/gaisler/memctrl/sdctrl.vhd index 3af141f7..61552efe 100644 --- a/lib/gaisler/memctrl/sdctrl.vhd +++ b/lib/gaisler/memctrl/sdctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/memctrl/sdctrl64.vhd b/lib/gaisler/memctrl/sdctrl64.vhd index fa9fb886..c7eb17a3 100644 --- a/lib/gaisler/memctrl/sdctrl64.vhd +++ b/lib/gaisler/memctrl/sdctrl64.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/memctrl/sdmctrl.vhd b/lib/gaisler/memctrl/sdmctrl.vhd index 9fef8df9..a6536428 100644 --- a/lib/gaisler/memctrl/sdmctrl.vhd +++ b/lib/gaisler/memctrl/sdmctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/memctrl/srctrl.vhd b/lib/gaisler/memctrl/srctrl.vhd index b7c74b46..42fdeeb0 100644 --- a/lib/gaisler/memctrl/srctrl.vhd +++ b/lib/gaisler/memctrl/srctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/memctrl/vhdlsyn.txt b/lib/gaisler/memctrl/vhdlsyn.txt index 87f28c47..26a91641 100644 --- a/lib/gaisler/memctrl/vhdlsyn.txt +++ b/lib/gaisler/memctrl/vhdlsyn.txt @@ -7,13 +7,9 @@ ssrctrl.vhd ftsrctrlc.vhd ftsrctrl.vhd ftsdctrl.vhd -ftsdmctrl.vhd -ftmctrlc.vhd ftsrctrl8.vhd -ftsdmctrlx.vhd -ftmctrlcx.vhd -ftsdmctrlxx.vhd -ftmctrlcxx.vhd -ftmctrl.vhd +ftsdmctrl.vhd +ftmctrl.vhd ftsdctrl64.vhd spimctrl.vhd +p8ctrl.vhd diff --git a/lib/gaisler/misc/ahb_mst_iface.vhd b/lib/gaisler/misc/ahb_mst_iface.vhd index ff0cca51..d7073c91 100644 --- a/lib/gaisler/misc/ahb_mst_iface.vhd +++ b/lib/gaisler/misc/ahb_mst_iface.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/ahbdpram.vhd b/lib/gaisler/misc/ahbdpram.vhd index ee47aee8..9dbd4c6c 100644 --- a/lib/gaisler/misc/ahbdpram.vhd +++ b/lib/gaisler/misc/ahbdpram.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/ahbram.vhd b/lib/gaisler/misc/ahbram.vhd index 4aabb476..551cba5c 100644 --- a/lib/gaisler/misc/ahbram.vhd +++ b/lib/gaisler/misc/ahbram.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/ahbstat.vhd b/lib/gaisler/misc/ahbstat.vhd index 1bd47207..727f602d 100644 --- a/lib/gaisler/misc/ahbstat.vhd +++ b/lib/gaisler/misc/ahbstat.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/ahbtrace.vhd b/lib/gaisler/misc/ahbtrace.vhd index 1f2a042a..ee97d8a4 100644 --- a/lib/gaisler/misc/ahbtrace.vhd +++ b/lib/gaisler/misc/ahbtrace.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -42,6 +42,7 @@ entity ahbtrace is tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; + bwidth : integer := 32; ahbfilt : integer := 0); port ( rst : in std_ulogic; @@ -64,6 +65,7 @@ begin tech => tech, irq => irq, kbytes => kbytes, + bwidth => bwidth, ahbfilt => ahbfilt) port map( rst => rst, diff --git a/lib/gaisler/misc/ahbtrace_mb.vhd b/lib/gaisler/misc/ahbtrace_mb.vhd index 1d85062f..3eeb822e 100644 --- a/lib/gaisler/misc/ahbtrace_mb.vhd +++ b/lib/gaisler/misc/ahbtrace_mb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -43,6 +43,7 @@ entity ahbtrace_mb is tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; + bwidth : integer := 32; ahbfilt : integer := 0); port ( rst : in std_ulogic; @@ -73,6 +74,7 @@ begin tech => tech, irq => irq, kbytes => kbytes, + bwidth => bwidth, ahbfilt => ahbfilt, ntrace => 1) port map( diff --git a/lib/gaisler/misc/ahbtrace_mmb.vhd b/lib/gaisler/misc/ahbtrace_mmb.vhd index 256a1a15..abfeba63 100644 --- a/lib/gaisler/misc/ahbtrace_mmb.vhd +++ b/lib/gaisler/misc/ahbtrace_mmb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -17,11 +17,11 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- --- Entity: ahbtrace_mmb --- File: ahbtrace_mmb.vhd --- Author: Jiri Gaisler - Gaisler Research +-- Entity: ahbtrace_mmb +-- File: ahbtrace_mmb.vhd +-- Author: Jiri Gaisler - Gaisler Research -- Modified: Jan Andersson - Aeroflex Gaisler --- Description: AHB trace unit that can have registers on a separate bus and +-- Description: AHB trace unit that can have registers on a separate bus and -- select between several trace buses. ------------------------------------------------------------------------------ @@ -43,6 +43,7 @@ entity ahbtrace_mmb is tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; + bwidth : integer := 32; ahbfilt : integer := 0; ntrace : integer range 1 to 8 := 1); port ( @@ -68,13 +69,13 @@ constant hconfig : ahb_config_type := ( type tracebuf_in_type is record addr : std_logic_vector(TBUFABITS-1 downto 0); - data : std_logic_vector(127 downto 0); + data : std_logic_vector(255 downto 0); enable : std_logic; - write : std_logic_vector(3 downto 0); + write : std_logic_vector(7 downto 0); end record; type tracebuf_out_type is record - data : std_logic_vector(127 downto 0); + data : std_logic_vector(255 downto 0); end record; type trace_break_reg is record @@ -87,32 +88,32 @@ end record; type regtype is record thaddr : std_logic_vector(31 downto 0); thwrite : std_logic; - thtrans : std_logic_vector(1 downto 0); + thtrans : std_logic_vector(1 downto 0); thsize : std_logic_vector(2 downto 0); thburst : std_logic_vector(2 downto 0); thmaster : std_logic_vector(3 downto 0); thmastlock : std_logic; ahbactive : std_logic; timer : std_logic_vector(TIMEBITS-1 downto 0); - aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index + aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index hready : std_logic; hready2 : std_logic; hready3 : std_logic; hsel : std_logic; hwrite : std_logic; - haddr : std_logic_vector(TBUFABITS+3 downto 2); + haddr : std_logic_vector(TBUFABITS+4 downto 2); hrdata : std_logic_vector(31 downto 0); regacc : std_logic; - enable : std_logic; -- trace enable - bahb : std_logic; -- break on AHB watchpoint hit - bhit : std_logic; -- breakpoint hit - dcnten : std_logic; -- delay counter enable + enable : std_logic; -- trace enable + bahb : std_logic; -- break on AHB watchpoint hit + bhit : std_logic; -- breakpoint hit + dcnten : std_logic; -- delay counter enable delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter - tbreg1 : trace_break_reg; - tbreg2 : trace_break_reg; + tbreg1 : trace_break_reg; + tbreg2 : trace_break_reg; end record; type fregtype is record @@ -183,7 +184,8 @@ begin variable regsd : std_logic_vector(31 downto 0); -- data from registers variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index variable bphit : std_logic; - variable bufdata : std_logic_vector(127 downto 0); + variable wdata, rdata : std_logic_vector(127 downto 0); + variable hwdata : std_logic_vector(31 downto 0); variable hirq : std_logic_vector(NAHBIRQ-1 downto 0); variable tahbmi : ahb_mst_in_type; variable tahbsi : ahb_slv_in_type; @@ -197,7 +199,7 @@ begin vabufi.data := (others => '0'); vabufi.addr := (others => '0'); vabufi.write := (others => '0'); bphit := '0'; v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0'; - bufdata := tbo.data; + hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2)); hirq := (others => '0'); hirq(irq) := r.bhit; vf := rf; vb := rb; if ntrace = 1 then @@ -206,7 +208,7 @@ begin tahbmi := tahbmiv(conv_integer(rb.bsel)); tahbsi := tahbsiv(conv_integer(rb.bsel)); end if; - regaddr := r.haddr(4 downto 2); tbaddr := r.haddr(3 downto 2); + regaddr := r.haddr(4 downto 2); --tbaddr := r.haddr(3 downto 2); -- trace buffer index and delay counters if r.enable = '1' then v.timer := r.timer + 1; end if; @@ -219,38 +221,46 @@ begin or ((((r.tbreg2.addr xor r.thaddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and (((r.tbreg2.read and not r.thwrite) or (r.tbreg2.write and r.thwrite)) = '1')) then - if (r.enable = '1') and (r.dcnten = '0') and - (r.delaycnt /= zero32(TBUFABITS-1 downto 0)) + if (r.enable = '1') and (r.dcnten = '0') and + (r.delaycnt /= zero32(TBUFABITS-1 downto 0)) then v.dcnten := '1'; bphit := '1'; - --else bphit := '1'; v.enable := '0'; end if; - elsif (r.enable = '1') and (r.dcnten = '0') then bphit := '1'; v.enable := '0'; end if; + --else bphit := '1'; v.enable := '0'; end if; + elsif (r.enable = '1') and (r.dcnten = '0') then bphit := '1'; v.enable := '0'; end if; end if; end if; -- generate buffer inputs - vabufi.write := "0000"; + vabufi.write := "00000000"; + wdata(AHBDW-1 downto 0) := tahbsi.hwdata; + rdata(AHBDW-1 downto 0) := tahbmi.hrdata; if r.enable = '1' then vabufi.addr(TBUFABITS-1 downto 0) := r.aindex; vabufi.data(127 downto 96) := r.timer; vabufi.data(95) := bphit; - vabufi.data(94 downto 80) := tahbmi.hirq(15 downto 1); - vabufi.data(79) := r.thwrite; - vabufi.data(78 downto 77) := r.thtrans; - vabufi.data(76 downto 74) := r.thsize; - vabufi.data(73 downto 71) := r.thburst; - vabufi.data(70 downto 67) := r.thmaster; - vabufi.data(66) := r.thmastlock; - vabufi.data(65 downto 64) := tahbmi.hresp; + vabufi.data(94 downto 80) := tahbmi.hirq(15 downto 1); + vabufi.data(79) := r.thwrite; + vabufi.data(78 downto 77) := r.thtrans; + vabufi.data(76 downto 74) := r.thsize; + vabufi.data(73 downto 71) := r.thburst; + vabufi.data(70 downto 67) := r.thmaster; + vabufi.data(66) := r.thmastlock; + vabufi.data(65 downto 64) := tahbmi.hresp; if r.thwrite = '1' then - vabufi.data(63 downto 32) := tahbsi.hwdata(31 downto 0); + vabufi.data(63 downto 32) := wdata(31 downto 0); + vabufi.data(223 downto 128) := wdata(127 downto 32); else - vabufi.data(63 downto 32) := tahbmi.hrdata(31 downto 0); + vabufi.data(63 downto 32) := rdata(31 downto 0); + vabufi.data(223 downto 128) := rdata(127 downto 32); end if; vabufi.data(31 downto 0) := r.thaddr; else - vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4); - vabufi.data := ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0) & - ahbsi.hwdata(31 downto 0) & ahbsi.hwdata(31 downto 0); + if bwidth = 32 then + vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4); + else + vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+4 downto 5); + end if; + -- Note: HWDATA from register i/f + vabufi.data := hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata & hwdata; end if; -- write trace buffer @@ -259,7 +269,7 @@ begin if (r.ahbactive and tahbsi.hready) = '1' then if not (FILTEN and ahb_filt_hit(r, rf, tahbmi.hresp)) then v.aindex := aindex; - vabufi.enable := '1'; vabufi.write := "1111"; + vabufi.enable := '1'; vabufi.write := "11111111"; end if; end if; end if; @@ -268,7 +278,7 @@ begin if (r.dcnten = '1') and (r.ahbactive and tahbsi.hready) = '1' then if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then - v.enable := '0'; v.dcnten := '0'; + v.enable := '0'; v.dcnten := '0'; end if; v.delaycnt := r.delaycnt - 1; end if; @@ -286,7 +296,7 @@ begin -- AHB transfer parameters for register accesses if (ahbsi.hready = '1' ) then - v.haddr := ahbsi.haddr(TBUFABITS+3 downto 2); v.hwrite := ahbsi.hwrite; + v.haddr := ahbsi.haddr(TBUFABITS+4 downto 2); v.hwrite := ahbsi.hwrite; v.regacc := ahbsi.haddr(16); v.hsel := ahbsi.htrans(1) and ahbsi.hsel(hindex); end if; @@ -294,24 +304,25 @@ begin -- AHB slave access to DSU registers and trace buffers if (r.hsel and not r.hready) = '1' then - if r.regacc = '0' then -- registers + if r.regacc = '0' then -- registers v.hready := '1'; case regaddr is when "000" => - regsd((TBUFABITS + 15) downto 16) := r.delaycnt; + regsd((TBUFABITS + 15) downto 16) := r.delaycnt; if ntrace /= 1 then regsd(15) := '1'; regsd(log2(ntrace)+12 downto 12) := vb.bsel; end if; + regsd(7 downto 6) := conv_std_logic_vector(log2(bwidth/32), 2); if FILTEN then regsd(5) := rf.rf; regsd(4) := rf.af; regsd(3) := rf.fr; regsd(2) := rf.fw; end if; - regsd(1 downto 0) := r.dcnten & r.enable; - if r.hwrite = '1' then - v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16); + regsd(1 downto 0) := r.dcnten & r.enable; + if r.hwrite = '1' then + v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16); if ntrace /= 1 then vb.bsel := ahbsi.hwdata(log2(ntrace)+12 downto 12); end if; @@ -321,19 +332,19 @@ begin vf.fr := ahbsi.hwdata(3); vf.fw := ahbsi.hwdata(2); end if; - v.dcnten := ahbsi.hwdata(1); - v.enable := ahbsi.hwdata(0); - end if; + v.dcnten := ahbsi.hwdata(1); + v.enable := ahbsi.hwdata(0); + end if; when "001" => - regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex; - if r.hwrite = '1' then - v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0); - end if; + regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex; + if r.hwrite = '1' then + v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0); + end if; when "010" => - regsd((TIMEBITS - 1) downto 0) := r.timer; - if r.hwrite = '1' then - v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0); - end if; + regsd((TIMEBITS - 1) downto 0) := r.timer; + if r.hwrite = '1' then + v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0); + end if; when "011" => if FILTEN then regsd(31 downto 0) := rf.smask & rf.mmask; @@ -343,57 +354,105 @@ begin end if; end if; when "100" => - regsd(31 downto 2) := r.tbreg1.addr; - if r.hwrite = '1' then - v.tbreg1.addr := ahbsi.hwdata(31 downto 2); - end if; + regsd(31 downto 2) := r.tbreg1.addr; + if r.hwrite = '1' then + v.tbreg1.addr := ahbsi.hwdata(31 downto 2); + end if; when "101" => - regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write; - if r.hwrite = '1' then - v.tbreg1.mask := ahbsi.hwdata(31 downto 2); - v.tbreg1.read := ahbsi.hwdata(1); - v.tbreg1.write := ahbsi.hwdata(0); - end if; + regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write; + if r.hwrite = '1' then + v.tbreg1.mask := ahbsi.hwdata(31 downto 2); + v.tbreg1.read := ahbsi.hwdata(1); + v.tbreg1.write := ahbsi.hwdata(0); + end if; when "110" => - regsd(31 downto 2) := r.tbreg2.addr; - if r.hwrite = '1' then - v.tbreg2.addr := ahbsi.hwdata(31 downto 2); - end if; + regsd(31 downto 2) := r.tbreg2.addr; + if r.hwrite = '1' then + v.tbreg2.addr := ahbsi.hwdata(31 downto 2); + end if; when others => - regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write; - if r.hwrite = '1' then - v.tbreg2.mask := ahbsi.hwdata(31 downto 2); - v.tbreg2.read := ahbsi.hwdata(1); - v.tbreg2.write := ahbsi.hwdata(0); - end if; - end case; - v.hrdata := regsd; - else -- read/write access to trace buffer + regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write; + if r.hwrite = '1' then + v.tbreg2.mask := ahbsi.hwdata(31 downto 2); + v.tbreg2.read := ahbsi.hwdata(1); + v.tbreg2.write := ahbsi.hwdata(0); + end if; + end case; + v.hrdata := regsd; + else -- read/write access to trace buffer if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if; vabufi.enable := not r.enable; - bufdata := tbo.data; - case tbaddr is - when "00" => - v.hrdata := bufdata(127 downto 96); - if r.hwrite = '1' then - vabufi.write(3) := vabufi.enable; - end if; - when "01" => - v.hrdata := bufdata(95 downto 64); - if r.hwrite = '1' then - vabufi.write(2) := vabufi.enable; - end if; - when "10" => - v.hrdata := bufdata(63 downto 32); - if r.hwrite = '1' then - vabufi.write(1) := vabufi.enable; - end if; + case regaddr is + when "000" => + v.hrdata := tbo.data(127 downto 96); + if r.hwrite = '1' then + vabufi.write(3) := vabufi.enable; + end if; + when "001" => + v.hrdata := tbo.data(95 downto 64); + if r.hwrite = '1' then + vabufi.write(2) := vabufi.enable; + end if; + when "010" => + v.hrdata := tbo.data(63 downto 32); + if r.hwrite = '1' then + vabufi.write(1) := vabufi.enable; + end if; + when "011" => + v.hrdata := tbo.data(31 downto 0); + if r.hwrite = '1' then + vabufi.write(0) := vabufi.enable; + end if; + when "100" => + if bwidth > 32 then + v.hrdata := tbo.data(159 downto 128); + if r.hwrite = '1' then + vabufi.write(7) := vabufi.enable; + end if; + else + v.hrdata := tbo.data(127 downto 96); + if r.hwrite = '1' then + vabufi.write(3) := vabufi.enable; + end if; + end if; + when "101" => + if bwidth > 32 then + if bwidth > 64 then + v.hrdata := tbo.data(223 downto 192); + if r.hwrite = '1' then + vabufi.write(6) := vabufi.enable; + end if; + else v.hrdata := zero32; end if; + else + v.hrdata := tbo.data(95 downto 64); + if r.hwrite = '1' then + vabufi.write(2) := vabufi.enable; + end if; + end if; + when "110" => + if bwidth > 32 then + if bwidth > 64 then + v.hrdata := tbo.data(191 downto 160); + if r.hwrite = '1' then + vabufi.write(5) := vabufi.enable; + end if; + else v.hrdata := zero32; end if; + else + v.hrdata := tbo.data(63 downto 32); + if r.hwrite = '1' then + vabufi.write(1) := vabufi.enable; + end if; + end if; when others => - v.hrdata := bufdata(31 downto 0); - if r.hwrite = '1' then - vabufi.write(0) := vabufi.enable; - end if; - end case; + if bwidth > 32 then + v.hrdata := zero32; + else + v.hrdata := tbo.data(31 downto 0); + if r.hwrite = '1' then + vabufi.write(0) := vabufi.enable; + end if; + end if; + end case; end if; end if; @@ -452,12 +511,23 @@ begin end generate; enable <= tbi.enable & tbi.enable; - mem0 : for i in 0 to 1 generate + mem32 : for i in 0 to 1 generate ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS) port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)), tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2)); end generate; + mem64 : if bwidth > 32 generate -- extra data buffer for 64-bit bus + ram0 : syncram generic map (tech => tech, abits => TBUFABITS, dbits => 32) + port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+31) downto 128), + tbo.data((128+31) downto 128), tbi.enable, tbi.write(7)); + end generate; + mem128 : if bwidth > 64 generate -- extra data buffer for 128-bit bus + ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS) + port map ( clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data((128+95) downto (128+32)), + tbo.data((128+95) downto (128+32)), enable, tbi.write(6 downto 5)); + end generate; + -- pragma translate_off bootmsg : report_version generic map ("ahbtrace" & tost(hindex) & diff --git a/lib/gaisler/misc/apbps2.vhd b/lib/gaisler/misc/apbps2.vhd index 9aa085c7..c0eadc6d 100644 --- a/lib/gaisler/misc/apbps2.vhd +++ b/lib/gaisler/misc/apbps2.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/apbvga.vhd b/lib/gaisler/misc/apbvga.vhd index 53230e64..a1863e63 100644 --- a/lib/gaisler/misc/apbvga.vhd +++ b/lib/gaisler/misc/apbvga.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/charrom.vhd b/lib/gaisler/misc/charrom.vhd index 028b1ae7..1a70aabc 100644 --- a/lib/gaisler/misc/charrom.vhd +++ b/lib/gaisler/misc/charrom.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/charrom_package.vhd b/lib/gaisler/misc/charrom_package.vhd index 5d727957..2302a4b7 100644 --- a/lib/gaisler/misc/charrom_package.vhd +++ b/lib/gaisler/misc/charrom_package.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/gptimer.vhd b/lib/gaisler/misc/gptimer.vhd index b1478e0c..5602422a 100644 --- a/lib/gaisler/misc/gptimer.vhd +++ b/lib/gaisler/misc/gptimer.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -23,6 +23,19 @@ -- Description: This unit implemets a set of general-purpose timers with a -- common prescaler. Then number of timers and the width of -- the timers is propgrammable through generics +-- +-- Revision 1 of this core merges functionality of the GRTIMET unit: +-- +-- This unit also implements the use of an external clock source for the +-- timers. +-- +-- This unit also implements a latching register for each timer, latching the +-- timer value on the occurence of an interrupt on the apbi.priq input. The +-- interrupt selection in possible via a mask register. +-- +-- This unit also implements loading of all timers on the event of a selected +-- incoming interrupt. +-- ------------------------------------------------------------------------------ library ieee; @@ -50,7 +63,10 @@ entity gptimer is ntimers : integer range 1 to 7 := 1; -- number of timers nbits : integer := 32; -- timer bits wdog : integer := 0; - ewdogen : integer := 0 + ewdogen : integer := 0; + glatch : integer := 0; + gextclk : integer := 0; + gset : integer := 0 ); port ( rst : in std_ulogic; @@ -64,10 +80,10 @@ end; architecture rtl of gptimer is -constant REVISION : integer := 0; +constant REVISION : integer := 1; constant pconfig : apb_config_type := ( - 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq), + 0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPTIMER, 0, REVISION, pirq), 1 => apb_iobar(paddr, pmask)); type timer_reg is record @@ -80,6 +96,7 @@ type timer_reg is record chain : std_ulogic; -- chain with previous timer value : std_logic_vector(nbits-1 downto 0); reload : std_logic_vector(nbits-1 downto 0); + latch : std_logic_vector(glatch*(nbits-1) downto 0); end record; type timer_reg_vector is array (Natural range <> ) of timer_reg; @@ -92,11 +109,25 @@ type registers is record tick : std_ulogic; tsel : integer range 0 to ntimers; timers : timer_reg_vector(1 to ntimers); - dishlt : std_ulogic; - wdogn : std_ulogic; - wdog : std_ulogic; + dishlt : std_ulogic; + wdogn : std_ulogic; + wdog : std_ulogic; + wdogdis : std_ulogic; + wdognmi : std_ulogic; end record; +type registers2 is record + latchsel : std_logic_vector(NAHBIRQ-1 downto 0); + latchen : std_ulogic; + latchdel : std_ulogic; + extclken : std_ulogic; + extclk : std_logic_vector(2 downto 0); + seten : std_ulogic; + setdel : std_ulogic; +end record; + +constant NMI : integer := 15; + constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1; function RESVAL_FUNC return registers is variable vres : registers; @@ -115,6 +146,7 @@ begin vres.timers(i).chain := '0'; vres.timers(i).value := (others => '0'); vres.timers(i).reload := (others => '0'); + vres.timers(i).latch := (others => '0'); end loop; if wdog /= 0 then vres.timers(ntimers).enable := '1'; -- May be overriden by ewdogen @@ -125,15 +157,26 @@ begin vres.dishlt := '0'; vres.wdogn := '1'; vres.wdog := '0'; + vres.wdogdis := '0'; + vres.wdognmi := '0'; return vres; end function RESVAL_FUNC; constant RESVAL : registers := RESVAL_FUNC; +constant RESVAL2 : registers2 := ( + latchsel => (others => '0'), + latchen => '0', + latchdel => '0', + extclken => '0', + extclk => (others => '0'), + seten => '0', + setdel => '0'); signal r, rin : registers; +signal r2, rin2 : registers2; begin - comb : process(rst, r, apbi, gpti) + comb : process(rst, r, r2, apbi, gpti) variable scaler : std_logic_vector(sbits downto 0); variable readdata, timer1 : std_logic_vector(31 downto 0); variable res, addin : std_logic_vector(nbits-1 downto 0); @@ -143,26 +186,37 @@ begin variable xirq : std_logic_vector(NAHBIRQ-1 downto 0); variable nirq : std_logic_vector(0 to ntimers-1); variable tick : std_logic_vector(1 to 7); + variable latch : std_ulogic; + variable v2 : registers2; begin - v := r; v.tick := '0'; tick := (others => '0'); + v := r; v2 := r2; v.tick := '0'; tick := (others => '0'); latch := '0'; vtimers(0) := ('0', '0', '0', '0', '0', '0', '0', - zero32(nbits-1 downto 0), zero32(nbits-1 downto 0) ); + zero32(nbits-1 downto 0), zero32(nbits-1 downto 0), + zero32(glatch*(nbits-1) downto 0)); vtimers(1 to ntimers) := r.timers; xirq := (others => '0'); for i in 1 to ntimers loop v.timers(i).irq := '0'; v.timers(i).load := '0'; tick(i) := r.timers(i).irq; end loop; - v.wdogn := not r.timers(ntimers).irqpen; v.wdog := r.timers(ntimers).irqpen; + v.wdog := r.timers(ntimers).irqpen and not r.wdogdis; + v.wdogn := not v.wdog; -- scaler operation scaler := ('0' & r.scaler) - 1; -- decrement scaler - if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode - if (scaler(sbits) = '1') then - v.scaler := r.reload; v.tick := '1'; -- reload scaler - else v.scaler := scaler(sbits-1 downto 0); end if; + if gextclk = 1 then -- optional external timer clock + v2.extclk := r2.extclk(1 downto 0) & gpti.extclk; + end if; + + if ((gextclk=0) or (gextclk=1 and r2.extclken='0') or + (gextclk=1 and r2.extclken='1' and r2.extclk(2 downto 1) = "01")) then + if (not gpti.dhalt or r.dishlt) = '1' then -- halt timers in debug mode + if (scaler(sbits) = '1') then + v.scaler := r.reload; v.tick := '1'; -- reload scaler + else v.scaler := scaler(sbits-1 downto 0); end if; + end if; end if; -- timer operation @@ -205,6 +259,29 @@ begin end if; end loop; +-- timer external set + if gset = 1 then + if NAHBIRQ <= 32 then + for i in NAHBIRQ-1 downto 0 loop + latch := latch or (v2.latchsel(i) and apbi.pirq(i)); + end loop; + else + for i in 31 downto 0 loop + latch := latch or (v2.latchsel(i) and apbi.pirq(i)); + end loop; + end if; + if (latch='1' and r2.seten='1' and r.tsel = 0) or + (r2.setdel = '1' and r2.seten='1' and r.tsel = 0) then + for i in 1 to ntimers loop + v.timers(i).value := r.timers(i).reload; + end loop; + v2.seten := '0'; + v2.setdel := '0'; + elsif latch='1' and r2.seten='1' and r.tsel /= 0 then + v2.setdel := '1'; + end if; + end if; + if sepirq /= 0 then for i in 1 to ntimers loop xirq(i-1+pirq) := r.timers(i).irq and r.timers(i).irqen; @@ -214,6 +291,11 @@ begin xirq(pirq) := xirq(pirq) or (r.timers(i).irq and r.timers(i).irqen); end loop; end if; + if wdog /= 0 then + if (r.wdognmi and r.timers(ntimers).irq and r.timers(ntimers).irqen) = '1' then + xirq(NMI) := '1'; + end if; + end if; -- read registers @@ -226,16 +308,39 @@ begin readdata(7 downto 3) := conv_std_logic_vector(pirq, 5) ; if (sepirq /= 0) then readdata(8) := '1'; end if; readdata(9) := r.dishlt; + if gextclk = 1 then readdata(10) := r2.extclken; end if; + if glatch = 1 then readdata(11) := r2.latchen; end if; + if gset = 1 then readdata(12) := r2.seten; end if; + when "00011" => + if glatch = 1 then + if NAHBIRQ <= 32 then + for i in NAHBIRQ-1 downto 0 loop + readdata(i) := r2.latchsel(i); + end loop; + else + for i in 31 downto 0 loop + readdata(i) := r2.latchsel(i); + end loop; + end if; + end if; when others => for i in 1 to ntimers loop if conv_integer(apbi.paddr(6 downto 4)) = i then case apbi.paddr(3 downto 2) is when "00" => readdata(nbits-1 downto 0) := r.timers(i).value; when "01" => readdata(nbits-1 downto 0) := r.timers(i).reload; - when "10" => readdata(6 downto 0) := - gpti.dhalt & r.timers(i).chain & - r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load & - r.timers(i).restart & r.timers(i).enable; + when "10" => + if wdog /= 0 and i = ntimers then + readdata(8 downto 7) := r.wdogdis & r.wdognmi; + end if; + readdata(6 downto 0) := + gpti.dhalt & r.timers(i).chain & + r.timers(i).irqpen & r.timers(i).irqen & r.timers(i).load & + r.timers(i).restart & r.timers(i).enable; + when "11" => + if glatch = 1 then + readdata(glatch*(nbits-1) downto 0) := r.timers(i).latch; + end if; when others => end case; end if; @@ -250,13 +355,32 @@ begin when "00001" => v.reload := apbi.pwdata(sbits-1 downto 0); v.scaler := apbi.pwdata(sbits-1 downto 0); when "00010" => v.dishlt := apbi.pwdata(9); + if gextclk = 1 then v2.extclken := apbi.pwdata(10); end if; + if glatch = 1 then v2.latchen := apbi.pwdata(11); end if; + if gset = 1 then v2.seten := apbi.pwdata(12); end if; + when "00011" => + if glatch=1 then + if NAHBIRQ <= 32 then + for i in NAHBIRQ-1 downto 0 loop + v2.latchsel(i) := apbi.pwdata(i); + end loop; + else + for i in 31 downto 0 loop + v2.latchsel(i) := apbi.pwdata(i); + end loop; + end if; + end if; when others => for i in 1 to ntimers loop if conv_integer(apbi.paddr(6 downto 4)) = i then case apbi.paddr(3 downto 2) is when "00" => v.timers(i).value := apbi.pwdata(nbits-1 downto 0); when "01" => v.timers(i).reload := apbi.pwdata(nbits-1 downto 0); - when "10" => v.timers(i).chain := apbi.pwdata(5); + when "10" => if wdog /= 0 and i = ntimers then + v.wdogdis := apbi.pwdata(8); + v.wdognmi := apbi.pwdata(7); + end if; + v.timers(i).chain := apbi.pwdata(5); v.timers(i).irqpen := v.timers(i).irqpen and not apbi.pwdata(4); v.timers(i).irqen := apbi.pwdata(3); v.timers(i).load := apbi.pwdata(2); @@ -269,6 +393,29 @@ begin end case; end if; +-- timer latches + if glatch=1 then + latch := '0'; + if NAHBIRQ <= 32 then + for i in NAHBIRQ-1 downto 0 loop + latch := latch or (v2.latchsel(i) and apbi.pirq(i)); + end loop; + else + for i in 31 downto 0 loop + latch := latch or (v2.latchsel(i) and apbi.pirq(i)); + end loop; + end if; + if ((latch='1' and r2.latchen='1' and r.tsel = 0) or + (r2.latchdel = '1' and r2.latchen='1' and r.tsel = 0)) then + for i in 1 to ntimers loop + v.timers(i).latch := r.timers(i).value(glatch*(nbits-1) downto 0); + end loop; + v2.latchen := '0'; + v2.latchdel := '0'; + elsif latch='1' and r2.latchen='1' and r.tsel /= 0 then + v2.latchdel := '1'; + end if; + end if; -- reset operation @@ -277,6 +424,7 @@ begin v.timers(i).enable := RESVAL.timers(i).enable; v.timers(i).irqen := RESVAL.timers(i).irqen; v.timers(i).irqpen := RESVAL.timers(i).irqpen; + v.timers(i).irq := RESVAL.timers(i).irq; end loop; v.scaler := RESVAL.scaler; v.reload := RESVAL.reload; v.tsel := RESVAL.tsel; v.dishlt := RESVAL.dishlt; @@ -291,11 +439,29 @@ begin v.timers(ntimers).irqpen := RESVAL.timers(ntimers).irqpen; v.timers(ntimers).restart := RESVAL.timers(ntimers).restart; end if; + v.wdogdis := RESVAL.wdogdis; v.wdognmi := RESVAL.wdognmi; + if glatch = 1 then + for i in 1 to ntimers loop v.timers(i).latch := RESVAL.timers(i).latch; end loop; + v2.latchen := RESVAL2.latchen; v2.latchdel := RESVAL2.latchdel; + v2.latchsel := RESVAL2.latchsel; + end if; + if gextclk = 1 then + v2.extclken := RESVAL2.extclken; + v2.extclk := RESVAL2.extclk; + end if; + if gset = 1 then v2.seten := RESVAL2.seten; v2.setdel := RESVAL2.setdel; end if; end if; - + if wdog = 0 then v.wdogdis := '0'; v.wdognmi := '0'; end if; + if glatch = 0 then + for i in 1 to ntimers loop v.timers(i).latch := (others => '0'); end loop; + v2.latchen := '0'; v2.latchdel := '0'; v2.latchsel := (others => '0'); + end if; + if gextclk = 0 then v2.extclken := '0'; v2.extclk := (others => '0'); end if; + if gset = 0 then v2.seten := '0'; v2.setdel := '0'; end if; + timer1 := (others => '0'); timer1(nbits-1 downto 0) := r.timers(1).value; - rin <= v; + rin <= v; rin2 <= v2; apbo.prdata <= readdata; -- drive apb read bus apbo.pirq <= xirq; apbo.pindex <= pindex; @@ -313,9 +479,9 @@ begin regs : process(clk) begin if rising_edge(clk) then - r <= rin; + r <= rin; r2 <= rin2; if RESET_ALL and rst = '0' then - r <= RESVAL; + r <= RESVAL; r2 <= RESVAL2; if wdog /= 0 and ewdogen /= 0 then r.timers(ntimers).enable <= gpti.wdogen; end if; @@ -328,7 +494,7 @@ begin -- pragma translate_off bootmsg : report_version generic map ("gptimer" & tost(pindex) & - ": GR Timer Unit rev " & tost(REVISION) & + ": Timer Unit rev " & tost(REVISION) & ", " & tost(sbits) & "-bit scaler, " & tost(ntimers) & " " & tost(nbits) & "-bit timers" & ", irq " & tost(pirq)); -- pragma translate_on diff --git a/lib/gaisler/misc/gracectrl.vhd b/lib/gaisler/misc/gracectrl.vhd index a0603758..3d60ba97 100644 --- a/lib/gaisler/misc/gracectrl.vhd +++ b/lib/gaisler/misc/gracectrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/grgpio.vhd b/lib/gaisler/misc/grgpio.vhd index a54e4409..dbbf143b 100644 --- a/lib/gaisler/misc/grgpio.vhd +++ b/lib/gaisler/misc/grgpio.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/grgprbank.vhd b/lib/gaisler/misc/grgprbank.vhd index ea620915..7fe5af17 100644 --- a/lib/gaisler/misc/grgprbank.vhd +++ b/lib/gaisler/misc/grgprbank.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/grgpreg.vhd b/lib/gaisler/misc/grgpreg.vhd index cc83efdc..87801499 100644 --- a/lib/gaisler/misc/grgpreg.vhd +++ b/lib/gaisler/misc/grgpreg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/grsysmon.vhd b/lib/gaisler/misc/grsysmon.vhd index 0e1d26e1..fda75c60 100644 --- a/lib/gaisler/misc/grsysmon.vhd +++ b/lib/gaisler/misc/grsysmon.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/logan.vhd b/lib/gaisler/misc/logan.vhd index b3eb2c5f..8510bb03 100644 --- a/lib/gaisler/misc/logan.vhd +++ b/lib/gaisler/misc/logan.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/misc.vhd b/lib/gaisler/misc/misc.vhd index fab9c15c..ab30bc2e 100644 --- a/lib/gaisler/misc/misc.vhd +++ b/lib/gaisler/misc/misc.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -84,7 +84,10 @@ package misc is ntimers : integer range 1 to 7 := 1; -- number of timers nbits : integer := 32; -- timer bits wdog : integer := 0; - ewdogen : integer := 0 + ewdogen : integer := 0; + glatch : integer := 0; + gextclk : integer := 0; + gset : integer := 0 ); port ( rst : in std_ulogic; @@ -199,6 +202,7 @@ package misc is tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; + bwidth : integer := 32; ahbfilt : integer := 0); port ( rst : in std_ulogic; @@ -217,6 +221,7 @@ package misc is tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; + bwidth : integer := 32; ahbfilt : integer := 0); port ( rst : in std_ulogic; @@ -236,6 +241,7 @@ package misc is tech : integer := DEFMEMTECH; irq : integer := 0; kbytes : integer := 1; + bwidth : integer := 32; ahbfilt : integer := 0; ntrace : integer range 1 to 8 := 1); port ( diff --git a/lib/gaisler/misc/rstgen.vhd b/lib/gaisler/misc/rstgen.vhd index a8677eed..212a8428 100644 --- a/lib/gaisler/misc/rstgen.vhd +++ b/lib/gaisler/misc/rstgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/misc/svgactrl.vhd b/lib/gaisler/misc/svgactrl.vhd index f6930f8d..8fb43ed0 100644 --- a/lib/gaisler/misc/svgactrl.vhd +++ b/lib/gaisler/misc/svgactrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/net/edcl.in b/lib/gaisler/net/edcl.in index f0590150..7fa4aa15 100644 --- a/lib/gaisler/net/edcl.in +++ b/lib/gaisler/net/edcl.in @@ -12,9 +12,9 @@ if [ "$CONFIG_GRETH_ENABLE" = "y" ]; then hex 'LSB 16 bits of IP address (hex) ' CONFIG_DSU_IPLSB 0033 hex 'MSB 24 bits of ethern number (hex) ' CONFIG_DSU_ETHMSB 020000 hex 'LSB 24 bits of ethern number (hex) ' CONFIG_DSU_ETHLSB 000000 - if [ "$CONFIG_GRETH_GIGA" = "n" ]; then - bool 'Programmable 4-bit LSB of MAC/IP address' CONFIG_DSU_ETH_PROG - bool 'EDCL disable pin ' CONFIG_DSU_ETH_DIS + bool 'Programmable 4-bit LSB of MAC/IP address' CONFIG_DSU_ETH_PROG + if [ "$CONFIG_DSU_ETH_PROG" = "y" ]; then + bool 'EDCL disable pin ' CONFIG_DSU_ETH_DIS fi fi fi diff --git a/lib/gaisler/net/net.vhd b/lib/gaisler/net/net.vhd index 0dd1c10b..9c3dc0a5 100644 --- a/lib/gaisler/net/net.vhd +++ b/lib/gaisler/net/net.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -34,12 +34,15 @@ package net is gtx_clk : std_ulogic; rmii_clk : std_ulogic; tx_clk : std_ulogic; + tx_clk_90 : std_ulogic; + tx_dv : std_ulogic; rx_clk : std_ulogic; rxd : std_logic_vector(7 downto 0); rx_dv : std_ulogic; rx_er : std_ulogic; rx_col : std_ulogic; rx_crs : std_ulogic; + rx_en : std_ulogic; mdio_i : std_ulogic; mdint : std_ulogic; phyrstaddr : std_logic_vector(4 downto 0); @@ -49,7 +52,7 @@ package net is end record; constant eth_in_none : eth_in_type := - ('0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', + ('0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'), '0', '0'); type eth_out_type is record @@ -136,7 +139,8 @@ package net is multicast : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer := 1500 + maxsize : integer := 1500; + gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -185,7 +189,8 @@ package net is edclsepahb : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; mdiohold : integer := 1; - maxsize : integer := 1500 + maxsize : integer := 1500; + gmiimode : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -234,7 +239,9 @@ package net is multicast : integer range 0 to 1 := 0; edclsepahb : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - mdiohold : integer := 1); + mdiohold : integer := 1; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -280,7 +287,9 @@ package net is enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - mdiohold : integer := 1); + mdiohold : integer := 1; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -328,7 +337,9 @@ package net is enable_mdint : integer range 0 to 1 := 0; multicast : integer range 0 to 1 := 0; ramdebug : integer range 0 to 2 := 0; - mdiohold : integer := 1); + mdiohold : integer := 1; + gmiimode : integer range 0 to 1 := 0 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -343,18 +354,19 @@ package net is component rgmii is generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - tech : integer := 0; - gmii : integer := 0; - extclk : integer := 0; - clkdiv2 : integer := 0; - debugmem : integer := 0 + pindex : integer := 0; + paddr : integer := 0; + pmask : integer := 16#fff#; + tech : integer := 0; + gmii : integer := 0; + debugmem : integer := 0; + abits : integer := 8; + no_clk_mux : integer := 0; + pirq : integer := 0; + use90degtxclk : integer := 0 ); port ( rstn : in std_ulogic; - clk_tx_g : in std_ulogic; gmiii : out eth_in_type; gmiio : in eth_out_type; rgmiii : in eth_in_type; @@ -367,4 +379,57 @@ package net is ); end component; + component sgmii is + generic ( + fabtech : integer := 0; + phy_addr : integer := 0; + mode : integer := 0 -- unused + ); + port ( + clk_125 : in std_logic; + rst_125 : in std_logic; + + ser_rx_p : in std_logic; + ser_tx_p : out std_logic; + + txd : in std_logic_vector(7 downto 0); + tx_en : in std_logic; + tx_er : in std_logic; + tx_clk : out std_logic; + + rxd : out std_logic_vector(7 downto 0); + rx_dv : out std_logic; + rx_er : out std_logic; + rx_col : out std_logic; + rx_crs : out std_logic; + rx_clk : out std_logic; + + -- optional MDIO interface to PCS + mdc : in std_logic; + mdio_o : in std_logic := '0'; + mdio_oe : in std_logic := '1'; + mdio_i : out std_logic + ); + end component ; + + component comma_detect is + port ( + clk : in std_logic; + rstn : in std_logic; + indata : in std_logic_vector(9 downto 0); + bitslip : out std_logic + ); + end component; + + component elastic_buffer is + port ( + wr_clk : in std_logic; + wr_rst : in std_logic; + wr_data : in std_logic_vector(9 downto 0); + rd_clk : in std_logic; + rd_rst : in std_logic; + rd_data : out std_logic_vector(9 downto 0) + ) ; + end component ; + end; diff --git a/lib/gaisler/pci/grpci1/dmactrl.vhd b/lib/gaisler/pci/grpci1/dmactrl.vhd index cf0d16f9..84daebb8 100644 --- a/lib/gaisler/pci/grpci1/dmactrl.vhd +++ b/lib/gaisler/pci/grpci1/dmactrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/grpci1/pci_mt.vhd b/lib/gaisler/pci/grpci1/pci_mt.vhd index faf3204e..03e989a6 100644 --- a/lib/gaisler/pci/grpci1/pci_mt.vhd +++ b/lib/gaisler/pci/grpci1/pci_mt.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/grpci1/pci_mtf.vhd b/lib/gaisler/pci/grpci1/pci_mtf.vhd index a948eed1..77708f98 100644 --- a/lib/gaisler/pci/grpci1/pci_mtf.vhd +++ b/lib/gaisler/pci/grpci1/pci_mtf.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/grpci1/pci_target.vhd b/lib/gaisler/pci/grpci1/pci_target.vhd index ff5ffa8c..3410d670 100644 --- a/lib/gaisler/pci/grpci1/pci_target.vhd +++ b/lib/gaisler/pci/grpci1/pci_target.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/grpci1/pciahbmst.vhd b/lib/gaisler/pci/grpci1/pciahbmst.vhd index 066f1730..a838e51e 100644 --- a/lib/gaisler/pci/grpci1/pciahbmst.vhd +++ b/lib/gaisler/pci/grpci1/pciahbmst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/grpci1/pcidma.vhd b/lib/gaisler/pci/grpci1/pcidma.vhd index ec32a226..4da71eeb 100644 --- a/lib/gaisler/pci/grpci1/pcidma.vhd +++ b/lib/gaisler/pci/grpci1/pcidma.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/grpci1/pcilib.vhd b/lib/gaisler/pci/grpci1/pcilib.vhd index 4adcf3e2..70a0f2cd 100644 --- a/lib/gaisler/pci/grpci1/pcilib.vhd +++ b/lib/gaisler/pci/grpci1/pcilib.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/pci.vhd b/lib/gaisler/pci/pci.vhd index 2e0a6114..14ec04ab 100644 --- a/lib/gaisler/pci/pci.vhd +++ b/lib/gaisler/pci/pci.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -247,7 +247,8 @@ component pcipads drivereset : integer := 0; constidsel : integer := 0; level : integer := pci33; - voltage : integer := x33v + voltage : integer := x33v; + nolock : integer := 0 ); port ( pci_rst : inout std_logic; diff --git a/lib/gaisler/pci/pcipads.vhd b/lib/gaisler/pci/pcipads.vhd index 1de1005b..93390170 100644 --- a/lib/gaisler/pci/pcipads.vhd +++ b/lib/gaisler/pci/pcipads.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -44,7 +44,8 @@ entity pcipads is drivereset : integer := 0; -- Drive PCI rst with outpad constidsel : integer := 0; -- pci_idsel is tied to local constant level : integer := pci33; -- input/output level - voltage : integer := x33v -- input/output voltage + voltage : integer := x33v; -- input/output voltage + nolock : integer := 0 ); port ( pci_rst : inout std_logic; @@ -131,9 +132,16 @@ begin pcii.pci66 <= '0'; end generate; - pad_pci_lock : iopad generic map (tech => padtech, level => level, - voltage => voltage, oepol => oepol) - port map (pci_lock, pcio.lock, pcio.locken, pcii.lock); + dolock : if nolock = 0 generate + pad_pci_lock : iopad + generic map (tech => padtech, level => level, + voltage => voltage, oepol => oepol) + port map (pci_lock, pcio.lock, pcio.locken, pcii.lock); + end generate; + donolock : if nolock = 1 generate + pcii.lock <= pci_lock; + end generate; + pad_pci_ad : iopadvv generic map (tech => padtech, level => level, voltage => voltage, width => 32, oepol => oepol) diff --git a/lib/gaisler/pci/pcitrace/pcitrace.vhd b/lib/gaisler/pci/pcitrace/pcitrace.vhd index 7b1f3328..e2b7f461 100644 --- a/lib/gaisler/pci/pcitrace/pcitrace.vhd +++ b/lib/gaisler/pci/pcitrace/pcitrace.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/ptf/pt_pci_arb.vhd b/lib/gaisler/pci/ptf/pt_pci_arb.vhd index 0470b6c2..3e399dc4 100644 --- a/lib/gaisler/pci/ptf/pt_pci_arb.vhd +++ b/lib/gaisler/pci/ptf/pt_pci_arb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/ptf/pt_pci_master.vhd b/lib/gaisler/pci/ptf/pt_pci_master.vhd index 0cf9110d..1b72d097 100644 --- a/lib/gaisler/pci/ptf/pt_pci_master.vhd +++ b/lib/gaisler/pci/ptf/pt_pci_master.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/ptf/pt_pci_monitor.vhd b/lib/gaisler/pci/ptf/pt_pci_monitor.vhd index 4aa32c79..33a1a1d6 100644 --- a/lib/gaisler/pci/ptf/pt_pci_monitor.vhd +++ b/lib/gaisler/pci/ptf/pt_pci_monitor.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/ptf/pt_pci_target.vhd b/lib/gaisler/pci/ptf/pt_pci_target.vhd index 442a325f..8c689b69 100644 --- a/lib/gaisler/pci/ptf/pt_pci_target.vhd +++ b/lib/gaisler/pci/ptf/pt_pci_target.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/pci/ptf/pt_pkg.vhd b/lib/gaisler/pci/ptf/pt_pkg.vhd index 1a2764cb..db800299 100644 --- a/lib/gaisler/pci/ptf/pt_pkg.vhd +++ b/lib/gaisler/pci/ptf/pt_pkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/ahbrep.vhd b/lib/gaisler/sim/ahbrep.vhd index 6a283c03..79ab974d 100644 --- a/lib/gaisler/sim/ahbrep.vhd +++ b/lib/gaisler/sim/ahbrep.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/ddr2ram.vhd b/lib/gaisler/sim/ddr2ram.vhd new file mode 100644 index 00000000..8a8d98a0 --- /dev/null +++ b/lib/gaisler/sim/ddr2ram.vhd @@ -0,0 +1,563 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: ddr2ram +-- File: ddr2ram.vhd +-- Author: Magnus Hjorth, Aeroflex Gaisler +-- Description: Generic simulation model of DDR2 SDRAM (JESD79-2C) +------------------------------------------------------------------------------ + +--pragma translate_off + +use std.textio.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library grlib; +use grlib.stdio.hread; +use grlib.stdlib.all; + +entity ddr2ram is + generic ( + width: integer := 32; + abits: integer range 13 to 16 := 13; + babits: integer range 2 to 3 := 3; + colbits: integer range 9 to 11 := 9; + rowbits: integer range 1 to 16 := 13; + implbanks: integer range 1 to 8 := 1; + fname: string; + lddelay: time := (0 ns); + -- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C + -- 9:800+ (MT47H-25E) + speedbin: integer range 0 to 9 := 0; + density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip + pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD) + ); + port ( + ck: in std_ulogic; + ckn: in std_ulogic; + cke: in std_ulogic; + csn: in std_ulogic; + odt: in std_ulogic; + rasn: in std_ulogic; + casn: in std_ulogic; + wen: in std_ulogic; + dm: in std_logic_vector(width/8-1 downto 0); + ba: in std_logic_vector(babits-1 downto 0); + a: in std_logic_vector(abits-1 downto 0); + dq: inout std_logic_vector(width-1 downto 0); + dqs: inout std_logic_vector(width/8-1 downto 0); + dqsn: inout std_logic_vector(width/8-1 downto 0) + ); +end; + +architecture sim of ddr2ram is + + type moderegs is record + -- Mode register (0) + pd: std_ulogic; + wr: std_logic_vector(2 downto 0); + dllres: std_ulogic; + tm: std_ulogic; + caslat: std_logic_vector(2 downto 0); + bt: std_ulogic; + blen: std_logic_vector(2 downto 0); + -- Extended mode register 1 + qoff: std_ulogic; + rdqsen: std_ulogic; + dqsndis: std_ulogic; + ocdprog: std_logic_vector(2 downto 0); + al: std_logic_vector(2 downto 0); + rtt: std_logic_vector(1 downto 0); + ds: std_ulogic; + dlldis: std_ulogic; + -- Extended mode register 2 + srf: std_ulogic; + dccen: std_ulogic; + pasr: std_logic_vector(2 downto 0); + -- Extended mode register 3 + emr3: std_logic_vector(abits-1 downto 0); + end record; + + -- Mode registers as signal, useful for debugging + signal mr: moderegs; + + -- Handshaking between command and DQ/DQS processes + signal read_en, write_en: boolean := false; + signal read_data, write_data: std_logic_vector(2*width-1 downto 0); + signal write_mask: std_logic_vector(width/4-1 downto 0); + + signal initdone: boolean := false; + + -- Small delta-t to adjust calculations for jitter tol. + constant deltat: time := 50 ps; + + -- Timing parameters + constant tWR: time := 15 ns; + constant tMRD_ck: integer := 2; + constant tRTP: time := 7.5 ns; + type timetab is array (0 to 9) of time; + -- 400C 400B 533C 533B 667D 667C 800E 800D 800C MT-2.5E + constant tRAS : timetab := (45 ns, 40 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 45 ns, 40 ns); + constant tRP : timetab := (20 ns, 15 ns, 15 ns, 11.25 ns, 15 ns, 12 ns, 15 ns, 12.5 ns, 10 ns, 12.5 ns); + constant tRCD: timetab := tRP; + + type timetab2 is array(1 to 5) of time; + constant tRFC: timetab2 := (75 ns, 105 ns, 127.5 ns, 195 ns, 327.5 ns); + + type timetab3 is array(1 to 2) of time; + constant tRRD: timetab3 := (7.5 ns, 10 ns); + +begin + + ----------------------------------------------------------------------------- + -- Init sequence checker + ----------------------------------------------------------------------------- + initp: process + + variable cyctr: integer := 0; + + procedure checkcmd(crasn,ccasn,cwen: std_ulogic; + cba: std_logic_vector(1 downto 0); + ca: std_logic_vector(15 downto 0)) is + variable amatch: boolean; + begin + wait until rising_edge(ck); + cyctr := cyctr+1; + while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop + wait until rising_edge(ck); + cyctr := cyctr+1; + end loop; + amatch := true; + for x in a'range loop + if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if; + end loop; + assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and + (cba="--" or cba=ba(1 downto 0)) and amatch + report "Wrong command during init sequence" severity warning; + end checkcmd; + + variable t: time; + begin + initdone <= false; + -- Allow cke to be X or U for a while during sim start + if is_x(cke) then + wait until not is_x(cke); + end if; + assert cke='0' report "CKE not deasserted on power-up" severity warning; + wait until cke/='0' for 200 us; + assert cke='0' report "CKE raised with less than 200 us init delay" severity warning; + wait until cke/='0' and rising_edge(ck); + assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')); + t := now; + -- Precharge all + checkcmd('0','1','0',"--","-----1----------"); + assert (now-t) > 400 ns report "Less than 400 ns wait period after CKE high!" severity warning; + -- EMRS EMR2 + checkcmd('0','0','0',"10","----------------"); + -- EMRS EMR3 + checkcmd('0','0','0',"11","----------------"); + -- EMRS enable DLL + checkcmd('0','0','0',"01","000---000-------"); + -- MRS reset DLL + checkcmd('0','0','0',"00","000----1--------"); + cyctr := 0; + -- Precharge all + checkcmd('0','1','0',"--","-----1----------"); + -- 2 x auto refresh + checkcmd('0','0','1',"--","----------------"); + checkcmd('0','0','1',"--","----------------"); + -- MRS !reset DLL + checkcmd('0','0','0',"00","-------0--------"); + -- EMRS EMR1 OCD default, EMRS EMR1 exit OCD cal + -- (assume OCD impedance adjust not performed) + checkcmd('0','0','0',"01","------111-------"); + assert cyctr >= 200 report "Less than 200 cycles (" & tost(cyctr) & ") between DLL reset and OCD cal" severity warning; + checkcmd('0','0','0',"01","------000-------"); + initdone <= true; + wait; + end process; + + ----------------------------------------------------------------------------- + -- Command state machine + ----------------------------------------------------------------------------- + cmdp: process(ck) + subtype coldata is std_logic_vector(width-1 downto 0); + type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata; + variable memdata: coldata_arr; + + procedure load_srec is + file TCF : text open read_mode is fname; + variable L1: line; + variable CH : character; + variable rectype : std_logic_vector(3 downto 0); + variable recaddr : std_logic_vector(31 downto 0); + variable reclen : std_logic_vector(7 downto 0); + variable recdata : std_logic_vector(0 to 16*8-1); + variable col, coloffs, len: integer; + begin + L1:= new string'(""); + while not endfile(TCF) loop + readline(TCF,L1); + if (L1'length /= 0) then + while (not (L1'length=0)) and (L1(L1'left) = ' ') loop + std.textio.read(L1,CH); + end loop; + if L1'length > 0 then + read(L1, ch); + if (ch = 'S') or (ch = 's') then + hread(L1, rectype); + hread(L1, reclen); + len := to_integer(unsigned(reclen))-1; + recaddr := (others => '0'); + case rectype is + when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2; + when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3; + when "0011" => hread(L1, recaddr); len := len - 4; + when others => next; + end case; + hread(L1, recdata(0 to len*8-1)); + col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8)))); + coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0))); + while len > width/8 loop + assert coloffs=0; + memdata(col) := recdata(0 to width-1); + col := col+1; + len := len-width/8; + recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1); + end loop; + memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1); + end if; + end if; + end if; + end loop; + end load_srec; + + variable vmr: moderegs; + type bankstate is record + openrow: integer; + opentime: time; + closetime: time; + writetime: time; + readtime: time; + autopch: integer; + pchpush: boolean; + end record; + type bankstate_arr is array(natural range <>) of bankstate; + variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false)); + type int_arr is array(natural range <>) of integer; + type dataacc is record + r,w: boolean; + col: int_arr(0 to 1); + bank: integer; + end record; + type dataacc_arr is array(natural range <>) of dataacc; + variable accpipe: dataacc_arr(0 to 9); + variable cmd: std_logic_vector(2 downto 0); + variable bank: integer; + variable colv: unsigned(a'high-1 downto 0); + variable alow: unsigned(2 downto 0); + variable col: integer; + variable prev_re, re: time; + variable blen: integer; + variable lastref: time := 0 ns; + variable i, al, cl, wrap: integer; + variable b: boolean; + variable mrscount: integer := 0; + variable loaded: boolean := false; + + procedure checktime(got, exp: time; gt: boolean; req: string) is + begin + assert (got + deltat > exp and gt) or (got-deltat < exp and not gt) + report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps") + severity warning; + end checktime; + begin + if rising_edge(ck) then + -- Update pipe regs + prev_re := re; + re := now; + accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1); + accpipe(0).r:=false; accpipe(0).w:=false; + -- Parse MR fields + cmd := rasn & casn & wen; + if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat)); end if; + if cl<2 or cl>6 then cl:=0; end if; + if is_x(vmr.al) then al:=0; else al:=to_integer(unsigned(vmr.al)); end if; + if al>5 then al:=0; end if; + if is_x(vmr.wr) then wrap:=0; else wrap:=1+to_integer(unsigned(vmr.wr)); end if; + if wrap<2 or wrap>6 then wrap:=0; end if; + -- Checks for all-bank commands + if mrscount > 0 then + mrscount := mrscount-1; + assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning; + end if; + if cke='1' and csn='0' and cmd/="111" then + checktime(now-lastref, tRFC(density), true, "tRFC"); + end if; + -- Main command handler + if cke='1' and csn='0' then + case cmd is + when "111" => -- NOP + + when "011" => -- RAS + assert initdone report "Opening row before init sequence done!" severity warning; + bank := to_integer(unsigned(ba)); + assert banks(bank).openrow < 0 + report "Row already open" severity warning; + checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP"); + for x in 0 to 7 loop + checktime(now-banks(x).opentime, tRRD(pagesize), true, "tRRD"); + end loop; + banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0))); + banks(bank).opentime := now; + + when "101" | "100" => -- Read/Write + bank := to_integer(unsigned(ba)); + -- Get additive latency + i := to_integer(unsigned(vmr.al)); + assert banks(bank).openrow >= 0 + report "Row not open" severity error; + checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD"); + -- Allow interrupting read in case of middle of BL8 burst only + if (accpipe(3).r and accpipe(2).r and + not (accpipe(1).r or accpipe(1).w or accpipe(0).r or accpipe(0).w)) then + accpipe(3).r := false; + accpipe(2).r := false; + end if; + for x in 0 to 3 loop + assert not accpipe(x).r and not accpipe(x).w; + end loop; + if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if; + colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0))); + case vmr.blen is + when "010" => blen := 4; + when "011" => blen := 8; + when others => assert false report "Invalid burst length setting in MR!" severity error; + end case; + alow := unsigned(a(2 downto 0)); + for x in 0 to blen-1 loop + accpipe(3-x/2).bank := bank; + if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if; + if vmr.bt='0' then -- Sequential + colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x; + else -- Interleaved + colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen)); + end if; + col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) + + banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0)); + accpipe(3-x/2).col(x mod 2) := col; + end loop; + -- Auto precharge + if a(10)='1' then + if cmd(0)='1' then + banks(bank).autopch := al+blen/2; + else + banks(bank).autopch := cl+al-1+blen/2+wrap; + end if; + banks(bank).pchpush := true; + end if; + + when "110" => -- Reserved (Burst terminate on DDR1) + assert false report "Invalid command RAS=1 CAS=1 WE=0" severity warning; + + when "010" => -- Precharge + if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if; + for x in 3 downto 0 loop -- FIXME potential window which isn't checked if AL>0 + assert (not (accpipe(x).r or accpipe(x).w)) or (a(10)='0' and bank/=accpipe(x).bank) + report "Precharging bank with access in progress" + severity warning; + end loop; + for x in 0 to (2**babits)-1 loop + if a(10)='1' or ba=std_logic_vector(to_unsigned(x,babits)) then + assert banks(x).autopch<0 + report "Precharging bank that is auto-precharged!" severity note; + assert a(10)='1' or banks(x).openrow >= 0 + report "Precharging single bank that is in idle state!" severity note; + banks(x).autopch := 0; -- Handled below case statement + banks(x).pchpush := false; + end if; + end loop; + + + when "001" => -- Auto refresh + for x in 0 to 7 loop + assert banks(x).openrow < 0 + report "Bank in wrong state for auto refresh!" severity warning; + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + lastref := now; + + + when "000" => -- MRS + for x in 0 to 7 loop + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + bank := to_integer(unsigned(ba)); + case bank is + when 0 => + vmr.pd := a(12); + vmr.wr := a(11 downto 9); + vmr.dllres := a(8); + vmr.tm := a(7); + vmr.caslat := a(6 downto 4); + vmr.bt := a(3); + vmr.blen := a(2 downto 0); + when 1 => + vmr.qoff := a(12); + vmr.rdqsen := a(11); + vmr.dqsndis := a(10); + vmr.ocdprog := a(9 downto 7); + vmr.al := a(5 downto 3); + vmr.rtt := a(6) & a(2); + vmr.ds := a(1); + vmr.dlldis := a(0); + when 2 => + vmr.srf := a(7); + vmr.dccen := a(3); + vmr.pasr := a(2 downto 0); + when 3 => + vmr.emr3 := a; + when others => + assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning; + end case; + mrscount := tMRD_ck-1; + + when others => + assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning; + end case; + end if; + + -- Manual or auto precharge handling + for x in 0 to 7 loop + if banks(x).autopch=0 then + if banks(x).pchpush and (now-banks(x).opentime-deltat) < tRAS(speedbin) then + -- Auto delay auto-precharge to satisfy tRAS/tRC + banks(x).autopch := banks(x).autopch+1; + elsif banks(x).pchpush and (now-banks(x).readtime-deltat) < tRTP then + -- Auto delay auto-precharge to satisfy tRTP + banks(x).autopch := banks(x).autopch+1; + else + checktime(now-banks(x).writetime, tWR, true, "tWR"); + checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS"); + checktime(now-banks(x).readtime, tRTP, true, "tRTP"); + banks(x).openrow := -1; + banks(x).closetime := now; + end if; + end if; + if banks(x).autopch >= 0 then + banks(x).autopch := banks(x).autopch - 1; + end if; + end loop; + + -- Read/write management + if not loaded and lddelay < now then + load_srec; + loaded := true; + end if; + if accpipe(2+cl+al).r then + assert cl>1 report "Incorrect CL setting!" severity warning; + read_en <= true; + -- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1))); + -- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1); + read_data <= memdata(accpipe(2+cl+al).col(0)) & memdata(accpipe(2+cl+al).col(1)); + else + read_en <= false; + end if; + -- tRTP is counted from read command + AL for BL4, read command + AL + 2 + -- for BL8. This check covers both cases by writing readtime on the next-to-last + -- transfer. + if accpipe(3+al).r and accpipe(2+al).r and accpipe(3+al).bank=accpipe(2+al).bank then + banks(accpipe(2+al).bank).readtime := now; + end if; + write_en <= accpipe(1+cl+al).w or accpipe(2+cl+al).w; + if accpipe(3+cl+al).w then + assert not is_x(write_mask) report "Write error!"; + for x in 0 to 1 loop + for b in width/8-1 downto 0 loop + if write_mask((1-x)*width/8+b)='0' then + memdata(accpipe(3+cl+al).col(x))(8*b+7 downto 8*b) := + write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8); + end if; + end loop; + end loop; + banks(accpipe(3+cl+al).bank).writetime := now; + end if; + end if; + mr <= vmr; + end process; + + ----------------------------------------------------------------------------- + -- DQS/DQ handling and data sampling process + ----------------------------------------------------------------------------- + dqproc: process + variable rdata: std_logic_vector(2*width-1 downto 0); + variable hdata: std_logic_vector(width-1 downto 0); + variable hmask: std_logic_vector(width/8-1 downto 0); + variable prevdqs: std_logic_vector(width/8-1 downto 0); + begin + dq <= (others => 'Z'); + dqs <= (others => 'Z'); + dqsn <= (others => 'Z'); + wait until read_en or write_en; + assert not (read_en and write_en); + if read_en then + dqs <= (others => '0'); + dqsn <= (others => '1'); + wait until falling_edge(ck); + while read_en loop + rdata := read_data; + wait until rising_edge(ck); + dqs <= (others => '1'); + dqsn <= (others => '0'); + dq <= rdata(2*width-1 downto width); + wait until falling_edge(ck); + dqs <= (others => '0'); + dqsn <= (others => '1'); + dq <= rdata(width-1 downto 0); + end loop; + wait until rising_edge(ck); + else + wait until falling_edge(ck); + assert to_X01(dqs)=(dqs'range => '0'); + while write_en loop + prevdqs := to_X01(dqs); + wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck); + if rising_edge(ck) then + write_data <= (others => 'X'); + write_mask <= (others => 'X'); + end if; + for x in dqs'range loop + if prevdqs(x)='0' and to_X01(dqs(x))='1' then + hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x); + hmask(x) := dm(x); + elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then + write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x); + write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x); + write_mask(width/8+x) <= hmask(x); + write_mask(x) <= dm(x); + end if; + end loop; + end loop; + end if; + end process; + +end; + +-- pragma translate_on diff --git a/lib/gaisler/sim/ddr3ram.vhd b/lib/gaisler/sim/ddr3ram.vhd new file mode 100644 index 00000000..b22b8949 --- /dev/null +++ b/lib/gaisler/sim/ddr3ram.vhd @@ -0,0 +1,774 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: ddr3ram +-- File: ddr3ram.vhd +-- Author: Magnus Hjorth, Aeroflex Gaisler +-- Description: Generic simulation model of DDR3 SDRAM (JESD79-3) +------------------------------------------------------------------------------ + +--pragma translate_off + +use std.textio.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library grlib; +use grlib.stdio.hread; +use grlib.stdlib.all; + +entity ddr3ram is + generic ( + width: integer := 32; + abits: integer range 13 to 16 := 13; + colbits: integer range 9 to 12 := 10; + rowbits: integer range 1 to 16 := 13; + implbanks: integer range 1 to 8 := 1; + fname: string; + lddelay: time := (0 ns); + ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before + -- loading RAM + -- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G + speedbin: integer range 0 to 12 := 0; + density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip + pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD) + changeendian: integer range 0 to 32 := 0 + ); + port ( + ck: in std_ulogic; + ckn: in std_ulogic; + cke: in std_ulogic; + csn: in std_ulogic; + odt: in std_ulogic; + rasn: in std_ulogic; + casn: in std_ulogic; + wen: in std_ulogic; + dm: in std_logic_vector(width/8-1 downto 0); + ba: in std_logic_vector(2 downto 0); + a: in std_logic_vector(abits-1 downto 0); + resetn: in std_ulogic; + dq: inout std_logic_vector(width-1 downto 0); + dqs: inout std_logic_vector(width/8-1 downto 0); + dqsn: inout std_logic_vector(width/8-1 downto 0); + doload: in std_ulogic := '1' + ); +end; + +architecture sim of ddr3ram is + + type moderegs is record + -- Mode register (0) + ppd: std_ulogic; + wr: std_logic_vector(2 downto 0); + dllres: std_ulogic; + tm: std_ulogic; + rbt: std_ulogic; + caslat: std_logic_vector(3 downto 0); + blen: std_logic_vector(1 downto 0); + -- Extended mode register 1 + qoff: std_ulogic; + tdqsen: std_ulogic; + level: std_ulogic; + al: std_logic_vector(1 downto 0); + rtt_nom: std_logic_vector(2 downto 0); + dic: std_logic_vector(1 downto 0); + dlldis: std_ulogic; + -- Extended mode register 2 + rtt_wr: std_logic_vector(1 downto 0); + srt: std_ulogic; + asr: std_ulogic; + cwl: std_logic_vector(2 downto 0); + pasr: std_logic_vector(2 downto 0); + -- Extended mode register 3 + mpr: std_ulogic; + mprloc: std_logic_vector(1 downto 0); + end record; + + -- Mode registers as signal, useful for debugging + signal mr: moderegs; + + -- Handshaking between command and DQ/DQS processes + signal read_en, write_en, dqscal_en: boolean := false; + signal read_data, write_data: std_logic_vector(2*width-1 downto 0); + signal write_mask: std_logic_vector(width/4-1 downto 0); + + signal initdone: boolean := false; + + -- Small delta-t to adjust calculations for jitter tol. + constant deltat: time := 50 ps; + + -- Timing parameters + constant tWR: time := 15 ns; + constant tMRD_ck: integer := 4; + constant tRTP_ck: integer := 4; + constant tRTP_t: time := 7.5 ns; + function tRTP(tper: time) return time is + begin + if tRTP_ck*tper > tRTP_t then return tRTP_ck*tper; else return tRTP_t; end if; + end tRTP; + constant tMOD_ck: integer := 12; + constant tMOD_t: time := 15 ns; + + type timetab is array (0 to 12) of time; + -- 800E 800D 1066G 1066H 1066E 1333J 1333H 1333G 1333F 1600K 1600J 1600H 1600G + constant tRAS : timetab := + (37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 36 ns, 36 ns, 36 ns, 36 ns, 35 ns, 35 ns, 35 ns, 35 ns); + constant tRP : timetab := + (15 ns, 12.5 ns, 15 ns, 13.125 ns, 11.25 ns, 15 ns, 13.5 ns, 12 ns, 10.5 ns, 13.75 ns, 12.5 ns, 11.25 ns, 10 ns); + constant tRCD: timetab := tRP; + + type timetab2 is array(2 to 6) of time; + constant tRFC: timetab2 := (90 ns, 110 ns, 160 ns, 300 ns, 350 ns); + + function tRRD(tper: time; speedbin: integer range 0 to 12) return time is + variable t: time; + begin + case speedbin is + when 0 to 1 => t:=10 ns; + when 2 to 4 => if pagesize<2 then t:=7.5 ns; else t:=10 ns; end if; + when 5 to 12 => if pagesize<2 then t:=6 ns; else t:=7.5 ns; end if; + end case; + if t < 4*tper then t:=4*tper; end if; + return t; + end tRRD; + + function pick(t,f: integer; b: boolean) return integer is + begin + if b then return t; else return f; end if; + end pick; + +begin + ----------------------------------------------------------------------------- + -- Init sequence checker + ----------------------------------------------------------------------------- + initp: process + + procedure checkcmd(crasn,ccasn,cwen: std_ulogic; + cba: std_logic_vector(2 downto 0); + ca: std_logic_vector(15 downto 0)) is + variable amatch: boolean; + begin + wait until rising_edge(ck); + while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop + wait until rising_edge(ck); + end loop; + amatch := true; + for x in a'range loop + if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if; + end loop; + assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and + (cba="---" or cba=ba) and amatch + report "Wrong command during init sequence" severity warning; + end checkcmd; + + variable t,t2: time; + variable i: integer; + begin + initdone <= false; + -- Allow resetn to be X or U for a while during sim start + if resetn /= '0' then + wait until resetn='0' for 1 us; + end if; + assert resetn='0' report "RESETn not asserted on power-up" severity warning; + wait until resetn/='0' for 200 us; + assert resetn='0' report "RESETn raised with less than 200 us init delay" severity warning; + l0: loop + initdone <= false; + wait until resetn/='0'; + assert cke='0' report "CKE not low when RESETn deasserted" severity warning; + wait until (resetn='0' or cke/='0') for 500 us; + if resetn='0' then next; end if; + assert cke='0' report "CKE raised with less than 500 us delay after RESETn deasserted" severity warning; + wait until (resetn='0' or cke/='0') and rising_edge(ck); + if resetn='0' then next; end if; + assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')); + t := now; + t2 := t+tRFC(density)+(10 ns); + i := 0; + while i<5 and now1); + constant b2size: integer := pick(b0size, 1, implbanks>2); + constant b3size: integer := pick(b0size, 1, implbanks>3); + constant b4size: integer := pick(b0size, 1, implbanks>4); + constant b5size: integer := pick(b0size, 1, implbanks>5); + constant b6size: integer := pick(b0size, 1, implbanks>6); + constant b7size: integer := pick(b0size, 1, implbanks>7); + + subtype coldata is std_logic_vector(width-1 downto 0); + subtype idata is integer range 0 to (2**20)-1; -- 16 data bits + 2x2 X/U state + type idata_arr is array(natural range <>) of idata; + variable memdata0: idata_arr(0 to b0size-1); + variable memdata1: idata_arr(0 to b1size-1); + variable memdata2: idata_arr(0 to b2size-1); + variable memdata3: idata_arr(0 to b3size-1); + variable memdata4: idata_arr(0 to b4size-1); + variable memdata5: idata_arr(0 to b5size-1); + variable memdata6: idata_arr(0 to b6size-1); + variable memdata7: idata_arr(0 to b7size-1); + + function reversedata(data : std_logic_vector; step : integer) + return std_logic_vector is + variable rdata: std_logic_vector(data'length-1 downto 0); + begin + for i in 0 to (data'length/step-1) loop + rdata(i*step+step-1 downto i*step) := data(data'length-i*step-1 downto data'length-i*step-step); + end loop; + return rdata; + end function reversedata; + + impure function memdata_get(bank,idx: integer) return coldata is + variable r: coldata; + variable x: idata; + variable p: std_logic_vector(19 downto 0); + variable iidx: integer; + begin + iidx := (idx*width)/16; + for q in 0 to (width+15)/16-1 loop + case bank is + when 0 => x := memdata0(iidx+q); + when 1 => x := memdata1(iidx+q); + when 2 => x := memdata2(iidx+q); + when 3 => x := memdata3(iidx+q); + when 4 => x := memdata4(iidx+q); + when 5 => x := memdata5(iidx+q); + when 6 => x := memdata6(iidx+q); + when others => x := memdata7(iidx+q); + end case; + p := std_logic_vector(to_unsigned(x,20)); + if p(18)='0' then p(15 downto 8) := "UUUUUUUU"; + elsif p(19)='1' then p(15 downto 8) := "XXXXXXXX"; end if; + if p(16)='0' then p(7 downto 0) := "UUUUUUUU"; + elsif p(17)='1' then p(7 downto 0) := "XXXXXXXX"; end if; + if width < 16 then + r := p(7 downto 0); + else + r(width-16*q-1 downto width-16*q-16) := p(15 downto 0); + end if; + end loop; + if changeendian /= 0 then + r := reversedata(r, changeendian); + end if; + return r; + end memdata_get; + + procedure memdata_set(bank,idx: integer; v: coldata) is + variable n: coldata; + variable x: idata; + variable p: std_logic_vector(19 downto 0); + variable iidx: integer; + begin +-- assert false +-- report ("memdata_set: bank " & tost(bank) & " idx " & tost(idx) & " data " & tost(v)) +-- severity note; + n := v; + if changeendian /= 0 then + n := reversedata(n, changeendian); + end if; + iidx := (idx*width)/16; + for q in 0 to (width+15)/16-1 loop + p := "0101" & x"0000"; + if width < 16 then + p(7 downto 0) := n; + else + p(15 downto 0) := n(width-16*q-1 downto width-16*q-16); + end if; + if p(15 downto 8)="UUUUUUUU" then p(18):='0'; p(15 downto 8):=x"00"; + elsif is_x(p(15 downto 8)) then p(19):='1'; p(15 downto 8):=x"00"; end if; + if p(7 downto 0)="UUUUUUUU" then p(16):='0'; p(7 downto 0):=x"00"; + elsif is_x(p(7 downto 0)) then p(17):='1'; p(7 downto 0):=x"00"; end if; + x := to_integer(unsigned(p)); + case bank is + when 0 => memdata0(iidx+q) := x; + when 1 => memdata1(iidx+q) := x; + when 2 => memdata2(iidx+q) := x; + when 3 => memdata3(iidx+q) := x; + when 4 => memdata4(iidx+q) := x; + when 5 => memdata5(iidx+q) := x; + when 6 => memdata6(iidx+q) := x; + when others => memdata7(iidx+q) := x; + end case; + end loop; + end memdata_set; + + procedure load_srec is + file TCF : text open read_mode is fname; + variable L1: line; + variable CH : character; + variable rectype : std_logic_vector(3 downto 0); + variable recaddr : std_logic_vector(31 downto 0); + variable reclen : std_logic_vector(7 downto 0); + variable recdata : std_logic_vector(0 to 16*8-1); + variable idx, coloffs, len: integer; + begin + L1:= new string'(""); + while not endfile(TCF) loop + readline(TCF,L1); + if (L1'length /= 0) then + while (not (L1'length=0)) and (L1(L1'left) = ' ') loop + std.textio.read(L1,CH); + end loop; + if L1'length > 0 then + read(L1, ch); + if (ch = 'S') or (ch = 's') then + hread(L1, rectype); + hread(L1, reclen); + len := to_integer(unsigned(reclen))-1; + recaddr := (others => '0'); + case rectype is + when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2; + when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3; + when "0011" => hread(L1, recaddr); len := len - 4; + when others => next; + end case; + hread(L1, recdata(0 to len*8-1)); + if width < 16 then + idx := to_integer(unsigned(recaddr(rowbits+colbits-1 downto 0))); + while len > 1 loop + memdata0(idx) := 16#10000# + to_integer(unsigned(recdata(0 to 7))); + idx := idx+1; + len := len-1; + recdata(0 to recdata'length-8-1) := recdata(8 to recdata'length-1); + end loop; + else + assert recaddr(0)='0'; -- Assume 16-bit alignment on SREC entry + idx := to_integer(unsigned(recaddr(rowbits+colbits+log2(width/16) downto 1))); + while len > 1 loop + memdata0(idx) := 16#50000# + to_integer(unsigned(recdata(0 to 15))); + idx := idx+1; + len := len-2; + recdata(0 to recdata'length-16-1) := recdata(16 to recdata'length-1); + end loop; + if len > 0 then + memdata0(idx) := 16#40000# + to_integer(unsigned(recdata(0 to 15))); + end if; + end if; + end if; + end if; + end if; + end loop; + end load_srec; + + variable vmr: moderegs; + type bankstate is record + openrow: integer; + opentime: time; + closetime: time; + writetime: time; + readtime: time; + autopch: integer; + pchpush: boolean; + end record; + type bankstate_arr is array(natural range <>) of bankstate; + variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false)); + type int_arr is array(natural range <>) of integer; + type dataacc is record + r,w: boolean; + col: int_arr(0 to 1); + bank: integer; + first,wchop: boolean; + end record; + type dataacc_arr is array(natural range <>) of dataacc; + variable accpipe: dataacc_arr(0 to 25); + variable cmd: std_logic_vector(2 downto 0); + variable bank: integer; + variable colv: unsigned(a'high-2 downto 0); + variable alow: unsigned(2 downto 0); + variable col: integer; + variable prev_re, re: time; + variable blen, wblen: integer; + variable lastref: time := 0 ns; + variable i, al, cl, cwl, wrap: integer; + variable b: boolean; + variable mrscount: integer := 100; + variable mrstime: time; + variable loaded: boolean := false; + variable cold: coldata; + + procedure checktime(got, exp: time; gt: boolean; req: string) is + begin + assert (got + deltat > exp and gt) or (got-deltat < exp and not gt) + report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps") + severity warning; + end checktime; + begin + if rising_edge(ck) and resetn='1' then + -- Update pipe regs + prev_re := re; + re := now; + accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1); + accpipe(0).r:=false; accpipe(0).w:=false; accpipe(0).first:=false; + -- Parse MR fields + cmd := rasn & casn & wen; + if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat(3 downto 1)))+4; end if; + if cl<5 or cl>11 then cl:=0; end if; + case vmr.al is + when "00" => al:=0; + when "01" => al:=cl-1; + when "10" => al:=cl-2; + when others => al:=-1; + end case; + if is_x(vmr.cwl) then cwl:=0; else cwl:=to_integer(unsigned(vmr.cwl))+5; end if; + if cwl>8 then cwl:=0; end if; + if is_x(vmr.wr) then wrap:=0; else wrap:=to_integer(unsigned(vmr.wr))+4; end if; + if wrap<5 or wrap>12 then wrap:=0; end if; + -- Checks for all-bank commands + mrscount := mrscount+1; + assert (mrscount >= tMRD_ck) or (cke='1' and (csn='1' or cmd="111")) + report "tMRD violation!" severity warning; + assert (mrscount > tMOD_ck and now > mrstime+tMOD_t-deltat) or + (cke='1' and (csn='1' or cmd="111" or cmd="000")) + report "tMOD violation!" severity warning; + if cke='1' and csn='0' and cmd/="111" then + checktime(now-lastref, tRFC(density), true, "tRFC"); + end if; + if vmr.mpr='1' then + assert cke='0' or csn='1' or cmd="111" or cmd="101" + report "Command other than read in MPR mode!" severity warning; + for x in 7 downto 0 loop + assert banks(x).openrow<0 + report "Row opened in MPR mode!" severity warning; + end loop; + end if; + -- Main command handler + if cke='1' and csn='0' then + case cmd is + when "111" => -- NOP + + when "011" => -- RAS + assert initdone report "Opening row before init sequence done!" severity warning; + bank := to_integer(unsigned(ba)); + assert banks(bank).openrow < 0 + report "Row already open" severity warning; + checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP"); + for x in 0 to 7 loop + checktime(now-banks(x).opentime, tRRD(re-prev_re, speedbin), true, "tRRD"); + end loop; + banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0))); + banks(bank).opentime := now; + + when "101" | "100" => -- Read/Write + bank := to_integer(unsigned(ba)); + assert banks(bank).openrow >= 0 or vmr.mpr='1' + report "Row not open" severity error; + checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD"); + for x in 0 to 3 loop + assert not accpipe(x).r and not accpipe(x).w; + end loop; + if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if; + colv := unsigned(std_logic_vector'(a(a'high downto 13) & a(11) & a(9 downto 0))); + wblen := 8; + case vmr.blen is + when "00" => blen := 8; + when "01" => if a(12)='1' then blen:=8; else blen:=4; end if; + when "11" => blen := 4; wblen:=4; + when others => assert false report "Invalid burst length setting in MR!" severity error; + end case; + alow := unsigned(a(2 downto 0)); + if cmd(0)='0' then + alow(1 downto 0) := "00"; + if blen=8 then alow(2):='0'; end if; + end if; + for x in 0 to blen-1 loop + accpipe(3-x/2).bank := bank; + if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if; + if vmr.rbt='0' then -- Sequential + colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x; + else -- Interleaved + colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen)); + end if; + col := banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0)); + accpipe(3-x/2).col(x mod 2) := col; + accpipe(3-x/2).wchop := (blen -- ZQInit + for x in 0 to 7 loop + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + for x in 3+cl+al downto 0 loop + assert not accpipe(x).r severity warning; + end loop; + for x in 4+cwl+al downto 0 loop + assert not accpipe(x).w severity warning; + end loop; + -- Currently does not check TZQCoper/TZQCs + + + when "010" => -- Precharge + if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if; + for x in 6+cwl+al downto 0 loop + assert ( (not ((accpipe(x).r and x<=3+al) or accpipe(x).w)) or + (a(10)='0' and accpipe(x).bank/=bank) ) + report "Precharging bank with access in progress" severity warning; + end loop; + for x in 0 to 7 loop + if a(10)='1' or ba=std_logic_vector(to_unsigned(x,3)) then + assert banks(x).autopch<0 + report "Precharging bank that is auto-precharged!" severity note; + assert a(10)='1' or banks(x).openrow >= 0 + report "Precharging single bank that is in idle state!" severity note; + banks(x).autopch := 0; -- Handled below case statement + banks(x).pchpush := false; + end if; + end loop; + + + when "001" => -- Auto refresh + for x in 0 to 7 loop + assert banks(x).openrow < 0 + report "Bank in wrong state for auto refresh!" severity warning; + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + lastref := now; + + + when "000" => -- MRS + for x in 0 to 7 loop + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + bank := to_integer(unsigned(ba)); + case bank is + when 0 => + vmr.ppd := a(12); + vmr.wr := a(11 downto 9); + vmr.dllres := a(8); + vmr.tm := a(7); + vmr.caslat := a(6 downto 4) & a(2); + vmr.rbt := a(3); + vmr.blen := a(1 downto 0); + when 1 => + vmr.qoff := a(12); + vmr.tdqsen := a(11); + vmr.level := a(7); + vmr.al := a(4 downto 3); + vmr.rtt_nom := a(9) & a(6) & a(2); + vmr.dic := a(5) & a(1); + vmr.dlldis := a(0); + when 2 => + vmr.rtt_wr := a(10 downto 9); + vmr.srt := a(7); + vmr.asr := a(6); + vmr.cwl := a(5 downto 3); + vmr.pasr := a(2 downto 0); + when 3 => + vmr.mpr := a(2); + vmr.mprloc := a(1 downto 0); + when others => + assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning; + end case; + mrscount := 0; + mrstime := now; + + when others => + assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning; + end case; + end if; + + -- Manual or auto precharge handling + for x in 0 to 7 loop + if banks(x).autopch=0 then + if banks(x).pchpush and + ((now-banks(x).readtime-deltat) < tRTP_t or + (now-banks(x).opentime-deltat) < tRAS(speedbin)) then + -- Auto delay auto-precharge to satisfy tRTP_t + -- NOTE: According to Micron's datasheets, their DDR3 memories + -- automatically hold off the auto precharge so that also tRAS is satisfied, + -- and the MIG controller seems to depend on this. It is not clear in the + -- JEDEC standard (rev F) whether this is guaranteed behavior for all DDR3 + -- RAMs, but we emulate that behavior here. + banks(x).autopch := banks(x).autopch+1; + else + checktime(now-banks(x).writetime, tWR, true, "tWR"); + checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS"); + checktime(now-banks(x).readtime, tRTP(re-prev_re), true, "tRTP"); + banks(x).openrow := -1; + banks(x).closetime := now; + end if; + end if; + if banks(x).autopch >= 0 then + banks(x).autopch := banks(x).autopch - 1; + end if; + end loop; + + -- Read/write management + if not loaded and lddelay < now and (ldguard=0 or doload='1') then + load_srec; + loaded := true; + end if; + if accpipe(2+cl+al).r then + assert cl>1 report "Incorrect CL setting!" severity warning; + read_en <= true; + -- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1))); + -- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1); + if vmr.mpr='1' then + assert vmr.mprloc="00" report "Read from undefined MPR!" severity warning; + read_data <= (others => '0'); + for x in width/8-1 downto 0 loop + read_data(x*8) <= '1'; + end loop; + else + read_data <= memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(0)) & + memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(1)); + end if; + else + read_en <= false; + end if; + if accpipe(3+al).r and accpipe(3+al).first then + banks(accpipe(3+al).bank).readtime := now; + end if; + write_en <= accpipe(2+cwl+al).w or accpipe(3+cwl+al).w; + if accpipe(4+cwl+al).w then + assert not is_x(write_mask) report "Write error!"; + for x in 0 to 1 loop + cold := memdata_get(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x)); + for b in width/8-1 downto 0 loop + if write_mask((1-x)*width/8+b)='0' then + cold(8*b+7 downto 8*b) := + write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8); + end if; + end loop; + memdata_set(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x), cold); + end loop; + banks(accpipe(4+cwl+al).bank).writetime := now; + end if; + if accpipe(6+cwl+al).w and accpipe(6+cwl+al).wchop then + banks(accpipe(6+cwl+al).bank).writetime := now; + end if; + dqscal_en <= (vmr.level='1'); + elsif resetn='0' then + for x in banks'range loop + banks(x).openrow := -1; + end loop; + end if; + mr <= vmr; + end process; + + ----------------------------------------------------------------------------- + -- DQS/DQ handling and data sampling process + ----------------------------------------------------------------------------- + dqproc: process + variable rdata: std_logic_vector(2*width-1 downto 0); + variable hdata: std_logic_vector(width-1 downto 0); + variable hmask: std_logic_vector(width/8-1 downto 0); + variable prevdqs: std_logic_vector(width/8-1 downto 0); + begin + dq <= (others => 'Z'); + dqs <= (others => 'Z'); + dqsn <= (others => 'Z'); + wait until read_en or write_en or dqscal_en; + assert not (read_en and write_en); + if dqscal_en then + while dqscal_en loop + prevdqs := dqs; + wait on dqs,dqscal_en; + for x in dqs'range loop + if dqs(x)='1' and prevdqs(x)='0' then + dq(8*x+7 downto 8*x) <= "0000000" & ck; + end if; + end loop; + end loop; + elsif read_en then + dqs <= (others => '0'); + dqsn <= (others => '1'); + wait until falling_edge(ck); + while read_en loop + rdata := read_data; + wait until rising_edge(ck); + dqs <= (others => '1'); + dqsn <= (others => '0'); + dq <= rdata(2*width-1 downto width); + wait until falling_edge(ck); + dqs <= (others => '0'); + dqsn <= (others => '1'); + dq <= rdata(width-1 downto 0); + end loop; + wait until rising_edge(ck); + else + wait until falling_edge(ck); + while write_en loop + prevdqs := to_X01(dqs); + wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck); + if rising_edge(ck) then + write_data <= (others => 'X'); + write_mask <= (others => 'X'); + end if; + for x in dqs'range loop + if prevdqs(x)='0' and to_X01(dqs(x))='1' then + hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x); + hmask(x) := dm(x); + elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then + write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x); + write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x); + write_mask(width/8+x) <= hmask(x); + write_mask(x) <= dm(x); + end if; + end loop; + end loop; + end if; + end process; + +end; + +-- pragma translate_on diff --git a/lib/gaisler/sim/ddrram.vhd b/lib/gaisler/sim/ddrram.vhd new file mode 100644 index 00000000..74bb7cfc --- /dev/null +++ b/lib/gaisler/sim/ddrram.vhd @@ -0,0 +1,518 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: ddrram +-- File: ddrram.vhd +-- Author: Magnus Hjorth, Aeroflex Gaisler +-- Description: Generic simulation model of DDR SDRAM (JESD79E) +------------------------------------------------------------------------------ + +--pragma translate_off + +use std.textio.all; +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +library grlib; +use grlib.stdio.hread; +use grlib.stdlib.all; + +entity ddrram is + generic ( + width: integer := 32; + abits: integer range 12 to 14 := 12; + colbits: integer range 8 to 13 := 8; + rowbits: integer range 1 to 14 := 12; + implbanks: integer range 1 to 4 := 1; + fname: string; + lddelay: time := (0 ns); + speedbin: integer range 0 to 5 := 0; -- 0:DDR200,1:266,2:333,3:400C,4:400B,5:400A + density: integer range 0 to 3 := 0; -- 0:128Mbit 1:256Mbit 2:512Mbit 3:1Gbit / chip + igndqs: integer range 0 to 1 := 0 + ); + port ( + ck: in std_ulogic; + cke: in std_ulogic; + csn: in std_ulogic; + rasn: in std_ulogic; + casn: in std_ulogic; + wen: in std_ulogic; + dm: in std_logic_vector(width/8-1 downto 0); + ba: in std_logic_vector(1 downto 0); + a: in std_logic_vector(abits-1 downto 0); + dq: inout std_logic_vector(width-1 downto 0); + dqs: inout std_logic_vector(width/8-1 downto 0) + ); +end; + +architecture sim of ddrram is + + type moderegs is record + -- Mode register (0) + opmode: std_logic_vector(6 downto 0); + caslat: std_logic_vector(2 downto 0); + bt: std_ulogic; + blen: std_logic_vector(2 downto 0); + -- Extended mode register (1) + opmode1: std_logic_vector(10 downto 0); + res1: std_ulogic; + ds: std_ulogic; + dlldis: std_ulogic; + end record; + + -- Mode registers as signal, useful for debugging + signal mr: moderegs; + + -- Handshaking between command and DQ/DQS processes + signal read_en, write_en: boolean := false; + signal hcmode: boolean := false; -- Shift DQS/read data one cycle for CL=1.5/2.5 + signal hcread_en: boolean := false; -- One cycle earlier for half-cycle mode read preamble gen + signal read_data, write_data: std_logic_vector(2*width-1 downto 0); + signal write_mask: std_logic_vector(width/4-1 downto 0); + + signal initdone: boolean := false; + + -- Small delta-t to adjust calculations for jitter tol. + constant deltat: time := 50 ps; + -- Timing parameters + constant tWR: time := 15 ns; + constant tMRD_ck: integer := 2; + type timetab is array (0 to 5) of time; + constant tRAS : timetab := (50 ns, 45 ns, 42 ns, 40 ns, 40 ns, 40 ns); + constant tRP : timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns); + constant tRCD: timetab := (20 ns, 20 ns, 18 ns, 18 ns, 15 ns, 15 ns); + constant tRRD: timetab := (15 ns, 15 ns, 12 ns, 10 ns, 10 ns, 10 ns); + constant tRFC_lt1G: timetab := (80 ns, 75 ns, 72 ns, 70 ns, 70 ns, 70 ns); --Assuming<1Gb + constant tRFC_mt1G: time := 120 ns; + function tRFC return time is + begin + if density < 3 then return tRFC_lt1G(speedbin); + else return tRFC_mt1G; end if; + end tRFC; + +begin + + ----------------------------------------------------------------------------- + -- Init sequence checker + ----------------------------------------------------------------------------- + initp: process + + variable cyctr : integer := 0; + + procedure checkcmd(crasn,ccasn,cwen: std_ulogic; + cba: std_logic_vector(1 downto 0); + a10,a8,a0: std_ulogic) is + begin + wait until rising_edge(ck); + cyctr := cyctr+1; + while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop + wait until rising_edge(ck); + cyctr := cyctr+1; + end loop; + assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and + (cba="--" or cba=ba) and (a10='-' or a10=a(10)) and (a8='-' or a8=a(8)) and + (a0='-' or a0=a(0)) + report "Wrong command during init sequence" severity warning; + end checkcmd; + + begin + initdone <= false; + -- Allow cke to be X or U for a while during sim start + if is_x(cke) then + wait until not is_x(cke); + end if; + assert cke='0' report "CKE not deasserted on power-up" severity warning; + wait until cke/='0' for 200 us; + assert cke='0' report "CKE raised with less than 200 us init delay" severity warning; + wait until cke/='0' and rising_edge(ck); + assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')); + -- Precharge all + checkcmd('0','1','0',"--",'1','-','-'); + -- EMRS enable DLL + checkcmd('0','0','0',"01",'-','-','0'); + -- MRS reset DLL + checkcmd('0','0','0',"00",'-','1','-'); + cyctr := 0; + -- 200 cycle NOP + -- Precharge all + checkcmd('0','1','0',"--",'1','-','-'); + assert cyctr >= 200 + report "Command issued too quickly after DLL reset" severity warning; + -- 2 x auto refresh + checkcmd('0','0','1',"--",'-','-','-'); + checkcmd('0','0','1',"--",'-','-','-'); + -- MRS !reset DLL + checkcmd('0','0','0',"00",'-','0','-'); + initdone <= true; + wait; + end process; + + ----------------------------------------------------------------------------- + -- Command state machine + ----------------------------------------------------------------------------- + cmdp: process(ck) + subtype coldata is std_logic_vector(width-1 downto 0); + type coldata_arr is array(0 to implbanks*(2**(colbits+rowbits))-1) of coldata; + variable memdata: coldata_arr; + + procedure load_srec is + file TCF : text open read_mode is fname; + variable L1: line; + variable CH : character; + variable rectype : std_logic_vector(3 downto 0); + variable recaddr : std_logic_vector(31 downto 0); + variable reclen : std_logic_vector(7 downto 0); + variable recdata : std_logic_vector(0 to 16*8-1); + variable col, coloffs, len: integer; + begin + L1:= new string'(""); + while not endfile(TCF) loop + readline(TCF,L1); + if (L1'length /= 0) then + while (not (L1'length=0)) and (L1(L1'left) = ' ') loop + std.textio.read(L1,CH); + end loop; + if L1'length > 0 then + read(L1, ch); + if (ch = 'S') or (ch = 's') then + hread(L1, rectype); + hread(L1, reclen); + len := to_integer(unsigned(reclen))-1; + recaddr := (others => '0'); + case rectype is + when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2; + when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3; + when "0011" => hread(L1, recaddr); len := len - 4; + when others => next; + end case; + hread(L1, recdata(0 to len*8-1)); + col := to_integer(unsigned(recaddr(log2(width/8)+rowbits+colbits+1 downto log2(width/8)))); + coloffs := 8*to_integer(unsigned(recaddr(log2(width/8)-1 downto 0))); + while len > width/8 loop + assert coloffs=0; + memdata(col) := recdata(0 to width-1); + col := col+1; + len := len-width/8; + recdata(0 to recdata'length-width-1) := recdata(width to recdata'length-1); + end loop; + memdata(col)(width-1-coloffs downto width-coloffs-len*8) := recdata(0 to len*8-1); + end if; + end if; + end if; + end loop; + end load_srec; + + variable vmr: moderegs := ((others => '0'), "UUU", 'U', "UUU", (others => '0'), '0', '0', '0'); + type bankstate is record + openrow: integer; + opentime: time; + closetime: time; + writetime: time; + autopch: integer; + end record; + type bankstate_arr is array(natural range <>) of bankstate; + variable banks: bankstate_arr(3 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, -1)); + type int_arr is array(natural range <>) of integer; + type dataacc is record + r,w: boolean; + col: int_arr(0 to 1); + bank: integer; + end record; + type dataacc_arr is array(natural range <>) of dataacc; + variable accpipe: dataacc_arr(0 to 9); + variable cmd: std_logic_vector(2 downto 0); + variable bank: integer; + variable colv: unsigned(a'high-1 downto 0); + variable alow: unsigned(2 downto 0); + variable col: integer; + variable prev_re, re: time; + variable blen: integer; + variable lastref: time := 0 ns; + variable i: integer; + variable b: boolean; + variable mrscount: integer := 0; + variable loaded: boolean := false; + + procedure checktime(got, exp: time; gt: boolean; req: string) is + begin + assert (got + deltat > exp and gt) or (got-deltat < exp and not gt) + report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps") + severity warning; + end checktime; + begin + if rising_edge(ck) then + -- Update pipe regs + prev_re := re; + re := now; + accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1); + accpipe(0).r:=false; accpipe(0).w:=false; + -- Main command handler + cmd := rasn & casn & wen; + if mrscount > 0 then + mrscount := mrscount-1; + assert cke='1' and (csn='1' or cmd="111") report "tMRS violation!" severity warning; + end if; + if cke='1' and csn='0' and cmd/="111" then + checktime(now-lastref, tRFC, true, "tRFC"); + end if; + if cke='1' and csn='0' then + case cmd is + when "111" => -- NOP + + when "011" => -- RAS + assert initdone report "Opening row before init sequence done!" severity warning; + bank := to_integer(unsigned(ba)); + assert banks(bank).openrow < 0 + report "Row already open" severity warning; + checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP"); + for x in 0 to 3 loop + checktime(now-banks(x).opentime, tRRD(speedbin), true, "tRRD"); + end loop; + banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0))); + banks(bank).opentime := now; + + when "101" | "100" => -- Read/Write + bank := to_integer(unsigned(ba)); + assert banks(bank).openrow >= 0 + report "Row not open" severity error; + checktime(now-banks(bank).opentime, tRCD(speedbin), true, "tRCD"); + for x in 0 to 3 loop + -- Xilinx V4 MIG controller issues multiple overlapping load commands + -- during calibration, therefore this assertion is bypassed before + -- load-delay has passed. + assert (not accpipe(x).r and not accpipe(x).w) or (now < lddelay); + end loop; + if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if; + colv := unsigned(std_logic_vector'(a(a'high downto 11) & a(9 downto 0))); + case vmr.blen is + when "001" => blen := 2; + when "010" => blen := 4; + when "011" => blen := 8; + when others => assert false report "Invalid burst length setting in MR!" severity error; + end case; + alow := unsigned(a(2 downto 0)); + for x in 0 to blen-1 loop + accpipe(3-x/2).bank := bank; + if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if; + if vmr.bt='0' then -- Sequential + colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x; + else -- Interleaved + colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen)); + end if; + col := to_integer(unsigned(ba))*(2**(colbits+rowbits)) + + banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0)); + accpipe(3-x/2).col(x mod 2) := col; + end loop; + -- Auto precharge + if a(10)='1' then + if cmd(0)='1' then + banks(bank).autopch := blen/2; + else + banks(bank).autopch := 1+blen/2 + (tWR-deltat+(re-prev_re))/(re-prev_re); + end if; + end if; + + when "110" => -- Burst terminate + assert not accpipe(3).w + report "Burst terminate on write burst!" severity warning; + assert banks(accpipe(3).bank).autopch<0 + report "Burst terminate on read with auto-precharge!" severity warning; + assert accpipe(3).r + report "Burst terminate with no effect!" severity warning; + for x in 3 downto 0 loop + accpipe(x).r := false; + accpipe(x).w := false; + end loop; + + when "010" => -- Precharge + for x in 3 downto 0 loop + accpipe(x).r := false; + accpipe(x).w := false; + end loop; + for x in 0 to 3 loop + if a(10)='1' or ba=std_logic_vector(to_unsigned(x,2)) then + assert banks(x).autopch<0 + report "Precharging bank that is auto-precharged" severity note; + assert a(10)='1' or banks(x).openrow>=0 + report "Precharging single bank that is in idle state" severity note; + banks(x).autopch := 0; -- Handled below + end if; + end loop; + + + when "001" => -- Auto refresh + for x in 0 to 3 loop + assert banks(x).openrow < 0 + report "Bank in wrong state for auto refresh!" severity warning; + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + lastref := now; + + + when "000" => -- MRS + for x in 0 to 3 loop + checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP"); + end loop; + case ba is + when "00" => + vmr.opmode(a'high-7 downto 0) := a(a'high downto 7); + vmr.caslat := a(6 downto 4); + vmr.bt := a(3); + vmr.blen := a(2 downto 0); + when "01" => + vmr.opmode1(a'high-3 downto 0) := a(a'high downto 3); + vmr.res1 := a(2); + vmr.ds := a(1); + vmr.dlldis := a(0); + when others => + assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning; + end case; + mrscount := tMRD_ck-1; + + when others => + assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning; + end case; + end if; + + -- Manual or auto precharge + for x in 0 to 3 loop + if banks(x).autopch=0 then + checktime(now-banks(x).writetime, tWR, true, "tWR"); + checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS"); + banks(x).openrow := -1; + banks(x).closetime := now; + end if; + if banks(x).autopch >= 0 then + banks(x).autopch := banks(x).autopch - 1; + end if; + end loop; + + -- Read/write management + if not loaded and lddelay < now then + load_srec; + loaded := true; + end if; + case vmr.caslat is + when "010" => i := 2; b:=false; -- CL2 + when "011" => i := 3; b:=false; -- CL3 + when "101" => i := 2; b:=true; -- CL1.5 + when "110" => i := 3; b:=true; -- CL2.5 + when others => i := 1; + end case; + hcmode <= b; + if b then hcread_en <= accpipe(1+i).r; else hcread_en <= false; end if; + if accpipe(2+i).r then + assert i>1 report "Incorrect CL setting!" severity warning; + read_en <= true; + -- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1))); + -- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1); + read_data <= memdata(accpipe(2+i).col(0)) & memdata(accpipe(2+i).col(1)); + else + read_en <= false; + end if; + write_en <= accpipe(3).w or accpipe(4).w; + if accpipe(5).w and write_mask/=(write_mask'range => '1') then + assert not is_x(write_mask) report "Write error"; + for x in 0 to 1 loop + for b in width/8-1 downto 0 loop + if write_mask((1-x)*width/8+b)='0' then + memdata(accpipe(5).col(x))(8*b+7 downto 8*b) := + write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8); + end if; + end loop; + end loop; + banks(accpipe(5).bank).writetime := now; + end if; + end if; + mr <= vmr; + end process; + + ----------------------------------------------------------------------------- + -- DQS/DQ handling and data sampling process + ----------------------------------------------------------------------------- + dqproc: process + variable rdata: std_logic_vector(2*width-1 downto 0); + variable hdata: std_logic_vector(width-1 downto 0); + variable hmask: std_logic_vector(width/8-1 downto 0); + variable prevdqs: std_logic_vector(width/8-1 downto 0); + begin + dq <= (others => 'Z'); + dqs <= (others => 'Z'); + wait until (hcmode and hcread_en) or read_en or write_en; + assert not ((read_en or hcread_en) and write_en); + if (read_en or hcread_en) then + if hcmode then + wait until falling_edge(ck); + end if; + dqs <= (others => '0'); + wait until falling_edge(ck); + while read_en loop + rdata := read_data; + if not hcmode then + wait until rising_edge(ck); + end if; + dqs <= (others => '1'); + dq <= rdata(2*width-1 downto width); + if hcmode then + wait until rising_edge(ck); + else + wait until falling_edge(ck); + end if; + dqs <= (others => '0'); + dq <= rdata(width-1 downto 0); + if hcmode then + wait until falling_edge(ck); + end if; + end loop; + if not hcmode then + wait until rising_edge(ck); + end if; + else + wait until falling_edge(ck); + assert to_X01(dqs)=(dqs'range => '0') or igndqs/=0; + while write_en loop + prevdqs := to_X01(dqs); + if igndqs /= 0 then + wait on ck,write_en; + else + wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck); + end if; + if rising_edge(ck) then + -- Just to make sure missing DQS is not undetected + write_data <= (others => 'X'); + write_mask <= (others => 'X'); + end if; + for x in dqs'range loop + if (igndqs=0 and prevdqs(x)='0' and to_X01(dqs(x))='1') or (igndqs/=0 and rising_edge(ck)) then + hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x); + hmask(x) := dm(x); + elsif (igndqs=0 and prevdqs(x)='1' and to_X01(dqs(x))='0') or (igndqs/=0 and falling_edge(ck)) then + write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x); + write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x); + write_mask(width/8+x) <= hmask(x); + write_mask(x) <= dm(x); + end if; + end loop; + end loop; + end if; + end process; + +end; + +-- pragma translate_on diff --git a/lib/gaisler/sim/delay_wire.vhd b/lib/gaisler/sim/delay_wire.vhd index 3c9f0e8c..21cef508 100644 --- a/lib/gaisler/sim/delay_wire.vhd +++ b/lib/gaisler/sim/delay_wire.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/phy.vhd b/lib/gaisler/sim/phy.vhd index 3d7a7154..638e8f73 100644 --- a/lib/gaisler/sim/phy.vhd +++ b/lib/gaisler/sim/phy.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/pwm_check.vhd b/lib/gaisler/sim/pwm_check.vhd index aa6cfea0..da075a7e 100644 --- a/lib/gaisler/sim/pwm_check.vhd +++ b/lib/gaisler/sim/pwm_check.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/sim.vhd b/lib/gaisler/sim/sim.vhd index 882c8dd5..45088fe5 100644 --- a/lib/gaisler/sim/sim.vhd +++ b/lib/gaisler/sim/sim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -85,6 +85,104 @@ package sim is function buskeep(signal v : in std_logic_vector) return std_logic_vector; function buskeep(signal c : in std_logic) return std_logic; + component ddrram is + generic ( + width: integer := 32; + abits: integer range 12 to 14 := 12; + colbits: integer range 8 to 13 := 8; + rowbits: integer range 1 to 14 := 12; + implbanks: integer range 1 to 4 := 1; + fname: string; + lddelay: time := (0 ns); + speedbin: integer range 0 to 5 := 0; -- 0:DDR200,1:266,2:333,3:400C,4:400B,5:400A + density: integer range 0 to 3 := 0; -- 0:128Mbit 1:256Mbit 2:512Mbit 3:1Gbit / chip + igndqs: integer range 0 to 1 := 0 + ); + port ( + ck: in std_ulogic; + cke: in std_ulogic; + csn: in std_ulogic; + rasn: in std_ulogic; + casn: in std_ulogic; + wen: in std_ulogic; + dm: in std_logic_vector(width/8-1 downto 0); + ba: in std_logic_vector(1 downto 0); + a: in std_logic_vector(abits-1 downto 0); + dq: inout std_logic_vector(width-1 downto 0); + dqs: inout std_logic_vector(width/8-1 downto 0) + ); + end component; + + component ddr2ram is + generic ( + width: integer := 32; + abits: integer range 13 to 16 := 13; + babits: integer range 2 to 3 := 3; + colbits: integer range 9 to 11 := 9; + rowbits: integer range 1 to 16 := 13; + implbanks: integer range 1 to 8 := 1; + fname: string; + lddelay: time := (0 ns); + -- Speed bins: 0:DDR2-400C,1:400B,2:533C,3:533B,4:667D,5:667C,6:800E,7:800D,8:800C + -- 9:800+tRAS=40ns + speedbin: integer range 0 to 9 := 0; + density: integer range 1 to 5 := 3; -- 1:256M 2:512M 3:1G 4:2G 5:4G bits/chip + pagesize: integer range 1 to 2 := 1 -- 1K/2K page size (controls tRRD) + ); + port ( + ck: in std_ulogic; + ckn: in std_ulogic; + cke: in std_ulogic; + csn: in std_ulogic; + odt: in std_ulogic; + rasn: in std_ulogic; + casn: in std_ulogic; + wen: in std_ulogic; + dm: in std_logic_vector(width/8-1 downto 0); + ba: in std_logic_vector(babits-1 downto 0); + a: in std_logic_vector(abits-1 downto 0); + dq: inout std_logic_vector(width-1 downto 0); + dqs: inout std_logic_vector(width/8-1 downto 0); + dqsn: inout std_logic_vector(width/8-1 downto 0) + ); + end component; + + component ddr3ram is + generic ( + width: integer := 32; + abits: integer range 13 to 16 := 13; + colbits: integer range 9 to 12 := 10; + rowbits: integer range 1 to 16 := 13; + implbanks: integer range 1 to 8 := 1; + fname: string; + lddelay: time := (0 ns); + ldguard: integer range 0 to 1 := 0; + -- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G + speedbin: integer range 0 to 12 := 0; + density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip + pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD) + changeendian: integer range 0 to 32 := 0 + ); + port ( + ck: in std_ulogic; + ckn: in std_ulogic; + cke: in std_ulogic; + csn: in std_ulogic; + odt: in std_ulogic; + rasn: in std_ulogic; + casn: in std_ulogic; + wen: in std_ulogic; + dm: in std_logic_vector(width/8-1 downto 0); + ba: in std_logic_vector(2 downto 0); + a: in std_logic_vector(abits-1 downto 0); + resetn: in std_ulogic; + dq: inout std_logic_vector(width-1 downto 0); + dqs: inout std_logic_vector(width/8-1 downto 0); + dqsn: inout std_logic_vector(width/8-1 downto 0); + doload: in std_ulogic := '1' + ); + end component; + component phy is generic( address : integer range 0 to 31 := 0; diff --git a/lib/gaisler/sim/sram.vhd b/lib/gaisler/sim/sram.vhd index ecf6cd30..b3369bd3 100644 --- a/lib/gaisler/sim/sram.vhd +++ b/lib/gaisler/sim/sram.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/sram16.vhd b/lib/gaisler/sim/sram16.vhd index 6e1c1781..50fa84db 100644 --- a/lib/gaisler/sim/sram16.vhd +++ b/lib/gaisler/sim/sram16.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/sim/vhdlsim.txt b/lib/gaisler/sim/vhdlsim.txt index 641801e4..7f642362 100644 --- a/lib/gaisler/sim/vhdlsim.txt +++ b/lib/gaisler/sim/vhdlsim.txt @@ -4,3 +4,4 @@ delay_wire.vhd spi_flash.vhd pwm_check.vhd usbsim.vhd grusbdcsim.vhd grusb_dclsim.vhd ramback.vhd zbtssram.vhd slavecheck.vhd spwtrace.vhd spwtracev.vhd +ddrram.vhd ddr2ram.vhd ddr3ram.vhd diff --git a/lib/gaisler/spacewire/spacewire.vhd b/lib/gaisler/spacewire/spacewire.vhd index 70d50f25..fcbcba13 100644 --- a/lib/gaisler/spacewire/spacewire.vhd +++ b/lib/gaisler/spacewire/spacewire.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -26,19 +26,28 @@ use techmap.gencomp.all; package spacewire is type grspw_in_type is record - d : std_logic_vector(3 downto 0); - dv : std_logic_vector(3 downto 0); - s : std_logic_vector(1 downto 0); - dconnect : std_logic_vector(3 downto 0); - tickin : std_ulogic; - tickinraw : std_ulogic; - timein : std_logic_vector(7 downto 0); - clkdiv10 : std_logic_vector(7 downto 0); - rmapen : std_ulogic; - rmapnodeaddr: std_logic_vector(7 downto 0); - dcrstval : std_logic_vector(9 downto 0); - timerrstval : std_logic_vector(11 downto 0); - nd : std_logic_vector(9 downto 0); + d : std_logic_vector(3 downto 0); + dv : std_logic_vector(3 downto 0); + s : std_logic_vector(1 downto 0); + dconnect : std_logic_vector(3 downto 0); + tickin : std_ulogic; + tickinraw : std_ulogic; + timein : std_logic_vector(7 downto 0); + clkdiv10 : std_logic_vector(7 downto 0); + rmapen : std_ulogic; + rmapnodeaddr : std_logic_vector(7 downto 0); + dcrstval : std_logic_vector(9 downto 0); + timerrstval : std_logic_vector(11 downto 0); + nd : std_logic_vector(9 downto 0); + intpreload : std_logic_vector(30 downto 0); + inttreload : std_logic_vector(30 downto 0); + intiareload : std_logic_vector(30 downto 0); + intcreload : std_logic_vector(30 downto 0); + irqtxdefault : std_logic_vector(4 downto 0); + pnpen : std_ulogic; + pnpuvendid : std_logic_vector(15 downto 0); + pnpuprodid : std_logic_vector(15 downto 0); + pnpusn : std_logic_vector(31 downto 0); end record; type grspw_out_type is record @@ -59,7 +68,10 @@ package spacewire is constant grspw_in_none : grspw_in_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', (others => '0'), (others => '0'), '0', - (others => '0'), (others => '0'), (others => '0'), (others => '0')); + (others => '0'), (others => '0'), (others => '0'), (others => '0'), + (others => '0'), (others => '0'), (others => '0'), (others => '0'), + (others => '0'), '0', (others => '0'), (others => '0'), + (others => '0')); constant grspw_out_none : grspw_out_type := ((others => '0'), (others => '0'), '0', '0', '0', (others => '0'), @@ -88,6 +100,10 @@ package spacewire is --time iface tickin : std_ulogic; timein : std_logic_vector(7 downto 0); + -- input timing testing + testd : std_logic_vector(1 downto 0); + tests : std_logic_vector(1 downto 0); + testinput : std_ulogic; end record; type grspw_codec_out_type is record @@ -112,9 +128,17 @@ package spacewire is txififorst : std_ulogic; --time iface tickin_done : std_ulogic; + tickin_busy : std_ulogic; tickout : std_ulogic; timeout : std_logic_vector(7 downto 0); + --memory error merror : std_ulogic; + --credit counters + ocredcnt : std_logic_vector(5 downto 0); + credcnt : std_logic_vector(5 downto 0); + --misc + powerdown : std_ulogic; + powerdownrx : std_ulogic; end record; type grspw_dma_in_type is record @@ -149,6 +173,7 @@ package spacewire is --time iface tickout : std_ulogic; timeout : std_logic_vector(7 downto 0); + --memory error merror : std_ulogic; end record; @@ -188,7 +213,6 @@ package spacewire is itimeout : std_logic_vector(7 downto 0); ienexttime : std_ulogic; --time iface - tickin_done : std_ulogic; tickout : std_ulogic; timeout : std_logic_vector(7 downto 0); --external interface @@ -197,6 +221,7 @@ package spacewire is etxfull : std_ulogic; etxafull : std_ulogic; erxchar : std_logic_vector(8 downto 0); + --memory errors merror : std_ulogic; end record; @@ -204,25 +229,43 @@ package spacewire is type grspw_router_time_type is array (0 to 30) of std_logic_vector(7 downto 0); type grspw_router_in_type is record - rmapen : std_logic_vector(30 downto 0); - idivisor : std_logic_vector(7 downto 0); - txwrite : std_logic_vector(30 downto 0); - txchar : grspw_router_fifo_char_type; - rxread : std_logic_vector(30 downto 0); - tickin : std_logic_vector(30 downto 0); - timein : grspw_router_time_type; - reload : std_logic_vector(31 downto 0); - reloadn : std_logic_vector(9 downto 0); - timeren : std_ulogic; - timecodeen : std_ulogic; - cfglock : std_ulogic; - selfaddren : std_ulogic; - linkstartreq : std_ulogic; - autodconnect : std_ulogic; - instanceid : std_logic_vector(7 downto 0); - enbridge : std_logic_vector(30 downto 0); - enexttime : std_logic_vector(30 downto 0); - nodeaddr : std_logic_vector(7 downto 0); + rmapen : std_logic_vector(30 downto 0); + idivisor : std_logic_vector(7 downto 0); + txwrite : std_logic_vector(30 downto 0); + txchar : grspw_router_fifo_char_type; + rxread : std_logic_vector(30 downto 0); + tickin : std_logic_vector(30 downto 0); + timein : grspw_router_time_type; + reload : std_logic_vector(31 downto 0); + reloadn : std_logic_vector(31 downto 0); + timeren : std_ulogic; + timecodeen : std_ulogic; + cfglock : std_ulogic; + selfaddren : std_ulogic; + linkstartreq : std_logic_vector(31 downto 1); + autodconnect : std_logic_vector(31 downto 1); + instanceid : std_logic_vector(7 downto 0); + enbridge : std_logic_vector(30 downto 0); + enexttime : std_logic_vector(30 downto 0); + auxtickin : std_ulogic; + auxtimeinen : std_ulogic; + auxtimein : std_logic_vector(7 downto 0); + irqtimeoutreload : std_logic_vector(31 downto 0); + ahbso : ahb_slv_out_type; + interruptcodeen : std_ulogic; + pnpen : std_ulogic; + timecodefilt : std_ulogic; + interruptfwd : std_ulogic; + spillifnrdy : std_logic_vector(31 downto 1); + timecoderegen : std_ulogic; + gpi : std_logic_vector(127 downto 0); + staticrouteen : std_ulogic; + spwclklock : std_ulogic; + irqgenreload : std_logic_vector(31 downto 0); + -- input timing testing + testd : std_logic_vector(61 downto 0); + tests : std_logic_vector(61 downto 0); + testinput : std_ulogic; end record; type grspw_router_out_type is record @@ -231,24 +274,34 @@ package spacewire is txfull : std_logic_vector(30 downto 0); txafull : std_logic_vector(30 downto 0); rxchar : grspw_router_fifo_char_type; + auxtickout : std_ulogic; + auxtimeout : std_logic_vector(7 downto 0); tickout : std_logic_vector(30 downto 0); timeout : grspw_router_time_type; - merror : std_ulogic; gerror : std_ulogic; lerror : std_ulogic; + merror : std_ulogic; linkrun : std_logic_vector(30 downto 0); + porterr : std_logic_vector(31 downto 0); + spwen : std_logic_vector(30 downto 0); + ahbsi : ahb_slv_in_type; + powerdown : std_logic_vector(30 downto 0); + powerdownrx : std_logic_vector(30 downto 0); + gpo : std_logic_vector(127 downto 0); end record; constant grspw_router_in_none : grspw_router_in_type := ((others => '0'), (others => '0'), (others => '0'), (others => (others => '0')), (others => '0'), (others => '0'), (others => (others => '0')), (others => '0'), - (others => '0'), '0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'), - (others => '0'), (others => '0')); + (others => '0'), '0', '0', '0', '0', (others => '0') , (others => '0'), (others => '0'), (others => '0'), + (others => '0'), '0', '0', (others => '0'), (others => '0'), ahbs_none, '0', '0', '0', '0', + (others => '0'), '0', (others => '0'), '0', '1', (others => '0'), (others => '0'), (others => '0'), '0'); constant grspw_router_out_none : grspw_router_out_type := ((others => '0'), (others => '0'), (others => '0'), (others => '0'), - (others => (others => '0')), (others => '0'), (others => (others => '0')), '0', - '0', '0', (others => '0')); + (others => (others => '0')), '0', (others => '0'), (others => '0'), (others => (others => '0')), '0', + '0', '0', (others => '0'), (others => '0'), (others => '0'), ahbs_in_none, + (others => '0'), (others => '0'), (others => '0')); type spw_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type; @@ -295,38 +348,55 @@ package spacewire is dconnect : out std_logic_vector(1 downto 0); rxclko : out std_ulogic; testrst : in std_ulogic := '0'; - testen : in std_ulogic := '0' + testen : in std_ulogic := '0'; + -- input timing testing + testdo : out std_logic_vector(1 downto 0); + testso : out std_logic_vector(1 downto 0) ); end component; component grspw2 is generic( - tech : integer range 0 to NTECH := inferred; - hindex : integer range 0 to NAHBMST-1 := 0; - pindex : integer range 0 to NAPBSLV-1 := 0; - paddr : integer range 0 to 16#FFF# := 0; - pmask : integer range 0 to 16#FFF# := 16#FFF#; - pirq : integer range 0 to NAHBIRQ-1 := 0; - rmap : integer range 0 to 2 := 0; - rmapcrc : integer range 0 to 1 := 0; - fifosize1 : integer range 4 to 32 := 32; - fifosize2 : integer range 16 to 64 := 64; - rxclkbuftype : integer range 0 to 2 := 0; - rxunaligned : integer range 0 to 1 := 0; - rmapbufs : integer range 2 to 8 := 4; - ft : integer range 0 to 2 := 0; - scantest : integer range 0 to 1 := 0; - techfifo : integer range 0 to 1 := 1; - ports : integer range 1 to 2 := 1; - dmachan : integer range 1 to 4 := 1; - memtech : integer range 0 to NTECH := DEFMEMTECH; - input_type : integer range 0 to 4 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - netlist : integer range 0 to 1 := 0; - nodeaddr : integer range 0 to 255 := 254; - destkey : integer range 0 to 255 := 0 - ); + tech : integer range 0 to NTECH := inferred; + hindex : integer range 0 to NAHBMST-1 := 0; + pindex : integer range 0 to NAPBSLV-1 := 0; + paddr : integer range 0 to 16#FFF# := 0; + pmask : integer range 0 to 16#FFF# := 16#FFF#; + pirq : integer range 0 to NAHBIRQ-1 := 0; + rmap : integer range 0 to 2 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 64 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxclkbuftype : integer range 0 to 2 := 0; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + ft : integer range 0 to 2 := 0; + scantest : integer range 0 to 1 := 0; + techfifo : integer range 0 to 1 := 1; + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; + memtech : integer range 0 to NTECH := DEFMEMTECH; + input_type : integer range 0 to 4 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + netlist : integer range 0 to 1 := 0; + nodeaddr : integer range 0 to 255 := 254; + destkey : integer range 0 to 255 := 0; + interruptdist : integer range 0 to 32 := 0; + intscalerbits : integer range 0 to 31 := 0; + intisrtimerbits : integer range 0 to 31 := 0; + intiatimerbits : integer range 0 to 31 := 0; + intctimerbits : integer range 0 to 31 := 0; + tickinasync : integer range 0 to 1 := 0; + pnp : integer range 0 to 2 := 0; + pnpvendid : integer range 0 to 16#FFFF# := 0; + pnpprodid : integer range 0 to 16#FFFF# := 0; + pnpmajorver : integer range 0 to 16#FF# := 0; + pnpminorver : integer range 0 to 16#FF# := 0; + pnppatch : integer range 0 to 16#FF# := 0; + num_txdesc : integer range 64 to 512 := 64; + num_rxdesc : integer range 128 to 1024 := 128 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -388,35 +458,49 @@ package spacewire is component grspwm is generic( - tech : integer range 0 to NTECH := DEFFABTECH; - hindex : integer range 0 to NAHBMST-1 := 0; - pindex : integer range 0 to NAPBSLV-1 := 0; - paddr : integer range 0 to 16#FFF# := 0; - pmask : integer range 0 to 16#FFF# := 16#FFF#; - pirq : integer range 0 to NAHBIRQ-1 := 0; - sysfreq : integer := 10000; - usegen : integer range 0 to 1 := 1; - nsync : integer range 1 to 2 := 1; - rmap : integer range 0 to 2 := 0; - rmapcrc : integer range 0 to 1 := 0; - fifosize1 : integer range 4 to 32 := 32; - fifosize2 : integer range 16 to 64 := 64; - rxclkbuftype : integer range 0 to 2 := 0; - rxunaligned : integer range 0 to 1 := 0; - rmapbufs : integer range 2 to 8 := 4; - ft : integer range 0 to 2 := 0; - scantest : integer range 0 to 1 := 0; - techfifo : integer range 0 to 1 := 1; - netlist : integer range 0 to 1 := 0; - ports : integer range 1 to 2 := 1; - dmachan : integer range 1 to 4 := 1; - memtech : integer range 0 to NTECH := DEFMEMTECH; - spwcore : integer range 1 to 2 := 2; - input_type : integer range 0 to 4 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - nodeaddr : integer range 0 to 255 := 254; - destkey : integer range 0 to 255 := 0 + tech : integer range 0 to NTECH := DEFFABTECH; + hindex : integer range 0 to NAHBMST-1 := 0; + pindex : integer range 0 to NAPBSLV-1 := 0; + paddr : integer range 0 to 16#FFF# := 0; + pmask : integer range 0 to 16#FFF# := 16#FFF#; + pirq : integer range 0 to NAHBIRQ-1 := 0; + sysfreq : integer := 10000; -- spw1 + usegen : integer range 0 to 1 := 1; -- spw1 + nsync : integer range 1 to 2 := 1; + rmap : integer range 0 to 2 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 64 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxclkbuftype : integer range 0 to 2 := 0; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + ft : integer range 0 to 2 := 0; + scantest : integer range 0 to 1 := 0; + techfifo : integer range 0 to 1 := 1; + netlist : integer range 0 to 1 := 0; -- spw1 + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; -- spw2 + memtech : integer range 0 to NTECH := DEFMEMTECH; + spwcore : integer range 1 to 2 := 2; + input_type : integer range 0 to 4 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + nodeaddr : integer range 0 to 255 := 254; + destkey : integer range 0 to 255 := 0; + interruptdist : integer range 0 to 32 := 0; -- spw2 + intscalerbits : integer range 0 to 31 := 0; -- spw2 + intisrtimerbits : integer range 0 to 31 := 0; -- spw2 + intiatimerbits : integer range 0 to 31 := 0; -- spw2 + intctimerbits : integer range 0 to 31 := 0; -- spw2 + tickinasync : integer range 0 to 2 := 0; -- spw2 + pnp : integer range 0 to 2 := 0; -- spw2 + pnpvendid : integer range 0 to 16#FFF# := 0; -- spw2 + pnpprodid : integer range 0 to 16#FFF# := 0; -- spw2 + pnpmajorver : integer range 0 to 16#FF# := 0; -- spw2 + pnpminorver : integer range 0 to 16#FF# := 0; -- spw2 + pnppatch : integer range 0 to 16#FF# := 0; -- spw2 + num_txdesc : integer range 64 to 512 := 64; -- spw2 + num_rxdesc : integer range 128 to 1024 := 128 -- spw2 ); port( rst : in std_ulogic; @@ -444,7 +528,8 @@ package spacewire is tech : integer; scantest : integer range 0 to 1 := 0; techfifo : integer range 0 to 1 := 0; - ft : integer range 0 to 2 := 0 + ft : integer range 0 to 2 := 0; + inputtest : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -461,7 +546,7 @@ package spacewire is ); end component; -component grspw_codec_clockgate is + component grspw_codec_clockgate is generic( tech : integer; scantest : integer range 0 to 1 := 0; @@ -492,49 +577,63 @@ component grspw_codec_clockgate is ); end component; + component grspwrouter is generic( - input_type : integer range 0 to 4 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - fifosize : integer range 16 to 2048 := 64; - tech : integer; - scantest : integer range 0 to 1 := 0; - techfifo : integer range 0 to 255 := 0; - ft : integer range 0 to 2 := 0; - spwen : integer range 0 to 1 := 1; - ambaen : integer range 0 to 1 := 0; - fifoen : integer range 0 to 1 := 0; - spwports : integer range 0 to 31 := 2; - ambaports : integer range 0 to 16 := 0; - fifoports : integer range 0 to 31 := 0; - arbitration : integer range 0 to 1 := 0; --0=rrobin, 1=priority - rmap : integer range 0 to 16#FFFF# := 0; - rmapcrc : integer range 0 to 16#FFFF# := 0; - fifosize2 : integer range 4 to 32 := 32; - almostsize : integer range 1 to 32 := 8; - rxunaligned : integer range 0 to 16#FFFF# := 0; - rmapbufs : integer range 2 to 8 := 4; - dmachan : integer range 1 to 4 := 1; - hindex : integer range 0 to NAHBMST-1 := 0; - pindex : integer range 0 to NAPBSLV-1 := 0; - paddr : integer range 0 to 16#FFF# := 0; - pmask : integer range 0 to 16#FFF# := 16#FFF#; - pirq : integer range 0 to NAHBIRQ-1 := 0; - cfghindex : integer range 0 to NAHBSLV-1 := 0; - cfghaddr : integer range 0 to 16#FFF# := 0; - cfghmask : integer range 0 to 16#FFF# := 16#FF0#; - ahbslven : integer range 0 to 1 := 0; - timerbits : integer range 0 to 31 := 0; - pnp : integer range 0 to 1 := 0; - autoscrub : integer range 0 to 1 := 0; - sim : integer range 0 to 1 := 0; - dualport : integer range 0 to 1 := 0; - charcntbits : integer range 0 to 32 := 0; - pktcntbits : integer range 0 to 32 := 0; - prescalermin : integer := 250; - simple : integer range 0 to 1 := 0; - nodeaddr : integer range 0 to 255 := 254 + input_type : integer range 0 to 4 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + fifosize : integer range 16 to 2048 := 64; + tech : integer; + scantest : integer range 0 to 1 := 0; + techfifo : integer range 0 to 255 := 0; + ft : integer range 0 to 2 := 0; + spwen : integer range 0 to 1 := 1; + ambaen : integer range 0 to 1 := 0; + fifoen : integer range 0 to 1 := 0; + spwports : integer range 0 to 31 := 2; + ambaports : integer range 0 to 16 := 0; + fifoports : integer range 0 to 31 := 0; + arbitration : integer range 0 to 1 := 0; --0=rrobin, 1=priority + rmap : integer range 0 to 16#FFFF# := 0; + rmapcrc : integer range 0 to 16#FFFF# := 0; + fifosize2 : integer range 4 to 32 := 32; + almostsize : integer range 1 to 32 := 8; + rxunaligned : integer range 0 to 16#FFFF# := 0; + rmapbufs : integer range 2 to 8 := 4; + dmachan : integer range 1 to 4 := 1; + hindex : integer range 0 to NAHBMST-1 := 0; + pindex : integer range 0 to NAPBSLV-1 := 0; + paddr : integer range 0 to 16#FFF# := 0; + pmask : integer range 0 to 16#FFF# := 16#FFF#; + pirq : integer range 0 to NAHBIRQ-1 := 0; + cfghindex : integer range 0 to NAHBSLV-1 := 0; + cfghaddr : integer range 0 to 16#FFF# := 0; + cfghmask : integer range 0 to 16#FFF# := 16#FF0#; + ahbslven : integer range 0 to 1 := 0; + timerbits : integer range 0 to 31 := 0; + pnp : integer range 0 to 2 := 0; + autoscrub : integer range 0 to 1 := 0; + sim : integer range 0 to 1 := 0; + dualport : integer range 0 to 1 := 0; + charcntbits : integer range 0 to 32 := 0; + pktcntbits : integer range 0 to 32 := 0; + prescalermin : integer := 250; + spacewired : integer range 0 to 1 := 0; + interruptdist : integer range 0 to 1 := 0; + apbctrl : integer range 0 to 1 := 0; + rmapmaxsize : integer range 4 to 512 := 4; + gpolbits : integer range 0 to 128 := 0; + gpopbits : integer range 0 to 128 := 0; + gpibits : integer range 0 to 128 := 0; + customport : integer range 0 to 1 := 0; + codecclkgate : integer range 0 to 1 := 0; + inputtest : integer range 0 to 1 := 0; + spwpnpvendid : integer range 0 to 16#FFFF# := 0; + spwpnpprodid : integer range 0 to 16#FFFF# := 0; + porttimerbits : integer range 1 to 32 := 10; + irqtimerbits : integer range 1 to 32 := 10; + auxtimeen : integer range 0 to 1 := 1 ); port( rst : in std_ulogic; @@ -621,4 +720,42 @@ component grspw_codec_clockgate is ); end component; + type grspw_router_fifo_in_type is record + txwrite : std_ulogic; + txchar : std_logic_vector(8 downto 0); + rxread : std_ulogic; + tickin : std_ulogic; + timein : std_logic_vector(7 downto 0); + enbridge : std_ulogic; + enexttime : std_ulogic; + end record; + + type grspw_router_fifo_out_type is record + rxcharav : std_ulogic; + rxaempty : std_ulogic; + txfull : std_ulogic; + txafull : std_ulogic; + rxchar : std_logic_vector(8 downto 0); + tickout : std_ulogic; + timeout : std_logic_vector(7 downto 0); + end record; + + component grspw2_sist is + generic( + pindex : integer range 0 to NAPBSLV-1:= 0; + pirq : integer range 0 to NAHBIRQ-1 := 0; + paddr : integer range 0 to 16#FFF# := 0; + pmask : integer range 0 to 16#FFF# := 16#FFF#); + port( + rstn : in std_ulogic; + clk : in std_ulogic; + enable : in std_ulogic; + -- amba apb + apbi : in apb_slv_in_type; + apbo : out apb_slv_out_type; + -- fifo i/f + fifoi : in grspw_router_fifo_out_type; + fifoo : out grspw_router_fifo_in_type); + end component; + end package; diff --git a/lib/gaisler/spacewire/vhdlsyn.txt b/lib/gaisler/spacewire/vhdlsyn.txt index b89799ca..53b62b81 100644 --- a/lib/gaisler/spacewire/vhdlsyn.txt +++ b/lib/gaisler/spacewire/vhdlsyn.txt @@ -9,3 +9,4 @@ grspw_codec_clockgate.vhd grspw_codec.vhd grspwrouter.vhd grspw_phy.vhd +grspw2_sist.vhd diff --git a/lib/gaisler/spi/spi.vhd b/lib/gaisler/spi/spi.vhd index f2bcd83a..98bcff29 100644 --- a/lib/gaisler/spi/spi.vhd +++ b/lib/gaisler/spi/spi.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spi2ahb.vhd b/lib/gaisler/spi/spi2ahb.vhd index 00009cd8..215722d0 100644 --- a/lib/gaisler/spi/spi2ahb.vhd +++ b/lib/gaisler/spi/spi2ahb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spi2ahb_apb.vhd b/lib/gaisler/spi/spi2ahb_apb.vhd index 606cee27..13efa59d 100644 --- a/lib/gaisler/spi/spi2ahb_apb.vhd +++ b/lib/gaisler/spi/spi2ahb_apb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spi2ahbx.vhd b/lib/gaisler/spi/spi2ahbx.vhd index fd3355b5..1f9c8fcf 100644 --- a/lib/gaisler/spi/spi2ahbx.vhd +++ b/lib/gaisler/spi/spi2ahbx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spi_flash.vhd b/lib/gaisler/spi/spi_flash.vhd index 98405a09..d8caf5f5 100644 --- a/lib/gaisler/spi/spi_flash.vhd +++ b/lib/gaisler/spi/spi_flash.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spictrl.vhd b/lib/gaisler/spi/spictrl.vhd index 28cef499..b9504e65 100644 --- a/lib/gaisler/spi/spictrl.vhd +++ b/lib/gaisler/spi/spictrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spictrlx.vhd b/lib/gaisler/spi/spictrlx.vhd index 1159f341..1da2a693 100644 --- a/lib/gaisler/spi/spictrlx.vhd +++ b/lib/gaisler/spi/spictrlx.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/spi/spimctrl.vhd b/lib/gaisler/spi/spimctrl.vhd index c5fb7bf1..bed49859 100644 --- a/lib/gaisler/spi/spimctrl.vhd +++ b/lib/gaisler/spi/spimctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/libmmu.vhd b/lib/gaisler/srmmu/libmmu.vhd index 92fcd4de..cfeaa3c3 100644 --- a/lib/gaisler/srmmu/libmmu.vhd +++ b/lib/gaisler/srmmu/libmmu.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmu.vhd b/lib/gaisler/srmmu/mmu.vhd index 07f8c2de..ff86282f 100644 --- a/lib/gaisler/srmmu/mmu.vhd +++ b/lib/gaisler/srmmu/mmu.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmuconfig.vhd b/lib/gaisler/srmmu/mmuconfig.vhd index 9c1ebac6..67f318da 100644 --- a/lib/gaisler/srmmu/mmuconfig.vhd +++ b/lib/gaisler/srmmu/mmuconfig.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmuiface.vhd b/lib/gaisler/srmmu/mmuiface.vhd index 8344f602..c544ce80 100644 --- a/lib/gaisler/srmmu/mmuiface.vhd +++ b/lib/gaisler/srmmu/mmuiface.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmulru.vhd b/lib/gaisler/srmmu/mmulru.vhd index 6f54e71a..791509c8 100644 --- a/lib/gaisler/srmmu/mmulru.vhd +++ b/lib/gaisler/srmmu/mmulru.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmulrue.vhd b/lib/gaisler/srmmu/mmulrue.vhd index b56b459c..5ca0829b 100644 --- a/lib/gaisler/srmmu/mmulrue.vhd +++ b/lib/gaisler/srmmu/mmulrue.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmutlb.vhd b/lib/gaisler/srmmu/mmutlb.vhd index f0d04ec5..588aad94 100644 --- a/lib/gaisler/srmmu/mmutlb.vhd +++ b/lib/gaisler/srmmu/mmutlb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmutlbcam.vhd b/lib/gaisler/srmmu/mmutlbcam.vhd index adaacedf..3d063629 100644 --- a/lib/gaisler/srmmu/mmutlbcam.vhd +++ b/lib/gaisler/srmmu/mmutlbcam.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/srmmu/mmutw.vhd b/lib/gaisler/srmmu/mmutw.vhd index bde37e88..652dea0a 100644 --- a/lib/gaisler/srmmu/mmutw.vhd +++ b/lib/gaisler/srmmu/mmutw.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/uart/ahbuart.vhd b/lib/gaisler/uart/ahbuart.vhd index 65f76b10..a475d2f5 100644 --- a/lib/gaisler/uart/ahbuart.vhd +++ b/lib/gaisler/uart/ahbuart.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/uart/apbuart.vhd b/lib/gaisler/uart/apbuart.vhd index 27d6545e..3ed327fa 100644 --- a/lib/gaisler/uart/apbuart.vhd +++ b/lib/gaisler/uart/apbuart.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/uart/dcom.vhd b/lib/gaisler/uart/dcom.vhd index 0dcb41ce..d375a0d5 100644 --- a/lib/gaisler/uart/dcom.vhd +++ b/lib/gaisler/uart/dcom.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -139,6 +139,8 @@ begin end if; else vdmai.start := '1'; end if; v.clen := "00"; + when others => + v.state := idle; v.write := '0'; end case; if (not RESET_ALL) and (uarto.lock and rst) = '0' then diff --git a/lib/gaisler/uart/dcom_uart.vhd b/lib/gaisler/uart/dcom_uart.vhd index 0c37bac7..d83a197a 100644 --- a/lib/gaisler/uart/dcom_uart.vhd +++ b/lib/gaisler/uart/dcom_uart.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -238,7 +238,8 @@ begin if r.txtick = '1' then v.tshift := '1' & r.tshift(10 downto 1); v.txstate := idle; end if; - + when others => + v.txstate := idle; end case; -- writing of tx data register must be done after tx fsm to get correct @@ -292,7 +293,8 @@ begin end if; v.rxstate := idle; end if; - + when others => + v.rxstate := idle; end case; -- reset operation diff --git a/lib/gaisler/uart/libdcom.vhd b/lib/gaisler/uart/libdcom.vhd index fdc758e1..7ed7a515 100644 --- a/lib/gaisler/uart/libdcom.vhd +++ b/lib/gaisler/uart/libdcom.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/uart/uart.vhd b/lib/gaisler/uart/uart.vhd index 0d29b3f6..20d91498 100644 --- a/lib/gaisler/uart/uart.vhd +++ b/lib/gaisler/uart/uart.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/gaisler/usb/grusb.vhd b/lib/gaisler/usb/grusb.vhd index 0d56f3ce..bf25b1f7 100644 --- a/lib/gaisler/usb/grusb.vhd +++ b/lib/gaisler/usb/grusb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/ahbctrl.vhd b/lib/grlib/amba/ahbctrl.vhd index 8da8a1a4..7c6c9caa 100644 --- a/lib/grlib/amba/ahbctrl.vhd +++ b/lib/grlib/amba/ahbctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/ahbmst.vhd b/lib/grlib/amba/ahbmst.vhd index d8f58f40..49233af9 100644 --- a/lib/grlib/amba/ahbmst.vhd +++ b/lib/grlib/amba/ahbmst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/amba.vhd b/lib/grlib/amba/amba.vhd index ac8a540e..2cc8eef8 100644 --- a/lib/grlib/amba/amba.vhd +++ b/lib/grlib/amba/amba.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -17,11 +17,11 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- --- Package: amba --- File: amba.vhd --- Author: Jiri Gaisler, Gaisler Research +-- Package: amba +-- File: amba.vhd +-- Author: Jiri Gaisler, Gaisler Research -- Modified by: Jan Andersson, Aeroflex Gaisler --- Description: AMBA 2.0 bus signal definitions + support for plug&play +-- Description: AMBA 2.0 bus signal definitions + support for plug&play ------------------------------------------------------------------------------ library ieee; @@ -89,65 +89,65 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; -- AHB master inputs type ahb_mst_in_type is record - hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant - hready : std_ulogic; -- transfer done - hresp : std_logic_vector(1 downto 0); -- response type - hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus - hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus - testen : std_ulogic; -- scan test enable - testrst : std_ulogic; -- scan test reset - scanen : std_ulogic; -- scan enable - testoen : std_ulogic; -- test output enable + hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant + hready : std_ulogic; -- transfer done + hresp : std_logic_vector(1 downto 0); -- response type + hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus + hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus + testen : std_ulogic; -- scan test enable + testrst : std_ulogic; -- scan test reset + scanen : std_ulogic; -- scan enable + testoen : std_ulogic; -- test output enable testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams end record; -- AHB master outputs type ahb_mst_out_type is record - hbusreq : std_ulogic; -- bus request - hlock : std_ulogic; -- lock request - htrans : std_logic_vector(1 downto 0); -- transfer type - haddr : std_logic_vector(31 downto 0); -- address bus (byte) - hwrite : std_ulogic; -- read/write - hsize : std_logic_vector(2 downto 0); -- transfer size - hburst : std_logic_vector(2 downto 0); -- burst type - hprot : std_logic_vector(3 downto 0); -- protection control - hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus - hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus - hconfig : ahb_config_type; -- memory access reg. - hindex : integer range 0 to NAHBMST-1; -- diagnostic use only + hbusreq : std_ulogic; -- bus request + hlock : std_ulogic; -- lock request + htrans : std_logic_vector(1 downto 0); -- transfer type + haddr : std_logic_vector(31 downto 0); -- address bus (byte) + hwrite : std_ulogic; -- read/write + hsize : std_logic_vector(2 downto 0); -- transfer size + hburst : std_logic_vector(2 downto 0); -- burst type + hprot : std_logic_vector(3 downto 0); -- protection control + hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus + hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus + hconfig : ahb_config_type; -- memory access reg. + hindex : integer range 0 to NAHBMST-1; -- diagnostic use only end record; -- AHB slave inputs type ahb_slv_in_type is record - hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select - haddr : std_logic_vector(31 downto 0); -- address bus (byte) - hwrite : std_ulogic; -- read/write - htrans : std_logic_vector(1 downto 0); -- transfer type - hsize : std_logic_vector(2 downto 0); -- transfer size - hburst : std_logic_vector(2 downto 0); -- burst type - hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus - hprot : std_logic_vector(3 downto 0); -- protection control - hready : std_ulogic; -- transfer done - hmaster : std_logic_vector(3 downto 0); -- current master - hmastlock : std_ulogic; -- locked access - hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select - hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus - testen : std_ulogic; -- scan test enable - testrst : std_ulogic; -- scan test reset - scanen : std_ulogic; -- scan enable - testoen : std_ulogic; -- test output enable + hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select + haddr : std_logic_vector(31 downto 0); -- address bus (byte) + hwrite : std_ulogic; -- read/write + htrans : std_logic_vector(1 downto 0); -- transfer type + hsize : std_logic_vector(2 downto 0); -- transfer size + hburst : std_logic_vector(2 downto 0); -- burst type + hwdata : std_logic_vector(AHBDW-1 downto 0); -- write data bus + hprot : std_logic_vector(3 downto 0); -- protection control + hready : std_ulogic; -- transfer done + hmaster : std_logic_vector(3 downto 0); -- current master + hmastlock : std_ulogic; -- locked access + hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select + hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus + testen : std_ulogic; -- scan test enable + testrst : std_ulogic; -- scan test reset + scanen : std_ulogic; -- scan enable + testoen : std_ulogic; -- test output enable testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams end record; -- AHB slave outputs type ahb_slv_out_type is record - hready : std_ulogic; -- transfer done - hresp : std_logic_vector(1 downto 0); -- response type - hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus - hsplit : std_logic_vector(NAHBMST-1 downto 0); -- split completion - hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus - hconfig : ahb_config_type; -- memory access reg. - hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only + hready : std_ulogic; -- transfer done + hresp : std_logic_vector(1 downto 0); -- response type + hrdata : std_logic_vector(AHBDW-1 downto 0); -- read data bus + hsplit : std_logic_vector(NAHBMST-1 downto 0); -- split completion + hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus + hconfig : ahb_config_type; -- memory access reg. + hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only end record; -- array types @@ -157,6 +157,8 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; type ahb_slv_in_vector_type is array (natural range <>) of ahb_slv_in_type; subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0); subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0); + subtype ahb_mst_in_vector is ahb_mst_in_vector_type(NAHBMST-1 downto 0); + subtype ahb_slv_in_vector is ahb_slv_in_vector_type(NAHBSLV-1 downto 0); type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector; type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector; @@ -192,25 +194,25 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; -- APB slave inputs type apb_slv_in_type is record - psel : std_logic_vector(0 to NAPBSLV-1); -- slave select - penable : std_ulogic; -- strobe - paddr : std_logic_vector(31 downto 0); -- address bus (byte) - pwrite : std_ulogic; -- write - pwdata : std_logic_vector(31 downto 0); -- write data bus - pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus - testen : std_ulogic; -- scan test enable - testrst : std_ulogic; -- scan test reset - scanen : std_ulogic; -- scan enable - testoen : std_ulogic; -- test output enable + psel : std_logic_vector(0 to NAPBSLV-1); -- slave select + penable : std_ulogic; -- strobe + paddr : std_logic_vector(31 downto 0); -- address bus (byte) + pwrite : std_ulogic; -- write + pwdata : std_logic_vector(31 downto 0); -- write data bus + pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus + testen : std_ulogic; -- scan test enable + testrst : std_ulogic; -- scan test reset + scanen : std_ulogic; -- scan enable + testoen : std_ulogic; -- test output enable testin : std_logic_vector(NTESTINBITS-1 downto 0); -- test vector for syncrams end record; -- APB slave outputs type apb_slv_out_type is record - prdata : std_logic_vector(31 downto 0); -- read data bus - pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus - pconfig : apb_config_type; -- memory access reg. - pindex : integer range 0 to NAPBSLV -1; -- diag use only + prdata : std_logic_vector(31 downto 0); -- read data bus + pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus + pconfig : apb_config_type; -- memory access reg. + pindex : integer range 0 to NAPBSLV -1; -- diag use only end record; -- array types @@ -256,16 +258,16 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; ------------------------------------------------------------------------------- function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type; - cfgver : amba_cfgver_type; version : amba_version_type; + cfgver : amba_cfgver_type; version : amba_version_type; interrupt : amba_irq_type) return std_logic_vector; function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic; - addrmask : ahb_addr_type) + addrmask : ahb_addr_type) return std_logic_vector; function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic; - addrmask : ahb_addr_type; enable : integer) + addrmask : ahb_addr_type; enable : integer) return std_logic_vector; function ahb_iobar(memaddr : ahb_addr_type; addrmask : ahb_addr_type) @@ -396,9 +398,9 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; component ahbctrl generic ( - defmast : integer := 0; -- default master - split : integer := 0; -- split support - rrobin : integer := 0; -- round-robin arbitration + defmast : integer := 0; -- default master + split : integer := 0; -- split support + rrobin : integer := 0; -- round-robin arbitration timeout : integer range 0 to 255 := 0; -- HREADY timeout ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address iomask : ahb_addr_type := 16#fff#; -- I/O area address mask @@ -412,7 +414,7 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; debug : integer range 0 to 2 := 2; -- print config to console fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding icheck : integer range 0 to 1 := 1; - devid : integer := 0; -- unique device ID + devid : integer := 0; -- unique device ID enbusmon : integer range 0 to 1 := 0; --enable bus monitor assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings asserterr : integer range 0 to 1 := 0; --enable assertions for errors @@ -443,6 +445,57 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; ); end component; +component ahbxb is + generic( + defmast : integer := 0; -- default master + timeout : integer range 0 to 255 := 0; -- HREADY timeout + ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address + iomask : ahb_addr_type := 16#fff#; -- I/O area address mask + cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address + cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask + nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters + nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves + ioen : integer range 0 to 15 := 1; -- enable I/O area + disirq : integer range 0 to 1 := 0; -- disable interrupt routing + fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts + debug : integer range 0 to 2 := 2; -- report cores to console + fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding + icheck : integer range 0 to 1 := 1; + devid : integer := 0; -- unique device ID + enbusmon : integer range 0 to 1 := 0; --enable bus monitor + assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings + asserterr : integer range 0 to 1 := 0; --enable assertions for errors + hmstdisable : integer := 0; --disable master checks + hslvdisable : integer := 0; --disable slave checks + arbdisable : integer := 0; --disable arbiter checks + mprio : integer := 0; --master with highest priority + mcheck : integer range 0 to 2 := 1; --check memory map for intersects + ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config + index : integer := 0; --Index for trace print-out + ahbtrace : integer := 0; --AHB trace enable + hwdebug : integer := 0; --Hardware debug + fourgslv : integer := 0; --1=Single slave with single 4 GB bar + l2en : integer := 0; --enable l2 cache multiport decoding + l2bhindex : integer range 0 to NAHBSLV := 0; --base index for the l2 cache slaves + l2num : integer := 4; --Å„umber of l2 caches in system + l2linesize : integer := 32;--number of bytes in an l2 cache line + l2hmbsel : integer := 0 --index of L2 memory back + ); + port( + rst : in std_ulogic; + clk : in std_ulogic; + msti : out ahb_mst_in_vector; + msto : in ahb_mst_out_vector; + slvi : out ahb_slv_in_vector; + slvo : in ahb_slv_out_vector; + testen : in std_ulogic := '0'; + testrst : in std_ulogic := '1'; + scanen : in std_ulogic := '0'; + testoen : in std_ulogic := '1'; + testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0') + ); + end component; + component apbctrl generic ( hindex : integer := 0; @@ -470,9 +523,9 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; component ahbctrl_mb generic ( - defmast : integer := 0; -- default master - split : integer := 0; -- split support - rrobin : integer := 0; -- round-robin arbitration + defmast : integer := 0; -- default master + split : integer := 0; -- split support + rrobin : integer := 0; -- round-robin arbitration timeout : integer range 0 to 255 := 0; -- HREADY timeout ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address iomask : ahb_addr_type := 16#fff#; -- I/O area address mask @@ -487,7 +540,7 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding busndx : integer range 0 to 3 := 0; icheck : integer range 0 to 1 := 1; - devid : integer := 0; -- unique device ID + devid : integer := 0; -- unique device ID enbusmon : integer range 0 to 1 := 0; --enable bus monitor assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings asserterr : integer range 0 to 1 := 0; --enable assertions for errors @@ -625,7 +678,7 @@ type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word; subtype device_description is string(1 to 31); type device_table_type is array (0 to 1023) of device_description; type vendor_library_type is record - vendorid : amba_vendor_type; + vendorid : amba_vendor_type; vendordesc : vendor_description; device_table : device_table_type; end record; @@ -638,7 +691,7 @@ end; package body amba is function ahb_device_reg(vendor : amba_vendor_type; device : amba_device_type; - cfgver : amba_cfgver_type; version : amba_version_type; + cfgver : amba_cfgver_type; version : amba_version_type; interrupt : amba_irq_type) return std_logic_vector is variable cfg : std_logic_vector(31 downto 0); @@ -656,7 +709,7 @@ package body amba is end; function ahb_membar(memaddr : ahb_addr_type; prefetch, cache : std_ulogic; - addrmask : ahb_addr_type) + addrmask : ahb_addr_type) return std_logic_vector is variable cfg : std_logic_vector(31 downto 0); begin @@ -668,7 +721,7 @@ package body amba is end; function ahb_membar_opt(memaddr : ahb_addr_type; prefetch, cache : std_ulogic; - addrmask : ahb_addr_type; enable : integer) + addrmask : ahb_addr_type; enable : integer) return std_logic_vector is variable cfg : std_logic_vector(31 downto 0); begin @@ -711,8 +764,8 @@ package body amba is for i in 0 to NAHBSLV-1 loop for j in NAHBAMR to NAHBCFG-1 loop if (ahbso(i).hconfig(j)(16) = '1') and - (ahbso(i).hconfig(j)(15 downto 4) /= "000000000000") - then + (ahbso(i).hconfig(j)(15 downto 4) /= "000000000000") + then if (haddr(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) = (ahbso(i).hconfig(j)(31 downto 20) and ahbso(i).hconfig(j)(15 downto 4)) then hcache := '1'; diff --git a/lib/grlib/amba/amba_tp.vhd b/lib/grlib/amba/amba_tp.vhd index a5abaec5..1005bcef 100644 --- a/lib/grlib/amba/amba_tp.vhd +++ b/lib/grlib/amba/amba_tp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -1023,7 +1023,7 @@ package body AMBA_TestPackage is -- data phase if AHBIn.HREADY='1' then if W='1' then - alow := A(1 downto 0); + alow := A(1 downto 0); case alow is when "00" => D := AHBIn.HWDATA(31 downto 24); diff --git a/lib/grlib/amba/apbctrl.vhd b/lib/grlib/amba/apbctrl.vhd index 263158a9..0993b46c 100644 --- a/lib/grlib/amba/apbctrl.vhd +++ b/lib/grlib/amba/apbctrl.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/defmst.vhd b/lib/grlib/amba/defmst.vhd index f168f459..91c4b145 100644 --- a/lib/grlib/amba/defmst.vhd +++ b/lib/grlib/amba/defmst.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/devices.vhd b/lib/grlib/amba/devices.vhd index 8bda406e..897c3d30 100644 --- a/lib/grlib/amba/devices.vhd +++ b/lib/grlib/amba/devices.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -17,10 +17,10 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- --- Entity: devices --- File: devices.vhd --- Author: Jiri Gaisler, Aeroflex Gaisler --- Description: Vendor and devices id's for amba plug&play +-- Entity: devices +-- File: devices.vhd +-- Author: Aeroflex Gaisler AB +-- Description: Vendor and devices IDs for AMBA plug&play ------------------------------------------------------------------------------ library ieee; @@ -46,6 +46,8 @@ package devices is constant VENDOR_DLR : amba_vendor_type := 16#0A#; constant VENDOR_EONIC : amba_vendor_type := 16#0B#; constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#; + constant VENDOR_DTU : amba_vendor_type := 16#0D#; + constant VENDOR_BSC : amba_vendor_type := 16#0E#; constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#; constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#; constant VENDOR_MENTA : amba_vendor_type := 16#11#; @@ -57,11 +59,12 @@ package devices is constant VENDOR_S3 : amba_vendor_type := 16#31#; constant VENDOR_ACTEL : amba_vendor_type := 16#AC#; constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#; + constant VENDOR_C3E : amba_vendor_type := 16#C3#; constant VENDOR_CAL : amba_vendor_type := 16#CA#; constant VENDOR_CETON : amba_vendor_type := 16#CB#; constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#; --- Aeroflex Gaisler device id's +-- Aeroflex Gaisler device ids constant GAISLER_LEON2DSU : amba_device_type := 16#002#; constant GAISLER_LEON3 : amba_device_type := 16#003#; @@ -205,7 +208,7 @@ package devices is constant GAISLER_GRPWRX : amba_device_type := 16#08E#; constant GAISLER_GPREGBANK : amba_device_type := 16#08F#; constant GAISLER_MIG_SERIES7 : amba_device_type := 16#090#; - constant GAISLER_SPWBIST : amba_device_type := 16#091#; + constant GAISLER_GRSPW2_SIST : amba_device_type := 16#091#; constant GAISLER_SGMII : amba_device_type := 16#092#; constant GAISLER_RGMII : amba_device_type := 16#093#; constant GAISLER_IRQGEN : amba_device_type := 16#094#; @@ -215,14 +218,14 @@ package devices is -- Sun Microsystems - constant SUN_T1 : amba_device_type := 16#001#; - constant SUN_S1 : amba_device_type := 16#011#; + constant SUN_T1 : amba_device_type := 16#001#; + constant SUN_S1 : amba_device_type := 16#011#; -- Caltech - constant CAL_DDRCTRL : amba_device_type := 16#188#; + constant CAL_DDRCTRL : amba_device_type := 16#188#; --- European Space Agency device id's +-- European Space Agency device ids constant ESA_LEON2 : amba_device_type := 16#002#; constant ESA_LEON2APB : amba_device_type := 16#003#; @@ -246,7 +249,7 @@ package devices is constant ESA_PDEC3AMBA : amba_device_type := 16#020#; constant ESA_PTME3AMBA : amba_device_type := 16#021#; --- OpenChip ID's +-- OpenChip IDs constant OPENCHIP_APBGPIO : amba_device_type := 16#001#; constant OPENCHIP_APBI2C : amba_device_type := 16#002#; @@ -264,7 +267,7 @@ package devices is constant OPENCHIP_APBSUI : amba_device_type := 16#00E#; --- Gleichmann's device id's +-- Gleichmann's device ids constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#; constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#; @@ -276,7 +279,18 @@ package devices is constant GLEICHMANN_SPIOC : amba_device_type := 16#008#; constant GLEICHMANN_AC97 : amba_device_type := 16#009#; --- Orbita device id's +-- DTU device ids + + constant DTU_IV : amba_device_type := 16#001#; + constant DTU_RBMMTRANS : amba_device_type := 16#002#; + constant DTU_FTMCTRL : amba_device_type := 16#054#; + +-- BSC device ids + + constant BSC_CORE1 : amba_device_type := 16#001#; + constant BSC_CORE2 : amba_device_type := 16#002#; + +-- Orbita device ids constant ORBITA_1553B : amba_device_type := 16#001#; constant ORBITA_429 : amba_device_type := 16#002#; @@ -309,12 +323,12 @@ package devices is constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#; constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#; --- Contribution library ID's +-- Contribution library IDs constant CONTRIB_CORE1 : amba_device_type := 16#001#; constant CONTRIB_CORE2 : amba_device_type := 16#002#; --- grlib system device id's +-- grlib system device ids subtype system_device_type is integer range 0 to 16#ffff#; @@ -335,9 +349,11 @@ package devices is constant LEON3_RTAX_CID7 : system_device_type := 16#0207#; constant LEON3_RTAX_CID8 : system_device_type := 16#0208#; constant LEON3_IHP25RH1 : system_device_type := 16#0251#; + constant LEON3_PROXIMA : system_device_type := 16#0252#; constant NGMP_PROTOTYPE : system_device_type := 16#0281#; constant NGMP_PROTOTYPE2 : system_device_type := 16#0282#; constant ALTERA_DE2 : system_device_type := 16#0302#; + constant ALTERA_DE4 : system_device_type := 16#0303#; constant XILINX_ML401 : system_device_type := 16#0401#; constant LEON3FT_GRXC4V : system_device_type := 16#0453#; constant XILINX_ML501 : system_device_type := 16#0501#; @@ -507,18 +523,17 @@ package devices is GAISLER_AHBFROM => "Flash ROM Memory ", GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ", GAISLER_MIG_SERIES7 => "Xilinx MIG DDR3 Controller ", - GAISLER_SPWBIST => "GRSPW Router BIST ", + GAISLER_GRSPW2_SIST => "GRSPW Router SIST ", GAISLER_SGMII => "XILINX SGMII Interface ", GAISLER_RGMII => "Gaisler RGMII Interface ", GAISLER_IRQGEN => "Interrupt generator ", GAISLER_GRDMAC => "DMA Controller with APB bridge ", GAISLER_AHB2AVLA => "Avalon-MM memory controller ", GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ", - others => "Unknown Device "); constant gaisler_lib : vendor_library_type := ( - vendorid => VENDOR_GAISLER, + vendorid => VENDOR_GAISLER, vendordesc => GAISLER_DESC, device_table => gaisler_device_table ); @@ -575,7 +590,7 @@ package devices is others => "Unknown Device "); constant openchip_lib : vendor_library_type := ( - vendorid => VENDOR_OPENCHIP, + vendorid => VENDOR_OPENCHIP, vendordesc => OPENCHIP_DESC, device_table => openchip_device_table ); @@ -590,8 +605,8 @@ package devices is GLEICHMANN_SPI => "SPI master ", GLEICHMANN_HIFC => "Human interface controller ", GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ", - GLEICHMANN_SPIOC => "SPI master for SDCard IF ", - GLEICHMANN_AC97 => "AC97 Controller ", + GLEICHMANN_SPIOC => "SPI master for SDCard IF ", + GLEICHMANN_AC97 => "AC97 Controller ", others => "Unknown Device "); constant gleichmann_lib : vendor_library_type := ( @@ -608,7 +623,7 @@ package devices is others => "Unknown Device "); constant contrib_lib : vendor_library_type := ( - vendorid => VENDOR_CONTRIB, + vendorid => VENDOR_CONTRIB, vendordesc => CONTRIB_DESC, device_table => contrib_device_table ); @@ -619,7 +634,7 @@ package devices is others => "Unknown Device "); constant menta_lib : vendor_library_type := ( - vendorid => VENDOR_MENTA, + vendorid => VENDOR_MENTA, vendordesc => MENTA_DESC, device_table => menta_device_table ); @@ -632,7 +647,7 @@ package devices is others => "Unknown Device "); constant sun_lib : vendor_library_type := ( - vendorid => VENDOR_SUN, + vendorid => VENDOR_SUN, vendordesc => SUN_DESC, device_table => sun_device_table ); @@ -643,7 +658,7 @@ package devices is others => "Unknown Device "); constant opencores_lib : vendor_library_type := ( - vendorid => VENDOR_OPENCORES, + vendorid => VENDOR_OPENCORES, vendordesc => OPENCORES_DESC, device_table => opencores_device_table ); @@ -654,7 +669,7 @@ package devices is others => "Unknown Device "); constant ceton_lib : vendor_library_type := ( - vendorid => VENDOR_CETON, + vendorid => VENDOR_CETON, vendordesc => CETON_DESC, device_table => ceton_device_table ); @@ -665,7 +680,7 @@ package devices is others => "Unknown Device "); constant synopsys_lib : vendor_library_type := ( - vendorid => VENDOR_SYNOPSYS, + vendorid => VENDOR_SYNOPSYS, vendordesc => SYNOPSYS_DESC, device_table => synopsys_device_table ); @@ -676,7 +691,7 @@ package devices is others => "Unknown Device "); constant embeddit_lib : vendor_library_type := ( - vendorid => VENDOR_EMBEDDIT, + vendorid => VENDOR_EMBEDDIT, vendordesc => EMBEDDIT_DESC, device_table => embeddit_device_table ); @@ -687,7 +702,7 @@ package devices is constant DLR_DESC : vendor_description := "German Aerospace Center "; constant dlr_lib : vendor_library_type := ( - vendorid => VENDOR_DLR, + vendorid => VENDOR_DLR, vendordesc => DLR_DESC, device_table => dlr_device_table ); @@ -698,7 +713,7 @@ package devices is constant EONIC_DESC : vendor_description := "Eonic BV "; constant eonic_lib : vendor_library_type := ( - vendorid => VENDOR_EONIC, + vendorid => VENDOR_EONIC, vendordesc => EONIC_DESC, device_table => eonic_device_table ); @@ -709,7 +724,7 @@ package devices is constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech "; constant telecompt_lib : vendor_library_type := ( - vendorid => VENDOR_TELECOMPT, + vendorid => VENDOR_TELECOMPT, vendordesc => TELECOMPT_DESC, device_table => telecompt_device_table ); @@ -719,12 +734,39 @@ package devices is constant RADIONOR_DESC : vendor_description := "Radionor Communications "; - constant radionor_lib : vendor_library_type := ( - vendorid => VENDOR_RADIONOR, + constant radionor_lib : vendor_library_type := ( + vendorid => VENDOR_RADIONOR, vendordesc => RADIONOR_DESC, device_table => radionor_device_table ); + constant bsc_device_table : device_table_type := ( + BSC_CORE1 => "Core 1 ", + BSC_CORE2 => "Core 2 ", + others => "Unknown Device "); + + constant BSC_DESC : vendor_description := "BSC "; + + constant bsc_lib : vendor_library_type := ( + vendorid => VENDOR_BSC, + vendordesc => BSC_DESC, + device_table => bsc_device_table + ); + + constant dtu_device_table : device_table_type := ( + DTU_IV => "Instrument Virtualizer ", + DTU_RBMMTRANS => "RB/MM Transfer ", + DTU_FTMCTRL => "Memory controller with 8CS ", + others => "Unknown Device "); + + constant DTU_DESC : vendor_description := "DTU Space "; + + constant dtu_lib : vendor_library_type := ( + vendorid => VENDOR_DTU, + vendordesc => DTU_DESC, + device_table => dtu_device_table + ); + constant orbita_device_table : device_table_type := ( ORBITA_1553B => "MIL-STD-1553B Controller ", ORBITA_429 => "429 Interface ", @@ -747,7 +789,7 @@ package devices is constant ORBITA_DESC : vendor_description := "Orbita "; constant orbita_lib : vendor_library_type := ( - vendorid => VENDOR_ORBITA, + vendorid => VENDOR_ORBITA, vendordesc => ORBITA_DESC, device_table => orbita_device_table ); @@ -759,7 +801,7 @@ package devices is others => "Unknown Device "); constant actel_lib : vendor_library_type := ( - vendorid => VENDOR_ACTEL, + vendorid => VENDOR_ACTEL, vendordesc => ACTEL_DESC, device_table => actel_device_table ); @@ -771,7 +813,7 @@ package devices is others => "Unknown Device "); constant nasa_lib : vendor_library_type := ( - vendorid => VENDOR_NASA, + vendorid => VENDOR_NASA, vendordesc => NASA_DESC, device_table => nasa_device_table ); @@ -782,7 +824,7 @@ package devices is others => "Unknown Device "); constant s3_lib : vendor_library_type := ( - vendorid => VENDOR_S3, + vendorid => VENDOR_S3, vendordesc => S3_DESC, device_table => s3_device_table ); @@ -793,18 +835,27 @@ package devices is APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ", others => "Unknown Device "); constant applecore_lib : vendor_library_type := ( - vendorid => VENDOR_APPLECORE, + vendorid => VENDOR_APPLECORE, vendordesc => APPLECORE_DESC, device_table => applecore_device_table ); + constant C3E_DESC : vendor_description := "TU Braunschweig C3E "; + constant c3e_device_table : device_table_type := ( + others => "Unknown Device "); + constant c3e_lib : vendor_library_type := ( + vendorid => VENDOR_C3E, + vendordesc => C3E_DESC, + device_table => c3e_device_table + ); + constant UNKNOWN_DESC : vendor_description := "Unknown vendor "; constant unknown_device_table : device_table_type := ( others => "Unknown Device "); constant unknown_lib : vendor_library_type := ( - vendorid => 0, + vendorid => 0, vendordesc => UNKNOWN_DESC, device_table => unknown_device_table ); @@ -842,7 +893,9 @@ package devices is LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ", LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ", LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ", + LEON3_PROXIMA => "LEON3 PROXIMA FPGA design ", ALTERA_DE2 => "Altera DE2 Development board ", + ALTERA_DE4 => "TerASIC DE4 Development board ", XILINX_ML401 => "Xilinx ML401 Development board ", XILINX_ML501 => "Xilinx ML501 Development board ", XILINX_ML505 => "Xilinx ML505 Development board ", diff --git a/lib/grlib/amba/dma2ahb.vhd b/lib/grlib/amba/dma2ahb.vhd index d6f36a8d..8c264bbe 100644 --- a/lib/grlib/amba/dma2ahb.vhd +++ b/lib/grlib/amba/dma2ahb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/dma2ahb_pkg.vhd b/lib/grlib/amba/dma2ahb_pkg.vhd index 9ecca990..fa58a1ef 100644 --- a/lib/grlib/amba/dma2ahb_pkg.vhd +++ b/lib/grlib/amba/dma2ahb_pkg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/dma2ahb_tp.vhd b/lib/grlib/amba/dma2ahb_tp.vhd index a2f01514..e02335b6 100644 --- a/lib/grlib/amba/dma2ahb_tp.vhd +++ b/lib/grlib/amba/dma2ahb_tp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/amba/vhdlsyn.txt b/lib/grlib/amba/vhdlsyn.txt index 04809514..1c291ea6 100644 --- a/lib/grlib/amba/vhdlsyn.txt +++ b/lib/grlib/amba/vhdlsyn.txt @@ -3,6 +3,7 @@ devices.vhd defmst.vhd apbctrl.vhd ahbctrl.vhd +ahbxb.vhd dma2ahb_pkg.vhd dma2ahb.vhd ahbmst.vhd diff --git a/lib/grlib/sparc/cpu_disas.vhd b/lib/grlib/sparc/cpu_disas.vhd index 39234c6e..99ca02e6 100644 --- a/lib/grlib/sparc/cpu_disas.vhd +++ b/lib/grlib/sparc/cpu_disas.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/sparc/sparc.vhd b/lib/grlib/sparc/sparc.vhd index c69a1ebf..8983f9b1 100644 --- a/lib/grlib/sparc/sparc.vhd +++ b/lib/grlib/sparc/sparc.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/sparc/sparc_disas.vhd b/lib/grlib/sparc/sparc_disas.vhd index 26cbb5c0..d607c7ae 100644 --- a/lib/grlib/sparc/sparc_disas.vhd +++ b/lib/grlib/sparc/sparc_disas.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/stdlib/config.vhd b/lib/grlib/stdlib/config.vhd index c3842e6e..c1b53c69 100644 --- a/lib/grlib/stdlib/config.vhd +++ b/lib/grlib/stdlib/config.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/stdlib/config_types.vhd b/lib/grlib/stdlib/config_types.vhd index 1d038377..4512b3f4 100644 --- a/lib/grlib/stdlib/config_types.vhd +++ b/lib/grlib/stdlib/config_types.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/stdlib/stdio.vhd b/lib/grlib/stdlib/stdio.vhd index 33711686..23aab1b8 100644 --- a/lib/grlib/stdlib/stdio.vhd +++ b/lib/grlib/stdlib/stdio.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/stdlib/stdio_tb.vhd b/lib/grlib/stdlib/stdio_tb.vhd index 6cab8288..9a2fc307 100644 --- a/lib/grlib/stdlib/stdio_tb.vhd +++ b/lib/grlib/stdlib/stdio_tb.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/stdlib/stdlib.vhd b/lib/grlib/stdlib/stdlib.vhd index 0ad00025..58478d16 100644 --- a/lib/grlib/stdlib/stdlib.vhd +++ b/lib/grlib/stdlib/stdlib.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -121,6 +121,8 @@ end component; -- pragma translate_on +function unary_to_slv(i: std_logic_vector) return std_logic_vector; + end; package body stdlib is @@ -617,8 +619,46 @@ procedure print(s : string) is begin L := new string'(s); writeline(output, L); end; - -- pragma translate_on + + function unary_to_slv(i: std_logic_vector) return std_logic_vector is + variable o : std_logic_vector(log2(i'length)-1 downto 0); + begin + +-- -- 16 bits unary to binary conversion +-- o(0) := i(1) or i(3) or i(5) or i(7) or i(9) or i(11) or i(13) or i(15); +-- o(1) := i(2) or i(3) or i(6) or i(7) or i(10) or i(11) or i(14) or i(15); +-- o(2) := i(4) or i(5) or i(6) or i(7) or i(12) or i(13) or i(14) or i(15); +-- o(3) := i(8) or i(9) or i(10) or i(11) or i(12) or i(13) or i(14) or i(15); +-- +-- -- parametrized conversion +-- +-- o(0) := i(1); +-- +-- o(0) := unary_to_slv(i(3 downto 2)) or unary_to_slv(i(1 downto 0)); +-- o(1) := orv(i(3 downto 2)); +-- +-- o(1 downto 0) := unary_to_slv(i(7 downto 4)) or unary_to_slv(i(3 downto 0)); +-- o(2) := orv(i(7 downto 4)); +-- +-- o(2 downto 0) := unary_to_slv(i(15 downto 8)) or unary_to_slv(i(7 downto 0)); +-- o(3) := orv(i(15 downto 8)); +-- + + assert i'length = 0 or i'length = 2**log2(i'length) + report "unary_to_slv: input vector size must be power of 2" + severity failure; + + if i'length > 2 then + -- recursion on left and right halves + o(log2(i'length)-2 downto 0) := unary_to_slv(i(i'left downto (i'left-i'length/2+1))) or unary_to_slv(i((i'left-i'length/2) downto i'right)); + o(log2(i'length)-1) := orv(i(i'left downto (i'left-i'length/2+1))); + else + o(0 downto 0) := ( 0 => i(i'left)); + end if; + + return o; + end unary_to_slv; end; diff --git a/lib/grlib/stdlib/testlib.vhd b/lib/grlib/stdlib/testlib.vhd index 2ad75201..43875a4c 100644 --- a/lib/grlib/stdlib/testlib.vhd +++ b/lib/grlib/stdlib/testlib.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/stdlib/version.vhd b/lib/grlib/stdlib/version.vhd index fafea4e1..bb1784fb 100644 --- a/lib/grlib/stdlib/version.vhd +++ b/lib/grlib/stdlib/version.vhd @@ -2,9 +2,9 @@ use std.textio.all; -- pragma translate_on package version is - constant grlib_version : integer := 1304; + constant grlib_version : integer := 1307; -- pragma translate_off - constant grlib_date : string := "20131219"; + constant grlib_date : string := "20140416"; -- pragma translate_on - constant grlib_build : integer := 4140; + constant grlib_build : integer := 4144; end; diff --git a/lib/grlib/util/fpudummy.vhd b/lib/grlib/util/fpudummy.vhd index 4f080e94..42d4203d 100644 --- a/lib/grlib/util/fpudummy.vhd +++ b/lib/grlib/util/fpudummy.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/grlib/util/util.vhd b/lib/grlib/util/util.vhd index 4c2a7258..ffee7433 100644 --- a/lib/grlib/util/util.vhd +++ b/lib/grlib/util/util.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/hynix/ddr2/HY5PS121621F.vhd b/lib/hynix/ddr2/HY5PS121621F.vhd deleted file mode 100644 index 6002d7a4..00000000 --- a/lib/hynix/ddr2/HY5PS121621F.vhd +++ /dev/null @@ -1,2768 +0,0 @@ ------------------------------------------------------- --- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM -- --- -- --- VHDL Modeling -- --- -- --- PART : HY5PS121621F-B400/B533/B667/B800 -- --- -- --- HHHH HHHH -- --- HHHH HHHH -- --- ,O0O. ,O0 .HH ,O0 .HH -- --- (O000O)(O00 )H(O00 )H -- --- `O0O' `O0 'HH `O0 'HH -- --- HHHH HHHH Hynix -- --- HHHH HHHH Semiconductor -- ------------------------------------------------------- --- Modified by Gaisler Research to use GRLIB libraries --- and to load initial memory data from a file. ---------------------------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.all; -use std.textio.all; -library grlib, gaisler; -use grlib.stdlib.all; -use grlib.stdio.all; ---USE IEEE.STD_LOGIC_ARITH.all; ---USE IEEE.STD_LOGIC_UNSIGNED.all; -USE work.HY5PS121621F_PACK.all; ---------------------------------------------------------------------------------------------------- - -Entity HY5PS121621F Is - generic ( - TimingCheckFlag : boolean := TRUE; - PUSCheckFlag : boolean := FALSE; - Part_Number : PART_NUM_TYPE := B400; - index : integer := 0; - bbits : natural := 64; - fname : string := "ram.srec"; - fdelay : integer := 0); - Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z'); - LDQS : inout std_logic := 'Z'; - LDQSB : inout std_logic := 'Z'; - UDQS : inout std_logic := 'Z'; - UDQSB : inout std_logic := 'Z'; - LDM : in std_logic; - WEB : in std_logic; - CASB : in std_logic; - RASB : in std_logic; - CSB : in std_logic; - BA : in std_logic_vector(1 downto 0); - ADDR : in std_logic_vector(12 downto 0); - CKE : in std_logic; - CLK : in std_logic; - CLKB : in std_logic; - UDM : in std_logic ); -End HY5PS121621F; - ------------------------------------------------------------------------------------------------------ - -Architecture Behavioral_Model_HY5PS121621F Of HY5PS121621F Is - -signal RD_PIPE_REG : std_logic_vector(6 downto 0) := "0000000"; -signal WT_PIPE_REG : std_logic_vector(12 downto 0) := "0000000000000"; -signal ADD_PIPE_REG : ADD_PIPE_TYPE; -signal DLL_reset, DLL_lock_enable : std_logic := '0'; -signal yburst, RD_WR_ST, caspwt, casp6_rd, casp6_wt : std_logic := '0'; -signal casp_wtI, casp_wtII, wt_stdby : std_logic := '0'; -signal udspre_enable, ldspre_enable, udsh_dsl_enable, ldsh_dsl_enable : std_logic := '0'; -signal dq_bufferH, dq_bufferL : DATA_BUFFER_TYPE := ("0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ", - "0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ", "0ZZZZZZZZ"); -signal DQS_S : std_logic := 'Z'; -signal dqs_count : integer := 0; -signal dqs_pulse1, dqs_pulse2, dqs_pulse3, dqs_pulse4, dqs_pulse5, dqs_pulse6 : std_logic := '0'; -signal cur_time : time := 0 ns; -signal Ref_time, clk_cycle_rising : time := 0 ns; -signal tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3 : std_logic := '0'; -signal mrs_cmd_in : std_logic := '0'; -signal CKEN : CKE_TYPE := (others => '0'); -signal CLK_DLY2, CLK_DLY1, CLK_DLY15 : std_logic := '0'; -signal tmp_ref_addr1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0'); -signal tmp_ref_addr2 : std_logic_vector((NUM_OF_ROW_ADD + 1) downto 0) := (others => '0'); -signal tmp_ref_addr3_B0 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0'); -signal tmp_ref_addr3_B1 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0'); -signal tmp_ref_addr3_B2 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0'); -signal tmp_ref_addr3_B3 : std_logic_vector((NUM_OF_ROW_ADD - 1) downto 0) := (others => '0'); -signal tmp_ref_addr3_0, tmp_ref_addr3_1, tmp_ref_addr3_2, tmp_ref_addr3_3 : std_logic := '0'; -signal tmp_ref_addr1_trans, tmp_ref_addr2_trans, tmp_ref_addr3_trans : std_logic := '0'; -signal RefChkTimeInit : boolean := FALSE; -signal refresh_check : REF_CHECK; -signal real_col_addr : COL_ADDR_TYPE ; -signal Read_CA, Write_CA : std_logic := '0'; -signal tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3 : std_logic := '0'; -signal RA_Activated_B0 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U'); -signal RA_Activated_B1 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U'); -signal RA_Activated_B2 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U'); -signal RA_Activated_B3 : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'U'); -signal SA_ARRAY : SA_ARRAY_TYPE; -signal SA_ARRAY_A0 : SA_TYPE; -signal SA_ARRAY_A1 : SA_TYPE; -signal SA_ARRAY_A2 : SA_TYPE; -signal SA_ARRAY_A3 : SA_TYPE; -signal SA_ARRAY_W0 : SA_TYPE; -signal SA_ARRAY_W1 : SA_TYPE; -signal SA_ARRAY_W2 : SA_TYPE; -signal SA_ARRAY_W3 : SA_TYPE; -signal PcgPdExtFlag, ActPdExtFlag, SlowActPdExtFlag : boolean := FALSE; -signal PUSPCGAFlag1, PUSPCGAFlag2 : boolean := FALSE; -signal PUS_DLL_RESET : boolean := FALSE; -signal ModeRegisterSetFlag : boolean := FALSE; -signal ModeRegisterFlag : boolean := FALSE; -signal BankActivateFlag : boolean := FALSE; -signal BankActivateFinFlag : boolean := FALSE; -signal BankActivatedFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0'); -signal PcgPdFlag, ReadFlag : boolean := FALSE; -signal WriteFlag : boolean := FALSE; -signal DataBuffer : BUFFER_TYPE; -signal PrechargeFlag : boolean := FALSE; -signal AutoPrechargeFlag : std_logic_vector ((NUM_OF_BANKS - 1) downto 0) := (others => '0'); -signal PrechargeFinFlag : boolean := FALSE; -signal PrechargeAllFlag : boolean := FALSE; -signal PrechargeAllFinFlag : boolean := FALSE; -signal ReadFinFlag : boolean := FALSE; -signal WriteFinFlag : boolean := FALSE; -signal AutoRefFlag : boolean := FALSE; -signal SelfRefFlag : boolean := FALSE; -signal SelfRefExt2NRFlag, SelfRefExt2RDFlag : boolean := FALSE; -signal PUSCheckFinFlag : boolean := FALSE; -signal CurrentState : STATE_TYPE := PWRUP; -signal ModeRegister : MODE_REGISTER := ( - CAS_LATENCY => 2, - BURST_MODE => SEQUENTIAL, - BURST_LENGTH => 4, - DLL_STATE => NORST, - SAPD => '0', - TWR => 2 ); -signal ExtModeRegister : EMR_TYPE := ( - DLL_EN => '0', - AL => 0, - QOFF => '0', - DQSB_ENB => '0', - RDQS_EN => '0', - OCD_PGM => CAL_EXIT ); -signal ExtModeRegister2 : EMR2_TYPE := ( - SREF_HOT => '0' ); -signal last_ocd_adjust_cmd, clk_cycle : time := 0 ns; -signal clk_cycle_count: integer := 0; -signal clk_last_rising : time := 0 ns; -signal cke_last_rising : time := 0 ns; -signal clk_last_falling : time := 0 ns; -signal udqs_last_rising : time := 0 ns; -signal udqs_last_falling : time := 0 ns; -signal ldqs_last_rising : time := 0 ns; -signal ldqs_last_falling : time := 0 ns; -signal wr_cmd_time : time := 0 ns; -signal ldm_last_rising : time := 0 ns; -signal udm_last_rising : time := 0 ns; -signal b0_last_activate : time := 0 ns; -signal b1_last_activate : time := 0 ns; -signal b2_last_activate : time := 0 ns; -signal b3_last_activate : time := 0 ns; -signal b0_last_precharge : time := 0 ns; -signal b1_last_precharge : time := 0 ns; -signal b2_last_precharge : time := 0 ns; -signal b3_last_precharge : time := 0 ns; -signal b0_last_column_access : time := 0 ns; -signal b1_last_column_access : time := 0 ns; -signal b2_last_column_access : time := 0 ns; -signal b3_last_column_access : time := 0 ns; -signal b0_last_column_access_cycle : integer := -100; -signal b1_last_column_access_cycle : integer := -100; -signal b2_last_column_access_cycle : integer := -100; -signal b3_last_column_access_cycle : integer := -100; -signal b0_last_data_in : time := 0 ns; -signal b1_last_data_in : time := 0 ns; -signal b2_last_data_in : time := 0 ns; -signal b3_last_data_in : time := 0 ns; -signal last_mrs_set : time := 0 ns; -signal last_mrs_set_cycle: integer := -100; -signal last_aref : time := 0 ns; -signal tCH : time := 0 ns; -signal tCL : time := 0 ns; -signal tWPRE : time := 0 ns; -signal tRAS, tRCD, tRP, tRC, tCCD : time := 0 ns; -signal tCCD_cycles: positive; -signal tWTR : time := 0 ns; -signal tDQSH : time := 0 ns; -signal tDQSL : time := 0 ns; -signal tWPSTmin : time := 0 ns; -signal tWPSTmax : time := 0 ns; -signal tDQSSmin : time := 0 ns; -signal tDQSSmax : time := 0 ns; -signal tMRD : time := 0 ns; -signal tMRD_cycles: positive; -signal cke_ch : time := 0 ns; -signal rasb_ch : time := 0 ns; -signal casb_ch : time := 0 ns; -signal web_ch : time := 0 ns; -signal csb_ch : time := 0 ns; -signal udm_ch : time := 0 ns; -signal ldm_ch : time := 0 ns; -signal a0_ch : time := 0 ns; -signal a1_ch : time := 0 ns; -signal a2_ch : time := 0 ns; -signal a3_ch : time := 0 ns; -signal a4_ch : time := 0 ns; -signal a5_ch : time := 0 ns; -signal a6_ch : time := 0 ns; -signal a7_ch : time := 0 ns; -signal a8_ch : time := 0 ns; -signal a9_ch : time := 0 ns; -signal a10_ch : time := 0 ns; -signal a11_ch : time := 0 ns; -signal a12_ch : time := 0 ns; -signal ba0_ch : time := 0 ns; -signal ba1_ch : time := 0 ns; -signal dq0_ch : time := 0 ns; -signal dq1_ch : time := 0 ns; -signal dq2_ch : time := 0 ns; -signal dq3_ch : time := 0 ns; -signal dq4_ch : time := 0 ns; -signal dq5_ch : time := 0 ns; -signal dq6_ch : time := 0 ns; -signal dq7_ch : time := 0 ns; -signal dq8_ch : time := 0 ns; -signal dq9_ch : time := 0 ns; -signal dq10_ch : time := 0 ns; -signal dq11_ch : time := 0 ns; -signal dq12_ch : time := 0 ns; -signal dq13_ch : time := 0 ns; -signal dq14_ch : time := 0 ns; -signal dq15_ch : time := 0 ns; - -signal load_file : std_ulogic := '1'; - -begin - ------------------------------------------------------------------------------------------------------ - -CLK_CYCLE_CHECK : process(CLK) - -begin - CLK_DLY15 <= transport CLK after 1.5 ns; - CLK_DLY1 <= transport CLK after 1 ns; - CLK_DLY2 <= transport CLK after 2 ns; - if (rising_edge(CLK)) then - clk_cycle <= transport now - clk_cycle_rising; - clk_cycle_rising <= transport now; - clk_cycle_count <= transport (clk_cycle_count+1) mod 2000000000; - end if; -end Process; - ------------------------------------------------------------------------------------------------------ - -REFRESH_TIME_CHECK : process(tmp_ref_addr1_trans, tmp_ref_addr2_trans, tmp_ref_addr3_trans) - -variable i, j : integer := 0; - -begin - i := 0; - j := 0; - if (RefChkTimeInit = FALSE) then - loop - exit when (i > NUM_OF_BANKS - 1); - j := 0; - loop - exit when (j >= NUM_OF_ROWS); - refresh_check (i, j) <= 0 ns; - j := j + 1; - end loop; - i := i + 1; - end loop; - RefChkTimeInit <= TRUE; - end if; - if (tmp_ref_addr1_trans'event and tmp_ref_addr1_trans = '1') then - refresh_check (0, conv_integer(tmp_ref_addr1)) <= transport now; - refresh_check (1, conv_integer(tmp_ref_addr1)) <= transport now; - refresh_check (2, conv_integer(tmp_ref_addr1)) <= transport now; - refresh_check (3, conv_integer(tmp_ref_addr1)) <= transport now; - end if; - if (tmp_ref_addr2_trans'event and tmp_ref_addr2_trans = '1') then - refresh_check (conv_integer(tmp_ref_addr2(1 downto 0)), conv_integer(tmp_ref_addr2((NUM_OF_ROW_ADD + 1) downto 2))) <= transport now; - end if; - if (tmp_ref_addr3_trans'event and tmp_ref_addr3_trans = '1') then - if (tmp_ref_addr3_0 = '1') then - refresh_check (0, conv_integer(tmp_ref_addr3_B0)) <= transport now; - end if; - if (tmp_ref_addr3_1 = '1') then - refresh_check (1, conv_integer(tmp_ref_addr3_B1)) <= transport now; - end if; - if (tmp_ref_addr3_2 = '1') then - refresh_check (2, conv_integer(tmp_ref_addr3_B2)) <= transport now; - end if; - if (tmp_ref_addr3_3 = '1') then - refresh_check (3, conv_integer(tmp_ref_addr3_B3)) <= transport now; - end if; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -CKE_EVAL : process (CLK, CKE) - -begin - if (CKE'EVENT and CKE = '1' and CKE'LAST_VALUE = '0') then - cke_last_rising <= transport now; - end if; - if (CLK'EVENT and CLK = '0' and CLK'LAST_VALUE = '1') then - CKEN(-1) <= CKEN(0); - elsif (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then - CKEN(0) <= CKE; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -STATE_MACHINE : process (CLK, CKE, BankActivateFinFlag, PrechargeFinFlag, PrechargeAllFinFlag, BankActivatedFlag, PUSCheckFinFlag) - -variable ChipSelectBar : std_logic := '0'; -variable RowAddrStrobeBar : std_logic := '0'; -variable ColAddrStrobeBar : std_logic := '0'; -variable WriteEnableBar : std_logic := '0'; -variable Address10 : std_logic := '0'; -variable ClockEnable : CKE_TYPE := (others => '0'); -variable NextState, Cur_State : STATE_TYPE := PWRUP; -variable CurrentCommand : COMMAND_TYPE := NOP; -variable OpCode : MROPCODE_TYPE := (others => 'X'); -variable MR : MODE_REGISTER; -variable EMR : EMR_TYPE; -variable EMR2 : EMR2_TYPE; -variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0'); - -begin - if (CLK'EVENT and CLK = '1' and CLK'LAST_VALUE = '0') then - ClockEnable(-1) := CKEN(-1); - ClockEnable(0) := CKE; - ChipSelectBar := CSB; - RowAddrStrobeBar := RASB; - ColAddrStrobeBar := CASB; - WriteEnableBar := WEB; - Address10 := ADDR(10); - BkAdd := BA; - BankActFlag := BankActivatedFlag; - Cur_State := CurrentState; - COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar, - WriteEnableBar, Address10, BkAdd, ClockEnable, CurrentCommand, BankActFlag, Cur_State); - if (DLL_reset = '1' and (CurrentCommand = RD or CurrentCommand = RDAP)) then - if (TimingCheckFlag = TRUE) then - assert false report - "ERROR : (DLL Locking) : 200 clock cycles are needed after DLL reset." - severity ERROR; - end if; - end if; - Case CurrentState Is - When IDLE => - Case CurrentCommand Is - When DSEL => - NextState := IDLE; - When NOP => - NextState := IDLE; - When ACT => - if (TimingCheckFlag = TRUE) then - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - assert (now - last_aref >= tRFC) report - "WARNING : (tRFC_CHECK) : tRFC timing error!" - severity WARNING; - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - end if; - BankActivateFlag <= TRUE; - NextState := RACT; - When PCG => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - end if; - NextState := IDLE; - When PCGA => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - end if; - NextState := IDLE; - When AREF => - if (TimingCheckFlag = TRUE) then - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - assert (now - last_aref >= tRFC) report - "WARNING : (tRFC_CHECK) : tRFC timing error!" - severity WARNING; - end if; - last_aref <= transport now after 1 ns; - AutoRefFlag <= TRUE, FALSE after 2 ns; - NextState := IDLE; - When SREF => - if (TimingCheckFlag = TRUE) then - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - end if; - SelfRefFlag <= TRUE; - NextState := SLFREF; - When PDEN => - if (TimingCheckFlag = TRUE) then - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - end if; - PcgPdFlag <= TRUE; - NextState := PWRDN; - When EMRS3 => - NextState := IDLE; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When EMRS1 => - OpCode := ADDR(12 downto 0); - EXT_MODE_REGISTER_SET (OpCode, EMR); - ExtModeRegister <= EMR; - NextState := IDLE; - if (ADDR(0) = '0') then - DLL_lock_enable <= '1'; - end if; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When EMRS2 => - OpCode := ADDR(12 downto 0); - EXT_MODE_REGISTER_SET2 (OpCode, EMR2); - ExtModeRegister2 <= EMR2; - NextState := IDLE; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When MRS => - if (TimingCheckFlag = TRUE) then - assert (PcgPdExtFlag = FALSE) report - "WARNING : (tXP_CHECK) : tXP timing error!" - severity WARNING; - assert (SelfRefExt2NRFlag /= TRUE) report - "ERROR : (tXSNR_CHECK) : Needs tXSNR Timing after Self Refresh." - severity error; - end if; - OpCode := ADDR(12 downto 0); - MODE_REGISTER_SET (OpCode, MR); - ModeRegister <= MR; - ModeRegisterSetFlag <= TRUE; - if (ADDR(8) = '1') then - DLL_reset <= transport '1', '0' after 200 * clk_cycle; - end if; - NextState := IDLE; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When others => - assert false report - "WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored." - severity warning; - NextState := IDLE; - End Case; - When PWRUP => - Case CurrentCommand Is - When DSEL => - if (PUSCheckFlag = TRUE) then - NextState := PWRUP; - else - NextState := IDLE; - end if; - When NOP => - if (PUSCheckFlag = TRUE) then - NextState := PWRUP; - else - NextState := IDLE; - end if; - When EMRS3 => - NextState := PWRUP; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When EMRS1 => - if (TimingCheckFlag = TRUE and PUSCheckFlag = TRUE) then - assert (PUSPCGAFlag1 = TRUE) report - "ERROR : (Power Up Sequence) : PCGA Command must be issued before EMRS setting!" - severity error; - end if; - OpCode := ADDR(12 downto 0); - EXT_MODE_REGISTER_SET (OpCode, EMR); - ExtModeRegister <= EMR; - NextState := PWRUP; - if (ADDR(0) = '0') then - DLL_lock_enable <= '1'; - end if; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When EMRS2 => - OpCode := ADDR(12 downto 0); - EXT_MODE_REGISTER_SET2 (OpCode, EMR2); - ExtModeRegister2 <= EMR2; - NextState := PWRUP; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When MRS => - if (TimingCheckFlag = TRUE) then - assert (DLL_lock_enable = '1') report - "WARNING : (STATE_MACHINE) : EMRS Command (with DLL enable flag) Must be Issued before MRS Command !" - severity warning; - end if; - OpCode := ADDR(12 downto 0); - MODE_REGISTER_SET (OpCode, MR); - ModeRegister <= MR; - ModeRegisterSetFlag <= TRUE; - NextState := PWRUP; - if (ADDR(8) = '1') then - DLL_reset <= transport '1', '0' after 200 * clk_cycle; - end if; - mrs_cmd_in <= transport '1', '0' after 2 ns; - When PCGA => - PrechargeAllFlag <= TRUE; - NextState := PWRUP; - When AREF => - AutoRefFlag <= TRUE, FALSE after 2 ns; - if (PUSCheckFinFlag = TRUE) then - NextState := IDLE; - else - NextState := PWRUP; - end if; - last_aref <= transport now after 1 ns; - When others => - assert false report - "ERROR : (STATE_MACHINE) : Invalid Command Issued during Power Up Sequence." - severity error; - End Case; - When PWRDN => - Case CurrentCommand Is - When NOP => - NextState := PWRDN; - When PDEX => - if (PcgPdFlag = TRUE) then - PcgPdExtFlag <= transport TRUE, FALSE after tXP * clk_cycle; - PcgPdFlag <= FALSE; - NextState := IDLE; - elsif (ModeRegister.SAPD = '0') then - ActPdExtFlag <= transport TRUE, FALSE after tXARD * clk_cycle; - NextState := RACT; - elsif (ModeRegister.SAPD = '1') then - SlowActPdExtFlag <= transport TRUE, FALSE after (6 - ExtModeRegister.AL) * clk_cycle; - NextState := RACT; - end if; - When others => - assert false report - "WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored." - severity warning; - NextState := PWRDN; - End Case; - When SLFREF => - Case CurrentCommand Is - When NOP => - NextState := SLFREF; - When SREX => - SelfRefExt2NRFlag <= transport TRUE, FALSE after tXSNR; - SelfRefExt2RDFlag <= transport TRUE, FALSE after tXSRD * clk_cycle; - SelfRefFlag <= FALSE; - NextState := IDLE; - When others => - assert false report - "WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored." - severity warning; - NextState := SLFREF; - End Case; - When RACT => - Case CurrentCommand Is - When DSEL => - NextState := RACT; - When NOP => - NextState := RACT; - When RD => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2RDFlag /= TRUE) report - "ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh." - severity error; - assert (ActPdExtFlag = FALSE) report - "WARNING : (tXARD_CHECK) : tXARD timing error!" - severity WARNING; - assert (SlowActPdExtFlag = FALSE) report - "WARNING : (tXARDS_CHECK) : tXARDS timing error!" - severity WARNING; - end if; - Read_CA <= '1', '0' after 2 ns; - NextState := READ; - When RDAP => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2RDFlag /= TRUE) report - "ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh." - severity error; - assert (ActPdExtFlag = FALSE) report - "WARNING : (tXARD_CHECK) : tXARD timing error!" - severity WARNING; - assert (SlowActPdExtFlag = FALSE) report - "WARNING : (tXARDS_CHECK) : tXARDS timing error!" - severity WARNING; - end if; - AutoPrechargeFlag(conv_integer(BkAdd)) <= transport - '1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP, - '0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns; - Read_CA <= '1', '0' after 2 ns; - NextState := READ; - When WR => - Write_CA <= '1', '0' after 2 ns; - NextState := WRITE; - When WRAP => - AutoPrechargeFlag(conv_integer(BkAdd)) <= transport - '1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 + - ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle, - '0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 + - ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns; - Write_CA <= '1', '0' after 2 ns; - NextState := WRITE; - When ACT => - BankActivateFlag <= TRUE; - NextState := RACT; - When PCG => - PrechargeFlag <= TRUE; - if ((BankActivatedFlag = "0001") or (BankActivatedFlag = "0010") or - (BankActivatedFlag = "0100") or (BankActivatedFlag = "1000")) then - NextState := IDLE; - else - NextState := RACT; - end if; - When PCGA => - PrechargeAllFlag <= TRUE; - NextState := IDLE; - When PDEN => - NextState := PWRDN; - When others => - assert false report - "WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored." - severity warning; - NextState := RACT; - End Case; - When READ => - Case CurrentCommand Is - When DSEL => - NextState := READ; - When NOP => - NextState := READ; - When RD => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2RDFlag /= TRUE) report - "ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh." - severity error; - end if; - Read_CA <= '1', '0' after 2 ns; - NextState := READ; - When RDAP => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2RDFlag /= TRUE) report - "ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh." - severity error; - end if; - AutoPrechargeFlag(conv_integer(BkAdd)) <= transport - '1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP, - '0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns; - Read_CA <= '1', '0' after 2 ns; - NextState := READ; - When WR => - Write_CA <= '1', '0' after 2 ns; - NextState := WRITE; - When WRAP => - AutoPrechargeFlag(conv_integer(BkAdd)) <= transport - '1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 + - ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle, - '0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 + - ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns; - Write_CA <= '1', '0' after 2 ns; - NextState := WRITE; - When ACT => - BankActivateFlag <= TRUE; - NextState := READ; - When PCG => - PrechargeFlag <= TRUE; - NextState := READ; - When PCGA => - PrechargeAllFlag <= TRUE; - NextState := READ; - When others => - assert false report - "WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored." - severity warning; - NextState := READ; - End Case; - When WRITE => - Case CurrentCommand Is - When DSEL => - NextState := WRITE; - When NOP => - NextState := WRITE; - When RD => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2RDFlag /= TRUE) report - "ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh." - severity error; - end if; - Read_CA <= '1', '0' after 2 ns; - NextState := READ; - When RDAP => - if (TimingCheckFlag = TRUE) then - assert (SelfRefExt2RDFlag /= TRUE) report - "ERROR : (tXSRD_CHECK) : Needs tXSRD Timing after Self Refresh." - severity error; - end if; - AutoPrechargeFlag(conv_integer(BkAdd)) <= transport - '1' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP, - '0' after (ExtModeRegister.AL + ModeRegister.BURST_LENGTH/2 - 2) * clk_cycle + tRTP + 2 ns; - Read_CA <= '1', '0' after 2 ns; - NextState := READ; - When WR => - Write_CA <= '1', '0' after 2 ns; - NextState := WRITE; - When WRAP => - AutoPrechargeFlag(conv_integer(BkAdd)) <= transport - '1' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 + - ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle, - '0' after (ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 1 + - ModeRegister.BURST_LENGTH/2 + ModeRegister.TWR) * clk_cycle + 2 ns; - Write_CA <= '1', '0' after 2 ns; - NextState := WRITE; - When ACT => - BankActivateFlag <= TRUE; - NextState := WRITE; - When PCG => - PrechargeFlag <= TRUE; - NextState := WRITE; - When PCGA => - PrechargeAllFlag <= TRUE; - NextState := WRITE; - When others => - assert false report - "WARNING : (STATE_MACHINE) : Illegal Command Issued. Command Ignored." - severity warning; - NextState := WRITE; - End Case; - When others => - assert false report - "ERROR : (STATE_MACHINE) : Invalid Command Issued." - severity error; - End case; - end if; - if (BankActivateFinFlag = TRUE) then - BankActivateFlag <= FALSE; - end if; - if (PrechargeFinFlag = TRUE) then - PrechargeFlag <= FALSE; - end if; - if (PrechargeAllFinFlag = TRUE) then - PrechargeAllFlag <= FALSE; - end if; - if (PUSCheckFinFlag'EVENT and PUSCheckFinFlag = TRUE) then - NextState := IDLE; - end if; - if (BankActivatedFlag'EVENT and BankActivatedFlag /= BankActivatedFlag'LAST_VALUE) then - if (BankActivatedFlag = "0000") then - NextState := IDLE; - else - NextState := RACT; - end if; - end if; - CurrentState <= NextState; -end process; - ------------------------------------------------------------------------------------------------------ - -MEMORY_BANK_ACTIVATE_PRECHARGE : process (PrechargeFlag, AutoPrechargeFlag, PrechargeAllFlag, BankActivateFlag, CLK) - -variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -variable RA : std_logic_vector ((NUM_OF_ROW_ADD - 1) downto 0) := (others => 'X'); -variable COLA : std_logic_vector ((NUM_OF_COL_ADD-1) downto 0) := (others => '0'); -variable MEM_CELL_ARRAY0, MEM_CELL_ARRAY1, MEM_CELL_ARRAY2, MEM_CELL_ARRAY3 : MEM_CELL_TYPE; -variable i, j, k, l, m, u : integer := 0; - -file fload : text open read_mode is fname; -variable fline : line; -variable fchar : character; -variable rtype : std_logic_vector(3 downto 0); -variable raddr : std_logic_vector(31 downto 0); -variable rlen : std_logic_vector(7 downto 0); -variable rdata : std_logic_vector(0 to 16*8-1); - -begin - - -- Load initial memory data from file - if (now >= (fdelay * 1 us)) and (load_file = '1') then - - load_file <= '0'; - - while not endfile(fload) loop - readline(fload, fline); - read(fline, fchar); - if fchar /= 'S' or fchar /= 's' then - hread(fline, rtype); - hread(fline, rlen); - case rtype is - when "0001" => - hread(fline, raddr(15 downto 0)); - raddr(31 downto 16) := (others => '0'); - when "0010" => - hread(fline, raddr(23 downto 0)); - raddr(31 downto 24) := (others => '0'); - when "0011" => - hread(fline, raddr); - raddr(31 downto 24) := (others => '0'); - when others => next; - end case; - - case bbits is - -- 64 bit bank with four 16-bit... - when 64 => - hread(fline, rdata); - BkAdd := raddr(27 downto 26); - RA := raddr(25 downto 13); - COLA := raddr(12 downto 3); - - if (conv_integer (BkAdd) = 0) then - if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 1 loop - MEM_CELL_ARRAY0(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*64+index*16 to i*64+index*16+15)); - end loop; - elsif (conv_integer (BkAdd) = 1) then - if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 1 loop - MEM_CELL_ARRAY1(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*64+index*16 to i*64+index*16+15)); - end loop; - elsif (conv_integer (BkAdd) = 2) then - if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 1 loop - MEM_CELL_ARRAY2(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*64+index*16 to i*64+index*16+15)); - end loop; - elsif (conv_integer (BkAdd) = 3) then - if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 1 loop - MEM_CELL_ARRAY3(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*64+index*16 to i*64+index*16+15)); - end loop; - end if; - -- 32 bit bank with two 16-bit... - when 32 => - hread(fline, rdata); - BkAdd := raddr(26 downto 25); - RA := raddr(24 downto 12); - COLA := raddr(11 downto 2); - if (conv_integer (BkAdd) = 0) then - if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY0(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*32+index*16 to i*32+index*16+15)); - end loop; - elsif (conv_integer (BkAdd) = 1) then - if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY1(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*32+index*16 to i*32+index*16+15)); - end loop; - elsif (conv_integer (BkAdd) = 2) then - if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY2(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*32+index*16 to i*32+index*16+15)); - end loop; - elsif (conv_integer (BkAdd) = 3) then - if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY3(conv_integer (RA))(conv_integer(COLA)+i) := - conv_integer(rdata(i*32+index*16 to i*32+index*16+15)); - end loop; - end if; - -- 16 bit bank with one 16-bit... - when others => - hread(fline, rdata); - BkAdd := raddr(25 downto 24); - RA := raddr(23 downto 11); - COLA := raddr(10 downto 1); - if (conv_integer (BkAdd) = 0) then - if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY0(conv_integer (RA))(conv_integer(COLA)+i*2) := - conv_integer(rdata(i*32 to i*32+15)); - MEM_CELL_ARRAY0(conv_integer (RA))(conv_integer(COLA)+i*2+1) := - conv_integer(rdata(i*32+16 to i*32+31)); - end loop; - elsif (conv_integer (BkAdd) = 1) then - if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY1(conv_integer (RA))(conv_integer(COLA)+i*2) := - conv_integer(rdata(i*32 to i*32+15)); - MEM_CELL_ARRAY1(conv_integer (RA))(conv_integer(COLA)+i*2+1) := - conv_integer(rdata(i*32+16 to i*32+31)); - end loop; - elsif (conv_integer (BkAdd) = 2) then - if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY2(conv_integer (RA))(conv_integer(COLA)+i*2) := - conv_integer(rdata(i*32 to i*32+15)); - MEM_CELL_ARRAY2(conv_integer (RA))(conv_integer(COLA)+i*2+1) := - conv_integer(rdata(i*32+16 to i*32+31)); - end loop; - elsif (conv_integer (BkAdd) = 3) then - if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - for i in 0 to 3 loop - MEM_CELL_ARRAY3(conv_integer (RA))(conv_integer(COLA)+i*2) := - conv_integer(rdata(i*32 to i*32+15)); - MEM_CELL_ARRAY3(conv_integer (RA))(conv_integer(COLA)+i*2+1) := - conv_integer(rdata(i*32+16 to i*32+31)); - end loop; - end if; - end case; - u := 0; - i := 0; - end if; - end loop; - end if; - - if (CLK'EVENT and CLK = '0') then - if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans0 = '1'))) Then - tmp_act_trans0 <= '0'; - end if; - if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans1 = '1'))) Then - tmp_act_trans1 <= '0'; - end if; - if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans2 = '1'))) Then - tmp_act_trans2 <= '0'; - end if; - if ((BankActivateFlag = TRUE) or ((BankActivateFlag = FALSE) and (tmp_act_trans3 = '1'))) Then - tmp_act_trans3 <= '0'; - end if; - end if; - if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then - BkAdd := (BA); - RA := ADDR(NUM_OF_ROW_ADD - 1 downto 0); - BankActivatedFlag(conv_integer(BkAdd)) <= '1'; - i := 0; - j := 0; - u := 0; - if (BankActivatedFlag (conv_integer (BkAdd)) = '1') then - assert false report - "WARNING : (MEMORY_BANK_ACTIVATE) : Activating same bank without precharge. Command Ignored." - severity warning; - BankActivateFinFlag <= TRUE, FALSE after 2 ns; - elsif (BankActivatedFlag (conv_integer (BkAdd)) = '0') then - if (TimingCheckFlag = TRUE) then - if (now - refresh_check(conv_integer(BkAdd), conv_integer(RA)) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms. So, This Row's Data Is Lost." - severity warning; - end if; - end if; - case BkAdd is - when "00" => - b0_last_activate <= transport now; - RA_Activated_B0 <= RA; - when "01" => - b1_last_activate <= transport now; - RA_Activated_B1 <= RA; - when "10" => - b2_last_activate <= transport now; - RA_Activated_B2 <= RA; - when "11" => - b3_last_activate <= transport now; - RA_Activated_B3 <= RA; - when others => - assert false report - "WARNING : (MEMORY_REFRESH) : Impossible Bank Address" - severity warning; - end case; - if (conv_integer (BkAdd) = 0) then - if (MEM_CELL_ARRAY0(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY0(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY0(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - loop - exit when i >= NUM_OF_COLS; - SA_ARRAY_A0(i) <= MEM_CELL_ARRAY0(conv_integer (RA))(i); - i := i + 1; - end loop; - tmp_act_trans0 <= '1'; - elsif (conv_integer (BkAdd) = 1) then - if (MEM_CELL_ARRAY1(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY1(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY1(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - loop - exit when i >= NUM_OF_COLS; - SA_ARRAY_A1(i) <= MEM_CELL_ARRAY1(conv_integer (RA))(i); - i := i + 1; - end loop; - tmp_act_trans1 <= '1'; - elsif (conv_integer (BkAdd) = 2) then - if (MEM_CELL_ARRAY2(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY2(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY2(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - loop - exit when i >= NUM_OF_COLS; - SA_ARRAY_A2(i) <= MEM_CELL_ARRAY2(conv_integer (RA))(i); - i := i + 1; - end loop; - tmp_act_trans2 <= '1'; - elsif (conv_integer (BkAdd) = 3) then - if (MEM_CELL_ARRAY3(conv_integer (RA)) = NULL) then - MEM_CELL_ARRAY3(conv_integer (RA)) := NEW ROW_DATA_TYPE; - loop - exit when u >= NUM_OF_COLS; - MEM_CELL_ARRAY3(conv_integer (RA))(u) := 0; - u := u + 1; - end loop; - end if; - loop - exit when i >= NUM_OF_COLS; - SA_ARRAY_A3(i) <= MEM_CELL_ARRAY3(conv_integer (RA))(i); - i := i + 1; - end loop; - tmp_act_trans3 <= '1'; - end if; - BankActivateFinFlag <= TRUE, FALSE after 2 ns; - else - end if; - end if; - if ((PrechargeFlag'EVENT and PrechargeFlag = TRUE) or - (AutoPrechargeFlag(0)'EVENT and AutoPrechargeFlag(0) = '1') or - (AutoPrechargeFlag(1)'EVENT and AutoPrechargeFlag(1) = '1') or - (AutoPrechargeFlag(2)'EVENT and AutoPrechargeFlag(2) = '1') or - (AutoPrechargeFlag(3)'EVENT and AutoPrechargeFlag(3) = '1')) then - i := 0; - j := 0; - if (PrechargeFlag = TRUE) then - BkAdd := (BA); - elsif (AutoPrechargeFlag(0) = '1') then - BkAdd := "00"; - elsif (AutoPrechargeFlag(1) = '1') then - BkAdd := "01"; - elsif (AutoPrechargeFlag(2) = '1') then - BkAdd := "10"; - elsif (AutoPrechargeFlag(3) = '1') then - BkAdd := "11"; - end if; - if (BkAdd = "00") then - if (AutoPrechargeFlag(0) = '1' and (now - b0_last_activate) < tRAS) then - b0_last_precharge <= transport (tRAS + b0_last_activate) after 1 ns; - else - b0_last_precharge <= transport now after 1 ns; - end if; - if (BankActivatedFlag (0) /= '1') then - assert false report - "WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank." - severity warning; - else - RA := RA_Activated_B0; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY0(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - if (AutoPrechargeFlag(0) = '1' and (now - b0_last_activate) < tRAS) then - BankActivatedFlag (0) <= transport '0' after (tRAS - (now - b0_last_activate)); - else - BankActivatedFlag (0) <= '0'; - end if; - tmp_ref_addr2 <= RA&"00"; - end if; - elsif (BkAdd = "01") then - if (AutoPrechargeFlag(1) = '1' and (now - b1_last_activate) < tRAS) then - b1_last_precharge <= transport (tRAS + b1_last_activate) after 1 ns; - else - b1_last_precharge <= transport now after 1 ns; - end if; - if (BankActivatedFlag (1) /= '1') then - assert false report - "WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank." - severity warning; - else - RA := RA_Activated_B1; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY1(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - if (AutoPrechargeFlag(1) = '1' and (now - b1_last_activate) < tRAS) then - BankActivatedFlag (1) <= transport '0' after (tRAS - (now - b1_last_activate)); - else - BankActivatedFlag (1) <= '0'; - end if; - tmp_ref_addr2 <= RA&"01"; - end if; - elsif (BkAdd = "10") then - if (AutoPrechargeFlag(2) = '1' and (now - b2_last_activate) < tRAS) then - b2_last_precharge <= transport (tRAS + b2_last_activate) after 1 ns; - else - b2_last_precharge <= transport now after 1 ns; - end if; - if (BankActivatedFlag (2) /= '1') then - assert false report - "WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank." - severity warning; - else - RA := RA_Activated_B2; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY2(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - if (AutoPrechargeFlag(2) = '1' and (now - b2_last_activate) < tRAS) then - BankActivatedFlag (2) <= transport '0' after (tRAS - (now - b2_last_activate)); - else - BankActivatedFlag (2) <= '0'; - end if; - tmp_ref_addr2 <= RA&"10"; - end if; - elsif (BkAdd = "11") then - if (AutoPrechargeFlag(3) = '1' and (now - b3_last_activate) < tRAS) then - b3_last_precharge <= transport (tRAS + b3_last_activate) after 1 ns; - else - b3_last_precharge <= transport now after 1 ns; - end if; - if (BankActivatedFlag (3) /= '1') then - assert false report - "WARNING : (MEMORY_PRECHARGE) : Precharging deactivated bank." - severity warning; - else - RA := RA_Activated_B3; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY3(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - if (AutoPrechargeFlag(3) = '1' and (now - b3_last_activate) < tRAS) then - BankActivatedFlag (3) <= transport '0' after (tRAS - (now - b3_last_activate)); - else - BankActivatedFlag (3) <= '0'; - end if; - tmp_ref_addr2 <= RA&"11"; - end if; - end if; - if (PrechargeFlag = TRUE) then - PrechargeFinFlag <= TRUE, FALSE after 2 ns; - end if; - tmp_ref_addr2_trans <= transport '1', '0' after 1 ns; - end if; - if (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE) then - if BankActivatedFlag (0) = '1' then - BkAdd := "00"; - RA := RA_Activated_B0; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY0(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - BankActivatedFlag (0) <= '0'; - tmp_ref_addr3_B0 <= RA; - tmp_ref_addr3_0 <= transport '1', '0' after 1 ns; - b0_last_precharge <= transport now after 1 ns; - end if; - if BankActivatedFlag (1) = '1' then - BkAdd := "01"; - RA := RA_Activated_B1; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY1(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - BankActivatedFlag (1) <= '0'; - tmp_ref_addr3_B1 <= RA; - tmp_ref_addr3_1 <= transport '1', '0' after 1 ns; - b1_last_precharge <= transport now after 1 ns; - end if; - if BankActivatedFlag (2) = '1' then - BkAdd := "10"; - RA := RA_Activated_B2; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY2(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - BankActivatedFlag (2) <= '0'; - tmp_ref_addr3_B2 <= RA; - tmp_ref_addr3_2 <= transport '1', '0' after 1 ns; - b2_last_precharge <= transport now after 1 ns; - end if; - if BankActivatedFlag (3) = '1' then - BkAdd := "11"; - RA := RA_Activated_B3; - i := 0; - loop - exit when i >= NUM_OF_COLS; - MEM_CELL_ARRAY3(conv_integer (RA))(i) := SA_ARRAY (conv_integer(BkAdd))(i); - i := i + 1; - end loop; - BankActivatedFlag (3) <= '0'; - tmp_ref_addr3_B3 <= RA; - tmp_ref_addr3_3 <= transport '1', '0' after 1 ns; - b3_last_precharge <= transport now after 1 ns; - end if; - tmp_ref_addr3_trans <= transport '1', '0' after 1 ns; - if (BankActivatedFlag = "0000") then - if (PUSCheckFinFlag = TRUE) then - assert false report - "WARNING : (PRECHARGE_ALL) : No Activated Banks, PCGA command ignored." - severity WARNING; - else - BankActivatedFlag (0) <= '0'; - BankActivatedFlag (1) <= '0'; - BankActivatedFlag (2) <= '0'; - BankActivatedFlag (3) <= '0'; - end if; - end if; - PrechargeAllFinFlag <= TRUE, FALSE after 2 ns; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -SENSE_AMPLIFIER_UPDATE : process (tmp_act_trans0, tmp_act_trans1, tmp_act_trans2, tmp_act_trans3, tmp_w_trans0, tmp_w_trans1, tmp_w_trans2, tmp_w_trans3) -begin - if (tmp_act_trans0'EVENT and tmp_act_trans0 = '1') then - SA_ARRAY(0) <= SA_ARRAY_A0; - elsif (tmp_act_trans1'EVENT and tmp_act_trans1 = '1') then - SA_ARRAY(1) <= SA_ARRAY_A1; - elsif (tmp_act_trans2'EVENT and tmp_act_trans2 = '1') then - SA_ARRAY(2) <= SA_ARRAY_A2; - elsif (tmp_act_trans3'EVENT and tmp_act_trans3 = '1') then - SA_ARRAY(3) <= SA_ARRAY_A3; - elsif (tmp_w_trans0'EVENT and tmp_w_trans0 = '1') then - SA_ARRAY(0) <= SA_ARRAY_W0; - elsif (tmp_w_trans1'EVENT and tmp_w_trans1 = '1') then - SA_ARRAY(1) <= SA_ARRAY_W1; - elsif (tmp_w_trans2'EVENT and tmp_w_trans2 = '1') then - SA_ARRAY(2) <= SA_ARRAY_W2; - elsif (tmp_w_trans3'EVENT and tmp_w_trans3 = '1') then - SA_ARRAY(3) <= SA_ARRAY_W3; - End if; -end process; - ------------------------------------------------------------------------------------------------------ - -RD_WR_PIPE : process (CLK_DLY1, CLK) - -variable CA : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X'); -variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); - -begin - - if (CLK'EVENT and CLK = '1') then - BkAdd := (BA); - CA := ADDR(NUM_OF_COL_ADD - 1 downto 0); - end if; - if (CLK_DLY1'EVENT and CLK_DLY1 = '1') then - RD_PIPE_REG(6 downto 1) <= RD_PIPE_REG(5 downto 0); - WT_PIPE_REG(12 downto 1) <= WT_PIPE_REG(11 downto 0); - ADD_PIPE_REG(12) <= ADD_PIPE_REG(11); - ADD_PIPE_REG(11) <= ADD_PIPE_REG(10); - ADD_PIPE_REG(10) <= ADD_PIPE_REG(9); - ADD_PIPE_REG(9) <= ADD_PIPE_REG(8); - ADD_PIPE_REG(8) <= ADD_PIPE_REG(7); - ADD_PIPE_REG(7) <= ADD_PIPE_REG(6); - ADD_PIPE_REG(6) <= ADD_PIPE_REG(5); - ADD_PIPE_REG(5) <= ADD_PIPE_REG(4); - ADD_PIPE_REG(4) <= ADD_PIPE_REG(3); - ADD_PIPE_REG(3) <= ADD_PIPE_REG(2); - ADD_PIPE_REG(2) <= ADD_PIPE_REG(1); - ADD_PIPE_REG(1) <= ADD_PIPE_REG(0); - if (Read_CA = '1' or Write_CA = '1') then - ADD_PIPE_REG(0) <= BkAdd & CA; - if (Read_CA = '1') then - RD_PIPE_REG(0) <= '1'; - else - RD_PIPE_REG(0) <= '0'; - end if; - if (Write_CA = '1') then - WT_PIPE_REG(0) <= '1'; - else - WT_PIPE_REG(0) <= '0'; - end if; - else - ADD_PIPE_REG(0) <= (others => '0'); - RD_PIPE_REG(0) <= '0'; - WT_PIPE_REG(0) <= '0'; - end if; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -casp6_XX_Gen : process (RD_PIPE_REG, WT_PIPE_REG) - -begin - if (RD_PIPE_REG'event and RD_PIPE_REG(ExtModeRegister.AL) = '1') then - casp6_rd <= transport '1' after 0.5 ns, '0' after 2 ns; - elsif (WT_PIPE_REG'event and WT_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY - 2) = '1') then - caspwt <= transport '1', '0' after 2 ns; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -RD_WT_Flag_GEN : process (caspwt, casp6_rd, ReadFinFlag, WriteFinFlag) - -begin - if (ReadFinFlag'EVENT and ReadFinFlag = TRUE) then - ReadFlag <= FALSE; - elsif (WriteFinFlag'EVENT and WriteFinFlag = TRUE) then - WriteFlag <= FALSE; - end if; - if (casp6_rd'event and casp6_rd = '1') then - ReadFlag <= TRUE; - elsif (caspwt'event and caspwt = '1') then - WriteFlag <= TRUE; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -WRITE_ST_GEN : process(CLK_DLY1, caspwt) - -begin - if (caspwt'event and caspwt = '1') then - wt_stdby <= '1'; - end if; - if (CLK_DLY1'event and CLK_DLY1 = '1') then - if (casp_wtII = '1') then - casp6_wt <= transport '1' after 0.5 ns, '0' after 2 ns; - end if; - casp_wtII <= casp_wtI; - casp_wtI <= wt_stdby; - wt_stdby <= '0'; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -YBURST_GEN : process (casp6_rd, casp6_wt, CLK, ReadFinFlag, WriteFinFlag) - -begin - if ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1')) then - RD_WR_ST <= '1'; - yburst <= '0'; - end if; - if (CLK'event and CLK = '1') then - if (RD_WR_ST = '1' and ModeRegister.BURST_LENGTH = 8) then - yburst <= transport '1' after 2.1 ns; - end if; - RD_WR_ST <= '0'; - end if; - if ((ReadFinFlag'event and ReadFinFlag = TRUE) or (WriteFinFlag'event and WriteFinFlag = TRUE)) then - yburst <= '0'; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -DQS_PULSE_GEN : process (CLK, casp6_rd) - -begin - - if (casp6_rd'EVENT and casp6_rd = '1') then - dqs_pulse1 <= '1'; - end if; - if (CLK'EVENT and CLK = '1') then - dqs_pulse6 <= dqs_pulse5; - dqs_pulse5 <= dqs_pulse4; - dqs_pulse4 <= dqs_pulse3; - dqs_pulse3 <= dqs_pulse2; - dqs_pulse2 <= dqs_pulse1; - dqs_pulse1 <= '0'; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -DQS_GENERATION : process(CLK, dqs_pulse1, dqs_pulse2, dqs_pulse3, dqs_pulse4, dqs_pulse5, dqs_pulse6) - -begin - if (CLK'event and CLK = '1') then - if ((ModeRegister.CAS_LATENCY = 2 and dqs_pulse1 = '1') or - (ModeRegister.CAS_LATENCY = 3 and dqs_pulse2 = '1') or - (ModeRegister.CAS_LATENCY = 4 and dqs_pulse3 = '1') or - (ModeRegister.CAS_LATENCY = 5 and dqs_pulse4 = '1') or - (ModeRegister.CAS_LATENCY = 6 and dqs_pulse5 = '1')) then - if (DQS_S = 'Z') then - DQS_S <= '0'; - elsif (dqs_count = ModeRegister.BURST_LENGTH) then - DQS_S <= '0'; - else - DQS_S <= '1'; - end if; - elsif ((ModeRegister.CAS_LATENCY = 2 and dqs_pulse2 = '1') or - (ModeRegister.CAS_LATENCY = 3 and dqs_pulse3 = '1') or - (ModeRegister.CAS_LATENCY = 4 and dqs_pulse4 = '1') or - (ModeRegister.CAS_LATENCY = 5 and dqs_pulse5 = '1') or - (ModeRegister.CAS_LATENCY = 6 and dqs_pulse6 = '1')) then - if (DQS_S = '0') then - DQS_S <= '1'; - end if; - dqs_count <= 1; - elsif (dqs_count = ModeRegister.BURST_LENGTH) then - if (DQS_S = '0') then - DQS_S <= 'Z'; - end if; - dqs_count <= 0; - elsif (DQS_S = '0') then - DQS_S <= '1'; - dqs_count <= dqs_count + 1; - end if; - elsif (CLK'event and CLK = '0') then - if (DQS_S = '1') then - DQS_S <= '0'; - dqs_count <= dqs_count + 1; - end if; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -DQS_OPERATION : process(DQS_S, ExtModeRegister.OCD_PGM) - -begin - if (ExtModeRegister.QOFF = '0') then - if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE0) then - UDQS <= '0'; - LDQS <= '0'; - if (ExtModeRegister.DQSB_ENB = '1') then - UDQSB <= '1'; - LDQSB <= '1'; - else - UDQSB <= 'Z'; - LDQSB <= 'Z'; - end if; - elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE1) then - UDQS <= '1'; - LDQS <= '1'; - if (ExtModeRegister.DQSB_ENB = '1') then - UDQSB <= '0'; - LDQSB <= '0'; - else - UDQSB <= 'Z'; - LDQSB <= 'Z'; - end if; - elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then - UDQS <= 'Z'; - LDQS <= 'Z'; - UDQSB <= 'Z'; - LDQSB <= 'Z'; - elsif (DQS_S'event and DQS_S = '1') then - UDQS <= '1'; - LDQS <= '1'; - if (ExtModeRegister.DQSB_ENB = '0') then - UDQSB <= '0'; - LDQSB <= '0'; - else - UDQSB <= 'Z'; - LDQSB <= 'Z'; - end if; - elsif (DQS_S'event and DQS_S = '0') then - UDQS <= '0'; - LDQS <= '0'; - if (ExtModeRegister.DQSB_ENB = '0') then - UDQSB <= '1'; - LDQSB <= '1'; - else - UDQSB <= 'Z'; - LDQSB <= 'Z'; - end if; - elsif (DQS_S'event and DQS_S = 'Z' and DQS_S /= DQS_S'LAST_VALUE) then - UDQS <= 'Z'; - LDQS <= 'Z'; - UDQSB <= 'Z'; - LDQSB <= 'Z'; - end if; - else - UDQS <= 'Z'; - LDQS <= 'Z'; - UDQSB <= 'Z'; - LDQSB <= 'Z'; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -MEMORY_READ : process (DQS_S, CLK_DLY2, ExtModeRegister.OCD_PGM) - -variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -variable CRBI : integer := 0; -variable i, k, l : integer := 0; -begin - if (CLK_DLY2'EVENT and CLK_DLY2 = '1') then - if (casp6_rd = '1' or (ReadFlag = TRUE and yburst = '1')) then - if (casp6_rd = '1') then - BkAdd := ADD_PIPE_REG(ExtModeRegister.AL)(NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 1 downto - NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 2); - CRBI := 0; - end if; - if (BankActivatedFlag (conv_integer(BkAdd)) = '1') then - DataBuffer(i, 0) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(0))), WORD_SIZE); - DataBuffer(i, 1) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(1))), WORD_SIZE); - DataBuffer(i, 2) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(2))), WORD_SIZE); - DataBuffer(i, 3) <= conv_std_logic_vector(SA_ARRAY (conv_integer(BkAdd))(conv_integer(real_col_addr(3))), WORD_SIZE); - i := i + 1; - if (i = NUM_OF_BUFFERS) then - i := 0; - end if; - CRBI := CRBI + 4; - if (CRBI = ModeRegister.BURST_LENGTH) then - ReadFinFlag <= TRUE, FALSE after 2 ns; - CRBI := 0; - end if; - else - assert false report - "WARNING : (MEMORY_READ_PROCESS) : Accessing deactivated bank." - severity WARNING; - CRBI := CRBI + 4; - if (CRBI = ModeRegister.BURST_LENGTH) then - ReadFinFlag <= TRUE, FALSE after 2 ns; - CRBI := 0; - end if; - end if; - end if; - end if; - if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE0) then - DQ <= (others => '0'); - elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = DRIVE1) then - DQ <= (others => '1'); - elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then - DQ <= (others => 'Z'); - end if; - if (DQS_S'EVENT and DQS_S = '1' and DQS_S'LAST_VALUE = '0' and WriteFlag = FALSE) then - DQ <= transport DataBuffer(k, l), (others => 'Z') after 0.5 * clk_cycle; - l := l + 1; - elsif (DQS_S'EVENT and DQS_S = '0' and DQS_S'LAST_VALUE = '1' and WriteFlag = FALSE) then - DQ <= transport DataBuffer(k, l), (others => 'Z') after 0.5 * clk_cycle; - if (l = 3) then - l := 0; - k := k + 1; - if (k = NUM_OF_BUFFERS) then - k := 0; - end if; - else - l := l + 1; - end if; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -BURST_RD_WR_ADDR_GEN : process(CLK_DLY15, casp6_rd, casp6_wt, ReadFlag, WriteFlag) - -variable CA : std_logic_vector ((NUM_OF_COL_ADD - 1) downto 0) := (others => 'X'); -variable i, j : integer := 0; -variable col_addr_count : integer := 0; - -begin - if ((ReadFlag = FALSE) and (WriteFlag = FALSE)) then - real_col_addr(0) <= (others => '0'); - real_col_addr(1) <= (others => '0'); - real_col_addr(2) <= (others => '0'); - real_col_addr(3) <= (others => '0'); - col_addr_count := 0; - i := 0; - j := 0; - end if; - if ((casp6_rd'EVENT and casp6_rd = '1') or (casp6_wt'EVENT and casp6_wt = '1') or - (CLK_DLY15'EVENT and CLK_DLY15 = '1' and yburst = '1')) then - if (casp6_rd = '1') then - CA := ADD_PIPE_REG(ExtModeRegister.AL)(NUM_OF_COL_ADD - 1 downto 0); - col_addr_count := 0; - i := 0; - j := 0; - elsif (casp6_wt = '1') then - CA := ADD_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1)(NUM_OF_COL_ADD - 1 downto 0); - col_addr_count := 0; - i := 0; - j := 0; - end if; - if (col_addr_count < ModeRegister.BURST_LENGTH/4) then - loop - exit when (j > 3); - if ((col_addr_count = 0) and (j = 0)) then - real_col_addr(0) <= CA; - elsif (ModeRegister.BURST_LENGTH = 4) then - if (ModeRegister.BURST_MODE = SEQUENTIAL) then - real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 2)& - conv_std_logic_vector(remainder((conv_integer(CA(1 downto 0)) + i), 4), 2); - elsif (ModeRegister.BURST_MODE = INTERLEAVE) then - real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 2)& - xor_func(CA(1 downto 0), conv_std_logic_vector(i, 2)); - end if; - elsif (ModeRegister.BURST_LENGTH = 8) then - if (ModeRegister.BURST_MODE = SEQUENTIAL) then - real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 3)& - conv_std_logic_vector((conv_integer(CA(2)) + col_addr_count), 2)(0)& - conv_std_logic_vector(remainder((conv_integer(CA(1 downto 0)) + i), 4), 2); - elsif (ModeRegister.BURST_MODE = INTERLEAVE) then - real_col_addr(j) <= CA((NUM_OF_COL_ADD - 1) downto 3)& - xor_func(CA(2 downto 0), conv_std_logic_vector(i, 3)); - end if; - end if; - i := i + 1; - j := j + 1; - end loop; - end if; - j := 0; - col_addr_count := col_addr_count + 1; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -MEMORY_WRITE : process (CLK_DLY2, LDQS, UDQS, CLK) - -variable BkAdd : std_logic_vector ((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -variable TMP_VALUE : std_logic_vector ((WORD_SIZE - 1) downto 0) := (others => '0'); -variable WriteDriver : SA_TYPE; -variable i, j, k, l, m : integer := 0; -variable CWBI : integer := 0; -variable dq_buffL, dq_buffH : DATA_BUFFER_TYPE; - -begin - if (CLK'event and CLK = '1') then - dq_buffL(0) := dq_bufferL(0); - dq_buffL(1) := dq_bufferL(1); - dq_buffL(2) := dq_bufferL(2); - dq_buffL(3) := dq_bufferL(3); - dq_buffH(0) := dq_bufferH(0); - dq_buffH(1) := dq_bufferH(1); - dq_buffH(2) := dq_bufferH(2); - dq_buffH(3) := dq_bufferH(3); - end if; - if (CLK_DLY2'EVENT and CLK_DLY2 = '1') then - if (casp6_wt = '1' or (WriteFlag = TRUE and yburst = '1')) then - if (casp6_wt = '1') then - BkAdd := ADD_PIPE_REG(ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1) - (NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 1 downto NUM_OF_BANK_ADD + NUM_OF_COL_ADD - 2); - CWBI := 0; - WriteDriver := SA_ARRAY (conv_integer(BkAdd)); - end if; - if (BankActivatedFlag (conv_integer(BkAdd)) = '1') then - TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(0))), WORD_SIZE); - if (dq_buffL(0)(8) = '0' and dq_buffH(0)(8) = '0') then - TMP_VALUE := (dq_buffH(0)(7 downto 0) & dq_buffL(0)(7 downto 0)); - elsif (dq_buffL(0)(8) = '0' and dq_buffH(0)(8) = '1') then - TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(0)(7 downto 0)); - elsif (dq_buffL(0)(8) = '1' and dq_buffH(0)(8) = '0') then - TMP_VALUE := (dq_buffH(0)(7 downto 0) & TMP_VALUE(7 downto 0)); - elsif (dq_buffL(0)(8) = '1' and dq_buffH(0)(8) = '1') then - TMP_VALUE := (TMP_VALUE); - end if; - WriteDriver (conv_integer(real_col_addr(0))) := conv_integer(TMP_VALUE); - - TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(1))), WORD_SIZE); - if (dq_buffL(1)(8) = '0' and dq_buffH(1)(8) = '0') then - TMP_VALUE := (dq_buffH(1)(7 downto 0) & dq_buffL(1)(7 downto 0)); - elsif (dq_buffL(1)(8) = '0' and dq_buffH(1)(8) = '1') then - TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(1)(7 downto 0)); - elsif (dq_buffL(1)(8) = '1' and dq_buffH(1)(8) = '0') then - TMP_VALUE := (dq_buffH(1)(7 downto 0) & TMP_VALUE(7 downto 0)); - elsif (dq_buffL(1)(8) = '1' and dq_buffH(1)(8) = '1') then - TMP_VALUE := (TMP_VALUE); - end if; - WriteDriver (conv_integer(real_col_addr(1))) := conv_integer(TMP_VALUE); - - TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(2))), WORD_SIZE); - if (dq_buffL(2)(8) = '0' and dq_buffH(2)(8) = '0') then - TMP_VALUE := (dq_buffH(2)(7 downto 0) & dq_buffL(2)(7 downto 0)); - elsif (dq_buffL(2)(8) = '0' and dq_buffH(2)(8) = '1') then - TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(2)(7 downto 0)); - elsif (dq_buffL(2)(8) = '1' and dq_buffH(2)(8) = '0') then - TMP_VALUE := (dq_buffH(2)(7 downto 0) & TMP_VALUE(7 downto 0)); - elsif (dq_buffL(2)(8) = '1' and dq_buffH(2)(8) = '1') then - TMP_VALUE := (TMP_VALUE); - end if; - WriteDriver (conv_integer(real_col_addr(2))) := conv_integer(TMP_VALUE); - - TMP_VALUE := conv_std_logic_vector(WriteDriver(conv_integer(real_col_addr(3))), WORD_SIZE); - if (dq_buffL(3)(8) = '0' and dq_buffH(3)(8) = '0') then - TMP_VALUE := (dq_buffH(3)(7 downto 0) & dq_buffL(3)(7 downto 0)); - elsif (dq_buffL(3)(8) = '0' and dq_buffH(3)(8) = '1') then - TMP_VALUE := (TMP_VALUE(15 downto 8) & dq_buffL(3)(7 downto 0)); - elsif (dq_buffL(3)(8) = '1' and dq_buffH(3)(8) = '0') then - TMP_VALUE := (dq_buffH(3)(7 downto 0) & TMP_VALUE(7 downto 0)); - elsif (dq_buffL(3)(8) = '1' and dq_buffH(3)(8) = '1') then - TMP_VALUE := (TMP_VALUE); - end if; - WriteDriver (conv_integer(real_col_addr(3))) := conv_integer(TMP_VALUE); - if (conv_integer(BkAdd) = 0) then - SA_ARRAY_W0 <= WriteDriver; - tmp_w_trans0 <= '1', '0' after 2 ns; - b0_last_data_in <= (now - 2 ns); - elsif (conv_integer(BkAdd) = 1) then - SA_ARRAY_W1 <= WriteDriver; - tmp_w_trans1 <= '1', '0' after 2 ns; - b1_last_data_in <= (now - 2 ns); - elsif (conv_integer(BkAdd) = 2) then - SA_ARRAY_W2 <= WriteDriver; - tmp_w_trans2 <= '1', '0' after 2 ns; - b2_last_data_in <= (now - 2 ns); - elsif (conv_integer(BkAdd) = 3) then - SA_ARRAY_W3 <= WriteDriver; - tmp_w_trans3 <= '1', '0' after 2 ns; - b3_last_data_in <= (now - 2 ns); - end if; - CWBI := CWBI + 4; - if (CWBI = ModeRegister.BURST_LENGTH and casp_wtI /= '1' and caspwt /= '1') then - WriteFinFlag <= transport TRUE, FALSE after 2 ns; - CWBI := 0; - end if; - else - assert false report - "WARNING : (MEM_WRITE_PROCESS) : Accessing deactivated bank." - severity WARNING; - CWBI := CWBI + 4; - if (CWBI = ModeRegister.BURST_LENGTH and casp_wtI /= '1' and caspwt /= '1') then - WriteFinFlag <= transport TRUE, FALSE after 2 ns; - CWBI := 0; - end if; - end if; - end if; - end if; - if (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then - dq_bufferL(2) <= transport dq_bufferL(6); - dq_bufferL(1) <= transport dq_bufferL(5); - dq_bufferL(0) <= transport dq_bufferL(4); - dq_bufferL(3) <= transport (LDM & DQ(7 downto 0)); - end if; - if (LDQS'EVENT and LDQS = '1' and WriteFlag = TRUE) then - dq_bufferL(5) <= transport dq_bufferL(3); - dq_bufferL(4) <= transport dq_bufferL(2); - dq_bufferL(6) <= transport (LDM & DQ(7 downto 0)); - end if; - if (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then - dq_bufferH(2) <= transport dq_bufferH(6); - dq_bufferH(1) <= transport dq_bufferH(5); - dq_bufferH(0) <= transport dq_bufferH(4); - dq_bufferH(3) <= transport (UDM & DQ(15 downto 8)); - end if; - if (UDQS'EVENT and UDQS = '1' and WriteFlag = TRUE) then - dq_bufferH(5) <= transport dq_bufferH(3); - dq_bufferH(4) <= transport dq_bufferH(2); - dq_bufferH(6) <= transport (UDM & DQ(15 downto 8)); - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -REFRESH_COUNTER : process(AutoRefFlag, SelfRefFlag, CLK) - -variable rc : integer := 0; - -begin - if (AutoRefFlag'EVENT and AutoRefFlag = TRUE and TimingCheckFlag = TRUE) then - if (rc >= 8192) then - rc := rc - 8192; - end if; - if (now - refresh_check(0, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank0" - severity warning; - end if; - if (now - refresh_check(1, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank1" - severity warning; - end if; - if (now - refresh_check(2, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank2" - severity warning; - end if; - if (now - refresh_check(3, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank3" - severity warning; - end if; - tmp_ref_addr1 <= conv_std_logic_vector (rc, NUM_OF_ROW_ADD); - tmp_ref_addr1_trans <= transport '1', '0' after 1 ns; - rc := rc + 1; - end if; - if (CLK'EVENT and CLK = '1') then - if (SelfRefFlag = TRUE and TimingCheckFlag = TRUE) then - Ref_time <= Ref_time + clk_cycle; - if (Ref_time >= 7812.5 ns/(conv_integer(ExtModeRegister2.SREF_HOT) + 1)) then - Ref_time <= 0 ns; - if (rc >= 8192) then - rc := rc - 8192; - end if; - if (now - refresh_check(0, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank0" - severity warning; - end if; - if (now - refresh_check(1, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank1" - severity warning; - end if; - if (now - refresh_check(2, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank2" - severity warning; - end if; - if (now - refresh_check(3, rc) > tREF) then - assert false report - "WARNING : (REFRESH_INTERVAL) : Refresh Interval Exceeds 64ms for Bank3" - severity warning; - end if; - tmp_ref_addr1 <= conv_std_logic_vector (rc, NUM_OF_ROW_ADD); - tmp_ref_addr1_trans <= transport '1', '0' after 1 ns; - rc := rc + 1; - end if; - end if; - end if; - if (SelfRefFlag = FALSE) then - Ref_time <= 0 ns; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -PUS_CHECK : process(CLK, PrechargeAllFlag, AutoRefFlag, ModeRegister.DLL_STATE) - -variable ChipSelectBar : std_logic := '0'; -variable RowAddrStrobeBar : std_logic := '0'; -variable ColAddrStrobeBar : std_logic := '0'; -variable WriteEnableBar : std_logic := '0'; -variable Address10 : std_logic := '0'; -variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -variable ClockEnable : CKE_TYPE := (others => '0'); -variable CurrentCommand : COMMAND_TYPE := NOP; -variable i, j : integer := 0; -variable PUSNOP200USFlag : boolean := FALSE; -variable PUSAREF2Flag : boolean := FALSE; -variable BankActFlag : std_logic_vector((NUM_OF_BANKS - 1) downto 0) := (others => '0'); -variable pus_aref : integer := 0; -variable Cur_State : STATE_TYPE := IDLE; - -begin - if (PUSCheckFinFlag /= TRUE and PUSCheckFlag = TRUE) then - if (CLK'EVENT and CLK = '1') then - cur_time <= transport now; --- if (cur_time < 200000 ns) then --- if (CKE /= '0') then --- assert false report --- "ERROR : (Power Up Sequence) : CKE Should Be '0' during initial 200us!" --- severity error; --- end if; --- end if; - end if; - if (ModeRegister.DLL_STATE'EVENT and ModeRegister.DLL_STATE = RST and PUS_DLL_RESET = FALSE) then - PUS_DLL_RESET <= TRUE; - end if; - if (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE and CurrentState = PWRUP and TimingCheckFlag = TRUE) then - if (PUSPCGAFlag1 = TRUE) then - assert (PUS_DLL_RESET = TRUE) report - "ERROR : (Power Up Sequence) : The 2nd PCGA Command Should Be Issued after DLL Reset!" - severity error; - else - PUSPCGAFlag1 <= TRUE; --- assert (cur_time >= tPUS - clk_cycle) report --- "WARNING : (Power Up Sequence) : PCGA Command Should Be Issued after 200us(Input Stable)!" --- severity warning; - end if; - end if; - if (AutoRefFlag'EVENT and AutoRefFlag = TRUE) then - assert (PUSPCGAFlag2 = TRUE) report - "WARNING : (Power Up Sequence) : Needs Precharge All Bank Command before Auto Refresh !" - severity warning; - pus_aref := pus_aref + 1; - if (pus_aref >= 2) then - PUSAREF2Flag := TRUE; - end if; - if ((PUSNOP200USFlag = TRUE) and (PUSAREF2Flag = TRUE)) then - PUSCheckFinFlag <= TRUE; - end if; - end if; - ClockEnable := CKEN; - if ClockEnable (-1) = '1' then - ChipSelectBar := CSB; - RowAddrStrobeBar := RASB; - ColAddrStrobeBar := CASB; - WriteEnableBar := WEB; - Address10 := ADDR(10); - BkAdd := (BA); - BankActFlag := BankActivatedFlag; - end if; - COMMAND_DECODE (ChipSelectBar, RowAddrStrobeBar, ColAddrStrobeBar, WriteEnableBar, - Address10, BkAdd, ClockEnable, CurrentCommand, BankActFlag, Cur_State); - if ((PUSNOP200USFlag = FALSE) and (PUSAREF2Flag /= TRUE)) then - if (CLK = '1') then - i := i + 1; --- if (i * clk_cycle >= tPUS - clk_cycle) then - PUSNOP200USFlag := TRUE; --- end if; - end if; - elsif ((CurrentCommand = PCGA) and (PUSNOP200USFlag = TRUE) and (PUSPCGAFlag1 = TRUE) and (PUSAREF2Flag /= TRUE)) then - PUSPCGAFlag2 <= TRUE; - end if; - elsif (PUSCheckFinFlag /= TRUE and PUSCheckFlag = FALSE) then - PUSCheckFinFlag <= TRUE; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -BUS_CHANGE_DETECT : process(CKE, WEB, CASB, RASB, CSB, LDM, UDM, ADDR, DQ) - -begin - if (CKE'EVENT and CKE /= CKE'LAST_VALUE) then - cke_ch <= transport now after 0.1 ns; end if; - if (WEB'EVENT and WEB /= WEB'LAST_VALUE) then - web_ch <= transport now after 0.1 ns; end if; - if (CASB'EVENT and CASB /= CASB'LAST_VALUE) then - casb_ch <= transport now after 0.1 ns; end if; - if (RASB'EVENT and RASB /= RASB'LAST_VALUE) then - rasb_ch <= transport now after 0.1 ns; end if; - if (CSB'EVENT and CSB /= CSB'LAST_VALUE) then - csb_ch <= transport now after 0.1 ns; end if; - if (LDM'EVENT and LDM /= LDM'LAST_VALUE) then - ldm_ch <= transport now after 0.1 ns; end if; - if (UDM'EVENT and UDM /= UDM'LAST_VALUE) then - udm_ch <= transport now after 0.1 ns; end if; - if (ADDR(0)'EVENT and ADDR(0) /= ADDR(0)'LAST_VALUE) then - a0_ch <= transport now after 0.1 ns; end if; - if (ADDR(1)'EVENT and ADDR(1) /= ADDR(1)'LAST_VALUE) then - a1_ch <= transport now after 0.1 ns; end if; - if (ADDR(2)'EVENT and ADDR(2) /= ADDR(2)'LAST_VALUE) then - a2_ch <= transport now after 0.1 ns; end if; - if (ADDR(3)'EVENT and ADDR(3) /= ADDR(3)'LAST_VALUE) then - a3_ch <= transport now after 0.1 ns; end if; - if (ADDR(4)'EVENT and ADDR(4) /= ADDR(4)'LAST_VALUE) then - a4_ch <= transport now after 0.1 ns; end if; - if (ADDR(5)'EVENT and ADDR(5) /= ADDR(5)'LAST_VALUE) then - a5_ch <= transport now after 0.1 ns; end if; - if (ADDR(6)'EVENT and ADDR(6) /= ADDR(6)'LAST_VALUE) then - a6_ch <= transport now after 0.1 ns; end if; - if (ADDR(7)'EVENT and ADDR(7) /= ADDR(7)'LAST_VALUE) then - a7_ch <= transport now after 0.1 ns; end if; - if (ADDR(8)'EVENT and ADDR(8) /= ADDR(8)'LAST_VALUE) then - a8_ch <= transport now after 0.1 ns; end if; - if (ADDR(9)'EVENT and ADDR(9) /= ADDR(9)'LAST_VALUE) then - a9_ch <= transport now after 0.1 ns; end if; - if (ADDR(10)'EVENT and ADDR(10) /= ADDR(10)'LAST_VALUE) then - a10_ch <= transport now after 0.1 ns; end if; - if (ADDR(11)'EVENT and ADDR(11) /= ADDR(11)'LAST_VALUE) then - a11_ch <= transport now after 0.1 ns; end if; - if (ADDR(12)'EVENT and ADDR(12) /= ADDR(12)'LAST_VALUE) then - a12_ch <= transport now after 0.1 ns; end if; - if (BA(0)'EVENT and BA(0) /= BA(0)'LAST_VALUE) then - ba0_ch <= transport now after 0.1 ns; end if; - if (BA(1)'EVENT and BA(1) /= BA(1)'LAST_VALUE) then - ba1_ch <= transport now after 0.1 ns; end if; - if (DQ(0)'EVENT and STD_LOGIC_TO_BIT (DQ(0)) /= STD_LOGIC_TO_BIT (DQ(0)'LAST_VALUE)) then - dq0_ch <= transport now after 0.1 ns; end if; - if (DQ(1)'EVENT and STD_LOGIC_TO_BIT (DQ(1)) /= STD_LOGIC_TO_BIT (DQ(1)'LAST_VALUE)) then - dq1_ch <= transport now after 0.1 ns; end if; - if (DQ(2)'EVENT and STD_LOGIC_TO_BIT (DQ(2)) /= STD_LOGIC_TO_BIT (DQ(2)'LAST_VALUE)) then - dq2_ch <= transport now after 0.1 ns; end if; - if (DQ(3)'EVENT and STD_LOGIC_TO_BIT (DQ(3)) /= STD_LOGIC_TO_BIT (DQ(3)'LAST_VALUE)) then - dq3_ch <= transport now after 0.1 ns; end if; - if (DQ(4)'EVENT and STD_LOGIC_TO_BIT (DQ(4)) /= STD_LOGIC_TO_BIT (DQ(4)'LAST_VALUE)) then - dq4_ch <= transport now after 0.1 ns; end if; - if (DQ(5)'EVENT and STD_LOGIC_TO_BIT (DQ(5)) /= STD_LOGIC_TO_BIT (DQ(5)'LAST_VALUE)) then - dq5_ch <= transport now after 0.1 ns; end if; - if (DQ(6)'EVENT and STD_LOGIC_TO_BIT (DQ(6)) /= STD_LOGIC_TO_BIT (DQ(6)'LAST_VALUE)) then - dq6_ch <= transport now after 0.1 ns; end if; - if (DQ(7)'EVENT and STD_LOGIC_TO_BIT (DQ(7)) /= STD_LOGIC_TO_BIT (DQ(7)'LAST_VALUE)) then - dq7_ch <= transport now after 0.1 ns; end if; - if (DQ(8)'EVENT and STD_LOGIC_TO_BIT (DQ(8)) /= STD_LOGIC_TO_BIT (DQ(8)'LAST_VALUE)) then - dq8_ch <= transport now after 0.1 ns; end if; - if (DQ(9)'EVENT and STD_LOGIC_TO_BIT (DQ(9)) /= STD_LOGIC_TO_BIT (DQ(9)'LAST_VALUE)) then - dq9_ch <= transport now after 0.1 ns; end if; - if (DQ(10)'EVENT and STD_LOGIC_TO_BIT (DQ(10)) /= STD_LOGIC_TO_BIT (DQ(10)'LAST_VALUE)) then - dq10_ch <= transport now after 0.1 ns; end if; - if (DQ(11)'EVENT and STD_LOGIC_TO_BIT (DQ(11)) /= STD_LOGIC_TO_BIT (DQ(11)'LAST_VALUE)) then - dq11_ch <= transport now after 0.1 ns; end if; - if (DQ(12)'EVENT and STD_LOGIC_TO_BIT (DQ(12)) /= STD_LOGIC_TO_BIT (DQ(12)'LAST_VALUE)) then - dq12_ch <= transport now after 0.1 ns; end if; - if (DQ(13)'EVENT and STD_LOGIC_TO_BIT (DQ(13)) /= STD_LOGIC_TO_BIT (DQ(13)'LAST_VALUE)) then - dq13_ch <= transport now after 0.1 ns; end if; - if (DQ(14)'EVENT and STD_LOGIC_TO_BIT (DQ(14)) /= STD_LOGIC_TO_BIT (DQ(14)'LAST_VALUE)) then - dq14_ch <= transport now after 0.1 ns; end if; - if (DQ(15)'EVENT and STD_LOGIC_TO_BIT (DQ(15)) /= STD_LOGIC_TO_BIT (DQ(15)'LAST_VALUE)) then - dq15_ch <= transport now after 0.1 ns; end if; -end process; - ------------------------------------------------------------------------------------------------------ - -CLK_TIMING : process (CLK) - variable clk_last_cycle : time := 0 ns; - variable i : integer := 0; -begin - if (CLK'event and CLK='1') then - if (Part_Number = B400) then - tRCD <= ModeRegister.CAS_LATENCY * 5 ns; - tRP <= ModeRegister.CAS_LATENCY * 5 ns; - if (ModeRegister.CAS_LATENCY = 3) then - tRAS <= 40 ns; - else - tRAS <= 45 ns; - end if; - elsif (Part_Number = B533) then - tRCD <= ModeRegister.CAS_LATENCY * 3.75 ns; - tRP <= ModeRegister.CAS_LATENCY * 3.75 ns; - tRAS <= 45 ns; - elsif (Part_Number = B667) then - tRCD <= ModeRegister.CAS_LATENCY * 3 ns; - tRP <= ModeRegister.CAS_LATENCY * 3 ns; - tRAS <= 45 ns; - elsif (Part_Number = B800) then - tRCD <= ModeRegister.CAS_LATENCY * 2.5 ns; - tRP <= ModeRegister.CAS_LATENCY * 2.5 ns; - tRAS <= 45 ns; - end if; - tRC <= tRAS + tRP; - tCCD <= 2 * clk_cycle; - tCCD_cycles <= 2; - tDQSH <= 0.35 * clk_cycle; - tDQSL <= 0.35 * clk_cycle; - tWPSTmin <= 0.4 * clk_cycle; - tWPSTmax <= 0.6 * clk_cycle; - tDQSSmin <= 0.75 * clk_cycle; - tDQSSmax <= 1.25 * clk_cycle; - tMRD <= 2 * clk_cycle; - tMRD_cycles <= 2; - tWPRE <= 0.25 * clk_cycle; - tCH <= 0.45 * clk_cycle; - tCL <= 0.45 * clk_cycle; - if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - assert (clk_cycle >= tCKmin (Part_Number)) report - "ERROR : (CLK_TIMING) : Clock period is too small." - severity error; - assert (clk_cycle <= tCKmax (Part_Number)) report - "ERROR : (CLK_TIMING) : Clock period is too large." - severity error; - end if; - if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - assert (now - clk_last_falling >= tCL) report - "ERROR : (CLK_TIMING) : Clock low time is too small." - severity error; - end if; - clk_last_rising <= transport now; - end if; - if (CLK'event and CLK = '0') then - clk_last_falling <= transport now; - if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - assert (now - clk_last_rising >= tCH) report - "ERROR : (CLK_TIMING) : Clock high time is too small." - severity error; - end if; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -DQS_TIMING : process (LDQS, UDQS, caspwt) - -begin - if (caspwt'EVENT and caspwt = '1') then - wr_cmd_time <= transport now - 1 ns; - udspre_enable <= '0'; - ldspre_enable <= '0'; - udsh_dsl_enable <= '0'; - ldsh_dsl_enable <= '0'; - end if; - if (TimingCheckFlag = TRUE) then - if (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = 'Z' and WriteFlag = TRUE) then - udspre_enable <= '1'; - end if; - if (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = 'Z' and WriteFlag = TRUE) then - ldspre_enable <= '1'; - end if; - if (UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then - udqs_last_rising <= transport now; - if (udspre_enable = '1') then - if ((now - clk_last_falling) < tWPRE) then - assert false report - "WARNING : (tWPRE_CHECK) : tWPRE time violation!" - severity WARNING; - end if; - if ((now - wr_cmd_time) < tDQSSmin) then - assert false report - "WARNING : (tDQSS_CHECK) : Minimum tDQSS time violation!" - severity WARNING; - end if; - if ((now - wr_cmd_time) > tDQSSmax) then - assert false report - "WARNING : (tDQSS_CHECK) : Maximum tDQSS time violation!" - severity WARNING; - end if; - udspre_enable <= '0'; - udsh_dsl_enable <= '1'; - elsif (udsh_dsl_enable = '1') then - if ((now - udqs_last_falling) < tDQSL) then - assert false report - "ERROR : (tDQSL_CHECK) : Minimum tDQSL time violation!" - severity ERROR; - end if; - end if; - elsif (UDQS'EVENT and UDQS = '0' and UDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then - udqs_last_falling <= transport now; - if (udsh_dsl_enable = '1') then - if ((now - udqs_last_rising) < tDQSH) then - assert false report - "ERROR : (tDQSH_CHECK) : Minimum tDQSH time violation!" - severity ERROR; - end if; - end if; - udspre_enable <= '0'; - ldspre_enable <= '0'; - end if; - if (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then - ldqs_last_rising <= transport now; - if (ldspre_enable = '1') then - if ((now - clk_last_falling) < tWPRE) then - assert false report - "WARNING : (tWPRE_CHECK) : tWPRE time violation!" - severity WARNING; - end if; - if ((now - wr_cmd_time) < tDQSSmin) then - assert false report - "WARNING : (tDQSS_CHECK) : Minimum tDQSS time violation!" - severity WARNING; - end if; - if ((now - wr_cmd_time) > tDQSSmax) then - assert false report - "WARNING : (tDQSS_CHECK) : Maximum tDQSS time violation!" - severity WARNING; - end if; - ldspre_enable <= '0'; - ldsh_dsl_enable <= '1'; - elsif (ldsh_dsl_enable = '1') then - if ((now - ldqs_last_falling) < tDQSL) then - assert false report - "ERROR : (tDQSL_CHECK) : Minimum tDQSL time violation!" - severity ERROR; - end if; - end if; - elsif (LDQS'EVENT and LDQS = '0' and LDQS'LAST_VALUE = '1' and WriteFlag = TRUE) then - ldqs_last_falling <= transport now; - if (ldsh_dsl_enable = '1') then - if ((now - ldqs_last_rising) < tDQSH) then - assert false report - "ERROR : (tDQSH_CHECK) : Minimum tDQSH time violation!" - severity ERROR; - end if; - end if; - udspre_enable <= '0'; - ldspre_enable <= '0'; - end if; - if (LDQS'EVENT and LDQS = 'Z' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE and caspwt = '0') then - if ((now - ldqs_last_falling) < tWPSTmin) then - assert false report - "WARNING : (tWPST_CHECK) : Minimum tWPST time violation!" - severity WARNING; - end if; - if ((now - ldqs_last_falling) > tWPSTmax) then - assert false report - "WARNING : (tWPST_CHECK) : Maximum tWPST time violation!" - severity WARNING; - end if; - ldspre_enable <= '0'; - ldsh_dsl_enable <= '0'; - end if; - if (UDQS'EVENT and UDQS = 'Z' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE and caspwt = '0') then - if ((now - udqs_last_falling) < tWPSTmin) then - assert false report - "WARNING : (tWPST_CHECK) : Minimum tWPST time violation!" - severity WARNING; - end if; - if ((now - udqs_last_falling) > tWPSTmax) then - assert false report - "WARNING : (tWPST_CHECK) : Maximum tWPST time violation!" - severity WARNING; - end if; - udspre_enable <= '0'; - udsh_dsl_enable <= '0'; - end if; - end if; -end process; - ------------------------------------------------------------------------------------------------------ - -SETUP_CHECK : process (CLK, UDQS, LDQS) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - if (((UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0') or (UDQS'EVENT and UDQS = '0') or - (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0') or (LDQS'EVENT and LDQS = '0')) and - (WriteFlag = TRUE)) then - assert ( - ((now - dq0_ch) >= tDS (Part_Number)) and - ((now - dq1_ch) >= tDS (Part_Number)) and - ((now - dq2_ch) >= tDS (Part_Number)) and - ((now - dq3_ch) >= tDS (Part_Number)) and - ((now - dq4_ch) >= tDS (Part_Number)) and - ((now - dq5_ch) >= tDS (Part_Number)) and - ((now - dq6_ch) >= tDS (Part_Number)) and - ((now - dq7_ch) >= tDS (Part_Number)) and - ((now - dq8_ch) >= tDS (Part_Number)) and - ((now - dq9_ch) >= tDS (Part_Number)) and - ((now - dq10_ch) >= tDS (Part_Number)) and - ((now - dq11_ch) >= tDS (Part_Number)) and - ((now - dq12_ch) >= tDS (Part_Number)) and - ((now - dq13_ch) >= tDS (Part_Number)) and - ((now - dq14_ch) >= tDS (Part_Number)) and - ((now - dq15_ch) >= tDS (Part_Number))) report - "ERROR : (SETUP_HOLD) : Data input setup/hold time violation." - severity error; - end if; - if (CLK'EVENT and CLK = '1') then - assert ( - ((now - a0_ch) >= tIS (Part_Number)) and - ((now - a1_ch) >= tIS (Part_Number)) and - ((now - a2_ch) >= tIS (Part_Number)) and - ((now - a3_ch) >= tIS (Part_Number)) and - ((now - a4_ch) >= tIS (Part_Number)) and - ((now - a5_ch) >= tIS (Part_Number)) and - ((now - a6_ch) >= tIS (Part_Number)) and - ((now - a7_ch) >= tIS (Part_Number)) and - ((now - a8_ch) >= tIS (Part_Number)) and - ((now - a9_ch) >= tIS (Part_Number)) and - ((now - a10_ch) >= tIS (Part_Number)) and - ((now - a11_ch) >= tIS (Part_Number)) and - ((now - a12_ch) >= tIS (Part_Number)) and - ((now - ba0_ch) >= tIS (Part_Number)) and - ((now - ba1_ch) >= tIS (Part_Number))) report - "ERROR : (SETUP_HOLD) : Address input setup time violation." - severity error; - assert ( - ((now - csb_ch) >= tIS (Part_Number)) and - ((now - rasb_ch) >= tIS (Part_Number)) and - ((now - casb_ch) >= tIS (Part_Number)) and - ((now - web_ch) >= tIS (Part_Number))) report - "ERROR : (SETUP_HOLD) : Command input setup time violation." - severity error; - assert (now - cke_ch >= tIS (Part_Number)) report - "ERROR : (SETUP_HOLD) : Clock enable input setup time violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -DM_SETUP_HOLD_CHECK : process (LDM, UDM, LDQS, UDQS) -begin -if (TimingCheckFlag = TRUE) then - if (LDM'EVENT and LDM = '1' and WriteFlag = TRUE) then - ldm_last_rising <= transport now; - elsif (LDM'EVENT and LDM = '0' and WriteFlag = TRUE) then - if ((now - ldqs_last_rising) < tDH (Part_Number)) then - assert false report - "ERROR : (tDH_CHECK) : LDM Hold Time Violation!" - severity ERROR; - end if; - end if; - if (UDM'EVENT and UDM = '1' and WriteFlag = TRUE) then - udm_last_rising <= transport now; - elsif (UDM'EVENT and UDM = '0' and WriteFlag = TRUE) then - if ((now - udqs_last_rising) < tDH (Part_Number)) then - assert false report - "ERROR : (tDH_CHECK) : UDM Hold Time Violation!" - severity ERROR; - end if; - end if; - if (LDQS'EVENT and LDQS = '1' and LDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then - if ((now - ldm_last_rising) < tDS (Part_Number)) then - assert false report - "ERROR : (tDS_CHECK) : LDM Setup Time Violation!" - severity ERROR; - end if; - end if; - if (UDQS'EVENT and UDQS = '1' and UDQS'LAST_VALUE = '0' and WriteFlag = TRUE) then - if ((now - udm_last_rising) < tDS (Part_Number)) then - assert false report - "ERROR : (tDS_CHECK) : UDM Setup Time Violation!" - severity ERROR; - end if; - end if; -end if; -end process; ------------------------------------------------------------------------------------------------------ - -A_HOLD_CHECK : process (ADDR) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - assert ((now - clk_last_rising) >= tIH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Address hold time violation." - severity error; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -UDQ_HOLD_CHECK : process (DQ(15 downto 8)) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE and WriteFlag = TRUE) then - assert ((now - udqs_last_rising) >= tDH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Hold time violation of CLK rising-edge aligned data." - severity error; - assert ((now - udqs_last_falling) >= tDH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Hold time violation of CLK falling-edge aligned data." - severity error; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -LDQ_HOLD_CHECK : process (DQ(7 downto 0)) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE and WriteFlag = TRUE) then - assert ((now - ldqs_last_rising) >= tDH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Hold time violation of CLK rising-edge aligned data." - severity error; - assert ((now - udqs_last_falling) >= tDH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Hold time violation of CLK falling-edge aligned data." - severity error; -end if; -end process; ------------------------------------------------------------------------------------------------------ - -CMD_HOLD_CHECK : process (CSB, WEB, RASB, CASB) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - assert ((now - clk_last_rising) >= tIH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Command hold time violation." - severity error; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -CKE_HOLD_CHECK : process (CKE) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - assert ((now - clk_last_rising) >= tIH (Part_Number)) report - "ERROR : (SETUP_HOLD) : Clock enable hold time violation." - severity error; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tRC_CHECK : process (BankActivateFlag) -variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - BkAdd := (BA); - if (BkAdd = "00" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then - assert ((now - b0_last_activate) >= tRC) report - "ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation." - severity error; - elsif (BkAdd = "01" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then - assert ((now - b1_last_activate) >= tRC) report - "ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation." - severity error; - elsif (BkAdd = "10" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then - assert ((now - b2_last_activate) >= tRC) report - "ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation." - severity error; - elsif (BkAdd = "11" and (BankActivateFlag'EVENT and BankActivateFlag = TRUE)) then - assert ((now - b3_last_activate) >= tRC) report - "ERROR : (tRC_CHECK) : Row Address Strobe cycle time violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tRCD_CHECK : process (casp6_rd, casp6_wt) -variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - BkAdd := (BA); - if (BkAdd = "00" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then - assert ((now - b0_last_activate - 1.5 ns) >= tRCD) report - "ERROR : (tRCD_CHECK) : Active to column Access delay time violation." - severity error; - b0_last_column_access <= transport now after 1 ns; - b0_last_column_access_cycle <= transport clk_cycle_count; - elsif (BkAdd = "01" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then - assert ((now - b1_last_activate - 1.5 ns) >= tRCD) report - "ERROR : (tRCD_CHECK) : Active to column Access delay time violation." - severity error; - b1_last_column_access <= transport now after 1 ns; - b1_last_column_access_cycle <= transport clk_cycle_count; - elsif (BkAdd = "10" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then - assert ((now - b2_last_activate - 1.5 ns) >= tRCD) report - "ERROR : (tRCD_CHECK) : Active to column Access delay time violation." - severity error; - b2_last_column_access <= transport now after 1 ns; - b2_last_column_access_cycle <= transport clk_cycle_count; - elsif (BkAdd = "11" and ((casp6_rd'event and casp6_rd = '1') or (casp6_wt'event and casp6_wt = '1'))) then - assert ((now - b3_last_activate - 1.5 ns) >= tRCD) report - "ERROR : (tRCD_CHECK) : Active to column Access delay time violation." - severity error; - b3_last_column_access <= transport now after 1 ns; - b3_last_column_access_cycle <= transport clk_cycle_count; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tRAS_CHECK : process (BankActivatedFlag(0), BankActivatedFlag(1), BankActivatedFlag(2), BankActivatedFlag(3)) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - if (BankActivatedFlag(0)'EVENT and BankActivatedFlag(0) = '0' and BankActivatedFlag(0)'LAST_VALUE = '1') then - assert ((now - b0_last_activate) >= tRAS) report - "ERROR : (tRAS_CHECK) : Bank0 active time minimum violation." - severity error; - assert ((now - b0_last_activate) <= tRASmax (Part_Number)) report - "ERROR : (tRAS_CHECK) : Bank0 active time maximum violation." - severity error; - end if; - if (BankActivatedFlag(1)'EVENT and BankActivatedFlag(1) = '0' and BankActivatedFlag(1)'LAST_VALUE = '1') then - assert ((now - b1_last_activate) >= tRAS) report - "ERROR : (tRAS_CHECK) : Bank1 active time minimum violation." - severity error; - assert ((now - b1_last_activate) <= tRASmax (Part_Number)) report - "ERROR : (tRAS_CHECK) : Bank1 active time maximum violation." - severity error; - end if; - if (BankActivatedFlag(2)'EVENT and BankActivatedFlag(2) = '0' and BankActivatedFlag(2)'LAST_VALUE = '1') then - assert ((now - b2_last_activate) >= tRAS) report - "ERROR : (tRAS_CHECK) : Bank2 active time minimum violation." - severity error; - assert ((now - b2_last_activate) <= tRASmax (Part_Number)) report - "ERROR : (tRAS_CHECK) : Bank2 active time maximum violation." - severity error; - end if; - if (BankActivatedFlag(3)'EVENT and BankActivatedFlag(3) = '0' and BankActivatedFlag(3)'LAST_VALUE = '1') then - assert ((now - b3_last_activate) >= tRAS) report - "ERROR : (tRAS_CHECK) : Bank3 active time minimum violation." - severity error; - assert ((now - b3_last_activate) <= tRASmax (Part_Number)) report - "ERROR : (tRAS_CHECK) : Bank3 active time maximum violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tRP_CHECK : process (BankActivateFlag) -variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - BkAdd := (BA); - if (BkAdd = "00" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then - assert ((now - b0_last_precharge) >= tRP) report - "ERROR : (tRP_CHECK) : Precharge to active delay time violation." - severity error; - elsif (BkAdd = "01" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then - assert ((now - b1_last_precharge) >= tRP) report - "ERROR : (tRP_CHECK) : Precharge to active delay time violation." - severity error; - elsif (BkAdd = "10" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then - assert ((now - b2_last_precharge) >= tRP) report - "ERROR : (tRP_CHECK) : Precharge to active delay time violation." - severity error; - elsif (BkAdd = "11" and (BankActivateFlag'event and BankActivateFlag = TRUE)) then - assert ((now - b3_last_precharge) >= tRP) report - "ERROR : (tRP_CHECK) : Precharge to active delay time violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tRRD_CHECK : process (BankActivateFlag) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - if (BankActivateFlag'EVENT and BankActivateFlag = TRUE) then - assert ((now - b0_last_activate) >= tRRD) report - "ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation." - severity error; - assert ((now - b1_last_activate) >= tRRD) report - "ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation." - severity error; - assert ((now - b2_last_activate) >= tRRD) report - "ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation." - severity error; - assert ((now - b3_last_activate) >= tRRD) report - "ERROR : (tRRD_CHECK) : Active to the other bank active delay time violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tCCD_CHECK : process (casp6_rd, casp6_wt) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - if ((casp6_rd'EVENT and casp6_rd = '1') or (casp6_wt'EVENT and casp6_wt = '1')) then --- print("last_column_access : " & --- tost(b0_last_column_access_cycle) & " " & --- tost(b1_last_column_access_cycle) & " " & --- tost(b2_last_column_access_cycle) & " " & --- tost(b3_last_column_access_cycle) & " " & --- "clk_cycle_count: " & tost(clk_cycle_count)); - - assert (clk_cycle_count - b0_last_column_access_cycle >= tCCD_cycles or - clk_cycle_count <= b0_last_column_access_cycle) report - "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." - severity error; - assert (clk_cycle_count - b1_last_column_access_cycle >= tCCD_cycles or - clk_cycle_count <= b1_last_column_access_cycle) report - "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." - severity error; - assert (clk_cycle_count - b2_last_column_access_cycle >= tCCD_cycles or - clk_cycle_count <= b2_last_column_access_cycle) report - "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." - severity error; - assert (clk_cycle_count - b3_last_column_access_cycle >= tCCD_cycles or - clk_cycle_count <= b3_last_column_access_cycle) report - "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." - severity error; - --- assert ((now - b0_last_column_access) >= tCCD) report --- "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." --- severity error; --- assert ((now - b1_last_column_access) >= tCCD) report --- "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." --- severity error; --- assert ((now - b2_last_column_access) >= tCCD) report --- "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." --- severity error; --- assert ((now - b3_last_column_access) >= tCCD) report --- "ERROR : (tCCD_CHECK) : Column access to column access delay time violation." --- severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tWR_CHECK : process (PrechargeFlag, PrechargeAllFlag) -variable BkAdd : std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0) := (others => 'X'); -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - BkAdd := (BA); - if (BkAdd = "00" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then - assert ((now - b0_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - elsif (BkAdd = "01" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then - assert ((now - b1_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - elsif (BkAdd = "10" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then - assert ((now - b2_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - elsif (BkAdd = "11" and (PrechargeFlag'EVENT and PrechargeFlag = TRUE)) then - assert ((now - b3_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - elsif (PrechargeAllFlag'EVENT and PrechargeAllFlag = TRUE) then - assert ((now - b0_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - assert ((now - b1_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - assert ((now - b2_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - assert ((now - b3_last_data_in) >= tWR(Part_Number)) report - "ERROR : (tWR_CHECK) : Last data in to precharge command delay violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tWTR_CHECK : process (casp6_rd) -begin -if (TimingCheckFlag = TRUE and ModeRegisterSetFlag = TRUE) then - if (casp6_rd'event and casp6_rd = '1') then - assert ((now - b0_last_data_in - 1 ns) >= tWTR) report - "ERROR : (tWTR_CHECK) : Last data in to read command delay violation." - severity error; - assert ((now - b1_last_data_in - 1 ns) >= tWTR) report - "ERROR : (tWTR_CHECK) : Last data in to read command delay violation." - severity error; - assert ((now - b2_last_data_in - 1 ns) >= tWTR) report - "ERROR : (tWTR_CHECK) : Last data in to read command delay violation." - severity error; - assert ((now - b3_last_data_in - 1 ns) >= tWTR) report - "ERROR : (tWTR_CHECK) : Last data in to read command delay violation." - severity error; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -tMRD_CHECK : process (mrs_cmd_in) -begin -if (mrs_cmd_in'event and mrs_cmd_in = '1') then --- assert ((now - last_mrs_set) >= tMRD) report --- "ERROR : (tMRD_CHECK) : MRS to MRS delay violation." --- severity error; - -- print("clk_cycle_count: " & tost(clk_cycle_count) & " last_mrs_set_cycle:" & tost(last_mrs_set_cycle)); - assert (clk_cycle_count-last_mrs_set_cycle >= tMRD_cycles or - clk_cycle_count <= last_mrs_set_cycle) report - "ERROR : (tMRD_CHECK) : MRS to MRS delay violation." - severity error; - last_mrs_set <= transport now; - last_mrs_set_cycle <= transport clk_cycle_count; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -OCD_DEFAULT_CHECK : process (ExtModeRegister.OCD_PGM) -begin -if (TimingCheckFlag = TRUE) then - if (ExtModeRegister.OCD_PGM = CAL_DEFAULT and DLL_reset = '1') then - assert false report - "WARNING : DLL RESET to OCD Default Delay Violation." - severity warning; - end if; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -OCD_ADJUST_CHECK : process (ExtModeRegister.OCD_PGM) -begin -if (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = CAL_EXIT) then - if (TimingCheckFlag = TRUE) then - assert (now - last_ocd_adjust_cmd >= (ExtModeRegister.AL + ModeRegister.CAS_LATENCY + 1 + - ModeRegister.TWR) * clk_cycle) report - "WARNINg : OCD ADJUST to OCD CALIBRATION EXIT Delay Violation." - severity warning; - end if; -elsif (ExtModeRegister.OCD_PGM'event and ExtModeRegister.OCD_PGM = ADJUST) then - last_ocd_adjust_cmd <= transport now; -end if; -end process; - ------------------------------------------------------------------------------------------------------ - -End Behavioral_Model_HY5PS121621F; - ------------------------------------------------------------------------------------------------------ diff --git a/lib/hynix/ddr2/HY5PS121621F_PACK.vhd b/lib/hynix/ddr2/HY5PS121621F_PACK.vhd deleted file mode 100644 index ada92bfc..00000000 --- a/lib/hynix/ddr2/HY5PS121621F_PACK.vhd +++ /dev/null @@ -1,544 +0,0 @@ ------------------------------------------------------- --- Hynix 4BANKS X 8M X 16bits DDR2 SDRAM -- --- -- --- Packages for HY5PS121621F.vhd -- --- -- --- HHHH HHHH -- --- HHHH HHHH -- --- ,O0O. ,O0 .HH ,O0 .HH -- --- (O000O)(000 )H(000 )H Hynix -- --- `O0O' `O0 'HH `O0 'HH -- --- HHHH HHHH Semiconductor -- --- HHHH HHHH -- ------------------------------------------------------- - ---------------------------------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.all; -library grlib; -use grlib.stdlib.all; ---USE IEEE.STD_LOGIC_ARITH.all; ---USE IEEE.STD_LOGIC_UNSIGNED.all; ---------------------------------------------------------------------------------------------------- - -package HY5PS121621F_PACK is - ---------------------------------------------------------------------------------------------------- - constant NUM_OF_MROPCODE : integer := 13; - - constant NUM_OF_ROW_ADD : integer := 13; - - constant NUM_OF_COL_ADD : integer := 10; - - constant NUM_OF_BANK_ADD : integer := 2; - - constant WORD_SIZE : integer := 16; - - constant NUM_OF_ROWS : integer := 2**NUM_OF_ROW_ADD; - - constant NUM_OF_COLS : integer := 2**NUM_OF_COL_ADD; - - constant NUM_OF_BANKS : integer := 2**NUM_OF_BANK_ADD; - - constant NUM_OF_BUFFERS : integer := 3; - - type PART_NUM_TYPE is (B400, B533, B667, B800); - - type PART_NUM is array (B400 to B800) of time; - - constant tCKmin : PART_NUM := (B400 => 5 ns, B533 => 3.75 ns, B667 => 3 ns, B800 => 2.5 ns); - - constant tCKmax : PART_NUM := (B400 => 8 ns, B533 => 8 ns, B667 => 8 ns, B800 => 8 ns); - - constant tWR : PART_NUM := (B400 => 15 ns, B533 => 15 ns, B667 => 15 ns, B800 => 15 ns); - - constant tDS : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns); - - constant tDH : PART_NUM := (B400 => 0.4 ns, B533 => 0.35 ns, B667 => 0.3 ns, B800 => 0.3 ns); - - constant tIS : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns); - - constant tIH : PART_NUM := (B400 => 0.6 ns, B533 => 0.5 ns, B667 => 0.5 ns, B800 => 0.4 ns); - - constant tWTR : PART_NUM := (B400 => 10 ns, B533 => 7.5 ns, B667 => 7.5 ns, B800 => 7.5 ns); - - constant tRASmax : PART_NUM := (B400 => 70000 ns, B533 => 70000 ns, B667 => 70000 ns, B800 => 70000 ns); - - constant tRRD : time := 10 ns; - - constant tREF : time := 64 ms; - - constant tRFC : time := 75 ns; - - constant tRTP : time := 7.5 ns; - - constant tXSNR : time := tRFC + 10 ns; - - constant tXP : integer := 2; - - constant tCKE : integer := 3; - - constant tXARD : integer := 2; - - constant tXARDS : integer := 2; - - constant tXSRD : integer := 200; - - constant tPUS : time := 200 us; - - type STATE_TYPE is ( - PWRDN, - PWRUP, - SLFREF, - IDLE, - RACT, - READ, - WRITE); - - type COMMAND_TYPE is ( - DSEL, - NOP, - MRS, - EMRS1, - EMRS2, - EMRS3, - ACT, - RD, - RDAP, - WR, - WRAP, - PCG, - PCGA, - AREF, - SREF, - SREX, - PDEN, - PDEX, - ERROR, - ILLEGAL); - - type BURST_MODE_TYPE is ( - SEQUENTIAL, - INTERLEAVE); - - type OCD_DRIVE_MODE_TYPE is ( - CAL_EXIT, - DRIVE1, - DRIVE0, - ADJUST, - CAL_DEFAULT); - - subtype CL_TYPE is integer range 0 to 6; - - subtype BL_TYPE is integer range 4 to 8; - - subtype TWR_TYPE is integer range 2 to 6; - - type DLL_RST is ( - RST, - NORST); - - type MODE_REGISTER is - record - CAS_LATENCY : CL_TYPE; - BURST_MODE : BURST_MODE_TYPE; - BURST_LENGTH : BL_TYPE; - DLL_STATE : DLL_RST; - SAPD : std_logic; - TWR : TWR_TYPE; - end record; - - type EMR_TYPE is - record - DLL_EN : std_logic; - AL : CL_TYPE; - QOFF : std_logic; - DQSB_ENB : std_logic; - RDQS_EN : std_logic; - OCD_PGM : OCD_DRIVE_MODE_TYPE; - end record; - - type EMR2_TYPE is - record - SREF_HOT : std_logic; - end record; - - type REF_CHECK is array (0 to (NUM_OF_BANKS - 1), 0 to (NUM_OF_ROWS - 1)) of time; - - type COL_ADDR_TYPE is array (0 to 3) of std_logic_vector((NUM_OF_COL_ADD - 1) downto 0); - - type DATA_BUFFER_TYPE is array (0 to 6) of std_logic_vector(8 downto 0); - - subtype COL_DATA_TYPE is integer range 0 to 65535; - - type SA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE; - - type ROW_DATA_TYPE is array (0 to (NUM_OF_COLS - 1)) of COL_DATA_TYPE; - - type RAM_PNTR is ACCESS ROW_DATA_TYPE; - - type SA_ARRAY_TYPE is array (0 to (NUM_OF_BANKS - 1)) of SA_TYPE; - - type MEM_CELL_TYPE is array (0 to (NUM_OF_ROWS - 1)) of RAM_PNTR; - - subtype DATA_TYPE is std_logic_vector ((WORD_SIZE - 1) downto 0); - - type BUFFER_TYPE is array (0 to NUM_OF_BUFFERS - 1, 0 to 3) of DATA_TYPE; - - type ADD_PIPE_TYPE is array (0 to 12) of std_logic_vector((NUM_OF_COL_ADD + NUM_OF_BANK_ADD - 1) downto 0); - - type CKE_TYPE is array (integer range -1 to 0) of std_logic; - - subtype MROPCODE_TYPE is std_logic_vector ((NUM_OF_MROPCODE - 1) downto 0); - - procedure COMMAND_DECODE ( - variable - CSB, - RASB, - CASB, - WEB, - A10 : in std_logic; - variable - Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0); - variable - CKE : in CKE_TYPE; - variable - COMMAND : out COMMAND_TYPE; - variable - BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0); - variable - State : in STATE_TYPE); - - procedure MODE_REGISTER_SET ( - MROPCODE : in MROPCODE_TYPE; - MR : out MODE_REGISTER); - - procedure EXT_MODE_REGISTER_SET ( - MROPCODE : in MROPCODE_TYPE; - EMR : out EMR_TYPE); - - procedure EXT_MODE_REGISTER_SET2 ( - MROPCODE : in MROPCODE_TYPE; - EMR : out EMR2_TYPE); - - function REMAINDER ( - val0 : in integer; - val1 : in integer) return integer; - - function XOR_FUNC ( - val0 : in std_logic_vector; - val1 : in std_logic_vector) return std_logic_vector; - - function CHAR_TO_STD_LOGIC ( - c : in character) - return std_logic; - - function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT; - -end HY5PS121621F_PACK; ------------------------------------------------------HY5DU121622T Package - ---------------------------------------------------------------------------------------------------- - -package body HY5PS121621F_PACK is - ---------------------------------------------------------------------------------------------------- - procedure COMMAND_DECODE ( - variable - CSB, - RASB, - CASB, - WEB, - A10 : in std_logic; - variable - Bank_Add : in std_logic_vector((NUM_OF_BANK_ADD - 1) downto 0); - variable - CKE : in CKE_TYPE; - variable - COMMAND : out COMMAND_TYPE; - variable - BankState : in std_logic_vector((NUM_OF_BANKS - 1) downto 0); - variable - State : in STATE_TYPE) Is - - begin - case CKE (-1) is - when '1' => - case CKE (0) is - when '0' => - if (BankState = "0000") then - if (CSB = '0' and RASB = '0' and CASB = '0' and WEB = '1') then - COMMAND := SREF; - elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then - COMMAND := PDEN; - else - COMMAND := ILLEGAL; - end if; - elsif ((CSB = '1') or (CSB = '0' and RASB = '1' and CASB = '1' and WEB = '1')) then - COMMAND := PDEN; - else - COMMAND := ILLEGAL; - end if; - when '1' => - if (CSB = '1') then - COMMAND := DSEL; - elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then - COMMAND := NOP; - elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='1') then - if (A10 = '0') then - COMMAND := RD; - else - COMMAND := RDAP; - end if; - elsif (CSB = '0' and RASB = '1' and CASB = '0' and WEB ='0') then - if (A10 = '0') then - COMMAND := WR; - else - COMMAND := WRAP; - end if; - elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='1') then - COMMAND := ACT; - elsif (CSB = '0' and RASB = '0' and CASB = '1' and WEB ='0') then - if (A10 = '0') then - COMMAND := PCG; - else - COMMAND := PCGA; - end if; - elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='1') then - COMMAND := AREF; - elsif (CSB = '0' and RASB = '0' and CASB = '0' and WEB ='0') then - if (BankState = "0000") then - if (Bank_Add = "00") then - COMMAND := MRS; - elsif (Bank_Add = "01") then - COMMAND := EMRS1; - elsif (Bank_Add = "10") then - COMMAND := EMRS2; - elsif (Bank_Add = "11") then - COMMAND := EMRS3; - end if; - else - COMMAND := ILLEGAL; - end if; - end if; - when others => - COMMAND := ERROR; - end case; - when '0' => - case CKE (0) is - when '0' => - COMMAND := NOP; - when '1' => - if (State = PWRUP) then - COMMAND := NOP; - elsif (CSB = '1') then - if (State = SLFREF) then - COMMAND := SREX; - elsif (State = PWRDN) then - COMMAND := PDEX; - end if; - elsif (CSB = '0' and RASB = '1' and CASB = '1' and WEB ='1') then - if (State = SLFREF) then - COMMAND := SREX; - elsif (State = PWRDN) then - COMMAND := PDEX; - end if; - else - COMMAND := ERROR; - end if; - when others => - COMMAND := ERROR; - end case; - when others => - COMMAND := ERROR; - end case; - end COMMAND_DECODE; ------------------------------------------------------------------------------------------------- - procedure MODE_REGISTER_SET ( - MROPCODE : in MROPCODE_TYPE; - MR : out MODE_REGISTER) is - begin - if (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then - MR.CAS_LATENCY := 2; - elsif (MROPCODE(6) = '0' and MROPCODE(5) = '1' and MROPCODE(4) = '1')then - MR.CAS_LATENCY := 3; - elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '0')then - MR.CAS_LATENCY := 4; - elsif (MROPCODE(6) = '1' and MROPCODE(5) = '0' and MROPCODE(4) = '1')then - MR.CAS_LATENCY := 5; - elsif (MROPCODE(6) = '1' and MROPCODE(5) = '1' and MROPCODE(4) = '0')then - MR.CAS_LATENCY := 6; - else - assert false report - "ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Cas_Latency Encountered!" - severity WARNING; - end if; - if MROPCODE(3) = '0' then - MR.BURST_MODE := SEQUENTIAL; - elsif MROPCODE(3) = '1' then - MR.BURST_MODE := INTERLEAVE; - end if; - if MROPCODE(8) = '0' then - MR.DLL_STATE := NORST; - elsif MROPCODE(8) = '1' then - MR.DLL_STATE := RST; - end if; - if MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '0' then - MR.BURST_LENGTH := 4; - elsif MROPCODE(2) = '0' and MROPCODE(1) = '1' and MROPCODE(0) = '1' then - MR.BURST_LENGTH := 8; - else - assert false report - "ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Burst_Length Encountered!" - severity ERROR; - end if; - if MROPCODE(12) = '0' then - MR.SAPD := '0'; - elsif MROPCODE(12) = '1' then - MR.SAPD := '1'; - end if; - if MROPCODE(11) = '0' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then - MR.TWR := 2; - elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '0' then - MR.TWR := 3; - elsif MROPCODE(11) = '0' and MROPCODE(10) = '1' and MROPCODE(9) = '1' then - MR.TWR := 4; - elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '0' then - MR.TWR := 5; - elsif MROPCODE(11) = '1' and MROPCODE(10) = '0' and MROPCODE(9) = '1' then - MR.TWR := 6; - else - assert false report - "ERROR : (MODE_REGISTER_SET_PROCEDURE) : Invalid Write Recovery Value Encountered!" - severity ERROR; - end if; - end MODE_REGISTER_SET; ------------------------------------------------------------------------------------------------- - procedure EXT_MODE_REGISTER_SET ( - MROPCODE : in MROPCODE_TYPE; - EMR : out EMR_TYPE) is - begin - if (MROPCODE(0) = '0') then - EMR.DLL_EN := '1'; - elsif (MROPCODE(0) = '1') then - EMR.DLL_EN := '0'; - end if; - if (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then - EMR.AL := 0; - elsif (MROPCODE(5) = '0' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then - EMR.AL := 1; - elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '0')then - EMR.AL := 2; - elsif (MROPCODE(5) = '0' and MROPCODE(4) = '1' and MROPCODE(3) = '1')then - EMR.AL := 3; - elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '0')then - EMR.AL := 4; - elsif (MROPCODE(5) = '1' and MROPCODE(4) = '0' and MROPCODE(3) = '1')then - EMR.AL := 5; - else - assert false report - "ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid Additive_Latency Encountered!" - severity WARNING; - end if; - if MROPCODE(12) = '0' then - EMR.QOFF := '0'; - elsif MROPCODE(12) = '1' then - EMR.QOFF := '1'; - end if; - if MROPCODE(10) = '0' then - EMR.DQSB_ENB := '0'; - elsif MROPCODE(10) = '1' then - EMR.DQSB_ENB := '1'; - end if; - if MROPCODE(11) = '0' then - EMR.RDQS_EN := '0'; - elsif MROPCODE(11) = '1' then - EMR.RDQS_EN := '1'; - end if; - if MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then - EMR.OCD_PGM := CAL_EXIT; - elsif MROPCODE(9) = '0' and MROPCODE(8) = '0' and MROPCODE(7) = '1' then - EMR.OCD_PGM := DRIVE1; - elsif MROPCODE(9) = '0' and MROPCODE(8) = '1' and MROPCODE(7) = '0' then - EMR.OCD_PGM := DRIVE0; - elsif MROPCODE(9) = '1' and MROPCODE(8) = '0' and MROPCODE(7) = '0' then - EMR.OCD_PGM := ADJUST; - elsif MROPCODE(9) = '1' and MROPCODE(8) = '1' and MROPCODE(7) = '1' then - EMR.OCD_PGM := CAL_DEFAULT; - else - assert false report - "ERROR : (EXT_MODE_REGISTER_SET_PROCEDURE) : Invalid OCD Calibration Program Encountered!" - severity ERROR; - end if; - end EXT_MODE_REGISTER_SET; ------------------------------------------------------------------------------------------------- - procedure EXT_MODE_REGISTER_SET2 ( - MROPCODE : in MROPCODE_TYPE; - EMR : out EMR2_TYPE) is - begin - if (MROPCODE(7) = '0') then - EMR.SREF_HOT := '0'; - elsif (MROPCODE(7) = '1') then - EMR.SREF_HOT := '1'; - end if; - end EXT_MODE_REGISTER_SET2; ------------------------------------------------------------------------------------------------- - function REMAINDER (val0 : in integer; val1 : in integer) return integer is - variable Result : integer; - begin - Result := val0; - loop - exit when Result < val1; - Result := Result - val1; - end loop; - return Result; - end REMAINDER; ------------------------------------------------------------------------------------------------- - function XOR_FUNC (val0 : in std_logic_vector; val1 : in std_logic_vector) return std_logic_vector is - variable Result : std_logic_vector(2 downto 0); - variable j : integer := 0; - begin - for i in val0'RANGE LOOP - if (val0(i) /= val1(i)) then - Result(i) := '1'; - else - Result(i) := '0'; - end if; - j := j + 1; - end loop; - return Result((j - 1) downto 0); - end XOR_FUNC; ------------------------------------------------------------------------------------------------- - function CHAR_TO_STD_LOGIC ( - c : in character) - return std_logic is - variable r : std_logic; - begin - case c is - when '0' => r := '0'; - when 'L' => r := 'L'; - when '1' => r := '1'; - when 'H' => r := 'H'; - when 'W' => r := 'W'; - when 'Z' => r := 'Z'; - when 'U' => r := 'U'; - when '-' => r := '-'; - when others => r := 'X'; - end case; - return r; - end CHAR_TO_STD_LOGIC; ------------------------------------------------------------------------------------------------- - function STD_LOGIC_TO_BIT (V: STD_LOGIC) return BIT is - variable Result: BIT; - begin - case V is - when '0' | 'L' => - Result := '0'; - when '1' | 'H' => - Result := '1'; - when 'X' | 'W' | 'Z' | 'U' | '-' => - Result := '0'; - end case; - return Result; - end STD_LOGIC_TO_BIT; ------------------------------------------------------------------------------------------------- -end HY5PS121621F_PACK; diff --git a/lib/hynix/ddr2/components.vhd b/lib/hynix/ddr2/components.vhd deleted file mode 100644 index 1e693af6..00000000 --- a/lib/hynix/ddr2/components.vhd +++ /dev/null @@ -1,57 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2007 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- Package: components --- File: components.vhd --- Author: Jiri Gaisler, Gaisler Research --- Description: Component declaration of Hynix RAM ------------------------------------------------------------------------------- - --- pragma translate_off - -library ieee; -use ieee.std_logic_1164.all; -use std.textio.all; -use work.HY5PS121621F_PACK.all; - -package components is - -component HY5PS121621F - generic ( - TimingCheckFlag : boolean := TRUE; - PUSCheckFlag : boolean := FALSE; - Part_Number : PART_NUM_TYPE := B400; - bbits : natural := 64; - index : integer := 0; - fname : string := "ram.srec"; - fdelay : integer := 0); - Port ( DQ : inout std_logic_vector(15 downto 0) := (others => 'Z'); - LDQS : inout std_logic := 'Z'; - LDQSB : inout std_logic := 'Z'; - UDQS : inout std_logic := 'Z'; - UDQSB : inout std_logic := 'Z'; - LDM : in std_logic; - WEB : in std_logic; - CASB : in std_logic; - RASB : in std_logic; - CSB : in std_logic; - BA : in std_logic_vector(1 downto 0); - ADDR : in std_logic_vector(12 downto 0); - CKE : in std_logic; - CLK : in std_logic; - CLKB : in std_logic; - UDM : in std_logic ); -End component; - -end; - --- pragma translate_on diff --git a/lib/hynix/ddr2/vhdlsim.txt b/lib/hynix/ddr2/vhdlsim.txt deleted file mode 100644 index a3a15e1b..00000000 --- a/lib/hynix/ddr2/vhdlsim.txt +++ /dev/null @@ -1,3 +0,0 @@ -HY5PS121621F_PACK.vhd -HY5PS121621F.vhd -components.vhd diff --git a/lib/hynix/dirs.txt b/lib/hynix/dirs.txt deleted file mode 100644 index 65d6bfb9..00000000 --- a/lib/hynix/dirs.txt +++ /dev/null @@ -1 +0,0 @@ -ddr2 diff --git a/lib/hynix/libs.txt b/lib/hynix/libs.txt deleted file mode 100644 index 4dc6cadc..00000000 --- a/lib/hynix/libs.txt +++ /dev/null @@ -1 +0,0 @@ -hynix diff --git a/lib/micron/ddr_sdram/ddr2.v b/lib/micron/ddr_sdram/ddr2.v deleted file mode 100644 index 32130a20..00000000 --- a/lib/micron/ddr_sdram/ddr2.v +++ /dev/null @@ -1,2272 +0,0 @@ -/**************************************************************************************** -* -* File Name: ddr2.v -* Version: 5.20 -* Model: BUS Functional -* -* Dependencies: ddr2_parameters.vh -* -* Description: Micron SDRAM DDR2 (Double Data Rate 2) -* -* Limitation: - doesn't check for average refresh timings -* - positive ck and ck_n edges are used to form internal clock -* - positive dqs and dqs_n edges are used to latch data -* - test mode is not modeled -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set Debug = 0 to disable $display messages -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --------------------------------------------------------------------------------------- -* 1.00 JMK 07/29/03 Initial Release -* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH -* 2.20 JMK 08/07/03 General cleanup -* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters. -* Added AL_MIN and AL_MAX parameters. -* Removed support for OCD. -* 2.40 JMK 01/15/04 Removed verilog 2001 constructs. -* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command. -* 2.60 JMK 04/20/04 Fixed tWTR check. -* 2.70 JMK 04/30/04 Added tRFC maximum check. -* Combined Self Refresh and Power Down always blocks. -* Added Reset Function (CKE LOW Anytime). -* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active. -* Added checks for tRAS, tWR, tRTP to any bank during Pre-All. -* tRFC maximum violation will only display one time. -* 2.90 JMK 11/05/04 Fixed DQS checking during write. -* Fixed false tRFC max assertion during power up and self ref. -* Added warning for 200us CKE low time during initialization. -* Added -3, -3E, and -37V speed grades to ddr2_parameters.v -* 3.00 JMK 04/22/05 Removed ODT off requirement during power down. -* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters. -* Added ODT status messages. -* Updated the initialization sequence. -* Disable ODT and CLK pins during self refresh. -* Disable cmd and addr pins during power down and self refresh. -* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks. -* Changed tAXPD message from error to a warning. -* Added tDSS checking. -* Removed tDQSL checking during tWPRE and tWPST. -* Fixed a burst order error during writes. -* Renamed parameters file with .vh extension. -* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ. -* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge. -* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase. -* Clock jitter can be tolerated within specification range. -* Clock frequency is sampled from the CK pin. -* Scaleable up to 64 DQ and 16 DQS bits. -* Read data can be randomly skewed using RANDOM_OUT_DELAY. -* Parameterized read and write DQS, and read DQ. -* Initialization can be bypassed using initialize task. -* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined. -* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined. -* 4.30 JMK 02/15/06 Added dummy write to initialization sequence. -* Removed tWPST maximum checking. -* Rising dqs_n edge latches data when enabled in EMR. -* Fixed a sign error in the tJIT(cc) calculation. -* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined. -* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions. -* Fixed tRCD and tWTR checking. -* Errors entering Power Down or Self Refresh will cause reset. -* Ignore dqs_n when disabled in EMR. -* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh) -* Fixed tRFC max assertion during self refresh. -* Fixed tANPD checking during Power Down. -* Removed dummy write from initialization sequence. -* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh. -* Removed Auto Precharge error message during Power Down Enter. -* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n. -* RDQS can only be enabled in EMR for x8 configurations. -* CAS latency is checked vs frequency when DLL locks. -* tMOD changed from tCK units to ns units. -* Added 50 Ohm setting for Rtt in EMR. -* Improved checking of DQS during writes. -* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16. -****************************************************************************************/ - -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ps / 1ps - -module ddr2 ( - ck, - ck_n, - cke, - cs_n, - ras_n, - cas_n, - we_n, - dm_rdqs, - ba, - addr, - dq, - dqs, - dqs_n, - rdqs_n, - odt -); - -// `include "ddr2_parameters.vh" - - -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - - // Timing parameters based on Speed Grade - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- -`ifdef sg25E - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle) - parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle) - parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle) - parameter TQHS = 300; // tQHS ps Data hold skew factor - parameter TAC = 400; // tAC ps DQ output access time from CK/CK# - parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK# - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble - parameter TIS = 200; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12000; // tRCD ps Active to Read/Write command time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency -`else `ifdef sg25 - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle) - parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle) - parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle) - parameter TQHS = 300; // tQHS ps Data hold skew factor - parameter TAC = 400; // tAC ps DQ output access time from CK/CK# - parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK# - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble - parameter TIS = 200; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TWTR = 10000; // tWTR ps Write to Read command delay - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency -`else `ifdef sg3E - parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 125; // tJIT(per) ps Period JItter - parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter - parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle) - parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle) - parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle) - parameter TQHS = 340; // tQHS ps Data hold skew factor - parameter TAC = 450; // tAC ps DQ output access time from CK/CK# - parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble - parameter TIS = 200; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12000; // tRCD ps Active to Read/Write command time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TRP = 12000; // tRP ps Precharge command period - parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command - parameter CL_TIME = 12000; // CL ps Minimum CAS Latency -`else `ifdef sg3 - parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 125; // tJIT(per) ps Period JItter - parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter - parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle) - parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle) - parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle) - parameter TQHS = 340; // tQHS ps Data hold skew factor - parameter TAC = 450; // tAC ps DQ output access time from CK/CK# - parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble - parameter TIS = 200; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency -`else `ifdef sg37E - parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 125; // tJIT(per) ps Period JItter - parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter - parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle) - parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle) - parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle) - parameter TQHS = 400; // tQHS ps Data hold skew factor - parameter TAC = 500; // tAC ps DQ output access time from CK/CK# - parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK# - parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TWPRE = 0.25; // tWPRE tCK DQS Write Preamble - parameter TIS = 250; // tIS ps Input Setup Time - parameter TIH = 375; // tIH ps Input Hold Time - parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency -`else - `define sg5E - parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 125; // tJIT(per) ps Period JItter - parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter - parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle) - parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle) - parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle) - parameter TQHS = 450; // tQHS ps Data hold skew factor - parameter TAC = 600; // tAC ps DQ output access time from CK/CK# - parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK# - parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TWPRE = 0.25; // tWPRE tCK DQS Write Preamble - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 475; // tIH ps Input Hold Time - parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TWTR = 10000; // tWTR ps Write to Read command delay - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency -`endif `endif `endif `endif `endif - - // Timing Parameters - - // Mode Register - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 5; // AL tCK Maximum Additive Latency - parameter CL_MIN = 3; // CL tCK Minimum CAS Latency - parameter CL_MAX = 6; // CL tCK Maximum CAS Latency - parameter WR_MIN = 2; // WR tCK Minimum Write Recovery - parameter WR_MAX = 6; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - // Clock - parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time - parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width - // Data - parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK# - parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK# - parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width - // Data Strobe - parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - // Command and Address - parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width - parameter TCCD = 2; // tCCD tCK Cas to Cas command delay - parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time - parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time - parameter TDLLK = 200; // tDLLK tCK DLL locking time - // Refresh - parameter TRFC_MIN = 75000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value - // Self Refresh - parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command - parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - // ODT - parameter TAOND = 2; // tAOND tCK ODT turn-on delay - parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay - parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode) - parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode) - parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency - parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency - parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition - // Power Down - parameter TXARD = 2; // tXARD tCK Exit active power down to a read command - parameter TXP = 2; // tXP tCK Exit power down to a non-read command - parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width - - // Size Parameters based on Part Width - -`ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW Four access window time for the number of activates in an 8 bank device -`else `ifdef x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW Four access window time for the number of activates in an 8 bank device -`else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW Four access window time for the number of activates in an 8 bank device -`endif `endif - - // Size Parameters - parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BL_BITS = 3; // the number of bits required to count to MAX_BL - parameter BO_BITS = 2; // the number of Burst Order Bits - - // Simulation parameters - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 0; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last valid read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 1; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last valid write strobe - // text macros - `define DQ_PER_DQS DQ_BITS/DQS_BITS - `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); - if ((1< BL_MAX) - $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); - $timeformat (-12, 1, " ps", 1); - reset_task; - seed = RANDOM_SEED; - ck_cntr = 0; - end - - // calculate the absolute value of a real number - function real abs_value; - input arg; - real arg; - begin - if (arg < 0.0) - abs_value = -1.0 * arg; - else - abs_value = arg; - end - endfunction - -`ifdef MAX_MEM -`else - function get_index; - input [`MAX_BITS-1:0] addr; - begin : index - get_index = 0; - for (memory_index=0; memory_index TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); - if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end - {1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task - {1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK - {1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && ((ck_cntr - ck_write < write_latency + burst_length/2 + 2) || ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end - {1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end - {1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]); - else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end - {1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end - {1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end - {1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end - {1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end - endcase - end - endtask - - task cmd_task; - input cke; - input [2:0] cmd; - input [BA_BITS-1:0] bank; - input [ADDR_BITS-1:0] addr; - reg [`BANKS:0] i; - integer j; - reg [`BANKS:0] tfaw_cntr; - reg [COL_BITS-1:0] col; - begin - if ((cmd < NOP) && (cmd != PRECHARGE)) begin - for (j=0; j TRFC_MAX) begin - $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); - er_trfc_max = 1; - end - end - if (cke) begin - case (cmd) - LOAD_MODE : begin - if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank); - case (bank) - 0 : begin - // Burst Length - burst_length = 1<= BL_MIN) && (burst_length <= BL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end - // Burst Order - burst_order = addr[3]; - if (!burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); - end else if (burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); - end - // CAS Latency - cas_latency = addr[6:4]; - read_latency = cas_latency + additive_latency; - write_latency = read_latency - 1; - if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end - // Test Mode - if (!addr[7]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]); - end - // DLL Reset - dll_reset = addr[8]; - if (!dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); - end else if (dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); - dll_locked = 0; - ck_dll_reset <= ck_cntr; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); - end - // Write Recovery - write_recovery = addr[11:9] + 1; - if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end - // Power Down Mode - low_power = addr[12]; - if (!low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank); - end else if (low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); - end - end - 1 : begin - // DLL Enable - dll_en = !addr[0]; - if (!dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); - end - // Output Drive Strength - if (!addr[1]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank); - end else if (addr[1]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]); - end - // ODT Rtt - odt_rtt = {addr[6], addr[2]}; - if (odt_rtt == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); - odt_en = 0; - end else if (odt_rtt == 2'b01) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank); - odt_en = 1; - tm_odt_en <= $time; - end else if (odt_rtt == 2'b10) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank); - odt_en = 1; - tm_odt_en <= $time; - end else if (odt_rtt == 2'b11) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank); - odt_en = 1; - tm_odt_en <= $time; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt); - odt_en = 0; - end - // Additive Latency - additive_latency = addr[5:3]; - read_latency = cas_latency + additive_latency; - write_latency = read_latency - 1; - if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency); - end - // OCD Program - ocd = addr[9:7]; - if (ocd == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank); - end else if (ocd == 3'b111) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd); - end - - // DQS_N Enable - dqs_n_en = !addr[10]; - if (!dqs_n_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (dqs_n_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en); - end - // RDQS Enable - rdqs_en = addr[11]; - if (!rdqs_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (rdqs_en) begin -`ifdef x8 - if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank); -`else - $display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank); - rdqs_en = 0; -`endif - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en); - end - // Output Enable - out_en = !addr[12]; - if (!out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en); - end - end - 2, 3 : begin - if (addr !== 0) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - endcase - init_mode_reg[bank] = 1; - ck_load_mode <= ck_cntr; - end - end - REFRESH : begin - if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); - er_trfc_max = 0; - ref_cntr = ref_cntr + 1; - tm_refresh <= $time; - end - end - PRECHARGE : begin - // tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of - // the number of banks already open or closed. - if (addr[AP] && (`BANKS == 8)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]); - precharge_all = 1'b1; - end - // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), - // or if the previously open row is already in the process of precharging - if (|active_bank) begin - for (i=0; i<`BANKS; i=i+1) begin - if (active_bank[i]) begin - if (addr[AP] || (i == bank)) begin - - for (j=0; j 3) begin - $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); - end - end - - if (!init_done) begin - $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (active_bank[bank]) begin - $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (addr >= 1<>1) & -1*(1<= 1<>1) & -1*(1<= 1< $time) -// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time); - init_step = init_step + 1; - end - 1 : if (dll_en) init_step = init_step + 1; - 2 : begin - if (&init_mode_reg && dll_reset) begin - active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges - ref_cntr = 0; // require refresh - init_step = init_step + 1; - end - end - 3 : if (ref_cntr == 2) begin - init_step = init_step + 1; - end - 4 : if (!dll_reset) init_step = init_step + 1; - 5 : if (ocd == 3'b111) init_step = init_step + 1; - 6 : begin - if (ocd == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); - init_done = 1; - end - end - endcase - end - end else if (prev_cke) begin - if ((!init_done) && (init_step > 1)) begin - $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end - case (cmd) - REFRESH : begin - for (j=0; j TDQSS*tck_avg)) - $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - if (check_write_dqs_low[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16); - end - check_write_preamble <= 0; - check_write_postamble <= 0; - check_write_dqs_low <= 0; - end - - if (wr_pipeline[0] || rd_pipeline[0]) begin - bank = ba_pipeline[0]; - row = row_pipeline[0]; - col = col_pipeline[0]; - burst_cntr = 0; - memory_read(bank, row, col, memory_data); - end - - // burst counter - if (burst_cntr < burst_length) begin - burst_position = col ^ burst_cntr; - if (!burst_order) begin - burst_position[BO_BITS-1:0] = col + burst_cntr; - end - burst_cntr = burst_cntr + 1; - end - - // write dqs counter - if (wr_pipeline[WDQS_PRE + 1]) begin - wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1; - end - // write dqs - if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble - check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 1) begin // write data - if ((wdqs_cntr - WDQS_PST)%2) begin - check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}}; - end else begin - check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}}; - end - end - if (wdqs_cntr == WDQS_PST) begin // write postamble - check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 0) begin - wdqs_cntr = wdqs_cntr - 1; - end - - // write dq - if (dq_in_valid) begin // write data - bit_mask = 0; - if (diff_ck) begin - for (i=0; i>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - if (burst_cntr%BL_MIN == 0) begin - memory_write(bank, row, col, memory_data); - end - end - if (wr_pipeline[1]) begin - wdq_cntr = burst_length; - end - if (wdq_cntr > 0) begin - wdq_cntr = wdq_cntr - 1; - dq_in_valid = 1'b1; - end else begin - dq_in_valid = 1'b0; - dqs_in_valid <= 1'b0; - for (i=0; i<32; i=i+1) begin - wdqs_pos_cntr[i] <= 0; - end - end - if (wr_pipeline[0]) begin - b2b_write <= 1'b0; - end - if (wr_pipeline[2]) begin - if (dqs_in_valid) begin - b2b_write <= 1'b1; - end - dqs_in_valid <= 1'b1; - end - // read dqs enable counter - if (rd_pipeline[RDQSEN_PRE]) begin - rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1; - end - if (rdqsen_cntr > 0) begin - rdqsen_cntr = rdqsen_cntr - 1; - dqs_out_en = 1'b1; - end else begin - dqs_out_en = 1'b0; - end - - // read dqs counter - if (rd_pipeline[RDQS_PRE]) begin - rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1; - end - // read dqs - if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble - dqs_out = 1'b0; - end else if (rdqs_cntr > RDQS_PST) begin // read data - dqs_out = rdqs_cntr - RDQS_PST; - end else if (rdqs_cntr > 0) begin // read postamble - dqs_out = 1'b0; - end else begin - dqs_out = 1'b1; - end - if (rdqs_cntr > 0) begin - rdqs_cntr = rdqs_cntr - 1; - end - - // read dq enable counter - if (rd_pipeline[RDQEN_PRE]) begin - rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST; - end - if (rdqen_cntr > 0) begin - rdqen_cntr = rdqen_cntr - 1; - dq_out_en = 1'b1; - end else begin - dq_out_en = 1'b0; - end - // read dq - if (rd_pipeline[0]) begin - rdq_cntr = burst_length; - end - if (rdq_cntr > 0) begin // read data - dq_temp = memory_data>>(burst_position*DQ_BITS); - dq_out = dq_temp; - if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - rdq_cntr = rdq_cntr - 1; - end else begin - dq_out = {DQ_BITS{1'b1}}; - end - - // delay signals prior to output - if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin - for (i=0; i dqsck[i] + TQHS + TDQSQ) begin - dqsck_max = dqsck[i] + TQHS + TDQSQ; - end - dqsck_min = -1*TDQSCK; - if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin - dqsck_min = dqsck[i] - TQHS - TDQSQ; - end - - // DQSQ requirements - // 1.) less than tAC - DQSCK - // 2.) less than tDQSQ - // 3.) greater than -tAC - // 4.) greater than tQH from previous DQS edge - dqsq_min = -1*TAC; - if (dqsq_min < dqsck[i] - TQHS) begin - dqsq_min = dqsck[i] - TQHS; - end - if (dqsck_min == dqsck_max) begin - dqsck[i] = dqsck_min; - end else begin - dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); - end - dqsq_max = TAC; - if (dqsq_max > TDQSQ + dqsck[i]) begin - dqsq_max = TDQSQ + dqsck[i]; - end - - dqs_out_en_dly[i] <= #(tck_avg/2 + ($random % TAC)) dqs_out_en; - dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out; - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2 + ($random % TAC)) dq_out_en; - if (dqsq_min == dqsq_max) begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; - end else begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; - end - end - end - end else begin - out_delay = tck_avg/2; - dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; - dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; - dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; - dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; - end - end - endtask - - always @(diff_ck) begin : main - integer i; - - if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) - $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); - data_task; - if (diff_ck) begin - // check setup of command signals - if ($time > TIS) begin - if ($time - tm_cke < TIS) - $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); - if (cke_in) begin - for (i=0; i<22; i=i+1) begin - if ($time - tm_cmd_addr[i] < TIS) - $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); - end - end - end - - // update current state - if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin - // check CL value against the clock frequency - if (cas_latency*tck_avg < CL_TIME) - $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg); - // check WR value against the clock frequency - if (write_recovery*tck_avg < TWR) - $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); - dll_locked = 1; - end - if (precharge_all) begin - for (i=0; i<`BANKS; i=i+1) begin - tm_bank_precharge[i] = $time; - end - precharge_all = 1'b0; - tm_precharge = $time; - end - if (|auto_precharge_bank) begin - for (i=0; i<`BANKS; i=i+1) begin - // Write with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command - if (write_precharge_bank[i]) begin - if ($time - tm_bank_activate[i] >= TRAS_MIN) begin - if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - write_precharge_bank[i] = 0; - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - end - end - end - // Read with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Additive Latency plus BL/2 cycles after Read command - // 3. tRTP after the last 4-bit prefetch - if (read_precharge_bank[i]) begin - if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin - read_precharge_bank[i] = 0; - // In case the internal precharge is pushed out by tRTP, tRP starts at the point where - // the internal precharge happens (not at the next rising clock edge after this event). - if ($time - tm_bank_read_end[i] < TRTP) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); - active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - end - end - end - end - end - - // respond to incoming command - if (cke_in ^ prev_cke) begin - ck_cke <= ck_cntr; - end - - cmd_task(cke_in, cmd_n_in, ba_in, addr_in); - if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin - al_pipeline[2*additive_latency] = 1'b1; - end - if (al_pipeline[0]) begin - // check tRCD after additive latency - if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin - if (rd_pipeline[2*cas_latency - 1]) begin - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); - end else begin - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); - end - end - // check tWTR after additive latency - if (rd_pipeline[2*cas_latency - 1]) begin - if ($time - tm_write_end < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - end - end - if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin - tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time; - end - for (i=0; i<`BANKS; i=i+1) begin - if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin - tm_bank_write_end[i] <= $time; - tm_write_end <= $time; - end - end - - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - tjit_cc_time = $time - tm_ck_pos - tck_i; - tck_i = $time - tm_ck_pos; - tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tck_avg = tck_avg + tck_i/$itor(TDLLK); - tck_sample[ck_cntr%TDLLK] = tck_i; - tjit_per_rtime = tck_i - tck_avg; - - if (dll_locked) begin - // check accumulated error - terr_nper_rtime = 0; - for (i=0; i<50; i=i+1) begin - terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; - terr_nper_rtime = abs_value(terr_nper_rtime); - case (i) - 0 :; - 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); - 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); - 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); - 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); - 5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER); - default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER); - endcase - end - - // check tCK min/max/jitter - if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) - $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); - if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) - $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); - if (TCK_MIN - tck_avg >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); - if (tck_avg - TCK_MAX >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); - if (tm_ck_pos + TCK_MIN - TJIT_PER > $time) - $display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time); - if (tm_ck_pos + TCK_MAX + TJIT_PER < $time) - $display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER); - - // check tCL - if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time) - $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time); - if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time) - $display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY); - if (tcl_avg < TCL_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg); - if (tcl_avg > TCL_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg); - end - - // calculate the tch avg jitter - tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tch_avg = tch_avg + tch_i/$itor(TDLLK); - tch_sample[ck_cntr%TDLLK] = tch_i; - - // update timers/counters - tcl_i <= $time - tm_ck_neg; - end - - prev_odt <= odt_in; - // update timers/counters - ck_cntr <= ck_cntr + 1; - tm_ck_pos <= $time; - end else begin - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - if (dll_locked) begin - if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time) - $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time); - if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time) - $display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY); - if (tch_avg < TCH_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg); - if (tch_avg > TCH_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg); - end - - // calculate the tcl avg jitter - tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tcl_avg = tcl_avg + tcl_i/$itor(TDLLK); - tcl_sample[ck_cntr%TDLLK] = tcl_i; - - // update timers/counters - tch_i <= $time - tm_ck_pos; - end - tm_ck_neg <= $time; - end - - // on die termination - if (odt_en) begin - // clk pin is disabled during self refresh - if (!in_self_refresh && diff_ck) begin - if ($time - tm_odt < TIS) begin - $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); - end - if (prev_odt ^ odt_in) begin - if (!dll_locked) - $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); - if (odt_in && ($time - tm_odt_en < TMOD)) - $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); - if ($time - tm_self_refresh < TXSNR) - $display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time); - if (in_self_refresh) - $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); - - // async ODT mode applies: - // 1.) during active power down with slow exit - // 2.) during precharge power down - // 3.) if tANPD has not been satisfied - // 4.) until tAXPD has been satisfied - if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin - if (ck_cntr - ck_slow_exit_pd < TAXPD) - $display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); - if (odt_in) begin - if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1); - odt_state <= #(TAONPD) 1'b1; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0); - odt_state <= #(TAOFPD) 1'b0; - end - // sync ODT mode applies: - // 1.) during normal operation - // 2.) during active power down with fast exit - end else begin - if (odt_in) begin - i = TAOND*2; - odt_pipeline[i] = 1'b1; - end else begin - i = TAOFD*2; - odt_pipeline[i] = 1'b1; - end - end - ck_odt <= ck_cntr; - end - end - if (odt_pipeline[0]) begin - odt_state = ~odt_state; - if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state); - end - end - - // shift pipelines - if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin - al_pipeline = al_pipeline>>1; - wr_pipeline = wr_pipeline>>1; - rd_pipeline = rd_pipeline>>1; - for (i=0; i<`MAX_PIPE; i=i+1) begin - ba_pipeline[i] = ba_pipeline[i+1]; - row_pipeline[i] = row_pipeline[i+1]; - col_pipeline[i] = col_pipeline[i+1]; - end - end - if (|odt_pipeline) begin - odt_pipeline = odt_pipeline>>1; - end - end - - // receiver(s) - task dqs_even_receiver; - input [3:0] i; - reg [DQ_BITS-1:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_even[i]) begin - if (rdqs_en) begin // rdqs disables dm - dm_in_pos[i] = 1'b0; - end else begin - dm_in_pos[i] = dm_in[i]; - end - dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); - end - end - endtask - - always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); - always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); - always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); - always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); - always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); - always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); - always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); - always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); - always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); - always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); - always @(posedge dqs_even[10]) dqs_even_receiver(10); - always @(posedge dqs_even[11]) dqs_even_receiver(11); - always @(posedge dqs_even[12]) dqs_even_receiver(12); - always @(posedge dqs_even[13]) dqs_even_receiver(13); - always @(posedge dqs_even[14]) dqs_even_receiver(14); - always @(posedge dqs_even[15]) dqs_even_receiver(15); - - task dqs_odd_receiver; - input [3:0] i; - reg [DQ_BITS-1:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_odd[i]) begin - if (rdqs_en) begin // rdqs disables dm - dm_in_neg[i] = 1'b0; - end else begin - dm_in_neg[i] = dm_in[i]; - end - dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); - end - end - endtask - - always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); - always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); - always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); - always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); - always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); - always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); - always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); - always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); - always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); - always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); - always @(posedge dqs_odd[10]) dqs_odd_receiver(10); - always @(posedge dqs_odd[11]) dqs_odd_receiver(11); - always @(posedge dqs_odd[12]) dqs_odd_receiver(12); - always @(posedge dqs_odd[13]) dqs_odd_receiver(13); - always @(posedge dqs_odd[14]) dqs_odd_receiver(14); - always @(posedge dqs_odd[15]) dqs_odd_receiver(15); - - // Processes to check hold and pulse width of control signals - always @(cke_in) begin - if ($time > TIH) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); - end - if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg))) - $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time); - tm_cke = $time; - end - always @(odt_in) begin - if (odt_en && !in_self_refresh) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); - if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg))) - $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time); - end - tm_odt = $time; - end - - task cmd_addr_timing_check; - input i; - reg [4:0] i; - begin - if (prev_cke) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg))) - $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time); - end - tm_cmd_addr[i] = $time; - end - endtask - - always @(cs_n_in ) cmd_addr_timing_check( 0); - always @(ras_n_in ) cmd_addr_timing_check( 1); - always @(cas_n_in ) cmd_addr_timing_check( 2); - always @(we_n_in ) cmd_addr_timing_check( 3); - always @(ba_in [ 0]) cmd_addr_timing_check( 4); - always @(ba_in [ 1]) cmd_addr_timing_check( 5); - always @(ba_in [ 2]) cmd_addr_timing_check( 6); - always @(addr_in[ 0]) cmd_addr_timing_check( 7); - always @(addr_in[ 1]) cmd_addr_timing_check( 8); - always @(addr_in[ 2]) cmd_addr_timing_check( 9); - always @(addr_in[ 3]) cmd_addr_timing_check(10); - always @(addr_in[ 4]) cmd_addr_timing_check(11); - always @(addr_in[ 5]) cmd_addr_timing_check(12); - always @(addr_in[ 6]) cmd_addr_timing_check(13); - always @(addr_in[ 7]) cmd_addr_timing_check(14); - always @(addr_in[ 8]) cmd_addr_timing_check(15); - always @(addr_in[ 9]) cmd_addr_timing_check(16); - always @(addr_in[10]) cmd_addr_timing_check(17); - always @(addr_in[11]) cmd_addr_timing_check(18); - always @(addr_in[12]) cmd_addr_timing_check(19); - always @(addr_in[13]) cmd_addr_timing_check(20); - always @(addr_in[14]) cmd_addr_timing_check(21); - always @(addr_in[15]) cmd_addr_timing_check(22); - - // Processes to check setup and hold of data signals - task dm_timing_check; - input i; - reg [3:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); - if (check_dm_tdipw[i]) begin - if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg))) - $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time); - end - end - check_dm_tdipw[i] <= 1'b0; - tm_dm[i] = $time; - end - endtask - - always @(dm_in[ 0]) dm_timing_check( 0); - always @(dm_in[ 1]) dm_timing_check( 1); - always @(dm_in[ 2]) dm_timing_check( 2); - always @(dm_in[ 3]) dm_timing_check( 3); - always @(dm_in[ 4]) dm_timing_check( 4); - always @(dm_in[ 5]) dm_timing_check( 5); - always @(dm_in[ 6]) dm_timing_check( 6); - always @(dm_in[ 7]) dm_timing_check( 7); - always @(dm_in[ 8]) dm_timing_check( 8); - always @(dm_in[ 9]) dm_timing_check( 9); - always @(dm_in[10]) dm_timing_check(10); - always @(dm_in[11]) dm_timing_check(11); - always @(dm_in[12]) dm_timing_check(12); - always @(dm_in[13]) dm_timing_check(13); - always @(dm_in[14]) dm_timing_check(14); - always @(dm_in[15]) dm_timing_check(15); - - task dq_timing_check; - input i; - reg [5:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); - if (check_dq_tdipw[i]) begin - if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg))) - $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time); - end - end - check_dq_tdipw[i] <= 1'b0; - tm_dq[i] = $time; - end - endtask - - always @(dq_in[ 0]) dq_timing_check( 0); - always @(dq_in[ 1]) dq_timing_check( 1); - always @(dq_in[ 2]) dq_timing_check( 2); - always @(dq_in[ 3]) dq_timing_check( 3); - always @(dq_in[ 4]) dq_timing_check( 4); - always @(dq_in[ 5]) dq_timing_check( 5); - always @(dq_in[ 6]) dq_timing_check( 6); - always @(dq_in[ 7]) dq_timing_check( 7); - always @(dq_in[ 8]) dq_timing_check( 8); - always @(dq_in[ 9]) dq_timing_check( 9); - always @(dq_in[10]) dq_timing_check(10); - always @(dq_in[11]) dq_timing_check(11); - always @(dq_in[12]) dq_timing_check(12); - always @(dq_in[13]) dq_timing_check(13); - always @(dq_in[14]) dq_timing_check(14); - always @(dq_in[15]) dq_timing_check(15); - always @(dq_in[16]) dq_timing_check(16); - always @(dq_in[17]) dq_timing_check(17); - always @(dq_in[18]) dq_timing_check(18); - always @(dq_in[19]) dq_timing_check(19); - always @(dq_in[20]) dq_timing_check(20); - always @(dq_in[21]) dq_timing_check(21); - always @(dq_in[22]) dq_timing_check(22); - always @(dq_in[23]) dq_timing_check(23); - always @(dq_in[24]) dq_timing_check(24); - always @(dq_in[25]) dq_timing_check(25); - always @(dq_in[26]) dq_timing_check(26); - always @(dq_in[27]) dq_timing_check(27); - always @(dq_in[28]) dq_timing_check(28); - always @(dq_in[29]) dq_timing_check(29); - always @(dq_in[30]) dq_timing_check(30); - always @(dq_in[31]) dq_timing_check(31); - always @(dq_in[32]) dq_timing_check(32); - always @(dq_in[33]) dq_timing_check(33); - always @(dq_in[34]) dq_timing_check(34); - always @(dq_in[35]) dq_timing_check(35); - always @(dq_in[36]) dq_timing_check(36); - always @(dq_in[37]) dq_timing_check(37); - always @(dq_in[38]) dq_timing_check(38); - always @(dq_in[39]) dq_timing_check(39); - always @(dq_in[40]) dq_timing_check(40); - always @(dq_in[41]) dq_timing_check(41); - always @(dq_in[42]) dq_timing_check(42); - always @(dq_in[43]) dq_timing_check(43); - always @(dq_in[44]) dq_timing_check(44); - always @(dq_in[45]) dq_timing_check(45); - always @(dq_in[46]) dq_timing_check(46); - always @(dq_in[47]) dq_timing_check(47); - always @(dq_in[48]) dq_timing_check(48); - always @(dq_in[49]) dq_timing_check(49); - always @(dq_in[50]) dq_timing_check(50); - always @(dq_in[51]) dq_timing_check(51); - always @(dq_in[52]) dq_timing_check(52); - always @(dq_in[53]) dq_timing_check(53); - always @(dq_in[54]) dq_timing_check(54); - always @(dq_in[55]) dq_timing_check(55); - always @(dq_in[56]) dq_timing_check(56); - always @(dq_in[57]) dq_timing_check(57); - always @(dq_in[58]) dq_timing_check(58); - always @(dq_in[59]) dq_timing_check(59); - always @(dq_in[60]) dq_timing_check(60); - always @(dq_in[61]) dq_timing_check(61); - always @(dq_in[62]) dq_timing_check(62); - always @(dq_in[63]) dq_timing_check(63); - - task dqs_pos_timing_check; - input i; - reg [4:0] i; - reg [3:0] j; - begin - if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<16)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if (check_write_preamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg)) - $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16); - end else if (check_write_postamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) - $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16); - end else begin - if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) - $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - if ($time - tm_dm[i] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1; - end - end - if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin - wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; - end else begin - wdqs_pos_cntr[i] <= 1; - end - check_dm_tdipw[i%16] <= 1'b1; - check_write_preamble[i] <= 1'b0; - check_write_postamble[i] <= 1'b0; - check_write_dqs_low[i] <= 1'b0; - tm_dqs[i%16] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - tm_dqss_pos[i] <= $time; - tm_dqs_pos[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0); - always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1); - always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2); - always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3); - always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4); - always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5); - always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6); - always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7); - always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8); - always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9); - always @(posedge dqs_in[10]) dqs_pos_timing_check(10); - always @(posedge dqs_in[11]) dqs_pos_timing_check(11); - always @(posedge dqs_in[12]) dqs_pos_timing_check(12); - always @(posedge dqs_in[13]) dqs_pos_timing_check(13); - always @(posedge dqs_in[14]) dqs_pos_timing_check(14); - always @(posedge dqs_in[15]) dqs_pos_timing_check(15); - always @(negedge dqs_in[16]) dqs_pos_timing_check(16); - always @(negedge dqs_in[17]) dqs_pos_timing_check(17); - always @(negedge dqs_in[18]) dqs_pos_timing_check(18); - always @(negedge dqs_in[19]) dqs_pos_timing_check(19); - always @(negedge dqs_in[20]) dqs_pos_timing_check(20); - always @(negedge dqs_in[21]) dqs_pos_timing_check(21); - always @(negedge dqs_in[22]) dqs_pos_timing_check(22); - always @(negedge dqs_in[23]) dqs_pos_timing_check(23); - always @(negedge dqs_in[24]) dqs_pos_timing_check(24); - always @(negedge dqs_in[25]) dqs_pos_timing_check(25); - always @(negedge dqs_in[26]) dqs_pos_timing_check(26); - always @(negedge dqs_in[27]) dqs_pos_timing_check(27); - always @(negedge dqs_in[28]) dqs_pos_timing_check(28); - always @(negedge dqs_in[29]) dqs_pos_timing_check(29); - always @(negedge dqs_in[30]) dqs_pos_timing_check(30); - always @(negedge dqs_in[31]) dqs_pos_timing_check(31); - - task dqs_neg_timing_check; - input i; - reg [4:0] i; - reg [3:0] j; - begin - if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && (dqs_n_en || i < 16)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16); - if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) - $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - if ($time - tm_dm[i] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1; - end - end - check_dm_tdipw[i%16] <= 1'b1; - check_write_dqs_high[i] <= 1'b0; - tm_dqs[i%16] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - tm_dqs_neg[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0); - always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1); - always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2); - always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3); - always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4); - always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5); - always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6); - always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7); - always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8); - always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9); - always @(negedge dqs_in[10]) dqs_neg_timing_check(10); - always @(negedge dqs_in[11]) dqs_neg_timing_check(11); - always @(negedge dqs_in[12]) dqs_neg_timing_check(12); - always @(negedge dqs_in[13]) dqs_neg_timing_check(13); - always @(negedge dqs_in[14]) dqs_neg_timing_check(14); - always @(negedge dqs_in[15]) dqs_neg_timing_check(15); - always @(posedge dqs_in[16]) dqs_neg_timing_check(16); - always @(posedge dqs_in[17]) dqs_neg_timing_check(17); - always @(posedge dqs_in[18]) dqs_neg_timing_check(18); - always @(posedge dqs_in[19]) dqs_neg_timing_check(19); - always @(posedge dqs_in[20]) dqs_neg_timing_check(20); - always @(posedge dqs_in[21]) dqs_neg_timing_check(21); - always @(posedge dqs_in[22]) dqs_neg_timing_check(22); - always @(posedge dqs_in[23]) dqs_neg_timing_check(23); - always @(posedge dqs_in[24]) dqs_neg_timing_check(24); - always @(posedge dqs_in[25]) dqs_neg_timing_check(25); - always @(posedge dqs_in[26]) dqs_neg_timing_check(26); - always @(posedge dqs_in[27]) dqs_neg_timing_check(27); - always @(posedge dqs_in[28]) dqs_neg_timing_check(28); - always @(posedge dqs_in[29]) dqs_neg_timing_check(29); - always @(posedge dqs_in[30]) dqs_neg_timing_check(30); - always @(posedge dqs_in[31]) dqs_neg_timing_check(31); - -endmodule diff --git a/lib/micron/ddr_sdram/ddr3.v b/lib/micron/ddr_sdram/ddr3.v deleted file mode 100644 index cf7db33a..00000000 --- a/lib/micron/ddr_sdram/ddr3.v +++ /dev/null @@ -1,4140 +0,0 @@ -/**************************************************************************************** -* -* File Name: ddr3.v -* Version: 1.60 -* Model: BUS Functional -* -* Dependencies: ddr3_model_parameters.vh -* -* Description: Micron SDRAM DDR3 (Double Data Rate 3) -* -* Limitation: - doesn't check for average refresh timings -* - positive ck and ck_n edges are used to form internal clock -* - positive dqs and dqs_n edges are used to latch data -* - test mode is not modeled -* - Duty Cycle Corrector is not modeled -* - Temperature Compensated Self Refresh is not modeled -* - DLL off mode is not modeled. -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set DEBUG = 0 to disable $display messages -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --------------------------------------------------------------------------------------- -* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check. -* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n. -* TDQS can only be enabled in EMR for x8 configurations. -* CAS latency is checked vs frequency when DLL locks. -* Improved checking of DQS during writes. -* Added true BL4 operation. -* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers. -* Added ODTS Readout. -* Replaced tZQCL with tZQinit and tZQoper -* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS. -* Added tRFC checking for Refresh to Power-Down Re-Entry. -* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry -* Added Clock Frequency Change during Precharge Power-Down. -* Added -125x speed grades. -* Fixed tRCD checking during Write. -* 1.00 JMK 05/11/07 Initial release -* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF -* Removed temp sensor readout from MPR -* Updated initialization sequence -* Updated timing parameters -* 1.20 JMK 09/05/07 Updated clock frequency change -* Added ddr3_dimm module -* 1.30 JMK 01/23/08 Updated timing parameters -* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133 -* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support. -* Added multi-chip package model support in ddr3_mcp.v -* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades. -* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes -*****************************************************************************************/ -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ps / 1ps - -// model flags -// `define MODEL_PASR - -module ddr3 ( - rst_n, - ck, - ck_n, - cke, - cs_n, - ras_n, - cas_n, - we_n, - dm_tdqs, - ba, - addr, - dq, - dqs, - dqs_n, - tdqs_n, - odt -); - -`define x1Gb -`define sg187E -`define x16 - -/* `include "ddr3_model_parameters.vh" */ - - -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - - // Parameters current with 1Gb and 2Gb datasheet rev D - - // Timing parameters based on Speed Grade - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- -`ifdef x1Gb // 1Gb parameters - - `ifdef sg094E // sg094E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12187; // tRCD ps Active to Read/Write command time - parameter TRP = 12187; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12187; // TAA ps Internal READ command to first data - parameter CL_TIME = 12187; // CL ps Minimum CAS Latency - `else `ifdef sg094 // sg094 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `else `ifdef sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12857; // tRCD ps Active to Read/Write command time - parameter TRP = 12857; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12857; // TAA ps Internal READ command to first data - parameter CL_TIME = 12857; // CL ps Minimum CAS Latency - `else `ifdef sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13928; // tRCD ps Active to Read/Write command time - parameter TRP = 13928; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13928; // TAA ps Internal READ command to first data - parameter CL_TIME = 13928; // CL ps Minimum CAS Latency - `else `ifdef sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (14-14-14) speed bin - parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `else `ifdef sg125F // sg125F is equivalent to the JEDEC DDR3-1600 (9-9-9) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11250; // tRCD ps Active to Read/Write command time - parameter TRP = 11250; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11250; // TAA ps Internal READ command to first data - parameter CL_TIME = 11250; // CL ps Minimum CAS Latency - `else `ifdef sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else `ifdef sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `else `ifdef sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `else `ifdef sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `else `ifdef sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `else `ifdef sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `else `ifdef sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else - `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif - - `ifdef x16 - `ifdef sg094E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg094 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg107F - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg107E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg107 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg125F - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif - `else // x4, x8 - `ifdef sg094E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg094 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg107F - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg107E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg107 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg125F - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif -`endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 1Gb - parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else `ifdef x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `else `ifdef DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 0; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg094E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd8, 4'd12}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd9, 4'd14}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `else `ifdef sg094 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd8, 4'd12}, - {4'd9, 4'd13}, - {4'd9, 4'd14}, - {4'd10, 4'd14}: valid_cl = 1; - `else `ifdef sg107F - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd8, 4'd12}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd9, 4'd14}: valid_cl = 1; - `else `ifdef sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd8, 4'd12}, - {4'd9, 4'd13}, - {4'd9, 4'd14}: valid_cl = 1; - `else `ifdef sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd8, 4'd12}, - {4'd9, 4'd14}: valid_cl = 1; - `else `ifdef sg125F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `else `ifdef sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `else `ifdef sg125 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `else `ifdef sg15E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `else `ifdef sg15 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `else `ifdef sg187E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `else `ifdef sg187 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `else `ifdef sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `else `ifdef sg25 - {4'd5, 4'd6 }: valid_cl = 1; - `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 15e3/14) ? 9: - 10; // (period >= 937.5) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`elsif x2Gb // 2Gb parts - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg15E // sg15E is equivelant to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13500; // tRCD ps Active to Read/Write command time - parameter TRP = 13500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data - parameter CL_TIME = 13500; // CL ps Minimum CAS Latency - `else `ifdef sg15 // sg15 is equivelant to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `else `ifdef sg187E // sg187E is equivelant to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 25; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 125; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `else `ifdef sg187 // sg187 is equivelant to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 25; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 125; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `else `ifdef sg25E // sg25E is equivelant to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 200; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else - `define sg25 // sg25 is equivelant to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 200; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif `endif `endif `endif `endif - - `ifdef x16 - `ifdef sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else `ifdef sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif `endif - `else // x4, x8 - `ifdef sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else `ifdef sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif `endif `endif `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 11; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 12; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 8; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX =70312500; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 2Gb - parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 9000; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 9000; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else `ifdef x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `else `ifdef DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 0; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg15E - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `else `ifdef sg15 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `else `ifdef sg187E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `else `ifdef sg187 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `else `ifdef sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `else `ifdef sg25 - {4'd5, 4'd6 }: valid_cl = 1; - `endif `endif `endif `endif `endif `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - 8; //(period >= 1250.0) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`endif - parameter check_strict_mrbits = 1; - parameter check_strict_timing = 1; - parameter feature_pasr = 1; - parameter feature_truebl4 = 0; - - // text macros - `define DQ_PER_DQS DQ_BITS/DQS_BITS - `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); - if ((1< BL_MAX) - $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); - - $timeformat (-12, 1, " ps", 1); - seed = RANDOM_SEED; - - ck_cntr = 0; - end - - function integer get_rtt_wr; - input [1:0] rtt; - begin - get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0}; - end - endfunction - - function integer get_rtt_nom; - input [2:0] rtt; - begin - case (rtt) - 1: get_rtt_nom = RZQ/4; - 2: get_rtt_nom = RZQ/2; - 3: get_rtt_nom = RZQ/6; - 4: get_rtt_nom = RZQ/12; - 5: get_rtt_nom = RZQ/8; - default : get_rtt_nom = 0; - endcase - end - endfunction - - // calculate the absolute value of a real number - function real abs_value; - input arg; - real arg; - begin - if (arg < 0.0) - abs_value = -1.0 * arg; - else - abs_value = arg; - end - endfunction - - function integer ceil; - input number; - real number; - - // LMR 4.1.7 - // When either operand of a relational expression is a real operand then the other operand shall be converted - // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. - if (number > $rtoi(number)) - ceil = $rtoi(number) + 1; - else - ceil = number; - endfunction - - function integer floor; - input number; - real number; - - // LMR 4.1.7 - // When either operand of a relational expression is a real operand then the other operand shall be converted - // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. - if (number < $rtoi(number)) - floor = $rtoi(number) - 1; - else - floor = number; - endfunction - -`ifdef MAX_MEM - - function integer open_bank_file( input integer bank ); - integer fd; - reg [2048:1] filename; - begin - $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); - - fd = $fopen(filename, "w+"); - if (fd == 0) - begin - $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename); - $finish; - end - else - begin - if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename); - open_bank_file = fd; - end - - end - endfunction - - function [RFF_BITS:1] read_from_file( - input integer fd, - input integer index - ); - integer code; - integer offset; - reg [1024:1] msg; - reg [RFF_BITS:1] read_value; - - begin - offset = index * RFF_CHUNK; - code = $fseek( fd, offset, 0 ); - // $fseek returns 0 on success, -1 on failure - if (code != 0) - begin - $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); - $finish; - end - - code = $fscanf(fd, "%z", read_value); - // $fscanf returns number of items read - if (code != 1) - begin - if ($ferror(fd,msg) != 0) - begin - $display("%m: at time %t ERROR: fscanf failed at %d", $time, index); - $display(msg); - $finish; - end - else - read_value = 'hx; - end - - /* when reading from unwritten portions of the file, 0 will be returned. - * Use 0 in bit 1 as indicator that invalid data has been read. - * A true 0 is encoded as Z. - */ - if (read_value[1] === 1'bz) - // true 0 encoded as Z, data is valid - read_value[1] = 1'b0; - else if (read_value[1] === 1'b0) - // read from file section that has not been written - read_value = 'hx; - - read_from_file = read_value; - end - endfunction - - task write_to_file( - input integer fd, - input integer index, - input [RFF_BITS:1] data - ); - integer code; - integer offset; - - begin - offset = index * RFF_CHUNK; - code = $fseek( fd, offset, 0 ); - if (code != 0) - begin - $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); - $finish; - end - - // encode a valid data - if (data[1] === 1'bz) - data[1] = 1'bx; - else if (data[1] === 1'b0) - data[1] = 1'bz; - - $fwrite( fd, "%z", data ); - end - endtask -`else - function get_index; - input [`MAX_BITS-1:0] addr; - begin : index - get_index = 0; - for (memory_index=0; memory_index>(ROW_BITS+COL_BITS-BL_BITS)); - if (!banks[ba]) begin //bank is selected to keep - address[i] = address[memory_index]; - memory[i] = memory[memory_index]; - i = i + 1; - end - end - // clean up the unused banks - for (memory_index=i; memory_index TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); - if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end - {1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, SAME_BANK , ACTIVATE , WRITE } , - {1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task - {1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end - - // write - {1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end - - // read - {1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task - {1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task - {1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task - {1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end - - // zq - {1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK - {1'bx, DIFF_BANK , ZQ , REFRESH } , - {1'bx, DIFF_BANK , ZQ , PRECHARGE} , - {1'bx, DIFF_BANK , ZQ , ACTIVATE } , - {1'bx, DIFF_BANK , ZQ , ZQ } , - {1'bx, DIFF_BANK , ZQ , PWR_DOWN } , - {1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]); - if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]); - if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end - - // power down - {1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} , - {1'bx, DIFF_BANK , PWR_DOWN , REFRESH } , - {1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} , - {1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } , - {1'bx, DIFF_BANK , PWR_DOWN , WRITE } , - {1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); - else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } , - {1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); - if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); - if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); - if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end - - // self refresh - {1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} , - {1'bx, DIFF_BANK , SELF_REF , REFRESH } , - {1'bx, DIFF_BANK , SELF_REF , PRECHARGE} , - {1'bx, DIFF_BANK , SELF_REF , ACTIVATE } , - {1'bx, DIFF_BANK , SELF_REF , WRITE } , - {1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } , - {1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); - if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end - endcase - end - endtask - - task cmd_task; - input cke; - input [2:0] cmd; - input [BA_BITS-1:0] bank; - input [ADDR_BITS-1:0] addr; - reg [`BANKS:0] i; - integer j; - reg [`BANKS:0] tfaw_cntr; - reg [COL_BITS-1:0] col; - reg group; - begin - // tRFC max check - if (!er_trfc_max && !in_self_refresh) begin - if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin - $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); - er_trfc_max = 1; - end - end - if (cke) begin - if ((cmd < NOP) && (cmd != PRECHARGE)) begin - if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(SAME_BANK , bank, j, cmd); - chk_err(DIFF_BANK , bank, j, cmd); - chk_err(DIFF_GROUP, bank, j, cmd); - end - end - case (cmd) - LOAD_MODE : begin - if (|odt_pipeline) - $display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]); - if (odt_state) - $display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]); - - if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank); - if (bank>>2) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - case (bank) - 0 : begin - // Burst Length - if (addr[1:0] == 2'b00) begin - burst_length = 8; - blotf = 0; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end else if (addr[1:0] == 2'b01) begin - burst_length = 8; - blotf = 1; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank); - end else if (addr[1:0] == 2'b10) begin - burst_length = 4; - blotf = 0; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length); - end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin - burst_length = 4; - blotf = 0; - truebl4 = 1; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]); - end - // Burst Order - burst_order = addr[3]; - if (!burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); - end else if (burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); - end - // CAS Latency - cas_latency = {addr[2],addr[6:4]} + 4; - set_latency; - if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end - // Reserved - if (addr[7] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // DLL Reset - dll_reset = addr[8]; - if (!dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); - end else if (dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); - dll_locked = 0; - init_dll_reset = 1; - ck_dll_reset <= ck_cntr; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); - end - - // Write Recovery - if (addr[11:9] == 0) begin - write_recovery = 16; - end else if (addr[11:9] < 4) begin - write_recovery = addr[11:9] + 4; - end else begin - write_recovery = 2*addr[11:9]; - end - - if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end - // Power Down Mode - low_power = !addr[12]; - if (!low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank); - end else if (low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); - end - // Reserved - if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 1 : begin - // DLL Enable - dll_en = !addr[0]; - if (!dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank); - end else if (dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); - end - // Output Drive Strength - if ({addr[5], addr[1]} == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6); - end else if ({addr[5], addr[1]} == 2'b01) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7); - end else if ({addr[5], addr[1]} == 2'b11) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]}); - end - // ODT Rtt (Rtt_NOM) - odt_rtt_nom = {addr[9], addr[6], addr[2]}; - if (odt_rtt_nom == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); - odt_en = 0; - end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom)); - odt_en = 1; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom); - odt_en = 0; - end - // Report the additive latency value - al = addr[4:3]; - set_latency; - if (al == 0) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al); - end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al); - end - // Write Levelization - write_levelization = addr[7]; - if (!write_levelization) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank); - end else if (write_levelization) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization); - end - // Reserved - if (addr[8] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // Reserved - if (addr[10] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // TDQS Enable - tdqs_en = addr[11]; - if (!tdqs_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (tdqs_en) begin - if (8 == DQ_BITS) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank); - end - else begin - $display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank); - tdqs_en = 0; - end - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en); - end - // Output Enable - out_en = !addr[12]; - if (!out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank); - end else if (out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en); - end - // Reserved - if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 2 : begin - if (feature_pasr) begin - // Partial Array Self Refresh - pasr = addr[2:0]; - case (pasr) - 3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank); - 3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank); - 3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank); - 3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank); - 3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank); - 3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank); - 3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank); - 3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank); - default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr); - endcase - end - else - if (addr[2:0] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // CAS Write Latency - cas_write_latency = addr[5:3]+5; - set_latency; - if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); - end - // Auto Self Refresh Method - asr = addr[6]; - if (!asr) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank); - end else if (asr) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr); - end - // Self Refresh Temperature - srt = addr[7]; - if (!srt) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank); - end else if (srt) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt); - end - if (asr && srt) - $display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank); - // Reserved - if (addr[8] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // Dynamic ODT (Rtt_WR) - odt_rtt_wr = addr[10:9]; - if (odt_rtt_wr == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank); - dyn_odt_en = 0; - end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr)); - dyn_odt_en = 1; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr); - dyn_odt_en = 0; - end - // Reserved - if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 3 : begin - mpr_select = addr[1:0]; - // MultiPurpose Register Select - if (mpr_select == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank); - end else begin - if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select); - end - // MultiPurpose Register Enable - mpr_en = addr[2]; - if (!mpr_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (mpr_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en); - end - // Reserved - if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - endcase - if (dyn_odt_en && write_levelization) - $display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time); - init_mode_reg[bank] = 1; - mode_reg[bank] = addr; - tm_load_mode <= $time; - ck_load_mode <= ck_cntr; - end - end - REFRESH : begin - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); - er_trfc_max = 0; - ref_cntr = ref_cntr + 1; - tm_refresh <= $time; - ck_refresh <= ck_cntr; - end - end - PRECHARGE : begin - if (addr[AP]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]); - end - // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), - // or if the previously open row is already in the process of precharging - if (|active_bank) begin - if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - for (i=0; i<`BANKS; i=i+1) begin - if (active_bank[i]) begin - if (addr[AP] || (i == bank)) begin - - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(SAME_BANK, i, j, cmd); - chk_err(DIFF_BANK, i, j, cmd); - end - - if (auto_precharge_bank[i]) begin - $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i); - active_bank[i] = 1'b0; - tm_bank_precharge[i] <= $time; - tm_precharge <= $time; - ck_precharge <= ck_cntr; - end - end - end - end - end - end - end - ACTIVATE : begin - tfaw_cntr = 0; - for (i=0; i<`BANKS; i=i+1) begin - if ($time - tm_bank_activate[i] < TFAW) begin - tfaw_cntr = tfaw_cntr + 1; - end - end - if (tfaw_cntr > 3) begin - $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (active_bank[bank]) begin - $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (addr >= 1< AP - if (col >= 1< AP - if (col >= 1< TPD_MAX) - $display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time); - if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time); - in_power_down = 0; - if ((active_bank == 0) && low_power) begin // precharge power down with dll off - if (ck_cntr - ck_odt < write_latency - 1) - $display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time); - tm_slow_exit_pd <= $time; - ck_slow_exit_pd <= ck_cntr; - end - tm_power_down <= $time; - ck_power_down <= ck_cntr; - end - if (in_self_refresh) begin - if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK)) - $display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time); - if (ck_cntr - ck_cke_cmd < TCKESR_TCK) - $display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time); - if ($time - tm_cke < TISXR) - $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time); - if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time); - in_self_refresh = 0; - ck_dll_reset <= ck_cntr; - ck_self_refresh <= ck_cntr; - tm_self_refresh <= $time; - tm_refresh <= $time; - end - end - endcase - if ((prev_cke !== 1) && (cmd !== NOP)) begin - $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time); - end - - if (!init_done) begin - case (init_step) - 0 : begin - if ($time - tm_rst_n < 500000000 && check_strict_timing) - $display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time); - tm_txpr <= $time; - ck_txpr <= ck_cntr; - init_step = init_step + 1; - end - 1 : if (dll_en) init_step = init_step + 1; - 2 : begin - if (&init_mode_reg && init_dll_reset && zq_set) begin - if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); - init_done = 1; - end - end - endcase - end - end else if (prev_cke) begin - if ((!init_done) && (init_step > 1)) begin - $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end - case (cmd) - REFRESH : begin - if ($time - tm_txpr < TXPR) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(DIFF_BANK, bank, j, SELF_REF); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (|active_bank) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (odt_state) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time); - if (feature_pasr) - // Partial Array Self Refresh - case (pasr) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end - 3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end - 3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end - 3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end - 3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end - 3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end - 3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end - endcase - in_self_refresh = 1; - dll_locked = 0; - end - end - NOP : begin - // entering precharge power down with dll off and tANPD has not been satisfied - if (low_power && (active_bank == 0) && |odt_pipeline) - $display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]); - if ($time - tm_txpr < TXPR) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(DIFF_BANK, bank, j, PWR_DOWN); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) begin - if (|active_bank) begin - $display ("%m: at time %t INFO: Active Power Down Enter", $time); - end else begin - $display ("%m: at time %t INFO: Precharge Power Down Enter", $time); - end - end - in_power_down = 1; - end - end - default : begin - $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time); - end - endcase - end else if (in_self_refresh || in_power_down) begin - if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP)) - $display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time); - end - prev_cke = cke; - - end - endtask - - task data_task; - reg [BA_BITS-1:0] bank; - reg [ROW_BITS-1:0] row; - reg [COL_BITS-1:0] col; - integer i; - integer j; - begin - - if (diff_ck) begin - for (i=0; i<32; i=i+1) begin - if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg))) - $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16); - if (check_write_dqs_high[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16); - end - check_write_dqs_high <= 0; - end else begin - for (i=0; i<32; i=i+1) begin - if (dll_locked && dq_in_valid) begin - tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]); - if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg)) - $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - if (check_write_dqs_low[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16); - end - check_write_preamble <= 0; - check_write_postamble <= 0; - check_write_dqs_low <= 0; - end - - if (wr_pipeline[0] || rd_pipeline[0]) begin - bank = ba_pipeline[0]; - row = row_pipeline[0]; - col = col_pipeline[0]; - burst_cntr = 0; - memory_read(bank, row, col, memory_data); - end - - // burst counter - if (burst_cntr < burst_length) begin - burst_position = col ^ burst_cntr; - if (!burst_order) begin - burst_position[BO_BITS-1:0] = col + burst_cntr; - end - burst_cntr = burst_cntr + 1; - end - - // write dqs counter - if (wr_pipeline[WDQS_PRE + 1]) begin - wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1; - end - // write dqs - if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble - check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 1) begin // write data - if ((wdqs_cntr - WDQS_PST)%2) begin - check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end else begin - check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end - end - if (wdqs_cntr == WDQS_PST) begin // write postamble - check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 0) begin - wdqs_cntr = wdqs_cntr - 1; - end - - // write dq - if (dq_in_valid) begin // write data - bit_mask = 0; - if (diff_ck) begin - for (i=0; i>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - if (burst_cntr%BL_MIN == 0) begin - memory_write(bank, row, col, memory_data); - end - end - if (wr_pipeline[1]) begin - wdq_cntr = bl_pipeline[1]; - end - if (wdq_cntr > 0) begin - wdq_cntr = wdq_cntr - 1; - dq_in_valid = 1'b1; - end else begin - dq_in_valid = 1'b0; - dqs_in_valid <= 1'b0; - for (i=0; i<31; i=i+1) begin - wdqs_pos_cntr[i] <= 0; - end - end - if (wr_pipeline[0]) begin - b2b_write <= 1'b0; - end - if (wr_pipeline[2]) begin - if (dqs_in_valid) begin - b2b_write <= 1'b1; - end - dqs_in_valid <= 1'b1; - wr_burst_length = bl_pipeline[2]; - end - - // read dqs enable counter - if (rd_pipeline[RDQSEN_PRE]) begin - rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; - end - if (rdqsen_cntr > 0) begin - rdqsen_cntr = rdqsen_cntr - 1; - dqs_out_en = 1'b1; - end else begin - dqs_out_en = 1'b0; - end - - // read dqs counter - if (rd_pipeline[RDQS_PRE]) begin - rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1; - end - // read dqs - if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble - dqs_out = 1'b0; - end else if (rdqs_cntr > RDQS_PST) begin // read data - dqs_out = rdqs_cntr - RDQS_PST; - end else if (rdqs_cntr > 0) begin // read postamble - dqs_out = 1'b0; - end else begin - dqs_out = 1'b1; - end - if (rdqs_cntr > 0) begin - rdqs_cntr = rdqs_cntr - 1; - end - - // read dq enable counter - if (rd_pipeline[RDQEN_PRE]) begin - rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST; - end - if (rdqen_cntr > 0) begin - rdqen_cntr = rdqen_cntr - 1; - dq_out_en = 1'b1; - end else begin - dq_out_en = 1'b0; - end - // read dq - if (rd_pipeline[0]) begin - rdq_cntr = bl_pipeline[0]; - end - if (rdq_cntr > 0) begin // read data - if (mpr_en) begin -`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low - if (mpr_select == 2'b00) begin // Calibration Pattern - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}}; - end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}}; - end else begin // Reserved - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}}; - end -`else // all DQ output MPR data - if (mpr_select == 2'b00) begin // Calibration Pattern - dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}}; - end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) - dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}}; - end else begin // Reserved - dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}}; - end -`endif - if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]); - end else begin - dq_temp = memory_data>>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - end - dq_out = dq_temp; - rdq_cntr = rdq_cntr - 1; - end else begin - dq_out = {DQ_BITS{1'b1}}; - end - - // delay signals prior to output - if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin - for (i=0; i dqsck[i] + TQH*tck_avg + TDQSQ) begin - dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ; - end - dqsck_min = -1*TDQSCK; - if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin - dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ; - end - - // DQSQ requirements - // 1.) less than tDQSQ - // 2.) greater than 0 - // 3.) greater than tQH from the previous DQS edge - dqsq_min = 0; - if (dqsq_min < dqsck[i] - TQH*tck_avg) begin - dqsq_min = dqsck[i] - TQH*tck_avg; - end - if (dqsck_min == dqsck_max) begin - dqsck[i] = dqsck_min; - end else begin - dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); - end - dqsq_max = TDQSQ + dqsck[i]; - - dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en; - dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out; - if (!write_levelization) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en; - if (dqsq_min == dqsq_max) begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; - end else begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; - end - end - end - end - end else begin - out_delay = tck_avg/2; - dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; - dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; - if (write_levelization !== 1'b1) begin - dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; - dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; - end - end - end - endtask - - always @ (posedge rst_n_in) begin : reset - integer i; - if (rst_n_in) begin - if ($time < 200000000 && check_strict_timing) - $display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time); - if (cke_in !== 1'b0) - $display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time); - if ($time - tm_cke < 10000) - $display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time); - - // clear memory -`ifdef MAX_MEM - // verification group does not erase memory - // for (banki = 0; banki < `BANKS; banki = banki + 1) begin - // $fclose(memfd[banki]); - // memfd[banki] = open_bank_file(banki); - // end -`else - memory_used <= 0; //erase memory -`endif - - end - end - - always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main - integer i; - if (!rst_n_in) begin - reset_task; - end else begin - if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) - $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); - data_task; - - // Clock Frequency Change is legal: - // 1.) During Self Refresh - // 2.) During Precharge Power Down (DLL on or off) - if (in_self_refresh || (in_power_down && (active_bank == 0))) begin - if (diff_ck) begin - tjit_per_rtime = $time - tm_ck_pos - tck_avg; - end else begin - tjit_per_rtime = $time - tm_ck_neg - tck_avg; - end - if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin - if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK)) - $display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time); - if (odt_state) begin - $display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time); - tm_freq_change <= $time; - ck_freq_change <= ck_cntr; - dll_locked = 0; - end - end - end - - if (diff_ck) begin - // check setup of command signals - if ($time > TIS) begin - if ($time - tm_cke < TIS) - $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); - if (cke_in) begin - for (i=0; i<22; i=i+1) begin - if ($time - tm_cmd_addr[i] < TIS) - $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); - end - end - end - - // update current state - if (dll_locked) begin - if (mr_chk == 0) begin - mr_chk = 1; - end else if (init_mode_reg[0] && (mr_chk == 1)) begin - // check CL value against the clock frequency - if (cas_latency*tck_avg < CL_TIME && check_strict_timing) - $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg); - // check WR value against the clock frequency - if (ceil(write_recovery*tck_avg) < TWR) - $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); - // check the CWL value against the clock frequency - if (check_strict_timing) begin - case (cas_write_latency) - 5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - endcase - // check the CL value against the clock frequency - if (!valid_cl(cas_latency, cas_write_latency)) - $display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency); - end - mr_chk = 2; - end - end else if (!in_self_refresh) begin - mr_chk = 0; - if (ck_cntr - ck_dll_reset == TDLLK) begin - dll_locked = 1; - end - end - - if (|auto_precharge_bank) begin - for (i=0; i<`BANKS; i=i+1) begin - // Write with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command - if (write_precharge_bank[i]) begin - if ($time - tm_bank_activate[i] >= TRAS_MIN) begin - if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - write_precharge_bank[i] = 0; - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - ck_precharge = ck_cntr; - end - end - end - // Read with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Additive Latency plus 4 cycles after Read command - // 3. tRTP after the last 8-bit prefetch - if (read_precharge_bank[i]) begin - if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin - read_precharge_bank[i] = 0; - // In case the internal precharge is pushed out by tRTP, tRP starts at the point where - // the internal precharge happens (not at the next rising clock edge after this event). - if ($time - tm_bank_read_end[i] < TRTP) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); - active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - ck_precharge = ck_cntr; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - ck_precharge = ck_cntr; - end - end - end - end - end - - // respond to incoming command - if (cke_in ^ prev_cke) begin - tm_cke_cmd <= $time; - ck_cke_cmd <= ck_cntr; - end - - cmd_task(cke_in, cmd_n_in, ba_in, addr_in); - if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin - al_pipeline[2*additive_latency] = 1'b1; - end - if (al_pipeline[0]) begin - // check tRCD after additive latency - if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD)) - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); - if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD)) - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); - // check tWTR after additive latency - if (rd_pipeline[2*cas_latency - 1]) begin //{ - if (truebl4) begin //{ - i = ba_pipeline[2*cas_latency - 1]; - if ($time - tm_group_write_end[i[1]] < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - if ($time - tm_write_end < TWTR_DG) - $display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]); - end else begin - if ($time - tm_write_end < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - end - end - end - if (rd_pipeline) begin - if (rd_pipeline[2*cas_latency - 1]) begin - tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time; - end - end - for (i=0; i<`BANKS; i=i+1) begin - if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin - tm_bank_write_end[i] <= $time; - tm_group_write_end[i[1]] <= $time; - tm_write_end <= $time; - end - end - - // clk pin is disabled during self refresh - if (!in_self_refresh && tm_ck_pos ) begin - tjit_cc_time = $time - tm_ck_pos - tck_i; - tck_i = $time - tm_ck_pos; - tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tck_avg = tck_avg + tck_i/$itor(TDLLK); - tck_sample[ck_cntr%TDLLK] = tck_i; - tjit_per_rtime = tck_i - tck_avg; - - if (dll_locked && check_strict_timing) begin - // check accumulated error - terr_nper_rtime = 0; - for (i=0; i<12; i=i+1) begin - terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; - terr_nper_rtime = abs_value(terr_nper_rtime); - case (i) - 0 :; - 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); - 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); - 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); - 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); - 5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER); - 6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER); - 7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER); - 8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER); - 9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER); - 10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER); - 11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER); - endcase - end - - // check tCK min/max/jitter - if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) - $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); - if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) - $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); - if (TCK_MIN - tck_avg >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); - if (tck_avg - TCK_MAX >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); - - // check tCL - if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time); - if (tcl_avg < TCL_AVG_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg); - if (tcl_avg > TCL_AVG_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg); - end - - // calculate the tch avg jitter - tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tch_avg = tch_avg + tch_i/$itor(TDLLK); - tch_sample[ck_cntr%TDLLK] = tch_i; - tjit_ch_rtime = tch_i - tch_avg; - duty_cycle = tch_avg/tck_avg; - - // update timers/counters - tcl_i <= $time - tm_ck_neg; - end - - prev_odt <= odt_in; - // update timers/counters - ck_cntr <= ck_cntr + 1; - tm_ck_pos = $time; - end else begin - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - if (dll_locked && check_strict_timing) begin - if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos); - if (tch_avg < TCH_AVG_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg); - if (tch_avg > TCH_AVG_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg); - end - - // calculate the tcl avg jitter - tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tcl_avg = tcl_avg + tcl_i/$itor(TDLLK); - tcl_sample[ck_cntr%TDLLK] = tcl_i; - - // update timers/counters - tch_i <= $time - tm_ck_pos; - end - tm_ck_neg = $time; - end - - // on die termination - if (odt_en || dyn_odt_en) begin - // odt pin is disabled during self refresh - if (!in_self_refresh && diff_ck) begin - if ($time - tm_odt < TIS) - $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); - if (prev_odt ^ odt_in) begin - if (!dll_locked) - $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); - if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) - $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); - if (ck_cntr - ck_zqinit < TZQINIT) - $display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time); - if (ck_cntr - ck_zqoper < TZQOPER) - $display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time); - if (ck_cntr - ck_zqcs < TZQCS) - $display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time); - // if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) - // $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time); - if (ck_cntr - ck_self_refresh < TXSDLL) - $display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time); - if (in_self_refresh) - $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); - if (!odt_in && (ck_cntr - ck_odt < ODTH4)) - $display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time); - if (!odt_in && (ck_cntr - ck_odth8 < ODTH8)) - $display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time); - if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) - $display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); - - // async ODT mode applies: - // 1.) during precharge power down with DLL off - // 2.) if tANPD has not been satisfied - // 3.) until tXPDLL has been satisfied - if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin - odt_state = odt_in; - if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); - if (odt_state) begin - odt_state_dly <= #(TAONPD) odt_state; - end else begin - odt_state_dly <= #(TAOFPD) odt_state; - end - // sync ODT mode applies: - // 1.) during normal operation - // 2.) during active power down - // 3.) during precharge power down with DLL on - end else begin - odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff - end - ck_odt <= ck_cntr; - end - end - if (odt_pipeline[0]) begin - odt_state = ~odt_state; - if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); - if (odt_state) begin - odt_state_dly <= #(TAON) odt_state; - end else begin - odt_state_dly <= #(TAOF*tck_avg) odt_state; - end - end - if (rd_pipeline[RDQSEN_PRE]) begin - odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; - end - if (odt_cntr > 0) begin - if (odt_state) begin - $display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time); - end - odt_cntr = odt_cntr - 1; - end - if (dyn_odt_en && odt_state) begin - if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0])) - $display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr)); - dyn_odt_state = dyn_odt_pipeline[0]; - end - dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state; - end - -/* - if (cke_in && write_levelization) begin - for (i=0; i>1; - wr_pipeline = wr_pipeline>>1; - rd_pipeline = rd_pipeline>>1; - for (i=0; i<`MAX_PIPE; i=i+1) begin - bl_pipeline[i] = bl_pipeline[i+1]; - ba_pipeline[i] = ba_pipeline[i+1]; - row_pipeline[i] = row_pipeline[i+1]; - col_pipeline[i] = col_pipeline[i+1]; - end - end - if (|odt_pipeline || |dyn_odt_pipeline) begin - odt_pipeline = odt_pipeline>>1; - dyn_odt_pipeline = dyn_odt_pipeline>>1; - end - end - end - - // receiver(s) - task dqs_even_receiver; - input [3:0] i; - reg [63:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_even[i]) begin - if (tdqs_en) begin // tdqs disables dm - dm_in_pos[i] = 1'b0; - end else begin - dm_in_pos[i] = dm_in[i]; - end - dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); - end - end - endtask - - always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); - always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); - always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); - always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); - always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); - always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); - always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); - always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); - always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); - always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); - always @(posedge dqs_even[10]) dqs_even_receiver(10); - always @(posedge dqs_even[11]) dqs_even_receiver(11); - always @(posedge dqs_even[12]) dqs_even_receiver(12); - always @(posedge dqs_even[13]) dqs_even_receiver(13); - always @(posedge dqs_even[14]) dqs_even_receiver(14); - always @(posedge dqs_even[15]) dqs_even_receiver(15); - - task dqs_odd_receiver; - input [3:0] i; - reg [63:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_odd[i]) begin - if (tdqs_en) begin // tdqs disables dm - dm_in_neg[i] = 1'b0; - end else begin - dm_in_neg[i] = dm_in[i]; - end - dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); - end - end - endtask - - always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); - always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); - always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); - always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); - always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); - always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); - always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); - always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); - always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); - always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); - always @(posedge dqs_odd[10]) dqs_odd_receiver(10); - always @(posedge dqs_odd[11]) dqs_odd_receiver(11); - always @(posedge dqs_odd[12]) dqs_odd_receiver(12); - always @(posedge dqs_odd[13]) dqs_odd_receiver(13); - always @(posedge dqs_odd[14]) dqs_odd_receiver(14); - always @(posedge dqs_odd[15]) dqs_odd_receiver(15); - - // Processes to check hold and pulse width of control signals - always @(posedge rst_n_in) begin - if ($time > 100000) begin - if (tm_rst_n + 100000 > $time) - $display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time); - end - tm_rst_n = $time; - end - always @(cke_in) begin - if (rst_n_in) begin - if ($time > TIH) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); - end - if ($time - tm_cke < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time); - end - tm_cke = $time; - end - always @(odt_in) begin - if (rst_n_in && odt_en && !in_self_refresh) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); - if ($time - tm_odt < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time); - end - tm_odt = $time; - end - - task cmd_addr_timing_check; - input i; - reg [4:0] i; - begin - if (rst_n_in && prev_cke) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if ($time - tm_cmd_addr[i] < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); - end - tm_cmd_addr[i] = $time; - end - endtask - - always @(cs_n_in ) cmd_addr_timing_check( 0); - always @(ras_n_in ) cmd_addr_timing_check( 1); - always @(cas_n_in ) cmd_addr_timing_check( 2); - always @(we_n_in ) cmd_addr_timing_check( 3); - always @(ba_in [ 0]) cmd_addr_timing_check( 4); - always @(ba_in [ 1]) cmd_addr_timing_check( 5); - always @(ba_in [ 2]) cmd_addr_timing_check( 6); - always @(addr_in[ 0]) cmd_addr_timing_check( 7); - always @(addr_in[ 1]) cmd_addr_timing_check( 8); - always @(addr_in[ 2]) cmd_addr_timing_check( 9); - always @(addr_in[ 3]) cmd_addr_timing_check(10); - always @(addr_in[ 4]) cmd_addr_timing_check(11); - always @(addr_in[ 5]) cmd_addr_timing_check(12); - always @(addr_in[ 6]) cmd_addr_timing_check(13); - always @(addr_in[ 7]) cmd_addr_timing_check(14); - always @(addr_in[ 8]) cmd_addr_timing_check(15); - always @(addr_in[ 9]) cmd_addr_timing_check(16); - always @(addr_in[10]) cmd_addr_timing_check(17); - always @(addr_in[11]) cmd_addr_timing_check(18); - always @(addr_in[12]) cmd_addr_timing_check(19); - always @(addr_in[13]) cmd_addr_timing_check(20); - always @(addr_in[14]) cmd_addr_timing_check(21); - always @(addr_in[15]) cmd_addr_timing_check(22); - - // Processes to check setup and hold of data signals - task dm_timing_check; - input i; - reg [3:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); - if (check_dm_tdipw[i]) begin - if ($time - tm_dm[i] < TDIPW) - $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time); - end - end - check_dm_tdipw[i] <= 1'b0; - tm_dm[i] = $time; - end - endtask - - always @(dm_in[ 0]) dm_timing_check( 0); - always @(dm_in[ 1]) dm_timing_check( 1); - always @(dm_in[ 2]) dm_timing_check( 2); - always @(dm_in[ 3]) dm_timing_check( 3); - always @(dm_in[ 4]) dm_timing_check( 4); - always @(dm_in[ 5]) dm_timing_check( 5); - always @(dm_in[ 6]) dm_timing_check( 6); - always @(dm_in[ 7]) dm_timing_check( 7); - always @(dm_in[ 8]) dm_timing_check( 8); - always @(dm_in[ 9]) dm_timing_check( 9); - always @(dm_in[10]) dm_timing_check(10); - always @(dm_in[11]) dm_timing_check(11); - always @(dm_in[12]) dm_timing_check(12); - always @(dm_in[13]) dm_timing_check(13); - always @(dm_in[14]) dm_timing_check(14); - always @(dm_in[15]) dm_timing_check(15); - - task dq_timing_check; - input i; - reg [5:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); - if (check_dq_tdipw[i]) begin - if ($time - tm_dq[i] < TDIPW) - $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time); - end - end - check_dq_tdipw[i] <= 1'b0; - tm_dq[i] = $time; - end - endtask - - always @(dq_in[ 0]) dq_timing_check( 0); - always @(dq_in[ 1]) dq_timing_check( 1); - always @(dq_in[ 2]) dq_timing_check( 2); - always @(dq_in[ 3]) dq_timing_check( 3); - always @(dq_in[ 4]) dq_timing_check( 4); - always @(dq_in[ 5]) dq_timing_check( 5); - always @(dq_in[ 6]) dq_timing_check( 6); - always @(dq_in[ 7]) dq_timing_check( 7); - always @(dq_in[ 8]) dq_timing_check( 8); - always @(dq_in[ 9]) dq_timing_check( 9); - always @(dq_in[10]) dq_timing_check(10); - always @(dq_in[11]) dq_timing_check(11); - always @(dq_in[12]) dq_timing_check(12); - always @(dq_in[13]) dq_timing_check(13); - always @(dq_in[14]) dq_timing_check(14); - always @(dq_in[15]) dq_timing_check(15); - always @(dq_in[16]) dq_timing_check(16); - always @(dq_in[17]) dq_timing_check(17); - always @(dq_in[18]) dq_timing_check(18); - always @(dq_in[19]) dq_timing_check(19); - always @(dq_in[20]) dq_timing_check(20); - always @(dq_in[21]) dq_timing_check(21); - always @(dq_in[22]) dq_timing_check(22); - always @(dq_in[23]) dq_timing_check(23); - always @(dq_in[24]) dq_timing_check(24); - always @(dq_in[25]) dq_timing_check(25); - always @(dq_in[26]) dq_timing_check(26); - always @(dq_in[27]) dq_timing_check(27); - always @(dq_in[28]) dq_timing_check(28); - always @(dq_in[29]) dq_timing_check(29); - always @(dq_in[30]) dq_timing_check(30); - always @(dq_in[31]) dq_timing_check(31); - always @(dq_in[32]) dq_timing_check(32); - always @(dq_in[33]) dq_timing_check(33); - always @(dq_in[34]) dq_timing_check(34); - always @(dq_in[35]) dq_timing_check(35); - always @(dq_in[36]) dq_timing_check(36); - always @(dq_in[37]) dq_timing_check(37); - always @(dq_in[38]) dq_timing_check(38); - always @(dq_in[39]) dq_timing_check(39); - always @(dq_in[40]) dq_timing_check(40); - always @(dq_in[41]) dq_timing_check(41); - always @(dq_in[42]) dq_timing_check(42); - always @(dq_in[43]) dq_timing_check(43); - always @(dq_in[44]) dq_timing_check(44); - always @(dq_in[45]) dq_timing_check(45); - always @(dq_in[46]) dq_timing_check(46); - always @(dq_in[47]) dq_timing_check(47); - always @(dq_in[48]) dq_timing_check(48); - always @(dq_in[49]) dq_timing_check(49); - always @(dq_in[50]) dq_timing_check(50); - always @(dq_in[51]) dq_timing_check(51); - always @(dq_in[52]) dq_timing_check(52); - always @(dq_in[53]) dq_timing_check(53); - always @(dq_in[54]) dq_timing_check(54); - always @(dq_in[55]) dq_timing_check(55); - always @(dq_in[56]) dq_timing_check(56); - always @(dq_in[57]) dq_timing_check(57); - always @(dq_in[58]) dq_timing_check(58); - always @(dq_in[59]) dq_timing_check(59); - always @(dq_in[60]) dq_timing_check(60); - always @(dq_in[61]) dq_timing_check(61); - always @(dq_in[62]) dq_timing_check(62); - always @(dq_in[63]) dq_timing_check(63); - - task dqs_pos_timing_check; - input i; - reg [4:0] i; - reg [3:0] j; - begin - if (write_levelization && i<16) begin - if (ck_cntr - ck_load_mode < TWLMRD) - $display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i); -/* - if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS)) - $display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i); -*/ - if (DEBUG) - $display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck); - dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1; - dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck; - for (j=1; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1; - dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0; - end - end - if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if (check_write_preamble[i]) begin - if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg)) - $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16); - end else if (check_write_postamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) - $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16); - end else begin - if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) - $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - if ($time - tm_dm[i%16] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1; - end - end - if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin - wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; - end else begin - wdqs_pos_cntr[i] <= 1; - end - check_dm_tdipw[i%16] <= 1'b1; - check_write_preamble[i] <= 1'b0; - check_write_postamble[i] <= 1'b0; - check_write_dqs_low[i] <= 1'b0; - tm_dqs[i%16] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - tm_dqss_pos[i] <= $time; - tm_dqs_pos[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0); - always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1); - always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2); - always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3); - always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4); - always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5); - always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6); - always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7); - always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8); - always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9); - always @(posedge dqs_in[10]) dqs_pos_timing_check(10); - always @(posedge dqs_in[11]) dqs_pos_timing_check(11); - always @(posedge dqs_in[12]) dqs_pos_timing_check(12); - always @(posedge dqs_in[13]) dqs_pos_timing_check(13); - always @(posedge dqs_in[14]) dqs_pos_timing_check(14); - always @(posedge dqs_in[15]) dqs_pos_timing_check(15); - always @(negedge dqs_in[16]) dqs_pos_timing_check(16); - always @(negedge dqs_in[17]) dqs_pos_timing_check(17); - always @(negedge dqs_in[18]) dqs_pos_timing_check(18); - always @(negedge dqs_in[19]) dqs_pos_timing_check(19); - always @(negedge dqs_in[20]) dqs_pos_timing_check(20); - always @(negedge dqs_in[21]) dqs_pos_timing_check(21); - always @(negedge dqs_in[22]) dqs_pos_timing_check(22); - always @(negedge dqs_in[23]) dqs_pos_timing_check(23); - always @(negedge dqs_in[24]) dqs_pos_timing_check(24); - always @(negedge dqs_in[25]) dqs_pos_timing_check(25); - always @(negedge dqs_in[26]) dqs_pos_timing_check(26); - always @(negedge dqs_in[27]) dqs_pos_timing_check(27); - always @(negedge dqs_in[28]) dqs_pos_timing_check(28); - always @(negedge dqs_in[29]) dqs_pos_timing_check(29); - always @(negedge dqs_in[30]) dqs_pos_timing_check(30); - always @(negedge dqs_in[31]) dqs_pos_timing_check(31); - - task dqs_neg_timing_check; - input i; - reg [4:0] i; - reg [3:0] j; - begin - if (write_levelization && i<16) begin - if (ck_cntr - ck_load_mode < TWLDQSEN) - $display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i); - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time); - end - if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16); - if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) - $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - if ($time - tm_dm[i%16] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1; - end - end - check_dm_tdipw[i%16] <= 1'b1; - tm_dqs[i%16] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - check_write_dqs_high[i] <= 1'b0; - tm_dqs_neg[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0); - always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1); - always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2); - always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3); - always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4); - always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5); - always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6); - always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7); - always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8); - always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9); - always @(negedge dqs_in[10]) dqs_neg_timing_check(10); - always @(negedge dqs_in[11]) dqs_neg_timing_check(11); - always @(negedge dqs_in[12]) dqs_neg_timing_check(12); - always @(negedge dqs_in[13]) dqs_neg_timing_check(13); - always @(negedge dqs_in[14]) dqs_neg_timing_check(14); - always @(negedge dqs_in[15]) dqs_neg_timing_check(15); - always @(posedge dqs_in[16]) dqs_neg_timing_check(16); - always @(posedge dqs_in[17]) dqs_neg_timing_check(17); - always @(posedge dqs_in[18]) dqs_neg_timing_check(18); - always @(posedge dqs_in[19]) dqs_neg_timing_check(19); - always @(posedge dqs_in[20]) dqs_neg_timing_check(20); - always @(posedge dqs_in[21]) dqs_neg_timing_check(21); - always @(posedge dqs_in[22]) dqs_neg_timing_check(22); - always @(posedge dqs_in[23]) dqs_neg_timing_check(23); - always @(posedge dqs_in[24]) dqs_neg_timing_check(24); - always @(posedge dqs_in[25]) dqs_neg_timing_check(25); - always @(posedge dqs_in[26]) dqs_neg_timing_check(26); - always @(posedge dqs_in[27]) dqs_neg_timing_check(27); - always @(posedge dqs_in[28]) dqs_neg_timing_check(28); - always @(posedge dqs_in[29]) dqs_neg_timing_check(29); - always @(posedge dqs_in[30]) dqs_neg_timing_check(30); - always @(posedge dqs_in[31]) dqs_neg_timing_check(31); - -endmodule diff --git a/lib/micron/ddr_sdram/ddr3_model.v b/lib/micron/ddr_sdram/ddr3_model.v deleted file mode 100644 index 0d0f990b..00000000 --- a/lib/micron/ddr_sdram/ddr3_model.v +++ /dev/null @@ -1,5577 +0,0 @@ -/**************************************************************************************** -* -* File Name: ddr3.v -* Version: 1.61 -* Model: BUS Functional -* -* Dependencies: ddr3_model_parameters.vh -* -* Description: Micron SDRAM DDR3 (Double Data Rate 3) -* -* Limitation: - doesn't check for average refresh timings -* - positive ck and ck_n edges are used to form internal clock -* - positive dqs and dqs_n edges are used to latch data -* - test mode is not modeled -* - Duty Cycle Corrector is not modeled -* - Temperature Compensated Self Refresh is not modeled -* - DLL off mode is not modeled. -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set DEBUG = 0 to disable $display messages -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --------------------------------------------------------------------------------------- -* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check. -* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n. -* TDQS can only be enabled in EMR for x8 configurations. -* CAS latency is checked vs frequency when DLL locks. -* Improved checking of DQS during writes. -* Added true BL4 operation. -* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers. -* Added ODTS Readout. -* Replaced tZQCL with tZQinit and tZQoper -* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS. -* Added tRFC checking for Refresh to Power-Down Re-Entry. -* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry -* Added Clock Frequency Change during Precharge Power-Down. -* Added -125x speed grades. -* Fixed tRCD checking during Write. -* 1.00 JMK 05/11/07 Initial release -* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF -* Removed temp sensor readout from MPR -* Updated initialization sequence -* Updated timing parameters -* 1.20 JMK 09/05/07 Updated clock frequency change -* Added ddr3_dimm module -* 1.30 JMK 01/23/08 Updated timing parameters -* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133 -* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support. -* Added multi-chip package model support in ddr3_mcp.v -* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades. -* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes -* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW -*****************************************************************************************/ -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ps / 1ps - -// model flags -// `define MODEL_PASR - -module ddr3_model ( - rst_n, - ck, - ck_n, - cke, - cs_n, - ras_n, - cas_n, - we_n, - dm_tdqs, - ba, - addr, - dq, - dqs, - dqs_n, - tdqs_n, - odt -); - -// `include "ddr3_model_parameters.vh" - -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - - // Parameters current with 1Gb, 2Gb and 4Gb datasheet rev D - - // Timing parameters based on Speed Grade - - -`ifdef x4Gb // 4Gb parameters - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13750 to 13125 - // as the speed grade supports down binning) - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13500 to 13125 - // as the speed grade supports down binning) - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else - `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 16; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 2Gb - parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 1; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1070.0) ? 9: - 10; // (period >= 935) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`elsif x2Gb // 2Gb parameters - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13750 to 13125 - // as the speed grade supports down binning) - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13500 to 13125 - // as the speed grade supports down binning) - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else - `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 2Gb - parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1070.0) ? 9: - 10; // (period >= 935) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - - -`else - `define x1Gb // 1Gb parts - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else - `define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg25 - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25 - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 1Gb - parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else - `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1070.0) ? 9: - 10; // (period >= 935) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`endif - - parameter check_strict_mrbits = 1; - parameter check_strict_timing = 1; - parameter feature_pasr = 1; - parameter feature_truebl4 = 0; - - // text macros - `define DQ_PER_DQS DQ_BITS/DQS_BITS - `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); - if ((1< BL_MAX) - $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); - - $timeformat (-12, 1, " ps", 1); - seed = RANDOM_SEED; - - ck_cntr = 0; - end - - function integer get_rtt_wr; - input [1:0] rtt; - begin - get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0}; - end - endfunction - - function integer get_rtt_nom; - input [2:0] rtt; - begin - case (rtt) - 1: get_rtt_nom = RZQ/4; - 2: get_rtt_nom = RZQ/2; - 3: get_rtt_nom = RZQ/6; - 4: get_rtt_nom = RZQ/12; - 5: get_rtt_nom = RZQ/8; - default : get_rtt_nom = 0; - endcase - end - endfunction - - // calculate the absolute value of a real number - function real abs_value; - input arg; - real arg; - begin - if (arg < 0.0) - abs_value = -1.0 * arg; - else - abs_value = arg; - end - endfunction - - function integer ceil; - input number; - real number; - - // LMR 4.1.7 - // When either operand of a relational expression is a real operand then the other operand shall be converted - // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. - if (number > $rtoi(number)) - ceil = $rtoi(number) + 1; - else - ceil = number; - endfunction - - function integer floor; - input number; - real number; - - // LMR 4.1.7 - // When either operand of a relational expression is a real operand then the other operand shall be converted - // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. - if (number < $rtoi(number)) - floor = $rtoi(number) - 1; - else - floor = number; - endfunction - -`ifdef MAX_MEM - - function integer open_bank_file( input integer bank ); - integer fd; - reg [2048:1] filename; - begin - $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); - - fd = $fopen(filename, "w+"); - if (fd == 0) - begin - $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename); - $finish; - end - else - begin - if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename); - open_bank_file = fd; - end - - end - endfunction - - function [RFF_BITS:1] read_from_file( - input integer fd, - input integer index - ); - integer code; - integer offset; - reg [1024:1] msg; - reg [RFF_BITS:1] read_value; - - begin - offset = index * RFF_CHUNK; - code = $fseek( fd, offset, 0 ); - // $fseek returns 0 on success, -1 on failure - if (code != 0) - begin - $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); - $finish; - end - - code = $fscanf(fd, "%z", read_value); - // $fscanf returns number of items read - if (code != 1) - begin - if ($ferror(fd,msg) != 0) - begin - $display("%m: at time %t ERROR: fscanf failed at %d", $time, index); - $display(msg); - $finish; - end - else - read_value = 'hx; - end - - /* when reading from unwritten portions of the file, 0 will be returned. - * Use 0 in bit 1 as indicator that invalid data has been read. - * A true 0 is encoded as Z. - */ - if (read_value[1] === 1'bz) - // true 0 encoded as Z, data is valid - read_value[1] = 1'b0; - else if (read_value[1] === 1'b0) - // read from file section that has not been written - read_value = 'hx; - - read_from_file = read_value; - end - endfunction - - task write_to_file( - input integer fd, - input integer index, - input [RFF_BITS:1] data - ); - integer code; - integer offset; - - begin - offset = index * RFF_CHUNK; - code = $fseek( fd, offset, 0 ); - if (code != 0) - begin - $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); - $finish; - end - - // encode a valid data - if (data[1] === 1'bz) - data[1] = 1'bx; - else if (data[1] === 1'b0) - data[1] = 1'bz; - - $fwrite( fd, "%z", data ); - end - endtask -`else - function get_index; - input [`MAX_BITS-1:0] addr; - begin : index - get_index = 0; - for (memory_index=0; memory_index>(ROW_BITS+COL_BITS-BL_BITS)); - if (!banks[ba]) begin //bank is selected to keep - address[i] = address[memory_index]; - memory[i] = memory[memory_index]; - i = i + 1; - end - end - // clean up the unused banks - for (memory_index=i; memory_index TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); - if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end - {1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, SAME_BANK , ACTIVATE , WRITE } , - {1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task - {1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end - - // write - {1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end - - // read - {1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task - {1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task - {1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task - {1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end - {1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end - - // zq - {1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK - {1'bx, DIFF_BANK , ZQ , REFRESH } , - {1'bx, DIFF_BANK , ZQ , PRECHARGE} , - {1'bx, DIFF_BANK , ZQ , ACTIVATE } , - {1'bx, DIFF_BANK , ZQ , ZQ } , - {1'bx, DIFF_BANK , ZQ , PWR_DOWN } , - {1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]); - if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]); - if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end - - // power down - {1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} , - {1'bx, DIFF_BANK , PWR_DOWN , REFRESH } , - {1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} , - {1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } , - {1'bx, DIFF_BANK , PWR_DOWN , WRITE } , - {1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); - else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } , - {1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); - if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); - if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); - if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end - - // self refresh - {1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} , - {1'bx, DIFF_BANK , SELF_REF , REFRESH } , - {1'bx, DIFF_BANK , SELF_REF , PRECHARGE} , - {1'bx, DIFF_BANK , SELF_REF , ACTIVATE } , - {1'bx, DIFF_BANK , SELF_REF , WRITE } , - {1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end - {1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } , - {1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); - if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end - endcase - end - endtask - - task cmd_task; - input cke; - input [2:0] cmd; - input [BA_BITS-1:0] bank; - input [ADDR_BITS-1:0] addr; - reg [`BANKS:0] i; - integer j; - reg [`BANKS:0] tfaw_cntr; - reg [COL_BITS-1:0] col; - reg group; - begin - // tRFC max check - if (!er_trfc_max && !in_self_refresh) begin - if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin - $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); - er_trfc_max = 1; - end - end - if (cke) begin - if ((cmd < NOP) && (cmd != PRECHARGE)) begin - if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(SAME_BANK , bank, j, cmd); - chk_err(DIFF_BANK , bank, j, cmd); - chk_err(DIFF_GROUP, bank, j, cmd); - end - end - case (cmd) - LOAD_MODE : begin - if (|odt_pipeline) - $display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]); - if (odt_state) - $display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]); - - if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank); - if (bank>>2) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - case (bank) - 0 : begin - // Burst Length - if (addr[1:0] == 2'b00) begin - burst_length = 8; - blotf = 0; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); - end else if (addr[1:0] == 2'b01) begin - burst_length = 8; - blotf = 1; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank); - end else if (addr[1:0] == 2'b10) begin - burst_length = 4; - blotf = 0; - truebl4 = 0; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length); - end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin - burst_length = 4; - blotf = 0; - truebl4 = 1; - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]); - end - // Burst Order - burst_order = addr[3]; - if (!burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); - end else if (burst_order) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); - end - // CAS Latency - cas_latency = {addr[2],addr[6:4]} + 4; - set_latency; - if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); - end - // Reserved - if (addr[7] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // DLL Reset - dll_reset = addr[8]; - if (!dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); - end else if (dll_reset) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); - dll_locked = 0; - init_dll_reset = 1; - ck_dll_reset <= ck_cntr; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); - end - - // Write Recovery - if (addr[11:9] == 0) begin - write_recovery = 16; - end else if (addr[11:9] < 4) begin - write_recovery = addr[11:9] + 4; - end else begin - write_recovery = 2*addr[11:9]; - end - - if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); - end - // Power Down Mode - low_power = !addr[12]; - if (!low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank); - end else if (low_power) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); - end - // Reserved - if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 1 : begin - // DLL Enable - dll_en = !addr[0]; - if (!dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank); - end else if (dll_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); - end - // Output Drive Strength - if ({addr[5], addr[1]} == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6); - end else if ({addr[5], addr[1]} == 2'b01) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7); - end else if ({addr[5], addr[1]} == 2'b11) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]}); - end - // ODT Rtt (Rtt_NOM) - odt_rtt_nom = {addr[9], addr[6], addr[2]}; - if (odt_rtt_nom == 3'b000) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); - odt_en = 0; - end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom)); - odt_en = 1; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom); - odt_en = 0; - end - // Report the additive latency value - al = addr[4:3]; - set_latency; - if (al == 0) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al); - end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al); - end - // Write Levelization - write_levelization = addr[7]; - if (!write_levelization) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank); - end else if (write_levelization) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization); - end - // Reserved - if (addr[8] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // Reserved - if (addr[10] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // TDQS Enable - tdqs_en = addr[11]; - if (!tdqs_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (tdqs_en) begin - if (8 == DQ_BITS) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank); - end - else begin - $display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank); - tdqs_en = 0; - end - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en); - end - // Output Enable - out_en = !addr[12]; - if (!out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank); - end else if (out_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en); - end - // Reserved - if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 2 : begin - if (feature_pasr) begin - // Partial Array Self Refresh - pasr = addr[2:0]; - case (pasr) - 3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank); - 3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank); - 3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank); - 3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank); - 3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank); - 3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank); - 3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank); - 3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank); - default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr); - endcase - end - else - if (addr[2:0] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // CAS Write Latency - cas_write_latency = addr[5:3]+5; - set_latency; - if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); - end - // Auto Self Refresh Method - asr = addr[6]; - if (!asr) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank); - end else if (asr) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr); - end - // Self Refresh Temperature - srt = addr[7]; - if (!srt) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank); - end else if (srt) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank); - if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt); - end - if (asr && srt) - $display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank); - // Reserved - if (addr[8] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - // Dynamic ODT (Rtt_WR) - odt_rtt_wr = addr[10:9]; - if (odt_rtt_wr == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank); - dyn_odt_en = 0; - end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr)); - dyn_odt_en = 1; - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr); - dyn_odt_en = 0; - end - // Reserved - if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - 3 : begin - mpr_select = addr[1:0]; - // MultiPurpose Register Select - if (mpr_select == 2'b00) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank); - end else begin - if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select); - end - // MultiPurpose Register Enable - mpr_en = addr[2]; - if (!mpr_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank); - end else if (mpr_en) begin - if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank); - end else begin - $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en); - end - // Reserved - if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin - $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); - end - end - endcase - if (dyn_odt_en && write_levelization) - $display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time); - init_mode_reg[bank] = 1; - mode_reg[bank] = addr; - tm_load_mode <= $time; - ck_load_mode <= ck_cntr; - end - end - REFRESH : begin - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (|active_bank) begin - $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); - er_trfc_max = 0; - ref_cntr = ref_cntr + 1; - tm_refresh <= $time; - ck_refresh <= ck_cntr; - end - end - PRECHARGE : begin - if (addr[AP]) begin - if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]); - end - // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), - // or if the previously open row is already in the process of precharging - if (|active_bank) begin - if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else begin - for (i=0; i<`BANKS; i=i+1) begin - if (active_bank[i]) begin - if (addr[AP] || (i == bank)) begin - - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(SAME_BANK, i, j, cmd); - chk_err(DIFF_BANK, i, j, cmd); - end - - if (auto_precharge_bank[i]) begin - $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i); - active_bank[i] = 1'b0; - tm_bank_precharge[i] <= $time; - tm_precharge <= $time; - ck_precharge <= ck_cntr; - end - end - end - end - end - end - end - ACTIVATE : begin - tfaw_cntr = 0; - for (i=0; i<`BANKS; i=i+1) begin - if ($time - tm_bank_activate[i] < TFAW) begin - tfaw_cntr = tfaw_cntr + 1; - end - end - if (tfaw_cntr > 3) begin - $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); - if (STOP_ON_ERROR) $stop(0); - end else if (active_bank[bank]) begin - $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (addr >= 1< AP - if (col >= 1< AP - if (col >= 1< TPD_MAX) - $display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time); - if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time); - in_power_down = 0; - if ((active_bank == 0) && low_power) begin // precharge power down with dll off - if (ck_cntr - ck_odt < write_latency - 1) - $display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time); - tm_slow_exit_pd <= $time; - ck_slow_exit_pd <= ck_cntr; - end - tm_power_down <= $time; - ck_power_down <= ck_cntr; - end - if (in_self_refresh) begin - if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK)) - $display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time); - if (ck_cntr - ck_cke_cmd < TCKESR_TCK) - $display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time); - if ($time - tm_cke < TISXR) - $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time); - if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time); - in_self_refresh = 0; - ck_dll_reset <= ck_cntr; - ck_self_refresh <= ck_cntr; - tm_self_refresh <= $time; - tm_refresh <= $time; - end - end - endcase - if ((prev_cke !== 1) && (cmd !== NOP)) begin - $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time); - end - - if (!init_done) begin - case (init_step) - 0 : begin - if ($time - tm_rst_n < 500000000 && check_strict_timing) - $display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time); - tm_txpr <= $time; - ck_txpr <= ck_cntr; - init_step = init_step + 1; - end - 1 : if (dll_en) init_step = init_step + 1; - 2 : begin - if (&init_mode_reg && init_dll_reset && zq_set) begin - if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); - init_done = 1; - end - end - endcase - end - end else if (prev_cke) begin - if ((!init_done) && (init_step > 1)) begin - $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end - case (cmd) - REFRESH : begin - if ($time - tm_txpr < TXPR) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(DIFF_BANK, bank, j, SELF_REF); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (|active_bank) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (odt_state) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time); - if (feature_pasr) - // Partial Array Self Refresh - case (pasr) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end - 3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end - 3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end - 3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end - 3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end - 3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end - 3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end - endcase - in_self_refresh = 1; - dll_locked = 0; - end - end - NOP : begin - // entering precharge power down with dll off and tANPD has not been satisfied - if (low_power && (active_bank == 0) && |odt_pipeline) - $display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]); - if ($time - tm_txpr < TXPR) - $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]); - for (j=0; j<=SELF_REF; j=j+1) begin - chk_err(DIFF_BANK, bank, j, PWR_DOWN); - end - - if (mpr_en) begin - $display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time); - if (STOP_ON_ERROR) $stop(0); - end else if (!init_done) begin - $display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) begin - if (|active_bank) begin - $display ("%m: at time %t INFO: Active Power Down Enter", $time); - end else begin - $display ("%m: at time %t INFO: Precharge Power Down Enter", $time); - end - end - in_power_down = 1; - end - end - default : begin - $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time); - end - endcase - end else if (in_self_refresh || in_power_down) begin - if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP)) - $display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time); - end - prev_cke = cke; - - end - endtask - - task data_task; - reg [BA_BITS-1:0] bank; - reg [ROW_BITS-1:0] row; - reg [COL_BITS-1:0] col; - integer i; - integer j; - begin - - if (diff_ck) begin - for (i=0; i<32; i=i+1) begin - if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg))) - $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16); - if (check_write_dqs_high[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16); - end - check_write_dqs_high <= 0; - end else begin - for (i=0; i<32; i=i+1) begin - if (dll_locked && dq_in_valid) begin - tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]); - if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg)) - $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - if (check_write_dqs_low[i]) - $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16); - end - check_write_preamble <= 0; - check_write_postamble <= 0; - check_write_dqs_low <= 0; - end - - if (wr_pipeline[0] || rd_pipeline[0]) begin - bank = ba_pipeline[0]; - row = row_pipeline[0]; - col = col_pipeline[0]; - burst_cntr = 0; - memory_read(bank, row, col, memory_data); - end - - // burst counter - if (burst_cntr < burst_length) begin - burst_position = col ^ burst_cntr; - if (!burst_order) begin - burst_position[BO_BITS-1:0] = col + burst_cntr; - end - burst_cntr = burst_cntr + 1; - end - - // write dqs counter - if (wr_pipeline[WDQS_PRE + 1]) begin - wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1; - end - // write dqs - if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble - check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 1) begin // write data - if ((wdqs_cntr - WDQS_PST)%2) begin - check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end else begin - check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end - end - if (wdqs_cntr == WDQS_PST) begin // write postamble - check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; - end - if (wdqs_cntr > 0) begin - wdqs_cntr = wdqs_cntr - 1; - end - - // write dq - if (dq_in_valid) begin // write data - bit_mask = 0; - if (diff_ck) begin - for (i=0; i>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - if (burst_cntr%BL_MIN == 0) begin - memory_write(bank, row, col, memory_data); - end - end - if (wr_pipeline[1]) begin - wdq_cntr = bl_pipeline[1]; - end - if (wdq_cntr > 0) begin - wdq_cntr = wdq_cntr - 1; - dq_in_valid = 1'b1; - end else begin - dq_in_valid = 1'b0; - dqs_in_valid <= 1'b0; - for (i=0; i<31; i=i+1) begin - wdqs_pos_cntr[i] <= 0; - end - end - if (wr_pipeline[0]) begin - b2b_write <= 1'b0; - end - if (wr_pipeline[2]) begin - if (dqs_in_valid) begin - b2b_write <= 1'b1; - end - dqs_in_valid <= 1'b1; - wr_burst_length = bl_pipeline[2]; - end - - // read dqs enable counter - if (rd_pipeline[RDQSEN_PRE]) begin - rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; - end - if (rdqsen_cntr > 0) begin - rdqsen_cntr = rdqsen_cntr - 1; - dqs_out_en = 1'b1; - end else begin - dqs_out_en = 1'b0; - end - - // read dqs counter - if (rd_pipeline[RDQS_PRE]) begin - rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1; - end - // read dqs - if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble - dqs_out = 1'b0; - end else if (rdqs_cntr > RDQS_PST) begin // read data - dqs_out = rdqs_cntr - RDQS_PST; - end else if (rdqs_cntr > 0) begin // read postamble - dqs_out = 1'b0; - end else begin - dqs_out = 1'b1; - end - if (rdqs_cntr > 0) begin - rdqs_cntr = rdqs_cntr - 1; - end - - // read dq enable counter - if (rd_pipeline[RDQEN_PRE]) begin - rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST; - end - if (rdqen_cntr > 0) begin - rdqen_cntr = rdqen_cntr - 1; - dq_out_en = 1'b1; - end else begin - dq_out_en = 1'b0; - end - // read dq - if (rd_pipeline[0]) begin - rdq_cntr = bl_pipeline[0]; - end - if (rdq_cntr > 0) begin // read data - if (mpr_en) begin -`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low - if (mpr_select == 2'b00) begin // Calibration Pattern - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}}; - end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}}; - end else begin // Reserved - dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}}; - end -`else // all DQ output MPR data - if (mpr_select == 2'b00) begin // Calibration Pattern - dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}}; - end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) - dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}}; - end else begin // Reserved - dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}}; - end -`endif - if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]); - end else begin - dq_temp = memory_data>>(burst_position*DQ_BITS); - if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); - end - dq_out = dq_temp; - rdq_cntr = rdq_cntr - 1; - end else begin - dq_out = {DQ_BITS{1'b1}}; - end - - // delay signals prior to output - if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin - for (i=0; i dqsck[i] + TQH*tck_avg + TDQSQ) begin - dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ; - end - dqsck_min = -1*TDQSCK; - if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin - dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ; - end - - // DQSQ requirements - // 1.) less than tDQSQ - // 2.) greater than 0 - // 3.) greater than tQH from the previous DQS edge - dqsq_min = 0; - if (dqsq_min < dqsck[i] - TQH*tck_avg) begin - dqsq_min = dqsck[i] - TQH*tck_avg; - end - if (dqsck_min == dqsck_max) begin - dqsck[i] = dqsck_min; - end else begin - dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); - end - dqsq_max = TDQSQ + dqsck[i]; - - dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en; - dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out; - if (!write_levelization) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en; - if (dqsq_min == dqsq_max) begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; - end else begin - dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; - end - end - end - end - end else begin - out_delay = tck_avg/2; - dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; - dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; - if (write_levelization !== 1'b1) begin - dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; - dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; - end - end - end - endtask - - always @ (posedge rst_n_in) begin : reset - integer i; - if (rst_n_in) begin - if ($time < 200000000 && check_strict_timing) - $display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time); - if (cke_in !== 1'b0) - $display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time); - if ($time - tm_cke < 10000) - $display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time); - - // clear memory -`ifdef MAX_MEM - // verification group does not erase memory - // for (banki = 0; banki < `BANKS; banki = banki + 1) begin - // $fclose(memfd[banki]); - // memfd[banki] = open_bank_file(banki); - // end -`else - memory_used <= 0; //erase memory -`endif - - end - end - - always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main - integer i; - if (!rst_n_in) begin - reset_task; - end else begin - if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) - $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); - data_task; - - // Clock Frequency Change is legal: - // 1.) During Self Refresh - // 2.) During Precharge Power Down (DLL on or off) - if (in_self_refresh || (in_power_down && (active_bank == 0))) begin - if (diff_ck) begin - tjit_per_rtime = $time - tm_ck_pos - tck_avg; - end else begin - tjit_per_rtime = $time - tm_ck_neg - tck_avg; - end - if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin - if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK)) - $display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time); - if (odt_state) begin - $display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time); - if (STOP_ON_ERROR) $stop(0); - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time); - tm_freq_change <= $time; - ck_freq_change <= ck_cntr; - dll_locked = 0; - end - end - end - - if (diff_ck) begin - // check setup of command signals - if ($time > TIS) begin - if ($time - tm_cke < TIS) - $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); - if (cke_in) begin - for (i=0; i<22; i=i+1) begin - if ($time - tm_cmd_addr[i] < TIS) - $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); - end - end - end - - // update current state - if (dll_locked) begin - if (mr_chk == 0) begin - mr_chk = 1; - end else if (init_mode_reg[0] && (mr_chk == 1)) begin - // check CL value against the clock frequency - if (cas_latency*tck_avg < CL_TIME && check_strict_timing) - $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg); - // check WR value against the clock frequency - if (ceil(write_recovery*tck_avg) < TWR) - $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); - // check the CWL value against the clock frequency - if (check_strict_timing) begin - case (cas_write_latency) - 5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - 10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); - endcase - // check the CL value against the clock frequency - if (!valid_cl(cas_latency, cas_write_latency)) - $display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency); - end - mr_chk = 2; - end - end else if (!in_self_refresh) begin - mr_chk = 0; - if (ck_cntr - ck_dll_reset == TDLLK) begin - dll_locked = 1; - end - end - - if (|auto_precharge_bank) begin - for (i=0; i<`BANKS; i=i+1) begin - // Write with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command - if (write_precharge_bank[i]) begin - if ($time - tm_bank_activate[i] >= TRAS_MIN) begin - if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - write_precharge_bank[i] = 0; - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - ck_precharge = ck_cntr; - end - end - end - // Read with Auto Precharge Calculation - // 1. Meet minimum tRAS requirement - // 2. Additive Latency plus 4 cycles after Read command - // 3. tRTP after the last 8-bit prefetch - if (read_precharge_bank[i]) begin - if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin - read_precharge_bank[i] = 0; - // In case the internal precharge is pushed out by tRTP, tRP starts at the point where - // the internal precharge happens (not at the next rising clock edge after this event). - if ($time - tm_bank_read_end[i] < TRTP) begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); - active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; - tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; - ck_precharge = ck_cntr; - end else begin - if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); - active_bank[i] = 0; - auto_precharge_bank[i] = 0; - tm_bank_precharge[i] = $time; - tm_precharge = $time; - ck_precharge = ck_cntr; - end - end - end - end - end - - // respond to incoming command - if (cke_in ^ prev_cke) begin - tm_cke_cmd <= $time; - ck_cke_cmd <= ck_cntr; - end - - cmd_task(cke_in, cmd_n_in, ba_in, addr_in); - if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin - al_pipeline[2*additive_latency] = 1'b1; - end - if (al_pipeline[0]) begin - // check tRCD after additive latency - if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD)) - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); - if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD)) - $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); - // check tWTR after additive latency - if (rd_pipeline[2*cas_latency - 1]) begin //{ - if (truebl4) begin //{ - i = ba_pipeline[2*cas_latency - 1]; - if ($time - tm_group_write_end[i[1]] < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - if ($time - tm_write_end < TWTR_DG) - $display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]); - end else begin - if ($time - tm_write_end < TWTR) - $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); - end - end - end - if (rd_pipeline) begin - if (rd_pipeline[2*cas_latency - 1]) begin - tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time; - end - end - for (i=0; i<`BANKS; i=i+1) begin - if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin - tm_bank_write_end[i] <= $time; - tm_group_write_end[i[1]] <= $time; - tm_write_end <= $time; - end - end - - // clk pin is disabled during self refresh - if (!in_self_refresh && tm_ck_pos ) begin - tjit_cc_time = $time - tm_ck_pos - tck_i; - tck_i = $time - tm_ck_pos; - tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tck_avg = tck_avg + tck_i/$itor(TDLLK); - tck_sample[ck_cntr%TDLLK] = tck_i; - tjit_per_rtime = tck_i - tck_avg; - - if (dll_locked && check_strict_timing) begin - // check accumulated error - terr_nper_rtime = 0; - for (i=0; i<12; i=i+1) begin - terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; - terr_nper_rtime = abs_value(terr_nper_rtime); - case (i) - 0 :; - 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); - 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); - 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); - 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); - 5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER); - 6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER); - 7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER); - 8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER); - 9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER); - 10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER); - 11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER); - endcase - end - - // check tCK min/max/jitter - if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) - $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); - if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) - $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); - if (TCK_MIN - tck_avg >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); - if (tck_avg - TCK_MAX >= 1.0) - $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); - - // check tCL - if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time); - if (tcl_avg < TCL_AVG_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg); - if (tcl_avg > TCL_AVG_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg); - end - - // calculate the tch avg jitter - tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tch_avg = tch_avg + tch_i/$itor(TDLLK); - tch_sample[ck_cntr%TDLLK] = tch_i; - tjit_ch_rtime = tch_i - tch_avg; - duty_cycle = tch_avg/tck_avg; - - // update timers/counters - tcl_i <= $time - tm_ck_neg; - end - - prev_odt <= odt_in; - // update timers/counters - ck_cntr <= ck_cntr + 1; - tm_ck_pos = $time; - end else begin - // clk pin is disabled during self refresh - if (!in_self_refresh) begin - if (dll_locked && check_strict_timing) begin - if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos); - if (tch_avg < TCH_AVG_MIN*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg); - if (tch_avg > TCH_AVG_MAX*tck_avg) - $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg); - end - - // calculate the tcl avg jitter - tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK); - tcl_avg = tcl_avg + tcl_i/$itor(TDLLK); - tcl_sample[ck_cntr%TDLLK] = tcl_i; - - // update timers/counters - tch_i <= $time - tm_ck_pos; - end - tm_ck_neg = $time; - end - - // on die termination - if (odt_en || dyn_odt_en) begin - // odt pin is disabled during self refresh - if (!in_self_refresh && diff_ck) begin - if ($time - tm_odt < TIS) - $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); - if (prev_odt ^ odt_in) begin - if (!dll_locked) - $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); - if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) - $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); - if (ck_cntr - ck_zqinit < TZQINIT) - $display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time); - if (ck_cntr - ck_zqoper < TZQOPER) - $display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time); - if (ck_cntr - ck_zqcs < TZQCS) - $display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time); - // if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) - // $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time); - if (ck_cntr - ck_self_refresh < TXSDLL) - $display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time); - if (in_self_refresh) - $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); - if (!odt_in && (ck_cntr - ck_odt < ODTH4)) - $display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time); - if (!odt_in && (ck_cntr - ck_odth8 < ODTH8)) - $display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time); - if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) - $display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); - - // async ODT mode applies: - // 1.) during precharge power down with DLL off - // 2.) if tANPD has not been satisfied - // 3.) until tXPDLL has been satisfied - if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin - odt_state = odt_in; - if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); - if (odt_state) begin - odt_state_dly <= #(TAONPD) odt_state; - end else begin - odt_state_dly <= #(TAOFPD) odt_state; - end - // sync ODT mode applies: - // 1.) during normal operation - // 2.) during active power down - // 3.) during precharge power down with DLL on - end else begin - odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff - end - ck_odt <= ck_cntr; - end - end - if (odt_pipeline[0]) begin - odt_state = ~odt_state; - if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); - if (odt_state) begin - odt_state_dly <= #(TAON) odt_state; - end else begin - odt_state_dly <= #(TAOF*tck_avg) odt_state; - end - end - if (rd_pipeline[RDQSEN_PRE]) begin - odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; - end - if (odt_cntr > 0) begin - if (odt_state) begin - $display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time); - end - odt_cntr = odt_cntr - 1; - end - if (dyn_odt_en && odt_state) begin - if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0])) - $display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr)); - dyn_odt_state = dyn_odt_pipeline[0]; - end - dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state; - end - - if (cke_in && write_levelization) begin - for (i=0; i>1; - wr_pipeline = wr_pipeline>>1; - rd_pipeline = rd_pipeline>>1; - for (i=0; i<`MAX_PIPE; i=i+1) begin - bl_pipeline[i] = bl_pipeline[i+1]; - ba_pipeline[i] = ba_pipeline[i+1]; - row_pipeline[i] = row_pipeline[i+1]; - col_pipeline[i] = col_pipeline[i+1]; - end - end - if (|odt_pipeline || |dyn_odt_pipeline) begin - odt_pipeline = odt_pipeline>>1; - dyn_odt_pipeline = dyn_odt_pipeline>>1; - end - end - end - - // receiver(s) - task dqs_even_receiver; - input [3:0] i; - reg [63:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_even[i]) begin - if (tdqs_en) begin // tdqs disables dm - dm_in_pos[i] = 1'b0; - end else begin - dm_in_pos[i] = dm_in[i]; - end - dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); - end - end - endtask - - always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); - always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); - always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); - always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); - always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); - always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); - always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); - always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); - always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); - always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); - always @(posedge dqs_even[10]) dqs_even_receiver(10); - always @(posedge dqs_even[11]) dqs_even_receiver(11); - always @(posedge dqs_even[12]) dqs_even_receiver(12); - always @(posedge dqs_even[13]) dqs_even_receiver(13); - always @(posedge dqs_even[14]) dqs_even_receiver(14); - always @(posedge dqs_even[15]) dqs_even_receiver(15); - - task dqs_odd_receiver; - input [3:0] i; - reg [63:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_odd[i]) begin - if (tdqs_en) begin // tdqs disables dm - dm_in_neg[i] = 1'b0; - end else begin - dm_in_neg[i] = dm_in[i]; - end - dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); - end - end - endtask - - always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); - always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); - always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); - always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); - always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); - always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); - always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); - always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); - always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); - always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); - always @(posedge dqs_odd[10]) dqs_odd_receiver(10); - always @(posedge dqs_odd[11]) dqs_odd_receiver(11); - always @(posedge dqs_odd[12]) dqs_odd_receiver(12); - always @(posedge dqs_odd[13]) dqs_odd_receiver(13); - always @(posedge dqs_odd[14]) dqs_odd_receiver(14); - always @(posedge dqs_odd[15]) dqs_odd_receiver(15); - - // Processes to check hold and pulse width of control signals - always @(posedge rst_n_in) begin - if ($time > 100000) begin - if (tm_rst_n + 100000 > $time) - $display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time); - end - tm_rst_n = $time; - end - always @(cke_in) begin - if (rst_n_in) begin - if ($time > TIH) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); - end - if ($time - tm_cke < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time); - end - tm_cke = $time; - end - always @(odt_in) begin - if (rst_n_in && odt_en && !in_self_refresh) begin - if ($time - tm_ck_pos < TIH) - $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); - if ($time - tm_odt < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time); - end - tm_odt = $time; - end - - task cmd_addr_timing_check; - input i; - reg [4:0] i; - begin - if (rst_n_in && prev_cke) begin - if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS# - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low - $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); - if ($time - tm_cmd_addr[i] < TIPW) - $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); - end - tm_cmd_addr[i] = $time; - end - endtask - - always @(cs_n_in ) cmd_addr_timing_check( 0); - always @(ras_n_in ) cmd_addr_timing_check( 1); - always @(cas_n_in ) cmd_addr_timing_check( 2); - always @(we_n_in ) cmd_addr_timing_check( 3); - always @(ba_in [ 0]) cmd_addr_timing_check( 4); - always @(ba_in [ 1]) cmd_addr_timing_check( 5); - always @(ba_in [ 2]) cmd_addr_timing_check( 6); - always @(addr_in[ 0]) cmd_addr_timing_check( 7); - always @(addr_in[ 1]) cmd_addr_timing_check( 8); - always @(addr_in[ 2]) cmd_addr_timing_check( 9); - always @(addr_in[ 3]) cmd_addr_timing_check(10); - always @(addr_in[ 4]) cmd_addr_timing_check(11); - always @(addr_in[ 5]) cmd_addr_timing_check(12); - always @(addr_in[ 6]) cmd_addr_timing_check(13); - always @(addr_in[ 7]) cmd_addr_timing_check(14); - always @(addr_in[ 8]) cmd_addr_timing_check(15); - always @(addr_in[ 9]) cmd_addr_timing_check(16); - always @(addr_in[10]) cmd_addr_timing_check(17); - always @(addr_in[11]) cmd_addr_timing_check(18); - always @(addr_in[12]) cmd_addr_timing_check(19); - always @(addr_in[13]) cmd_addr_timing_check(20); - always @(addr_in[14]) cmd_addr_timing_check(21); - always @(addr_in[15]) cmd_addr_timing_check(22); - - // Processes to check setup and hold of data signals - task dm_timing_check; - input i; - reg [3:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); - if (check_dm_tdipw[i]) begin - if ($time - tm_dm[i] < TDIPW) - $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time); - end - end - check_dm_tdipw[i] <= 1'b0; - tm_dm[i] = $time; - end - endtask - - always @(dm_in[ 0]) dm_timing_check( 0); - always @(dm_in[ 1]) dm_timing_check( 1); - always @(dm_in[ 2]) dm_timing_check( 2); - always @(dm_in[ 3]) dm_timing_check( 3); - always @(dm_in[ 4]) dm_timing_check( 4); - always @(dm_in[ 5]) dm_timing_check( 5); - always @(dm_in[ 6]) dm_timing_check( 6); - always @(dm_in[ 7]) dm_timing_check( 7); - always @(dm_in[ 8]) dm_timing_check( 8); - always @(dm_in[ 9]) dm_timing_check( 9); - always @(dm_in[10]) dm_timing_check(10); - always @(dm_in[11]) dm_timing_check(11); - always @(dm_in[12]) dm_timing_check(12); - always @(dm_in[13]) dm_timing_check(13); - always @(dm_in[14]) dm_timing_check(14); - always @(dm_in[15]) dm_timing_check(15); - - task dq_timing_check; - input i; - reg [5:0] i; - begin - if (dqs_in_valid) begin - if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) - $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); - if (check_dq_tdipw[i]) begin - if ($time - tm_dq[i] < TDIPW) - $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time); - end - end - check_dq_tdipw[i] <= 1'b0; - tm_dq[i] = $time; - end - endtask - - always @(dq_in[ 0]) dq_timing_check( 0); - always @(dq_in[ 1]) dq_timing_check( 1); - always @(dq_in[ 2]) dq_timing_check( 2); - always @(dq_in[ 3]) dq_timing_check( 3); - always @(dq_in[ 4]) dq_timing_check( 4); - always @(dq_in[ 5]) dq_timing_check( 5); - always @(dq_in[ 6]) dq_timing_check( 6); - always @(dq_in[ 7]) dq_timing_check( 7); - always @(dq_in[ 8]) dq_timing_check( 8); - always @(dq_in[ 9]) dq_timing_check( 9); - always @(dq_in[10]) dq_timing_check(10); - always @(dq_in[11]) dq_timing_check(11); - always @(dq_in[12]) dq_timing_check(12); - always @(dq_in[13]) dq_timing_check(13); - always @(dq_in[14]) dq_timing_check(14); - always @(dq_in[15]) dq_timing_check(15); - always @(dq_in[16]) dq_timing_check(16); - always @(dq_in[17]) dq_timing_check(17); - always @(dq_in[18]) dq_timing_check(18); - always @(dq_in[19]) dq_timing_check(19); - always @(dq_in[20]) dq_timing_check(20); - always @(dq_in[21]) dq_timing_check(21); - always @(dq_in[22]) dq_timing_check(22); - always @(dq_in[23]) dq_timing_check(23); - always @(dq_in[24]) dq_timing_check(24); - always @(dq_in[25]) dq_timing_check(25); - always @(dq_in[26]) dq_timing_check(26); - always @(dq_in[27]) dq_timing_check(27); - always @(dq_in[28]) dq_timing_check(28); - always @(dq_in[29]) dq_timing_check(29); - always @(dq_in[30]) dq_timing_check(30); - always @(dq_in[31]) dq_timing_check(31); - always @(dq_in[32]) dq_timing_check(32); - always @(dq_in[33]) dq_timing_check(33); - always @(dq_in[34]) dq_timing_check(34); - always @(dq_in[35]) dq_timing_check(35); - always @(dq_in[36]) dq_timing_check(36); - always @(dq_in[37]) dq_timing_check(37); - always @(dq_in[38]) dq_timing_check(38); - always @(dq_in[39]) dq_timing_check(39); - always @(dq_in[40]) dq_timing_check(40); - always @(dq_in[41]) dq_timing_check(41); - always @(dq_in[42]) dq_timing_check(42); - always @(dq_in[43]) dq_timing_check(43); - always @(dq_in[44]) dq_timing_check(44); - always @(dq_in[45]) dq_timing_check(45); - always @(dq_in[46]) dq_timing_check(46); - always @(dq_in[47]) dq_timing_check(47); - always @(dq_in[48]) dq_timing_check(48); - always @(dq_in[49]) dq_timing_check(49); - always @(dq_in[50]) dq_timing_check(50); - always @(dq_in[51]) dq_timing_check(51); - always @(dq_in[52]) dq_timing_check(52); - always @(dq_in[53]) dq_timing_check(53); - always @(dq_in[54]) dq_timing_check(54); - always @(dq_in[55]) dq_timing_check(55); - always @(dq_in[56]) dq_timing_check(56); - always @(dq_in[57]) dq_timing_check(57); - always @(dq_in[58]) dq_timing_check(58); - always @(dq_in[59]) dq_timing_check(59); - always @(dq_in[60]) dq_timing_check(60); - always @(dq_in[61]) dq_timing_check(61); - always @(dq_in[62]) dq_timing_check(62); - always @(dq_in[63]) dq_timing_check(63); - - task dqs_pos_timing_check; - input i; - reg [4:0] i; - reg [3:0] j; - begin - if (write_levelization && i<16) begin - if (ck_cntr - ck_load_mode < TWLMRD) - $display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i); - if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS)) - $display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i); - if (DEBUG) - $display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck); - dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1; - dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck; - for (j=1; j<`DQ_PER_DQS; j=j+1) begin - dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1; - dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0; - end - end - if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if (check_write_preamble[i]) begin - if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg)) - $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16); - end else if (check_write_postamble[i]) begin - if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) - $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16); - end else begin - if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) - $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - if ($time - tm_dm[i%16] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1; - end - end - if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin - wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; - end else begin - wdqs_pos_cntr[i] <= 1; - end - check_dm_tdipw[i%16] <= 1'b1; - check_write_preamble[i] <= 1'b0; - check_write_postamble[i] <= 1'b0; - check_write_dqs_low[i] <= 1'b0; - tm_dqs[i%16] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - tm_dqss_pos[i] <= $time; - tm_dqs_pos[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0); - always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1); - always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2); - always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3); - always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4); - always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5); - always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6); - always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7); - always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8); - always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9); - always @(posedge dqs_in[10]) dqs_pos_timing_check(10); - always @(posedge dqs_in[11]) dqs_pos_timing_check(11); - always @(posedge dqs_in[12]) dqs_pos_timing_check(12); - always @(posedge dqs_in[13]) dqs_pos_timing_check(13); - always @(posedge dqs_in[14]) dqs_pos_timing_check(14); - always @(posedge dqs_in[15]) dqs_pos_timing_check(15); - always @(negedge dqs_in[16]) dqs_pos_timing_check(16); - always @(negedge dqs_in[17]) dqs_pos_timing_check(17); - always @(negedge dqs_in[18]) dqs_pos_timing_check(18); - always @(negedge dqs_in[19]) dqs_pos_timing_check(19); - always @(negedge dqs_in[20]) dqs_pos_timing_check(20); - always @(negedge dqs_in[21]) dqs_pos_timing_check(21); - always @(negedge dqs_in[22]) dqs_pos_timing_check(22); - always @(negedge dqs_in[23]) dqs_pos_timing_check(23); - always @(negedge dqs_in[24]) dqs_pos_timing_check(24); - always @(negedge dqs_in[25]) dqs_pos_timing_check(25); - always @(negedge dqs_in[26]) dqs_pos_timing_check(26); - always @(negedge dqs_in[27]) dqs_pos_timing_check(27); - always @(negedge dqs_in[28]) dqs_pos_timing_check(28); - always @(negedge dqs_in[29]) dqs_pos_timing_check(29); - always @(negedge dqs_in[30]) dqs_pos_timing_check(30); - always @(negedge dqs_in[31]) dqs_pos_timing_check(31); - - task dqs_neg_timing_check; - input i; - reg [4:0] i; - reg [3:0] j; - begin - if (write_levelization && i<16) begin - if (ck_cntr - ck_load_mode < TWLDQSEN) - $display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i); - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time); - end - if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin - if (dqs_in[i] ^ prev_dqs_in[i]) begin - if (dll_locked) begin - if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) - $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16); - if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) - $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16); - end - if ($time - tm_dm[i%16] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time); - if (!dq_out_en) begin - for (j=0; j<`DQ_PER_DQS; j=j+1) begin - if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS) - $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time); - check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1; - end - end - check_dm_tdipw[i%16] <= 1'b1; - tm_dqs[i%16] <= $time; - end else begin - $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); - end - end - check_write_dqs_high[i] <= 1'b0; - tm_dqs_neg[i] = $time; - prev_dqs_in[i] <= dqs_in[i]; - end - endtask - - always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0); - always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1); - always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2); - always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3); - always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4); - always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5); - always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6); - always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7); - always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8); - always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9); - always @(negedge dqs_in[10]) dqs_neg_timing_check(10); - always @(negedge dqs_in[11]) dqs_neg_timing_check(11); - always @(negedge dqs_in[12]) dqs_neg_timing_check(12); - always @(negedge dqs_in[13]) dqs_neg_timing_check(13); - always @(negedge dqs_in[14]) dqs_neg_timing_check(14); - always @(negedge dqs_in[15]) dqs_neg_timing_check(15); - always @(posedge dqs_in[16]) dqs_neg_timing_check(16); - always @(posedge dqs_in[17]) dqs_neg_timing_check(17); - always @(posedge dqs_in[18]) dqs_neg_timing_check(18); - always @(posedge dqs_in[19]) dqs_neg_timing_check(19); - always @(posedge dqs_in[20]) dqs_neg_timing_check(20); - always @(posedge dqs_in[21]) dqs_neg_timing_check(21); - always @(posedge dqs_in[22]) dqs_neg_timing_check(22); - always @(posedge dqs_in[23]) dqs_neg_timing_check(23); - always @(posedge dqs_in[24]) dqs_neg_timing_check(24); - always @(posedge dqs_in[25]) dqs_neg_timing_check(25); - always @(posedge dqs_in[26]) dqs_neg_timing_check(26); - always @(posedge dqs_in[27]) dqs_neg_timing_check(27); - always @(posedge dqs_in[28]) dqs_neg_timing_check(28); - always @(posedge dqs_in[29]) dqs_neg_timing_check(29); - always @(posedge dqs_in[30]) dqs_neg_timing_check(30); - always @(posedge dqs_in[31]) dqs_neg_timing_check(31); - -endmodule diff --git a/lib/micron/ddr_sdram/ddr3_model_parameters.vh b/lib/micron/ddr_sdram/ddr3_model_parameters.vh deleted file mode 100644 index 4eafeb55..00000000 --- a/lib/micron/ddr_sdram/ddr3_model_parameters.vh +++ /dev/null @@ -1,2895 +0,0 @@ -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - - // Parameters current with 1Gb, 2Gb and 4Gb datasheet rev D - - // Timing parameters based on Speed Grade - - -`ifdef x4Gb // 4Gb parameters - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13750 to 13125 - // as the speed grade supports down binning) - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13500 to 13125 - // as the speed grade supports down binning) - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 16; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 2Gb - parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 16; // MAX Address Bits - parameter ROW_BITS = 16; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 1; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1070.0) ? 9: - 10; // (period >= 935) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`elsif x2Gb // 2Gb parameters - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13750 to 13125 - // as the speed grade supports down binning) - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency (Changed the value from 13500 to 13125 - // as the speed grade supports down binning) - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg187E, sg187, sg25, sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25, sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 2Gb - parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 15; // MAX Address Bits - parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1070.0) ? 9: - 10; // (period >= 935) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - - -`else `define x1Gb // 1Gb parts - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- - `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13090; // tRCD ps Active to Read/Write command time - parameter TRP = 13090; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data - parameter CL_TIME = 13090; // CL ps Minimum CAS Latency - `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12155; // tRCD ps Active to Read/Write command time - parameter TRP = 12155; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data - parameter CL_TIME = 12155; // CL ps Minimum CAS Latency - `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin - parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 50; // tJIT(per) ps Period JItter - parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width - parameter TIS = 35; // tIS ps Input Setup Time - parameter TIH = 75; // tIH ps Input Hold Time - parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11220; // tRCD ps Active to Read/Write command time - parameter TRP = 11220; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 122; // tWLS ps Setup time for tDQS flop - parameter TWLH = 122; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data - parameter CL_TIME = 11220; // CL ps Minimum CAS Latency - `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13910; // tRCD ps Active to Read/Write command time - parameter TRP = 13910; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data - parameter CL_TIME = 13910; // CL ps Minimum CAS Latency - `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12840; // tRCD ps Active to Read/Write command time - parameter TRP = 12840; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data - parameter CL_TIME = 12840; // CL ps Minimum CAS Latency - `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin - parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 60; // tJIT(per) ps Period JItter - parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width - parameter TIS = 50; // tIS ps Input Setup Time - parameter TIH = 100; // tIH ps Input Hold Time - parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 11770; // tRCD ps Active to Read/Write command time - parameter TRP = 11770; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 140; // tWLS ps Setup time for tDQS flop - parameter TWLH = 140; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data - parameter CL_TIME = 11770; // CL ps Minimum CAS Latency - `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin - parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 70; // tJIT(per) ps Period JItter - parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width - parameter TIS = 170; // tIS ps Input Setup Time - parameter TIH = 120; // tIH ps Input Hold Time - parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 48125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 165; // tWLS ps Setup time for tDQS flop - parameter TWLH = 165; // tWLH ps Hold time of tDQS flop - parameter TWLO = 7500; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 49125; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin - parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 80; // tJIT(per) ps Period JItter - parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width - parameter TIS = 190; // tIS ps Input Setup Time - parameter TIH = 140; // tIH ps Input Hold Time - parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 6000; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 195; // tWLS ps Setup time for tDQS flop - parameter TWLH = 195; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 13125; // tRCD ps Active to Read/Write command time - parameter TRP = 13125; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data - parameter CL_TIME = 13125; // CL ps Minimum CAS Latency - `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 90; // tJIT(per) ps Period JItter - parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width - parameter TIS = 275; // tIS ps Input Setup Time - parameter TIH = 200; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 245; // tWLS ps Setup time for tDQS flop - parameter TWLH = 245; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 12500; // tRCD ps Active to Read/Write command time - parameter TRP = 12500; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data - parameter CL_TIME = 12500; // CL ps Minimum CAS Latency - `else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TJIT_PER = 100; // tJIT(per) ps Period JItter - parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter - parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) - parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) - parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) - parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) - parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) - parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) - parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) - parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) - parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) - parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) - parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) - parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# - parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width - parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width - parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width - parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width - parameter TIS = 350; // tIS ps Input Setup Time - parameter TIH = 275; // tIH ps Input Hold Time - parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time - parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter TRP = 15000; // tRP ps Precharge command period - parameter TXP = 7500; // tXP ps Exit power down to a valid command - parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width - parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference - parameter TWLS = 325; // tWLS ps Setup time for tDQS flop - parameter TWLH = 325; // tWLH ps Hold time of tDQS flop - parameter TWLO = 9000; // tWLO ps Write levelization output delay - parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data - parameter CL_TIME = 15000; // CL ps Minimum CAS Latency - `endif - - `ifdef x16 - `ifdef sg093 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `elsif sg25E - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `else // sg25 - parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time - parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window - `endif - `else // x4, x8 - `ifdef sg093 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg093F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107 - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107E - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg107F - parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg125 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15E - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg15 - parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187E - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg187 - parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window - `elsif sg25E - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `else // sg25 - parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time - parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window - `endif - `endif - - // Timing Parameters - - // Mode Register - parameter CL_MIN = 5; // CL tCK Minimum CAS Latency - parameter CL_MAX = 14; // CL tCK Maximum CAS Latency - parameter AL_MIN = 0; // AL tCK Minimum Additive Latency - parameter AL_MAX = 2; // AL tCK Maximum Additive Latency - parameter WR_MIN = 5; // WR tCK Minimum Write Recovery - parameter WR_MAX = 16; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 8; // BL tCK Minimum Burst Length - parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency - parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency - - // Clock - parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time - parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width - parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width - parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width - parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data - - // Data OUT - parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# - // Data Strobe OUT - parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble - parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble - // Data Strobe IN - parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width - parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width - parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble - parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble - // Command and Address - parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time - parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time - parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time - parameter TCCD = 4; // tCCD tCK Cas to Cas command delay - parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group - parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time - parameter TWR = 15000; // tWR ps Write recovery time - parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time - parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time - parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time - parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time - parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group - parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group - parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay - parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group - parameter TDLLK = 512; // tDLLK tCK DLL locking time - // Refresh - 1Gb - parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value - parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value - // Power Down - parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command - parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) - parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry - parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry - parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry - parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay - parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing - parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command - parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command - // Self Refresh - parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command - parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command - parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command - parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. - parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) - parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) - parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing - // ODT - parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference - parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) - parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) - parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) - parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) - parameter TADC = 0.7; // tADC tCK RTT dynamic change skew - // Write Levelization - parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed - parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed - parameter TWLOE = 2000; // tWLOE ps Write levelization output error - - // Size Parameters based on Part Width - - `ifdef x4 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `elsif x8 - parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 14; // MAX Address Bits - parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used - `else `define x16 - parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used - parameter ADDR_BITS = 13; // MAX Address Bits - parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** - parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used - `endif - - // Size Parameters - parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used - parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter AP = 10; // the address bit that controls auto-precharge and precharge-all - parameter BC = 12; // the address bit that controls burst chop - parameter BL_BITS = 3; // the number of bits required to count to BL_MAX - parameter BO_BITS = 2; // the number of Burst Order Bits - - `ifdef QUAD_RANK - `define DUAL_RANK // also define DUAL_RANK - parameter CS_BITS = 4; // Number of Chip Select Bits - parameter RANKS = 4; // Number of Chip Selects - `elsif DUAL_RANK - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 2; // Number of Chip Selects - `else - parameter CS_BITS = 2; // Number of Chip Select Bits - parameter RANKS = 1; // Number of Chip Selects - `endif - - // Simulation parameters - parameter RZQ = 240; // termination resistance - parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout - parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors - parameter DEBUG = 1; // Turn on Debug messages - parameter BUS_DELAY = 0; // delay in nanoseconds - parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads - parameter RANDOM_SEED = 711689044; //seed value for random generator. - - parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe - parameter RDQSEN_PST = 1; // DQS driving time after last read strobe - parameter RDQS_PRE = 2; // DQS low time prior to first read strobe - parameter RDQS_PST = 1; // DQS low time after last read strobe - parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data - parameter RDQEN_PST = 0; // DQ/DM driving time after last read data - parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe - parameter WDQS_PST = 1; // DQS half clock periods after last write strobe - - // check for legal cas latency based on the cas write latency - function valid_cl; - input [3:0] cl; - input [3:0] cwl; - - case ({cwl, cl}) - `ifdef sg093 - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg093F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd9 }, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}, - {4'd10, 4'd12}, - {4'd10, 4'd13}, - {4'd10, 4'd14}: valid_cl = 1; - `elsif sg107 - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107E - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg107F - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}, - {4'd9, 4'd11}, - {4'd9, 4'd12}, - {4'd9, 4'd13}: valid_cl = 1; - `elsif sg125E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg125 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}, - {4'd8, 4'd11}: valid_cl = 1; - `elsif sg15E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }, - {4'd7, 4'd9 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg15 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }, - {4'd7, 4'd10}: valid_cl = 1; - `elsif sg187E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd7 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg187 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }, - {4'd6, 4'd8 }: valid_cl = 1; - `elsif sg25E - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `elsif sg25 - {4'd5, 4'd5 }, - {4'd5, 4'd6 }: valid_cl = 1; - `endif - default : valid_cl = 0; - endcase - endfunction - - // find the minimum valid cas write latency - function [3:0] min_cwl; - input period; - real period; - min_cwl = (period >= 2500.0) ? 5: - (period >= 1875.0) ? 6: - (period >= 1500.0) ? 7: - (period >= 1250.0) ? 8: - (period >= 1070.0) ? 9: - 10; // (period >= 935) - endfunction - - // find the minimum valid cas latency - function [3:0] min_cl; - input period; - real period; - reg [3:0] cwl; - reg [3:0] cl; - begin - cwl = min_cwl(period); - for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin - if (valid_cl(cl, cwl)) begin - min_cl = cl; - end - end - end - endfunction - -`endif diff --git a/lib/micron/ddr_sdram/mobile_ddr.v b/lib/micron/ddr_sdram/mobile_ddr.v deleted file mode 100644 index 3635f3ab..00000000 --- a/lib/micron/ddr_sdram/mobile_ddr.v +++ /dev/null @@ -1,2271 +0,0 @@ -/**************************************************************************************** -* -* File Name: mobile_ddr.v -* Version: 3.50 -* Model: BUS Functional -* -* Dependencies: mobile_ddr_parameters.vh -* -* Description: Micron MOBILE DDR SDRAM -* -* Limitation: - Doesn't check for 8K-cycle refresh -* -* Note: - Set simulator resolution to "ps" accuracy -* - Set Debug = 0 to disable $display messages -* - Model assume Clk and Clk# crossing at both edge -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2004 Micron Technology, Inc. All rights reserved. -* -* Rev Author Date Changes -* --- ------ ---------- --------------------------------------- -* 1.0 NMB 03/19/02 - Initial Release of Mobile DDR model -* based off of version 5.0 of DDR model -* 1.1 ritz 12/03/04 - New feature: 1/8th strength driver in Drive Strength (Ext Mode Reg). -* Bugfix - ba[0] ba[1] were swapped for determening ext_mode_enable -* thus ext_mode_reg wasnt being programmed. -* 1.2 ritz 12/07/04 - Logging transactions in transcript for automated testing -* 1.3 ritz 01/31/05 - updated to SMG DDR model version 5.2 (dqs edge checking errors fix) -* 1.4 ritz 02/15/05 - Fixed display.*WRITE to use hex for "data". -* 1.5 ritz 03/22/05 - Fixed read latency (#0.5 and 2*Read_latency-1) for MMG latency -* 2.0 bas 07/19/06 - Added PASR support and clk_n checking -* 3.0 bas 08/07/06 - Added tXP check, tCke check, Power-down/Deep power down enter/exit messages - FULL_MEM fix -* 3.11 bas 10/18/06 - Added clk spd chk, added RP support, added T48M part, added SRR functionality, changed tMRD checker to measure in tck pos edge, DPD optimization for FULL_MEM mode -* 3.12 bas 10/19/06 - Fixed PASR in FULL_MEM mode -* 3.20 bas 10/23/06 - changed tXP check to tPDX check for T25L, Initial release to web -* 3.30 bas 01/15/07 - Updated T48M Parameters (updated as of 12/06) -* 3.35 bas 02/28/07 - Model uses tAC correctly to calculate strobe/data launch -* 3.36 bas 03/05/07 - fixed error messages for different banks interrupting - reads/writes w/autoprecharge -* 3.37 bas 03/21/07 - Added T47M Part to 512Mb parameter file -* 3.40 bas 06/25/07 - Removed RP options from 1024Mb - Updated 128Mb, 256Mb, and 512Mb parts to 05/07 datasheet - Updated 1024Mb part to 02/07 - Added illegal Cas Latency check per speed grade -* 3.40 jwm 08/02/07 - Support for 512Mb T47M -****************************************************************************************/ - -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ns / 1ps - -module mobile_ddr (Dq, Dqs, Addr, Ba, Clk, Clk_n, Cke, Cs_n, Ras_n, Cas_n, We_n, Dm); - - // `include "mobile_ddr_parameters.vh" - -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2005 Micron Technology, Inc. All rights reserved. -* -* -* Revisions: baaab - 06/20/06 - tMRD was set to 2.0 ns but should be 2 * tCK. Fixed. -* Added ROW_BITS & BA_BITS for compatibility w/our system. -* Removed part size parameter. -* -****************************************************************************************/ - - // Parameters current with T47M datasheet rev M (07/07) - - // Timing parameters based on Speed Grade - -`define sg5 - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- -`ifdef sg5 // Timing Parameters for -5 (CL = 3) - parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK# - parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK# - parameter tCK = 5.0; // tCK ns Nominal Clock Cycle Time - parameter tCK3_min = 5.0; // tCK ns Nominal Clock Cycle Time - parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.40; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK# - parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK# - parameter tRAS = 40.0; // tRAS ns Active to Precharge command time - parameter tRC = 55.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRCD = 15.0; // tRCD ns Active to Read/Write command time - parameter tRP = 15.0; // tRP ns Precharge command period - parameter tRRD = 10.0; // tRRD ns Active bank a to Active bank b command time - parameter tXP = 10.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part -`else `ifdef sg6 // Timing Parameters for -6 (CL = 3) - parameter tAC3_max = 5.0; // tAC ns Access window of DQ from CK/CK# - parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK# - parameter tCK = 6.0; // tCK ns Nominal Clock Cycle Time - parameter tCK3_min = 6.0; // tCK ns Nominal Clock Cycle Time - parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.45; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tHZ3_max = 5.0; // tHZ ns Data-out high Z window from CK/CK# - parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK# - parameter tRAS = 42.0; // tRAS ns Active to Precharge command time - parameter tRC = 60.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRCD = 18.0; // tRCD ns Active to Read/Write command time - parameter tRP = 18.0; // tRP ns Precharge command period - parameter tRRD = 12.0; // tRRD ns Active bank a to Active bank b command time - parameter tXP = 6.0; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part -`else - `define sg75 // Timing Parameters for -75 (CL = 3) - parameter tAC3_max = 6.0; // tAC ns Access window of DQ from CK/CK# - parameter tAC2_max = 6.5; // tAC ns Access window of DQ from CK/CK# - parameter tCK = 7.5; // tCK ns Nominal Clock Cycle Time - parameter tCK3_min = 7.5; // tCK ns Nominal Clock Cycle Time - parameter tCK2_min = 12.0; // tCK ns Nominal Clock Cycle Time - parameter tDQSQ = 0.60; // tDQSQ ns DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter tHZ3_max = 6.0; // tHZ ns Data-out high Z window from CK/CK# - parameter tHZ2_max = 6.5; // tHZ ns Data-out high Z window from CK/CK# - parameter tRAS = 45.0; // tRAS ns Active to Precharge command time - parameter tRC = 75.0; // tRC ns Active to Active/Auto Refresh command time - parameter tRCD = 22.5; // tRCD ns Active to Read/Write command time - parameter tRP = 22.5; // tRP ns Precharge command period - parameter tRRD = 15.0; // tRRD ns Active bank a to Active bank b command time - parameter tXP = 7.5; // tXP ns Exit power-down to first valid cmd *note: In data sheet this is specified as one clk, but min tck fails before tXP on the actual part -`endif `endif - - parameter tLZ = 1.0; // tLZ ns Data-out low Z window from CK/CK# - parameter tMRD = 2.0; // tMRD tCK Load Mode Register command cycle time - parameter tRFC = 97.5; // tRFC ns Refresh to Refresh Command interval time - parameter tSRC = 1.0; // tSRC tCK SRR READ command to first valid command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts) - parameter tSRR = 2.0; // tSRR tCK SRR command to SRR READ command (Not Applicable for 128Mb, 256Mb, and 512Mb Parts) - parameter tWR = 15.0; // tWR ns Write recovery time - - // Size Parameters based on Part Width - `define x16 - `ifdef x16 - parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used - parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used - parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 2; // Set this parameter to control how many DQS bits are used - parameter DM_BITS = 2; // Set this parameter to control how many DM bits are used - parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used - parameter BA_BITS = 2; // Bank bits - `else - `define x32 - `ifdef RP - parameter ADDR_BITS = 14; // Set this parameter to control how many Address bits are used - parameter ROW_BITS = 14; // Set this parameter to control how many Row bits are used - parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used - parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used - parameter COL_BITS = 8; // Set this parameter to control how many Column bits are used - parameter BA_BITS = 2; // Bank bits - `else - parameter ADDR_BITS = 13; // Set this parameter to control how many Address bits are used - parameter ROW_BITS = 13; // Set this parameter to control how many Row bits are used - parameter DQ_BITS = 32; // Set this parameter to control how many Data bits are used - parameter DQS_BITS = 4; // Set this parameter to control how many DQS bits are used - parameter DM_BITS = 4; // Set this parameter to control how many DM bits are used - parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used - parameter BA_BITS = 2; // Bank bits - `endif -`endif - - parameter full_mem_bits = BA_BITS+ADDR_BITS+COL_BITS; // Set this parameter to control how many unique addresses are used - parameter part_mem_bits = 10; // Set this parameter to control how many unique addresses are used - parameter part_size = 512; // Set this parameter to indicate part size(512Mb, 256Mb, 128Mb) - parameter tCH_MAX = 0.55; // Clk high level width - parameter tCH_MIN = 0.45; // Clk high level width - parameter tCL_MAX = 0.55; // Clk low level width - parameter tCL_MIN = 0.45; // Clk low level width - parameter tCKE = 2.0; // Minimum tCKE High/Low time (in tCK's) - parameter CL_MAX = 3.0; // Maximum CAS Latency - - // Port Declarations - inout [DQ_BITS - 1 : 0] Dq; - inout [DQS_BITS - 1 : 0] Dqs; - input [ADDR_BITS - 1 : 0] Addr; - input [1 : 0] Ba; - input Clk; - input Clk_n; - input Cke; - input Cs_n; - input Ras_n; - input Cas_n; - input We_n; - input [DM_BITS - 1 : 0] Dm; - - //time variables - realtime tXP_chk ; - reg enter_DPD ; - reg enter_PD ; - reg enter_APD ; - - //integer clk checks - - // Internal Wires (fixed width) - wire [31 : 0] Dq_in; - wire [3 : 0] Dqs_in; - wire [3 : 0] Dm_in; - - assign Dq_in [DQ_BITS - 1 : 0] = Dq; - assign Dqs_in [DQS_BITS - 1 : 0] = Dqs; - assign Dm_in [DM_BITS - 1 : 0] = Dm; - - // Data pair - reg [31 : 0] dq_rise; - reg [3 : 0] dm_rise; - reg [31 : 0] dq_fall; - reg [3 : 0] dm_fall; - reg [7 : 0] dm_pair; - reg [31 : 0] Dq_buf; - - // Power-down cycle counter - reg [03:00] PD_cntr ; - - // prev cmd value - - reg prev_Cs_n ; - reg prev_Ras_n ; - reg prev_Cas_n ; - reg prev_We_n ; - reg [01:00] prev_Ba ; - reg prev_cke ; - - wire prev_nop = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & prev_We_n ; - wire prev_des = prev_Cs_n ; - wire prev_bt = ~prev_Cs_n & prev_Ras_n & prev_Cas_n & ~prev_We_n ; - - //differential clk - reg diff_ck; - always @(posedge Clk) diff_ck <= Clk; - always @(posedge Clk_n) diff_ck <= ~Clk_n; - - //measure clock period - realtime clk_period ; - realtime pos_clk_edge ; - integer clk_pos_edge_cnt ; - always @(posedge diff_ck) begin - clk_period = $realtime - pos_clk_edge ; - pos_clk_edge = $realtime ; - if ((Cke == 1'b1) && (clk_pos_edge_cnt < 2)) begin - clk_pos_edge_cnt = clk_pos_edge_cnt + 1 ; - end else if (Cke == 1'b0) begin - clk_pos_edge_cnt = 2'b00 ; - end - end - - //measure duty cycle - realtime neg_clk_edge ; - always @(negedge diff_ck) begin - neg_clk_edge = $realtime ; - end - realtime pos_clk_time ; - realtime neg_clk_time ; - always @(diff_ck) begin - if (diff_ck) begin - neg_clk_time = $realtime - neg_clk_edge ; - end - if (~diff_ck) begin - pos_clk_time = $realtime - pos_clk_edge ; - end - if (Cke) begin - if ((pos_clk_time/clk_period)tCH_MAX) begin - $display ("%m: at time %t ERROR: tCH maximum violation on CLK by %t", $time, pos_clk_time - tCH_MAX*clk_period); - end - if ((neg_clk_time/clk_period)tCL_MAX) begin - $display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, pos_clk_time - tCL_MAX*clk_period); - end - end - end - - // Mode Register - reg [ADDR_BITS - 1 : 0] Mode_reg; - reg [ADDR_BITS - 1 : 0] Ext_Mode_reg; - reg [2*DQ_BITS - 1 : 0] Srr_reg; - - // SRR Registers - reg SRR_read; - - // Internal System Clock - reg CkeZ, Sys_clk; - - // Internal Dqs initialize - reg Dqs_int; - - // Dqs buffer - reg [DQS_BITS - 1 : 0] Dqs_out; - reg [DQS_BITS - 1 : 0] Dqs_gen; - - // Dq buffer - reg [DQ_BITS - 1 : 0] Dq_out; - - // Read pipeline variables - reg Read_cmnd [0 : 6]; - reg [1 : 0] Read_bank [0 : 6]; - reg [COL_BITS - 1 : 0] Read_cols [0 : 6]; - - // Write pipeline variables - reg Write_cmnd [0 : 3]; - reg [1 : 0] Write_bank [0 : 3]; - reg [COL_BITS - 1 : 0] Write_cols [0 : 3]; - - // Auto precharge variables - reg Read_precharge [0 : 3]; - reg Write_precharge [0 : 3]; - integer Count_precharge [0 : 3]; - reg SelfRefresh; - reg [3:0] Read_precharge_count [3:0] ; - reg [3:0] Write_precharge_count [3:0]; - - - reg wr_ap_display_msg ; - reg rd_ap_display_msg ; - - // Manual precharge variables - reg A10_precharge [0 : 6]; - reg [1 : 0] Bank_precharge [0 : 6]; - reg Cmnd_precharge [0 : 6]; - - // Burst terminate variables - reg Cmnd_bst [0 : 6]; - - // tMRD counter - integer MRD_cntr ; - integer SRR_cntr ; - integer SRC_cntr ; - - // Memory Banks - `ifdef FULL_MEM - reg [DQ_BITS - 1 : 0] mem_array [0 : (1< 1) begin - if (Mode_reg[6:4] == 3'b011) begin - if (clk_period < (tCK3_min-0.001)) begin - $display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 3", $realtime); - $display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period); - end - end - if (Mode_reg[6:4] == 3'b010) begin - if (clk_period < (tCK2_min-0.001)) begin - $display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 2", $realtime); - $display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period); - end - end - end - end - - //SRR reg settings - always @(posedge power_up_done) begin - Srr_reg = 'b0 ; - Srr_reg[3:0] = 4'b1111 ; //Manufacturer(Micron) - Srr_reg[7:4] = 4'b0000 ; //Revision ID(Default to 0 in model) - Srr_reg[10:8] = 3'b100 ; //Refresh Rate(based on temp sensor - will default to 1x in model) - Srr_reg[11] = (DQ_BITS == 32)? 1'b1 : 1'b0 ; //Part width(x32 or x16) - Srr_reg[12] = 1'b0 ; //Device Type (LP DDR) - Srr_reg[15:13] = (part_size == 1024)? 3'b011 : - (part_size == 512 )? 3'b010 : - (part_size == 256 )? 3'b001 : - 3'b000 ; //Density(1024Mb, 512Mb, 256Mb, 128Mb) - end - - // System Clock - always begin - @ (posedge diff_ck) begin - Sys_clk = CkeZ; - CkeZ = Cke; - end - @ (negedge diff_ck) begin - Sys_clk = 1'b0; - end - end - - task store_prev_cmd; - begin - prev_Cs_n <= Cs_n ; - prev_Ras_n <= Ras_n ; - prev_Cas_n <= Cas_n ; - prev_We_n <= We_n ; - prev_Ba[1] <= Ba[1] ; - prev_Ba[0] <= Ba[0] ; - prev_cke <= Cke ; - end - endtask - - task MRD_counter; - begin - if (Cke) begin - if (MRD_cntr < tMRD) begin - MRD_cntr = MRD_cntr + 1'b1; - end - end - end - endtask - - task SRR_counter; - begin - if (Cke) begin - if (SRR_cntr < tSRR) begin - SRR_cntr = SRR_cntr + 1'b1; - end - end - end - endtask - - task SRC_counter; - begin - if (Cke) begin - if (SRC_cntr < ((Mode_reg[6:4])+1)) begin - SRC_cntr = SRC_cntr + 1'b1; - end - end - end - endtask - - task command_counter; - begin - if (Cke) begin - for (i=0; i<4;i=i+1) begin - if (Read_precharge_count[i] < 4'hf) begin - Read_precharge_count[i] = Read_precharge_count[i] + 1'b1; - end - end - for (i=0; i<4;i=i+1) begin - if (Write_precharge_count[i] < 4'hf) begin - Write_precharge_count[i] = Write_precharge_count[i] + 1'b1; - end - end - end - end - endtask - - - task PD_counter; - begin - if (~Cke) begin - if (PD_cntr < tCKE) begin - PD_cntr = PD_cntr + (enter_DPD | enter_PD | DPD_enable | PD_enable); - end - end else begin - PD_cntr = 4'h0 ; - end - end - endtask - - task tXP_check; - begin - if (Cke == 1'b1 && prev_cke == 1'b0) begin - tXP_chk = $realtime ; - end - if (Cke) begin - if (~nop_enable && ~des_enable) begin - if ($realtime-tXP_chk < tXP) begin -`ifdef T25L - $display ("%m: At time %t ERROR: tPDX violation", $realtime); -`else - $display ("%m: At time %t ERROR: tXP violation", $realtime); -`endif - end - end - end - end - endtask - - // DPD pos edge clk cntr - always begin - @ (posedge diff_ck) begin - tXP_check ; - Power_down_chk ; - PD_counter ; - store_prev_cmd ; - end - end - - // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high - always @(Cke) begin - if (Cke === 1'b1) begin - if (SelfRefresh === 1'b1) begin - SelfRefresh = 1'b0; - end - if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin - $display ("%m: At time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $realtime); - $display ("%m: when the Clock Enable is brought High."); - end - end - end - - //BL Mode Reg settings - always@(Mode_reg[2:0] or mode_load_done) begin - if (mode_load_done) begin - case (Mode_reg[2:0]) - 3'b001 : burst_length = 5'b00010; - 3'b010 : burst_length = 5'b00100; - 3'b011 : burst_length = 5'b01000; - default : burst_length = 5'bxxxxx; - endcase - end - end - -// Init sequence -always @* begin - if (current_init_state == begin_init) begin - if (Cke) begin - current_init_state = cke_init ; - power_up_done = 1'b0 ; - end - end - if (current_init_state == cke_init) begin - if (Prech_enable) begin - current_init_state = prech_init ; - aref_count = 0 ; - end - end - if (current_init_state == prech_init) begin - if (~Prech_enable) begin - current_init_state = begin_mode_init ; - end - end - if (current_init_state == begin_mode_init) begin - if (ext_mode_load_done) begin - current_init_state = ext_mode_init ; - end - if (mode_load_done) begin - current_init_state = mode_init ; - end - end - if (current_init_state == mode_init) begin - if (ext_mode_load_done) begin - current_init_state = mode_done_init ; - end - end - if (current_init_state == ext_mode_init) begin - if (mode_load_done) begin - current_init_state = mode_done_init ; - end - end - if (current_init_state == mode_done_init && aref_count >= 2) begin - power_up_done = 1'b1; - end -end - - - // this task will erase the contents of 0 or more banks - task erase_mem; - input [BA_BITS+1:0] bank_MSB_row; //bank bits + 2 row MSB - input DPD_mode ; //erase all memory locations - integer i; - begin - - if (DPD_mode) begin -`ifdef FULL_MEM - for (i=0; i<{(BA_BITS+ROW_BITS+COL_BITS){1'b1}}; i=i+1) begin - mem_array[i] = 'bx; - end -`else - memory_index = 0; - i = 0; - // remove the selected banks - for (memory_index=0; memory_index= burst_length) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - read_precharge_truncation = 1'b0; - //if (SRC_cntr == 2) begin // **** - if (((SRC_cntr == 2) & (Mode_reg[6:4] == 3'b010)) | ((SRC_cntr == 3) & (Mode_reg[6:4] == 3'b011))) begin - SRR_read = 1'b0; - end - end - end - endtask - -// // Burst Decode -// task Burst_Decode; -// begin -// -// // Advance Burst Counter -// if (Burst_counter < burst_length) begin -// Burst_counter = Burst_counter + 1; -// end -// -// // Burst Type -// if (Mode_reg[3] === 1'b0) begin // Sequential Burst -// Cols_temp = Cols_addr + 1; -// end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst -// Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2]; -// Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1]; -// Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0]; -// end -// -// // Burst Length -// if (burst_length === 2) begin -// Cols_addr [0] = Cols_temp [0]; -// end else if (burst_length === 4) begin -// Cols_addr [1 : 0] = Cols_temp [1 : 0]; -// end else if (burst_length === 8) begin -// Cols_addr [2 : 0] = Cols_temp [2 : 0]; -// end else if (burst_length === 16) begin -// Cols_addr [3 : 0] = Cols_temp [3 : 0]; -// end else begin -// Cols_addr = Cols_temp; -// end -// -// // Data Counter -// if (Burst_counter >= burst_length) begin -// Data_in_enable = 1'b0; -// Data_out_enable = 1'b0; -// read_precharge_truncation = 1'b0; -// SRR_read = 1'b0; -// end -// end -// endtask - - // SRC check - task Timing_chk_SRC; - begin - if (Active_enable || Aref_enable || Sref_enable || Burst_term || - Ext_mode_enable || Mode_reg_enable || Prech_enable || Read_enable || - Write_enable || DPD_enable || PD_enable || srr_enable) begin - if (part_size == 1024) begin - if (SRC_cntr < ((Mode_reg[6:4])+tSRC)) begin - $display ("%m: At time %t ERROR: tSRC Violation", $realtime); - end - end - end - end - endtask - - // Manual Precharge Pipeline - task Manual_Precharge_Pipeline; - begin - // A10 Precharge Pipeline - A10_precharge[0] = A10_precharge[1]; - A10_precharge[1] = A10_precharge[2]; - A10_precharge[2] = A10_precharge[3]; - A10_precharge[3] = A10_precharge[4]; - A10_precharge[4] = A10_precharge[5]; - A10_precharge[5] = A10_precharge[6]; - A10_precharge[6] = 1'b0; - - // Bank Precharge Pipeline - Bank_precharge[0] = Bank_precharge[1]; - Bank_precharge[1] = Bank_precharge[2]; - Bank_precharge[2] = Bank_precharge[3]; - Bank_precharge[3] = Bank_precharge[4]; - Bank_precharge[4] = Bank_precharge[5]; - Bank_precharge[5] = Bank_precharge[6]; - Bank_precharge[6] = 2'b0; - - // Command Precharge Pipeline - Cmnd_precharge[0] = Cmnd_precharge[1]; - Cmnd_precharge[1] = Cmnd_precharge[2]; - Cmnd_precharge[2] = Cmnd_precharge[3]; - Cmnd_precharge[3] = Cmnd_precharge[4]; - Cmnd_precharge[4] = Cmnd_precharge[5]; - Cmnd_precharge[5] = Cmnd_precharge[6]; - Cmnd_precharge[6] = 1'b0; - - // Terminate a Read if same bank or all banks - if (Cmnd_precharge[0] === 1'b1) begin - if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin - if (Data_out_enable === 1'b1) begin - Data_out_enable = 1'b0; - read_precharge_truncation = 1'b1; - end - end - end - end - endtask - - // Burst Terminate Pipeline - task Burst_Terminate_Pipeline; - begin - // Command Precharge Pipeline - Cmnd_bst[0] = Cmnd_bst[1]; - Cmnd_bst[1] = Cmnd_bst[2]; - Cmnd_bst[2] = Cmnd_bst[3]; - Cmnd_bst[3] = Cmnd_bst[4]; - Cmnd_bst[4] = Cmnd_bst[5]; - Cmnd_bst[5] = Cmnd_bst[6]; - Cmnd_bst[6] = 1'b0; - - // Terminate a Read regardless of banks - if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin - Data_out_enable = 1'b0; - end - end - endtask - - // Dq and Dqs Drivers - task Dq_Dqs_Drivers; - begin - // read command pipeline - Read_cmnd [0] = Read_cmnd [1]; - Read_cmnd [1] = Read_cmnd [2]; - Read_cmnd [2] = Read_cmnd [3]; - Read_cmnd [3] = Read_cmnd [4]; - Read_cmnd [4] = Read_cmnd [5]; - Read_cmnd [5] = Read_cmnd [6]; - Read_cmnd [6] = 1'b0; - - // read bank pipeline - Read_bank [0] = Read_bank [1]; - Read_bank [1] = Read_bank [2]; - Read_bank [2] = Read_bank [3]; - Read_bank [3] = Read_bank [4]; - Read_bank [4] = Read_bank [5]; - Read_bank [5] = Read_bank [6]; - Read_bank [6] = 2'b0; - - // read column pipeline - Read_cols [0] = Read_cols [1]; - Read_cols [1] = Read_cols [2]; - Read_cols [2] = Read_cols [3]; - Read_cols [3] = Read_cols [4]; - Read_cols [4] = Read_cols [5]; - Read_cols [5] = Read_cols [6]; - Read_cols [6] = 0; - - // Initialize Read command - if (Read_cmnd [1] === 1'b1) begin - Data_out_enable = 1'b1; - Bank_addr = Read_bank [1]; - Cols_addr = Read_cols [1]; - Cols_brst = Cols_addr [2 : 0]; - if (SRR_read == 1'b1) begin - Burst_counter = burst_length - 2; - end else begin - Burst_counter = 0; - end - - // Row Address Mux - case (Bank_addr) - 2'd0 : Rows_addr = B0_row_addr; - 2'd1 : Rows_addr = B1_row_addr; - 2'd2 : Rows_addr = B2_row_addr; - 2'd3 : Rows_addr = B3_row_addr; - default : $display ("%m: At time %t ERROR: Invalid Bank Address", $realtime); - endcase - end - - // Toggle Dqs during Read command - if (Data_out_enable === 1'b1) begin - Dqs_int = 1'b0; - if (Dqs_gen === {DQS_BITS{1'b0}}) begin - Dqs_gen = {DQS_BITS{1'b1}}; - end else if (Dqs_gen === {DQS_BITS{1'b1}}) begin - Dqs_gen = {DQS_BITS{1'b0}}; - end else if (Dqs_gen === {DQS_BITS{1'b0}}) begin - Dqs_gen = {DQS_BITS{1'b0}}; - end - if (Mode_reg[6:4] == 3'b010) begin - Dqs_out <= #tAC2_max Dqs_gen; - end else if (Mode_reg[6:4] == 3'b011) begin - Dqs_out <= #tAC3_max Dqs_gen; - end - end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0 && (Dqs_gen !== {DQS_BITS{1'bz}})) begin - Dqs_gen = {DQS_BITS{1'bz}} ; - if (Mode_reg[6:4] == 3'b010) begin - Dqs_out <= #tHZ2_max Dqs_gen; - end else if (Mode_reg[6:4] == 3'b011) begin - Dqs_out <= #tHZ3_max Dqs_gen; - end - end - - // Initialize dqs for Read command - if (Mode_reg[6:4] == 3'b010) begin - if ((Read_enable === 1'b1) && (Sys_clk == 1'b1)) begin - if (Data_out_enable === 1'b0) begin - Dqs_int = 1'b1; - Dqs_gen = {DQS_BITS{1'b0}}; -// Dqs_out <= #2.0 Dqs_gen; // used in place of tLZ for a one clock preamble - Dqs_out <= #tAC2_max Dqs_gen; // used in place of tLZ for a one clock preamble // **** - end - end - end else if (Mode_reg[6:4] == 3'b011) begin - if (Read_cmnd [3] === 1'b1) begin - if (Data_out_enable === 1'b0) begin - Dqs_int = 1'b1; - Dqs_gen = {DQS_BITS{1'b0}}; - Dqs_out <= #tAC3_max Dqs_gen; // used in place of tLZ for a one clock preamble - end - end - end - - // Read latch - if (Data_out_enable === 1'b1) begin - // output data - if (SRR_read == 1'b1) begin - if (Burst_counter == (burst_length-2)) begin - Dq_out <= Srr_reg[DQ_BITS-1:0]; - end else if (Burst_counter == (burst_length-1)) begin - Dq_out <= Srr_reg[2*DQ_BITS-1:DQ_BITS]; - end - end else begin - read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out); - end - if (Debug) begin - $display ("At time %t %m:READ: Bank = %d, Row = %d, Col = %d, Data = %d", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_out); - end - - end else begin - Dq_out = {DQ_BITS{1'bz}}; - end - end - endtask - - // Write FIFO and DM Mask Logic - task Write_FIFO_DM_Mask_Logic; - begin - // Write command pipeline - Write_cmnd [0] = Write_cmnd [1]; - Write_cmnd [1] = Write_cmnd [2]; - Write_cmnd [2] = Write_cmnd [3]; - Write_cmnd [3] = 1'b0; - - // Write command pipeline - Write_bank [0] = Write_bank [1]; - Write_bank [1] = Write_bank [2]; - Write_bank [2] = Write_bank [3]; - Write_bank [3] = 2'b0; - - // Write column pipeline - Write_cols [0] = Write_cols [1]; - Write_cols [1] = Write_cols [2]; - Write_cols [2] = Write_cols [3]; - Write_cols [3] = {COL_BITS{1'b0}}; - - // Initialize Write command - if (Write_cmnd [0] === 1'b1) begin - Data_in_enable = 1'b1; - Bank_addr = Write_bank [0]; - Cols_addr = Write_cols [0]; - Cols_brst = Cols_addr [2 : 0]; - Burst_counter = 0; - - // Row address mux - case (Bank_addr) - 2'd0 : Rows_addr = B0_row_addr; - 2'd1 : Rows_addr = B1_row_addr; - 2'd2 : Rows_addr = B2_row_addr; - 2'd3 : Rows_addr = B3_row_addr; - default : $display ("%m: At time %t ERROR: Invalid Row Address", $realtime); - endcase - end - - // Write data - if (Data_in_enable === 1'b1) begin - - // Data Buffer - read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); - - // write negedge Dqs on posedge Sys_clk - if (Sys_clk) begin - if (!dm_fall[0]) begin - Dq_buf [ 7 : 0] = dq_fall [ 7 : 0]; - end - if (!dm_fall[1]) begin - Dq_buf [15 : 8] = dq_fall [15 : 8]; - end - if (!dm_fall[2]) begin - Dq_buf [23 : 16] = dq_fall [23 : 16]; - end - if (!dm_fall[3]) begin - Dq_buf [31 : 24] = dq_fall [31 : 24]; - end - if (~&dm_fall) begin - if (Debug) begin - $display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); - end - end - // write posedge Dqs on negedge Sys_clk - end else begin - if (!dm_rise[0]) begin - Dq_buf [ 7 : 0] = dq_rise [ 7 : 0]; - end - if (!dm_rise[1]) begin - Dq_buf [15 : 8] = dq_rise [15 : 8]; - end - if (!dm_rise[2]) begin - Dq_buf [23 : 16] = dq_rise [23 : 16]; - end - if (!dm_rise[3]) begin - Dq_buf [31 : 24] = dq_rise [31 : 24]; - end - if (~&dm_rise) begin - if (Debug) begin - $display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); - end - end - end - - // Write Data - write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); - - // tWR start and tWTR check - if (Sys_clk && &dm_pair === 1'b0) begin - case (Bank_addr) - 2'd0 : WR_chk0 = $realtime; - 2'd1 : WR_chk1 = $realtime; - 2'd2 : WR_chk2 = $realtime; - 2'd3 : WR_chk3 = $realtime; - default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $realtime); - endcase - - // tWTR check - if (Read_enable === 1'b1) begin - $display ("%m: At time %t ERROR: tWTR violation during Read", $realtime); - end - end - end - end - endtask - - // Auto Precharge Calculation - task Auto_Precharge_Calculation; - begin - // Precharge counter - if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin - Count_precharge [0] = Count_precharge [0] + 1; - end - if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin - Count_precharge [1] = Count_precharge [1] + 1; - end - if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin - Count_precharge [2] = Count_precharge [2] + 1; - end - if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin - Count_precharge [3] = Count_precharge [3] + 1; - end - - // Read with AutoPrecharge Calculation - // The device start internal precharge when: - // 1. Meet tRAS requirement - // 2. BL/2 cycles after command - if ((Read_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin - if (Count_precharge[0] >= burst_length/2) begin - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $realtime; - Read_precharge[0] = 1'b0; - end - end - if ((Read_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin - if (Count_precharge[1] >= burst_length/2) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $realtime; - Read_precharge[1] = 1'b0; - end - end - if ((Read_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin - if (Count_precharge[2] >= burst_length/2) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $realtime; - Read_precharge[2] = 1'b0; - end - end - if ((Read_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin - if (Count_precharge[3] >= burst_length/2) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $realtime; - Read_precharge[3] = 1'b0; - end - end - - // Write with AutoPrecharge Calculation - // The device start internal precharge when: - // 1. Meet tRAS requirement - // 2. Two clock after last burst - // Since tWR is time base, the model will compensate tRP - if ((Write_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin - if (Count_precharge[0] >= burst_length/2+3) begin - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk0 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk0 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[0] = 1'b0; - end - end - if ((Write_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin - if (Count_precharge[1] >= burst_length/2+3) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk1 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk1 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[1] = 1'b0; - end - end - if ((Write_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin - if (Count_precharge[2] >= burst_length/2+3) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk2 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk2 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[2] = 1'b0; - end - end - if ((Write_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin - if (Count_precharge[3] >= burst_length/2+3) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk3 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk3 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[3] = 1'b0; - end - end - end - endtask - - task Power_down_chk; - begin - if (DPD_enable == 1'b1 && enter_DPD == 1'b0) begin - if (prev_cke & Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin - erase_mem(4'b0000, 1'b1); - current_init_state = begin_init ; - ext_mode_load_done = 1'b0 ; - mode_load_done = 1'b0 ; - enter_DPD = 1'b1; - $display ("%m: at time %t Entering Deep Power-Down Mode", $realtime); - end - end - if (enter_DPD == 1'b1) begin - if (Cke == 1'b1 && prev_cke == 1'b0) begin - if (PD_cntr < tCKE) begin - $display ("%m: At time %t ERROR: tCKE violation during exiting of Deep Power-Down Mode", $realtime); - end - $display ("%m: at time %t Exiting Deep Power-Down Mode - A 200 us delay is required with either DESELECT or NOP commands present before the initialization sequence may begin", $realtime); - enter_DPD = 1'b0; - end - end - if (PD_enable == 1'b1 && enter_PD == 1'b0) begin - if (prev_cke) begin - if (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin - $display ("%m: at time %t Entering Power-Down Mode", $realtime); - enter_PD = 1'b1; - end else if (~Pc_b0 | ~Pc_b1 | ~Pc_b2 | ~Pc_b3) begin - $display ("%m: at time %t Entering Active Power-Down Mode", $realtime); - enter_APD = 1'b1; - end - end - end - if (enter_PD == 1'b1 || enter_APD == 1'b1) begin - if (Cke == 1'b1 && prev_cke == 1'b0) begin - if (PD_cntr < tCKE) begin - if (enter_PD == 1'b1) begin - $display ("%m: At time %t ERROR: tCKE violation during exiting of Power-Down Mode", $realtime); - end else if (enter_APD == 1'b1) begin - $display ("%m: At time %t ERROR: tCKE violation during exiting of Active Power-Down Mode", $realtime); - end - end - if (enter_PD == 1'b1) begin - $display ("%m: at time %t Exiting Power-Down Mode", $realtime); - enter_PD = 1'b0 ; - end else if (enter_APD == 1'b1) begin - $display ("%m: at time %t Exiting Active Power-Down Mode", $realtime); - enter_APD = 1'b0 ; - end - end - end - - end - endtask - - // Control Logic - task Control_Logic; - begin - - // Self Refresh - if (Sref_enable === 1'b1) begin - // Partial Array Self Refresh - if (part_size == 128) begin - case (Ext_Mode_reg[2:0]) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end - 3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end - 3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b101 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b110 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - endcase - end else begin - case (Ext_Mode_reg[2:0]) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end - 3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end - 3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b101 : begin $display("%m: at time %t INFO: Banks 1-3 and 1/2 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0001, 1'b0); end - 3'b110 : begin $display("%m: at time %t INFO: Banks 1-3 and 3/4 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0000, 1'b0); end - endcase - end - SelfRefresh = 1'b1; - end - if (Aref_enable === 1'b1) begin - if (Debug) begin - $display ("Debug: At time %t %m:AUTOREFRESH: Auto Refresh", $realtime); - end - // aref_count is to make sure we have met part of the initialization sequence - if (~power_up_done) begin - aref_count = aref_count + 1; - end - - // Auto Refresh to Auto Refresh - if ($realtime - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $realtime); - end - - // Precharge to Auto Refresh - if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) || - ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $realtime); - end - - // Precharge to Auto Refresh - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $realtime); - end - - // Record Current tRFC time - RFC_chk = $realtime; - end - - // SRR Register - if (srr_enable == 1'b1) begin - if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1 && - Data_out_enable === 1'b0 && Data_in_enable === 1'b0) begin - SRR_read = 1'b1; - SRR_chk = $realtime; - SRR_cntr = 0; - end - end - - - // Extended Mode Register - if (Ext_mode_enable == 1'b1) begin - if (Debug) begin - $display ("Debug: At time %t %m:EMR : Extended Mode Register", $realtime); - end - - // Register Mode - Ext_Mode_reg = Addr; - - if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin - // ensure that power sequence is met properly - if (~power_up_done) begin - ext_mode_load_done = 1'b1; - end - $display ("At time %t %m:ELMR : Extended Load Mode Register", $realtime); - if (part_size == 128) begin - // Self Refresh Coverage - case (Addr[2 : 0]) - 3'b000 : $display ("%m : Self Refresh Cov = 4 banks"); - 3'b001 : $display ("%m : Self Refresh Cov = 2 banks"); - 3'b010 : $display ("%m : Self Refresh Cov = 1 bank"); - 3'b101 : $display ("%m : PASR = Reserved"); - 3'b110 : $display ("%m : PASR = Reserved"); - default : $display ("%m : PASR = Reserved"); - endcase - end else begin - // Self Refresh Coverage - case (Addr[2 : 0]) - 3'b000 : $display ("%m : Self Refresh Cov = 4 banks"); - 3'b001 : $display ("%m : Self Refresh Cov = 2 banks"); - 3'b010 : $display ("%m : Self Refresh Cov = 1 bank"); - 3'b101 : $display ("%m : Self Refresh Cov = 1/2 bank"); - 3'b110 : $display ("%m : Self Refresh Cov = 1/4 bank"); - default : $display ("%m : PASR = Reserved"); - endcase - end - // Maximum Case Temp - case (Addr[4 : 3]) - 2'b11 : $display ("%m : Maximum Case Temp = 85C"); - 2'b00 : $display ("%m : Maximum Case Temp = 70C"); - 2'b01 : $display ("%m : Maximum Case Temp = 45C"); - 2'b10 : $display ("%m : Maximum Case Temp = 15C"); - endcase - - // Drive Strength - case (Addr[6 : 5]) - 2'b00 : $display ("%m : Drive Strength = Full Strength"); - 2'b01 : $display ("%m : Drive Strength = Half Strength"); - 2'b10 : $display ("%m : Drive Strength = Quarter Strength"); - 2'b11 : $display ("%m : Drive Strength = One Eight Strength"); - endcase - - end else begin - $display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $realtime); - end - - // Precharge to EMR - if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) || - ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $realtime); - end - - // LMR/EMR to LMR/EMR -// if ($realtime - MRD_chk < tMRD) begin -// $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime); -// end - - if (MRD_cntr < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime); - end - - // Record current tMRD time -// MRD_chk = $realtime; - MRD_cntr = 0; - end - - // Load Mode Register - if (Mode_reg_enable === 1'b1) begin - if (Debug) begin - $display ("Debug: At time %t %m:LMR : Load Mode Register", $realtime); - end - - // Register Mode - Mode_reg = Addr; - - if (Mode_reg[6:4] == 3'b010) begin - if (tCK2_min == 0) begin - $display ("%m : at time %t ERROR : Illegal CAS Latency of 2 set for current speed grade", $realtime); - end - end - - // Precharge to LMR - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $realtime); - end - - // Precharge to LMR - if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) || - ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $realtime); - end - - // LMR/EMR to LMR/EMR -// if ($realtime - MRD_chk < tMRD) begin -// $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime); -// end - if (MRD_cntr < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime); - end - - if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin - // ensure that power sequence is met properly - if (~power_up_done) begin - mode_load_done = 1'b1; - end - // Burst Length - case (Addr [2 : 0]) - 3'b001 : $display ("At time %t %m:LMR : Burst Length = 2", $realtime); - 3'b010 : $display ("At time %t %m:LMR : Burst Length = 4", $realtime); - 3'b011 : $display ("At time %t %m:LMR : Burst Length = 8", $realtime); - default : - begin - $display ("%m: At time %t ERROR: Undefined burst length selection", $realtime); - $stop; - end - endcase - - // CAS Latency - case (Addr [6 : 4]) - 3'b010 : $display ("At time %t %m:LMR : CAS Latency = 2", $realtime); - 3'b011 : $display ("At time %t %m:LMR : CAS Latency = 3", $realtime); - default : begin - $display ("%m: At time %t ERROR: CAS Latency not supported", $realtime); - $stop; - end - endcase - - end - // Record current tMRD time -// MRD_chk = $realtime; - MRD_cntr = 0; - end - - // Activate Block - if (Active_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $realtime); - end - // Display Debug Message - if (Debug) begin - $display ("Debug: At time %t %m:ACTIVATE: Bank = %d, Row = %d", $realtime, Ba, Addr); - end - - // Activating an open bank can cause corruption. - if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) || - (Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin - $display ("%m: At time %t ERROR: Bank = %d is already activated - data can be corrupted", $realtime, Ba); - end - - // Activate Bank 0 - if (Ba === 2'b00 && Pc_b0 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk0 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk0 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b0 = 1'b1; - Pc_b0 = 1'b0; - B0_row_addr = Addr; - RC_chk0 = $realtime; - RCD_chk0 = $realtime; - RAS_chk0 = $realtime; - RAP_chk0 = $realtime; - end - - // Activate Bank 1 - if (Ba === 2'b01 && Pc_b1 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk1 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk1 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b1 = 1'b1; - Pc_b1 = 1'b0; - B1_row_addr = Addr; - RC_chk1 = $realtime; - RCD_chk1 = $realtime; - RAS_chk1 = $realtime; - RAP_chk1 = $realtime; - end - - // Activate Bank 2 - if (Ba === 2'b10 && Pc_b2 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk2 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk2 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b2 = 1'b1; - Pc_b2 = 1'b0; - B2_row_addr = Addr; - RC_chk2 = $realtime; - RCD_chk2 = $realtime; - RAS_chk2 = $realtime; - RAP_chk2 = $realtime; - end - - // Activate Bank 3 - if (Ba === 2'b11 && Pc_b3 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk3 < tRC) begin - $display ("%m: t time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk3 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b3 = 1'b1; - Pc_b3 = 1'b0; - B3_row_addr = Addr; - RC_chk3 = $realtime; - RCD_chk3 = $realtime; - RAS_chk3 = $realtime; - RAP_chk3 = $realtime; - end - - // Activate to Activate (different bank) - if ((Prev_bank != Ba) && ($realtime - RRD_chk < tRRD)) begin - $display ("%m: At time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba); - end - - // AutoRefresh to Activate - if ($realtime - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba); - end - - // Record variable for checking violation - RRD_chk = $realtime; - Prev_bank = Ba; - end - - // Precharge Block - consider NOP if bank already precharged or in process of precharging - if (Prech_enable === 1'b1) begin - // Display Debug Message - if (Debug) begin - $display ("Debug: At time %t %m:PRE: Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba); - end - - // EMR or LMR to Precharge -// if ($realtime - MRD_chk < tMRD) begin -// $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime); -// end - if (MRD_cntr < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime); - end - - // Precharge bank 0 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin - Act_b0 = 1'b0; - Pc_b0 = 1'b1; - RP_chk0 = $realtime; - - // Activate to Precharge Bank - if ($realtime - RAS_chk0 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk0 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Precharge bank 1 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin - Act_b1 = 1'b0; - Pc_b1 = 1'b1; - RP_chk1 = $realtime; - - // Activate to Precharge Bank 1 - if ($realtime - RAS_chk1 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk1 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Precharge bank 2 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin - Act_b2 = 1'b0; - Pc_b2 = 1'b1; - RP_chk2 = $realtime; - - // Activate to Precharge Bank 2 - if ($realtime - RAS_chk2 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk2 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Precharge bank 3 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin - Act_b3 = 1'b0; - Pc_b3 = 1'b1; - RP_chk3 = $realtime; - - // Activate to Precharge Bank 3 - if ($realtime - RAS_chk3 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk3 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Pipeline for READ - A10_precharge [cas_latency_x2] = Addr[10]; - Bank_precharge[cas_latency_x2] = Ba; - Cmnd_precharge[cas_latency_x2] = 1'b1; - end - - // Burst terminate - if (Burst_term === 1'b1) begin - // Display Debug Message - if (Debug) begin - $display ("Debug: %m: At time %t BURST_TERMINATE): Burst Terminate",$realtime); - end - - // Burst Terminate Command Pipeline for Read - Cmnd_bst[cas_latency_x2-1] = 1'b1; - - // Illegal to burst terminate a Write - if (Data_in_enable === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $realtime); - end - - // Illegal to burst terminate a Read with Auto Precharge - if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 || - Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime); - end - end - - // Read Command - if (Read_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $realtime); - end - // Display Debug Message - if (Debug) begin - $display ("Debug: At time %t %m:READ: Bank = %d, Col = %d", $realtime, Ba, {Addr [11], Addr [9 : 0]}); - end - if (part_size == 1024) begin - if (SRR_read == 1'b1) begin - if (SRR_cntr < tSRR) begin - $display ("%m: At time %t ERROR: tSRR Violation", $realtime); - end - SRC_cntr = 0 ; - end - end else begin - if (SRR_read == 1'b1) begin - if ($realtime - SRR_chk < tSRR-0.01) begin - $display ("%m: At time %t ERROR: tSRR Violation", $realtime); - end - SRC_cntr = 0; - end - end - // CAS Latency pipeline - Read_cmnd[cas_latency_x2] = 1'b1; - Read_bank[cas_latency_x2] = Ba; - Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - - // Terminate a Write - if (Data_in_enable === 1'b1) begin - Data_in_enable = 1'b0; - end - - // Interrupt a Read with Auto Precharge - if (Read_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime); - end else if ((Read_precharge [0] === 1'b1) | - (Read_precharge [1] === 1'b1) | - (Read_precharge [2] === 1'b1) | - (Read_precharge [3] === 1'b1) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (different banks)", $realtime); - end - - // Interrupt a Write with Auto Precharge - if (Write_precharge [Ba] === 1'b1) begin -// $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same banks)", $realtime); - end else if ((Write_precharge_count [0] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [1] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [2] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [3] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [0] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) | - (Write_precharge_count [1] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) | - (Write_precharge_count [2] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) | - (Write_precharge_count [3] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Write with Auto Precharge (different banks)", $realtime); - end - - // Activate to Read - if (((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) && - (SRR_read == 1'b0)) begin - $display("%m: At time %t ERROR: Bank is not Activated for Read", $realtime); - end - - // Activate to Read without Auto Precharge - if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin - $display("%m: At time %t ERROR: tRCD violation during Read", $realtime); - end - - // Auto Precharge - if (Addr[10] === 1'b1) begin - Read_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - Read_precharge_count[Ba] = 4'h0; - end - end - - // Write Command - if (Write_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $realtime); - end - // display debug message - if (Debug) begin - $display ("Debug: At time %t %m:WRITE: Bank = %d, Col = %d", $realtime, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}); - end - - // Pipeline for Write - Write_cmnd [3] = 1'b1; - Write_bank [3] = Ba; - Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - - // Interrupt a Write with Auto Precharge (same bank only) - if (Write_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $realtime); - end - - // Activate to Write - if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin - $display("%m: At time %t ERROR: Bank is not Activated for Write", $realtime); - end - - // Activate to Write - if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) || - (Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) || - (Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) || - (Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin - $display("%m: At time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba); - end - - // Read to Write - if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] || - Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter_dly < burst_length)) begin - if (Data_out_enable_dly || read_precharge_truncation) begin - $display("%m: At time %t ERROR: Read to Write violation", $realtime); - end - end - - // Interrupt a Write with Auto Precharge - if (Write_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same bank)", $realtime); - end else if (((Write_precharge [0] === 1'b1) & (Count_precharge[0] < (burst_length/2))) | - ((Write_precharge [1] === 1'b1) & (Count_precharge[1] < (burst_length/2))) | - ((Write_precharge [2] === 1'b1) & (Count_precharge[2] < (burst_length/2))) | - ((Write_precharge [3] === 1'b1) & (Count_precharge[3] < (burst_length/2))) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (different bank)", $realtime); - end - - // Interrupt a Read with Auto Precharge - if (((Read_precharge_count [Ba] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [Ba] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin -// $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime); - end else if (((Read_precharge_count [0] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [1] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [2] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [3] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [0] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) | - ((Read_precharge_count [1] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) | - ((Read_precharge_count [2] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) | - ((Read_precharge_count [3] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Read with Auto Precharge (different bank)", $realtime); - end - - // Auto Precharge - if (Addr[10] === 1'b1) begin - Write_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - Write_precharge_count[Ba] = 4'h0; - end - end - - end - endtask - - // Main Logic - always @ (posedge Sys_clk) begin - Manual_Precharge_Pipeline; - Burst_Terminate_Pipeline; - Dq_Dqs_Drivers; - Write_FIFO_DM_Mask_Logic; - Burst_Decode; - Auto_Precharge_Calculation; - Timing_chk_SRC; - Control_Logic; - MRD_counter; - SRR_counter; - SRC_counter; - command_counter; - end - - always @ (negedge Sys_clk) begin - Manual_Precharge_Pipeline; - Burst_Terminate_Pipeline; - Dq_Dqs_Drivers; - Write_FIFO_DM_Mask_Logic; - Burst_Decode; - end - - // Dqs Receiver - always @ (posedge Dqs_in[0]) begin - // Latch data at posedge Dqs - dq_rise[7 : 0] = Dq_in[7 : 0]; - dm_rise[0] = Dm_in[0]; - expect_pos_dqs[0] = 0; - end - - always @ (posedge Dqs_in[1]) begin - // Latch data at posedge Dqs - dq_rise[15 : 8] = Dq_in[15 : 8]; - dm_rise[1] = Dm_in [1]; - expect_pos_dqs[1] = 0; - end - -`ifdef x32 - always @ (posedge Dqs_in[2]) begin - // Latch data at posedge Dqs - dq_rise[23 : 16] = Dq_in[23 : 16]; - dm_rise[2] = Dm_in [2]; - expect_pos_dqs[2] = 0; - end - - always @ (posedge Dqs_in[3]) begin - // Latch data at posedge Dqs - dq_rise[31 : 24] = Dq_in[31 : 24]; - dm_rise[3] = Dm_in [3]; - expect_pos_dqs[3] = 0; - end -`endif - - always @ (negedge Dqs_in[0]) begin - // Latch data at negedge Dqs - dq_fall[7 : 0] = Dq_in[7 : 0]; - dm_fall[0] = Dm_in[0]; - dm_pair[1:0] = {dm_rise[0], dm_fall[0]}; - expect_neg_dqs[0] = 0; - end - - always @ (negedge Dqs_in[1]) begin - // Latch data at negedge Dqs - dq_fall[15: 8] = Dq_in[15 : 8]; - dm_fall[1] = Dm_in[1]; - dm_pair[3:2] = {dm_rise[1], dm_fall[1]}; - expect_neg_dqs[1] = 0; - end - -`ifdef x32 - always @ (negedge Dqs_in[2]) begin - // Latch data at negedge Dqs - dq_fall[23: 16] = Dq_in[23 : 16]; - dm_fall[2] = Dm_in[2]; - dm_pair[5:4] = {dm_rise[2], dm_fall[2]}; - expect_neg_dqs[2] = 0; - end - - always @ (negedge Dqs_in[3]) begin - // Latch data at negedge Dqs - dq_fall[31: 24] = Dq_in[31 : 24]; - dm_fall[3] = Dm_in[3]; - dm_pair[7:6] = {dm_rise[3], dm_fall[3]}; - expect_neg_dqs[3] = 0; - end -`endif - - // Dqs edge checking - always @ (posedge Sys_clk) begin - if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin - for (i=0; iWR, RD->RD, WR->BST, RD->BST -* Changed MRR to return 'x' except on first data beat of DQ[7:0] -* 0.30 JMK 01/31/08 Fixed BL4 + No Wrap -* Fixed Write with Auto Precharge timing checks -* Fixed timing checking for tRFCpb and tRFCab -* 0.40 JMK 02/26/08 Added LPDDR2-S2 support. S2/S4 selected using SX parameter -* 0.50 JMK 05/28/08 Fixed tCCD check for LPDDR2-S2 -* 0.60 JMK 08/15/08 Fixed timing checks for WR->RD, WR->PRE for partial writes -* Updated to match JEDEC Item #1725.01 LPDDR2 Draft Spec -* Changed $display to $fdisplay for info/errors/warnings/failures -* 0.70 JMK 09/19/08 Fixed MRR to odd address. -* 0.90 JMK 05/08/09 Fixed a compile error when MAX_MEM was defined -* Forced floating point division on arguments passed to -* the ceil function by multiplying operands by 1.0 -* 0.92 MYY 05/17/10 Added MRR 32/40 read out -* 0.94 MYY 08/09/10 Use File Access memory mode -* 0.96 MYY 02/27/12 Ignore PREab during init -****************************************************************************************/ - -// DO NOT CHANGE THE TIMESCALE -// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION -`timescale 1ps / 1ps - -module mobile_ddr2_fe ( - ck, - ck_n, - cke, - cs_n, - ca, - dm, - dq, - dqs, - dqs_n, - BEaddr, BEwr_h, BEwr_l, BEdin_h, BEdin_l, BEdout_h, BEdout_l, BEclear, BEreload, BEsynco, BEsynci -); -// `include "mobile_ddr2_parameters.vh" - -`define sg25 -`define x16 -`define REQUIRE_ZQINIT -// --------- Inlined mobile_ddr2_parameters.vh begins -/**************************************************************************************** -* -* Disclaimer This software code and all associated documentation, comments or other -* of Warranty: information (collectively "Software") is provided "AS IS" without -* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY -* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED -* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES -* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT -* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE -* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. -* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR -* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, -* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE -* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, -* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, -* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, -* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, -* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE -* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH -* DAMAGES. Because some jurisdictions prohibit the exclusion or -* limitation of liability for consequential or incidental damages, the -* above limitation may not apply to you. -* -* Copyright 2003 Micron Technology, Inc. All rights reserved. -* -****************************************************************************************/ - - // Parameters current with G80A datasheet rev 1.1 -`define lpddr2_4Gb - - // Timing parameters based on Speed Grade - - // SYMBOL UNITS DESCRIPTION - // ------ ----- ----------- -`ifdef sg18 - parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 210; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 210; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 220; // tIS ps Input Setup Time - parameter TIH = 220; // tIH ps Input Hold Time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 5620; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 50000; // tFAW ps Four-Bank Activate Window -`else `ifdef sg215 - parameter TCK_MIN = 2150; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 220; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 235; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 235; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 250; // tIS ps Input Setup Time - parameter TIH = 250; // tIH ps Input Hold Time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 6000; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 50000; // tFAW ps Four-Bank Activate Window -`else `ifdef sg25 - parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 270; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 270; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 290; // tIS ps Input Setup Time - parameter TIH = 290; // tIH ps Input Hold Time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 6000; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 50000; // tFAW ps Four-Bank Activate Window -`else `ifdef sg3 - parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 280; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 350; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 350; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 370; // tIS ps Input Setup Time - parameter TIH = 370; // tIH ps Input Hold Time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 6000; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 50000; // tFAW ps Four-Bank Activate Window -`else `ifdef sg37 - parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 340; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 430; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 430; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 460; // tIS ps Input Setup Time - parameter TIH = 460; // tIH ps Input Hold Time - parameter TWTR = 7500; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 6000; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 50000; // tFAW ps Four-Bank Activate Window -`else `ifdef sg5 - parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 400; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 480; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 480; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 600; // tIS ps Input Setup Time - parameter TIH = 600; // tIH ps Input Hold Time - parameter TWTR = 10000; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 6000; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 50000; // tFAW ps Four-Bank Activate Window -`else -`define sg6 - parameter TCK_MIN = 6000; // tCK ps Minimum Clock Cycle Time - parameter TDQSQ = 500; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access - parameter TDS = 600; // tDS ps DQ and DM input setup time relative to DQS - parameter TDH = 600; // tDH ps DQ and DM input hold time relative to DQS - parameter TIS = 740; // tIS ps Input Setup Time - parameter TIH = 740; // tIH ps Input Hold Time - parameter TWTR = 10000; // tWTR ps Write to Read command delay - parameter TDQSCK_MAX = 6000; // tDQSCK ps DQS output access time from CK/CK# - parameter TFAW = 60000; // tFAW ps Four-Bank Activate Window -`endif `endif `endif `endif `endif `endif - - // Timing Parameters - - // Clock - parameter CKH_MIN = 0.45; // tCH tCK Minimum Clock High-Level Pulse Width - parameter CKH_MAX = 0.55; // tCH tCK Maximum Clock High-Level Pulse Width - parameter CKL_MIN = 0.45; // tCL tCK Minimum Clock Low-Level Pulse Width - parameter CKL_MAX = 0.55; // tCL tCK Maximum Clock Low-Level Pulse Width - // Read - parameter TDQSCK = 2500; // tDQSCK ps DQS output access time from CK/CK# - // Write - parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width - parameter DQSH = 0.40; // tDQSH tCK DQS input High Pulse Width - parameter DQSL = 0.40; // tDQSL tCK DQS input Low Pulse Width - parameter DQSS = 0.75; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition - parameter DSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) - parameter DSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) - parameter WPRE = 0.35; // tWPRE tCK DQS Write Preamble - parameter WPST = 0.40; // tWPST tCK DQS Write Postamble - // CKE - parameter CKE = 3; // tCKE tCK CKE minimum high or low pulse width - parameter TCKESR = 15000; // tCKESR ps CKE minimum high or low pulse width self refresh - parameter ISCKE = 0.25; // tISCKE tCK CKE Input Setup Time - parameter IHCKE = 0.25; // tIHCKE tCK CKE Input Hold Time - // Mode Register - parameter MRR = 2; // tMRR tCK Load Mode Register command cycle time - parameter MRW = 3; // tMRW tCK Load Mode Register command cycle time - parameter CL_MIN = 3; // CL tCK Minimum CAS Latency - parameter CL_MAX = 8; // CL tCK Maximum CAS Latency - parameter TCL = 15000; // CL ps Minimum CAS Latency - parameter WR_MIN = 2; // WR tCK Minimum Write Recovery - parameter WR_MAX = 6; // WR tCK Maximum Write Recovery - parameter BL_MIN = 4; // BL tCK Minimum Burst Length - parameter BL_MAX = 16; // BL tCK Minimum Burst Length - parameter MR8RESID = 2'b00; - parameter DLLK = 200; // tDLLK tCK DLL locking time - // Command and Address - parameter CCD = 2; // tCCD tCK Cas to Cas command delay - parameter TDPD = 500000000; // tDPD ps Minimum Deep Power-Down time - parameter FAW = 8; // tFAW tCK Four-Bank Activate Window - parameter TIPW = 0.4; // tIPW tCK Control and Address input Pulse Width - parameter TRAS = 42000; // tRAS ps Minimum Active to Precharge command time - parameter RAS = 3; // tRAS tCK Minimum Active to Precharge command time - parameter TRCD = 15000; // tRCD ps Active to Read/Write command time - parameter RCD = 3; // tRCD tCK Active to Read/Write command time - parameter TRPAB = 18000; // tRPab ps Precharge All command period - parameter RPAB = 3; // tRPab tCK Precharge All command period - parameter TRPPB = 15000; // tRPpb ps Precharge command period - parameter RPPB = 3; // tRPpb tCK Precharge command period - parameter TRRD = 10000; // tRRD ps Active bank a to Active bank b command time - parameter RRD = 2; // tRRD tCK Active bank a to Active bank b command time - parameter TRTP = 7500; // tRTP ps Read to Precharge command delay - parameter RTP = 2; // tRTP tCK Read to Precharge command delay - parameter TWR = 15000; // tWR ps Write recovery time - parameter WR = 3; // tWR tCK Write recovery time - parameter WTR = 2; // tWTR tCK Write to Read command delay - parameter TXP = 7500; // tXP ps Exit power down to first valid command - parameter XP = 3; // tXP tCK Exit power down to first valid command - parameter TXSR = 140000; // tXSR ps Exit self refesh to first valid command - parameter XSR = 2; // tXSR tCK Exit self refesh to first valid command - // Refresh - parameter TRFCPB = 60000; // tRFCpb ps Refresh to Refresh Command interval minimum value - parameter TRFCAB = 130000; // tRFCab ps Refresh to Refresh Command interval minimum value - parameter TREFBW = 4160000; // tREFBW ps Burst Refresh Window - - // Initialization - parameter TINIT1 = 100000; // tINIT1 ps - parameter INIT2 = 5; // tINIT2 tCK - parameter TINIT3 = 200000000; // tINIT3 ps - parameter TINIT4 = 281000; // tINIT4 ps 2*tRFCab + tRP - parameter TINIT5 = 10000000; // tINIT5 ps - parameter TZQINIT = 1000000; // tZQINIT ps Calibration Initialization Time - parameter TZQCL = 360000; // tZQCL ps Long (Full) Calibration Time - parameter TZQCS = 90000; // tZQCS ps Short Calibration Time - parameter TZQRESET = 50000; // tZQRESET ps Calibration Reset Time - - - // Size Parameters based on Part Width -`ifdef x16 - parameter ROW_BITS = 14; // Address bits - parameter COL_BITS = 11; // Column bits - parameter DM_BITS = 2; // Data Mask bits - parameter DQ_BITS = 16; // Data bits **Same as part bit width** - parameter DQS_BITS = 2; // Dqs bits -`else -`define x32 - parameter ROW_BITS = 14; // Address bits - parameter COL_BITS = 10; // Column bits - parameter DM_BITS = 4; // Data Mask bits - parameter DQ_BITS = 32; // Data bits **Same as part bit width** - parameter DQS_BITS = 4; // Dqs bits -`endif - parameter COL_NOWRAPBITS = 9; // subpage for NOWRAP - parameter SUB_PAGE_BITS = 9; // Sub Page Bits = x32 COL_BITS - - // Size Parameters - parameter BA_BITS = 3; // Bank Address bits - parameter CA_BITS = 10; // Command Address Bits - parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. - parameter SX = 4; // prefetch architecture. 2 = LPDDR2-S2 device, 4 = LPDDR2-S4 device. - - // Simulation parameters - parameter STOP_ON_ERROR = 0; // If set to 1, the model will halt on errors - parameter MSGLENGTH = 256; // max length in characters of a debug string - -// --------- Inlined mobile_ddr2_parameters.vh ends - - `define DQ_PER_DQS DQ_BITS/DQS_BITS - `define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-1) - `define MAX_PIPE 2*CL_MAX + BL_MAX - `define MEM_SIZE (1<>3) & 1; - wire wc = (mr[1]>>4) & 1; - wire [3:0] nwr = ((mr[1]>>5) & 7) + 2; // range 3-8 - // MR2 - wire [3:0] rl = (mr[2] & 7) + 2; // range 4-8 - wire [2:0] wl = (rl>>1) + (&rl[2:0]); // range 2-4 - // MR10 - wire [7:0] calibration_code = mr[10]; - parameter - CAL_INIT = 8'hFF, - CAL_LONG = 8'hAB, - CAL_SHORT = 8'h56, - CAL_ZQ = 8'hC3 - ; - // MR16 - wire [1:0] pasr = mr[16]; // S2 - wire [7:0] pasr_bank = mr[16]; // S4 - // MR17 - wire [7:0] pasr_segment = mr[17]; // 1Gb-8Gb S4 - - reg [2:0] init; - reg [BA_BITS-1:0] cas_ba; - reg [(1<>1) && ($time - tm_cke < TINIT1)) begin - ERROR ("tINIT1 violation"); - end - if (ck_cntr - ck_cke < INIT2) begin - ERROR ("tINIT2 violation"); - end - // CKE high moves to tINIT3 - init = 3; - tm_init3 <= $time; - end - end - 3 : begin // 2. Reset command - // NOP allowed during tINIT3 - if ((cmd[4:1] !== 4'b1111) && ($time - tm_init3 < TINIT3)) begin - ERROR ("tINIT3 violation"); - end - // reset moves to tINIT4 - if ((cmd == MRW_CMD) && (ca[9:4] == 'h3F)) begin - init = 4; - tm_init4 <= $time; - end - - end - 4 : begin - // NOP required during tINIT4 - if ((cmd[4:1] !== 4'b1111) && ($time - tm_init4 < TINIT4)) begin - ERROR ("tINIT4 violation"); - end - // CMD or tINIT4 moves to tINIT5 - if ((cmd[4:1] !== 4'b1111) || ($time - tm_init4 >= TINIT4)) begin - init = 5; - end - end - 5 : begin // 3. Mode Registers Reads and Device Auto-Initialization (DAI) polling: - // PD and MRR allowed during tINIT5 - if ((cmd[3:1] !== 3'b111) && (cmd !== MRR_CMD) && ($time - tm_init4 < TINIT5)) begin - ERROR ("tINIT5 violation"); - end - // CMD or tINIT5 finishes - if (((cmd[3:1] !== 3'b111) && (cmd !== MRR_CMD)) || ($time - tm_init4 >= TINIT5)) begin - if (SX == 2) begin - INFO ("Initialization complete"); - init = 0; // done - end else begin - init = 6; - end - mr[0] = {7'h00, MRRBIT}; // DAI complete - end - end - 6 : begin // 4. ZQ Calibration -`ifdef REQUIRE_ZQINIT - if (calibration_code == CAL_INIT) begin - init = 7; - end -`else - init = 7; -`endif - end - 7 : begin - // CMD or tZQINIT finishes - if ((cmd[3:1] !== 3'b111) || ($time - tm_zq >= TZQINIT)) begin - INFO ("Initialization complete"); - init = 0; // done - mr[0] = {7'h00, MRRBIT}; - end - end - endcase - - // auto precharge - if (|bank_ap) begin - for (i=0; i<(1<= nwr) - && (ck_cntr - ck_bank_act[i] >= RAS) && ($time - tm_bank_act[i] >= TRAS))) begin - // tWR violation if nwr < tWR - ba = i; - ab = 0; - chk_err(WRITE_CMD, PRE_CMD); - write_ap[i] = 1'b0; - end - if (read_ap[i] && ((ck_cntr - ck_bank_read_end[i] >= RTP) && ($time - tm_bank_read_end[i] >= TRTP) - && (ck_cntr - ck_bank_act[i] >= RAS) && ($time - tm_bank_act[i] >= TRAS))) begin - read_ap[i] = 1'b0; - end - if (bank_ap[i] && !write_ap[i] && !read_ap[i]) begin - $sformat (msg, "Auto Precharge bank %1d", i); - INFO (msg); - bank_ap[i] = 1'b0; - bank_active[i] = 1'b0; - ck_pre <= ck_cntr; - tm_pre <= $time; - ck_bank_pre[i] <= ck_cntr; - tm_bank_pre[i] <= $time; - end - end - end - - // shift pipelines - if (|wr_pipeline || |rd_pipeline) begin - wr_pipeline <= wr_pipeline>>1; - rd_pipeline <= rd_pipeline>>1; - for (i=0; i<`MAX_PIPE; i=i+1) begin - ba_pipeline[i] <= ba_pipeline[i + 1]; - row_pipeline[i] <= row_pipeline[i + 1]; - col_pipeline[i] <= col_pipeline[i + 1]; - ma_pipeline[i] <= ma_pipeline[i + 1]; - end - end - - // *_read_end is start time for measuring tRTP - if ((ck_read > ck_bst) && ((ck_cntr - ck_read)%(SX/2) == 0) && (ck_cntr - ck_bank_read[cas_ba] <= (lastrd_bl - SX)/2) && (cmd != READ_CMD) && (cmd != BST_CMD)) begin - ck_read_end = ck_cntr; - tm_read_end = $time; - ck_bank_read_end[cas_ba] = ck_cntr; - tm_bank_read_end[cas_ba] = $time; - end - - // *_write_end is the start time for measuring tWR and tWTR - if ((ck_cntr - ck_write)%(SX/2) == 0) begin - for (i=0; i<(1< 4) begin - ERROR ("tFAW violation"); - end - $sformat (msg, "REFpb bank %d", bank_ref); - INFO (msg); - bank_ref <= bank_ref + 1; - ck_ref <= ck_cntr; - tm_ref <= $time; - ck_bank_ref[bank_ref] <= ck_cntr; - tm_bank_ref[bank_ref] <= $time; - end - end - {1'b1, REFAB_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to REFab"); - end else if (|bank_active) begin - ERROR ("All banks must be Precharged prior to REFab"); - end else begin - // a maximum of 8 REFab commands may be issued in any rolling tREFBW - j = 0; - for (i=0; i<16; i=i+1) begin - if ($time - tm_burst_refa[i] < TREFBW) begin - j = j + 1; - end - end - if (j > 8) begin - ERROR ("tREFBW violation"); - end - // INFO ("REFab"); - // bank_ref <= 0; // REFAB does not reset bank_ref counter - burst_refa <= burst_refa + 1; - tm_refa <= $time; - tm_burst_refa[burst_refa] <= $time; - end - end - {1'b1, ACT_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to ACT"); - end else if (bank_active[ba]) begin - $sformat (msg, "Bank %d must be Precharged prior to ACT", ba); - ERROR (msg); - end else begin - // a maximum of 4 Act commands may be issued in any rolling tFAW - j = 0; - for (i=0; i<(1< 4) begin - ERROR ("tFAW violation"); - end - neg_en <= 1'b1; - ck_act <= ck_cntr; - tm_act <= $time; - ck_bank_act[ba] <= ck_cntr; - tm_bank_act[ba] <= $time; - end - end - {1'b1, WRITE_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to WRITE"); - end else if (!bank_active[ba]) begin - $sformat (msg, "Bank %d must be Activated prior to WRITE", ba); - WARN (msg); // change from ERR to WAR - end else if (bank_ap[ba]) begin - $sformat (msg, "Auto Precharge is scheduled to bank %d", ba); - ERROR (msg); - end else if ((ck_write > ck_bst) && (ck_cntr - ck_write < lastwr_bl/2) && (ck_cntr - ck_write)%(SX/2)) begin - ERROR ("Illegal WRITE bust interruption"); - end else begin - neg_en <= 1'b1; - cas_ba <= ba; - ck_write <= ck_cntr; - ck_write_end <= ck_cntr; - ck_bank_write[ba] <= ck_cntr; - ck_bank_write_end[ba] <= ck_cntr; - tm_write_end <= $time; - tm_bank_write_end[ba] <= $time; - end - end - {1'b1, READ_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to READ"); - end else if (!bank_active[ba]) begin - $sformat (msg, "Bank %d must be Activated prior to READ", ba); - WARN (msg); // change from ERROR to WARN - end else if (bank_ap[ba]) begin - $sformat (msg, "Auto Precharge is scheduled to bank %d", ba); - ERROR (msg); - end else if ((ck_read > ck_bst) && (ck_cntr - ck_read < lastrd_bl/2) && (ck_cntr - ck_read)%(SX/2)) begin - ERROR ("Illegal READ burst interruption"); - end else begin - neg_en <= 1'b1; - cas_ba <= ba; - ck_read <= ck_cntr; - ck_read_end <= ck_cntr; - ck_bank_read[ba] <= ck_cntr; - ck_bank_read_end[ba] <= ck_cntr; - tm_read_end <= $time; - tm_bank_read_end[ba] <= $time; - end - end - {1'b1, BST_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to BST"); - end else if ((ck_cntr - ck_write >= lastwr_bl/2) && (ck_cntr - ck_read >= lastrd_bl/2)) begin - // ERROR ("BST may only be issued up to BL/2 - 1 clock cycles after a READ or WRITE"); // CHECK OFF - end else if ((ck_read > ck_write) && (ck_cntr - ck_read)%(SX/2)) begin - ERROR ("BST can only be issued an even number of clock cycles after a READ"); - end else if ((ck_write > ck_read) && (ck_cntr - ck_write)%(SX/2)) begin - ERROR ("BST can only be issued an even number of clock cycles after a WRITE"); - end else if (bank_ap[cas_ba]) begin - $sformat (msg, "Auto Precharge is scheduled to bank %d", cas_ba); - ERROR (msg); - end else begin - INFO ("BST"); - wr_pipeline <= (wr_pipeline>>1) & ((1<<(wl + 1))-1); - rd_pipeline <= (rd_pipeline>>1) & ((1<<(rl - 1))-1); - ck_bst <= ck_cntr; - end - end - {1'b1, PRE_CMD} : begin - // A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), - // or if the previously open row is already in the process of precharging. - if (ab) begin - if (|init) begin - INFO ("PREab during initialization sequence ignored"); - end else if (&(~bank_active | bank_ap)) begin - INFO ("PREab has been ignored"); - end else begin - INFO ("PREab"); - bank_active = 0; - ck_prea <= ck_cntr; - tm_prea <= $time; - end - end else if (bank_active[ba]) begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to PREpb"); - end else if (~bank_active[ba] | bank_ap[ba]) begin - $sformat (msg, "PREpb bank %d has been ignored", ba); - INFO (msg); - end else begin - $sformat (msg, "PREpb bank %d", ba); - // INFO (msg); - ck_pre <= ck_cntr; - tm_pre <= $time; - bank_active[ba] = 1'b0; - ck_bank_pre[ba] <= ck_cntr; - tm_bank_pre[ba] <= $time; - end - end - end - {1'b1, NOP_CMD} : ; // do nothing - {1'b1, SREF_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to SREF"); - end else if (|bank_active) begin - ERROR ("All banks must be Precharged prior to SREF"); - end else begin - INFO ("SREF"); - cke_cmd <= SREF_CMD>>1; - bank_ref <= 0; - ck_cke <= ck_cntr; - tm_cke <= $time; - end - end - {1'b1, DPD_CMD} : begin - if (|init) begin - ERROR ("Initialization sequence must be complete prior to DPD"); - end else begin - INFO ("DPD"); - init <= 1; - bank_active <= 0; // allow MRW(RESET) command - cke_cmd <= DPD_CMD>>1; -// `ifdef MAX_MEM -// erase_banks({(1<>1; - ck_cke <= ck_cntr; - tm_cke <= $time; - end - end - {1'b0, NOP_CMD} : begin // EXIT SREF, PD, DPD - case (cke_cmd) - SREF_CMD>>1 : begin - if ($time - tm_cke < TCKESR) - ERROR ("tCKESR violation"); - ck_sref <= ck_cntr; - tm_sref <= $time; - end - DPD_CMD>>1 , - PD_CMD>>1 : begin - ck_pd <= ck_cntr; - tm_pd <= $time; - end - endcase - if (ck_cntr - ck_cke < CKE) - ERROR ("tCKE violation"); - ck_cke <= ck_cntr; - tm_cke <= $time; - end - 6'b00xxxx : begin // Maintain SREF, PD, DPD - if ((ck_cntr - ck_cke == 1) && (cmd[3:1] !== 3'b111)) begin - ERROR ("Nop or Deselect must be driven in the clock cycle after CKE goes low"); - end - end - default : ERROR ("Illegal command"); - endcase - - cke_q <= cke_in; - ca_q <= ca; - ck_cntr <= ck_cntr + 1; - tck_i <= $time - tm_ck_pos; - tm_ck_pos <= $time; - - end else if (neg_en) begin - ma = {ca[1:0], ca_q[9:4]}; - op = ca[9:2]; - ba = ca_q[9:7]; - r = {ca[9:8], ca_q[6:2], ca[7:0]}; - c = {ca[9:1], ca_q[6:5], 1'b0}; - ecbbl = {ca_q[3], ca_q[4]}; - casex ({ca_q[0], ca_q[1], ca_q[2]}) - 3'b000 : begin // MRW/MRR - if (ca_q[3]) begin // MRR - if (mrwe[ma]) begin - $sformat (msg, "Register %d is Write Only", ma); - WARN (msg); - end - // still output data for write only registers - $sformat (msg, "MRR ma %h op %h", ma, mr[ma]); - INFO (msg); - for (i=0; i<2; i=i+1) begin - rd_pipeline[rl - 1 + i] <= 1'b1; - ba_pipeline[rl - 1 + i] <= {BA_BITS{1'bx}}; - ma_pipeline[rl - 1 + i] <= ma + i*256; - end - end else begin // MRW - if (~mrwe[ma]) begin - $sformat (msg, "Register %d is Read Only or RFU", ma); - WARN (msg); - end else begin - if (~mrmask[ma] & op) begin - $sformat(msg, "RFU bits in ma %h cannot be set", ma); - WARN (msg); - end - if (ma == 10) begin - if (SX == 2) begin - INFO ("ZQ Calibration command has been ignored"); - end else begin - tm_zq <= tm_ck_pos; - end - end - $sformat (msg, "MRW ma %h op %h", ma, op); - INFO (msg); - mr[ma] <= mrmask[ma] & op; - end - end - end - 3'b01x : begin // ACT - if (r >= 1<= 1<= 1<>(c[0]*DQ_BITS); - $sformat (msg, "Write @dqs, bank = %h, row = %h, col = %h, dq = %h", ba, r, c, dq_temp); - // INFO (msg); - end - - // read data - if (diff_ck) begin - dqs_out_en <= #(TDQSCK) (|rd_pipeline[1:0]); - dq_out_en <= #(TDQSCK) (rd_pipeline[0]); - end - dqs_out <= #(TDQSCK) rd_pipeline[0] && diff_ck; - dq_out <= #(TDQSCK) dq_temp; - - if (rd_pipeline[0]) begin - if (!diff_ck) begin - if (ba === {BA_BITS{1'bx}}) begin // MRR command - if(ma==32 || ma==(32+256)) begin - memory_data = {{DQ_BITS{1'b0}},{DQ_BITS{1'b1}}}; - end - else if (ma==40) begin - memory_data = {{DQ_BITS{1'b0}},{DQ_BITS{1'b0}}}; - end - else if (ma==(40+256)) begin - memory_data = {{DQ_BITS{1'b1}},{DQ_BITS{1'b1}}}; - end - else - memory_data = {{2*DQ_BITS - 8{MRRBIT}}, mr[ma]}; - end else begin - memory_read(ba, r, c, memory_data); - end - end - - if (ba === {BA_BITS{1'bx}}) // MRR command // no need to shift for MRR - dq_temp = memory_data>>(diff_ck*DQ_BITS); - else - dq_temp = memory_data>>(c[0]*DQ_BITS); - - $sformat (msg, "Read @dqs, bank = %h, row = %h, col = %h, dq = %h", ba, r, c, dq_temp); - // INFO (msg); - end - end - - // receiver(s) - task dqs_even_receiver; - input [3:0] i; - reg [63:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_even[i]) begin - dm_in_pos[i] = dm_in[i]; - dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); - end - end - endtask - - always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); - always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); - always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); - always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); - always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); - always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); - always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); - always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); - - task dqs_odd_receiver; - input [3:0] i; - reg [63:0] bit_mask; - begin - bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); - if (dqs_odd[i]) begin - dm_in_neg[i] = dm_in[i]; - dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); - end - end - endtask - - always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); - always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); - always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); - always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); - always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); - always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); - always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); - always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); - - //--------------------------------------------------- - // TASK: INFO("msg") - //--------------------------------------------------- - task INFO; - input [MSGLENGTH*8:1] msg; - begin - $fdisplay(mcd_error, "%m at time %t: %0s", $time, msg); - end - endtask - - //--------------------------------------------------- - // TASK: WARN("msg") - //--------------------------------------------------- - task WARN; - input [MSGLENGTH*8:1] msg; - begin - $fdisplay(mcd_warn, "%m at time %t: %0s", $time, msg); - warnings = warnings + 1; - end - endtask - - //--------------------------------------------------- - // TASK: ERROR(errcode, "msg") - //--------------------------------------------------- - task ERROR; - input [MSGLENGTH*8:1] msg; - begin - $fdisplay(mcd_error, "%m at time %t: %0s", $time, msg); - errors = errors + 1; - if (STOP_ON_ERROR) begin - STOP; - end - end - endtask - - //--------------------------------------------------- - // TASK: FAIL("msg") - //--------------------------------------------------- - task FAIL; - input [MSGLENGTH*8:1] msg; - begin - $fdisplay(mcd_fail, "%m at time %t: %0s", $time, msg); - failures = failures + 1; - STOP; - end - endtask - - //--------------------------------------------------- - // TASK: Stop() - //--------------------------------------------------- - task STOP; - begin - $display("%m at time %t: %d warnings, %d errors, %d failures", $time, warnings, errors, failures); - $stop(0); - end - endtask - - - function integer ceil; - input number; - real number; - if (number > $rtoi(number)) - ceil = $rtoi(number) + 1; - else - ceil = number; - endfunction - -// `ifdef MAX_MEM -// function integer open_bank_file( input integer bank ); -// integer fd; -// reg [2048:1] filename; -// begin -// $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); - -// fd = $fopen(filename, "w+"); -// if (fd == 0) -// begin -// if (mcd_error) -// $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename); -// $finish; -// end -// else -// begin -// if (mcd_info) -// $display("%m: at time %0t INFO: opening %0s.", $time, filename); -// open_bank_file = fd; -// end - -// end -// endfunction - -// function [2*RFF_BITS:1] read_from_file( -// input integer fd, -// input integer index -// ); -// integer code; -// integer offset; -// reg [1024:1] msg; -// reg [2*RFF_BITS:1] read_value; - -// begin -// offset = index * RFF_CHUNK; -// code = $fseek( fd, offset, 0 ); -// // $fseek returns 0 on success, -1 on failure -// if (code != 0) -// begin -// $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); -// $finish; -// end - -// code = $fscanf(fd, "%z", read_value); -// // $fscanf returns number of items read -// if (code != 1) -// begin -// if ($ferror(fd,msg) != 0) -// begin -// $display("%m: at time %t ERROR: fscanf failed at %d", $time, index); -// $display(msg); -// $finish; -// end -// else -// read_value = 'hx; -// end - -// /* when reading from unwritten portions of the file, 0 will be returned. -// * Use 0 in bit 1 as indicator that invalid data has been read. -// * A true 0 is encoded as Z. -// */ -// if (read_value[1] === 1'bz) -// // true 0 encoded as Z, data is valid -// read_value[1] = 1'b0; -// else if (read_value[1] === 1'b0) -// // read from file section that has not been written -// read_value = 'hx; - -// read_from_file = read_value; -// end -// endfunction - -// task write_to_file( -// input integer fd, -// input integer index, -// input [2*RFF_BITS:1] data -// ); -// integer code; -// integer offset; - -// begin -// offset = index * RFF_CHUNK; -// code = $fseek( fd, offset, 0 ); -// if (code != 0) -// begin -// $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); -// $finish; -// end - -// // encode a valid data -// if (data[1] === 1'bz) -// data[1] = 1'bx; -// else if (data[1] === 1'b0) -// data[1] = 1'bz; - -// $fwrite( fd, "%z", data ); -// end -// endtask - -// task erase_banks; -// input [(1<tCH_MAX) begin - $display ("%m: at time %t ERROR: tCH maximum violation on CLK by %t", $time, pos_clk_time - tCH_MAX*clk_period); - end - if ((neg_clk_time/clk_period)tCL_MAX) begin - $display ("%m: at time %t ERROR: tCH minimum violation on CLK by %t", $time, pos_clk_time - tCL_MAX*clk_period); - end - end - end - - // Mode Register - reg [ADDR_BITS - 1 : 0] Mode_reg; - reg [ADDR_BITS - 1 : 0] Ext_Mode_reg; - reg [2*DQ_BITS - 1 : 0] Srr_reg; - - // SRR Registers - reg SRR_read; - - // Internal System Clock - reg CkeZ, Sys_clk; - - // Internal Dqs initialize - reg Dqs_int; - - // Dqs buffer - reg [DQS_BITS - 1 : 0] Dqs_out; - reg [DQS_BITS - 1 : 0] Dqs_gen; - - // Dq buffer - reg [DQ_BITS - 1 : 0] Dq_out; - - // Read pipeline variables - reg Read_cmnd [0 : 6]; - reg [1 : 0] Read_bank [0 : 6]; - reg [COL_BITS - 1 : 0] Read_cols [0 : 6]; - - // Write pipeline variables - reg Write_cmnd [0 : 3]; - reg [1 : 0] Write_bank [0 : 3]; - reg [COL_BITS - 1 : 0] Write_cols [0 : 3]; - - // Auto precharge variables - reg Read_precharge [0 : 3]; - reg Write_precharge [0 : 3]; - integer Count_precharge [0 : 3]; - reg SelfRefresh; - reg [3:0] Read_precharge_count [3:0] ; - reg [3:0] Write_precharge_count [3:0]; - - - reg wr_ap_display_msg ; - reg rd_ap_display_msg ; - - // Manual precharge variables - reg A10_precharge [0 : 6]; - reg [1 : 0] Bank_precharge [0 : 6]; - reg Cmnd_precharge [0 : 6]; - - // Burst terminate variables - reg Cmnd_bst [0 : 6]; - - // tMRD counter - integer MRD_cntr ; - integer SRR_cntr ; - integer SRC_cntr ; - - // Dqs edge checking - integer i; - reg [3:0] expect_pos_dqs; - reg [3:0] expect_neg_dqs; - - // Burst counter - reg [COL_BITS - 1 : 0] Burst_counter; - - // Burst counter delay - reg [COL_BITS - 1 : 0] Burst_counter_dly; - always@* begin - if (Mode_reg[6:4] == 3'b010) begin - Burst_counter_dly = #tAC2_max Burst_counter; - end else if (Mode_reg[6:4] == 3'b011) begin - Burst_counter_dly = #tAC3_max Burst_counter; - end - end - - // Precharge variables - reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; - - // Activate variables - reg Act_b0, Act_b1, Act_b2, Act_b3; - - // Data IO variables - reg Data_in_enable; - reg Data_out_enable; - - // Data Out Enable delay - reg Data_out_enable_dly; - always@* begin - if (Mode_reg[6:4] == 3'b010) begin - Data_out_enable_dly <= #tAC2_max Data_out_enable; - end else if (Mode_reg[6:4] == 3'b011) begin - Data_out_enable_dly <= #tAC3_max Data_out_enable; - end - end - - // Internal address mux variables - reg [1 : 0] Prev_bank; - reg [1 : 0] Bank_addr; - reg [COL_BITS - 1 : 0] Cols_addr, Cols_brst, Cols_temp; - reg [ADDR_BITS - 1 : 0] Rows_addr; - reg [ADDR_BITS - 1 : 0] B0_row_addr; - reg [ADDR_BITS - 1 : 0] B1_row_addr; - reg [ADDR_BITS - 1 : 0] B2_row_addr; - reg [ADDR_BITS - 1 : 0] B3_row_addr; - - integer aref_count; - reg ext_mode_load_done; - reg mode_load_done; - reg power_up_done; - - reg file_load_done; - - // Write DQS for tDSS , tDSH, tDQSH, tDQSL checks - wire wdqs_valid = Write_cmnd[1] || Write_cmnd[2] || Data_in_enable; - - // Commands Decode - wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n; - wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & Cke; - wire Sref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n & ~Cke; - wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n; - wire Ext_mode_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & Ba[1] & ~Ba[0]; - wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & ~Ba[0]; - wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n; - wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n; - wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n; - wire DPD_enable = ~Cs_n & Ras_n & Cas_n & ~We_n & ~Cke; - wire PD_enable = ((~Cs_n & Ras_n & Cas_n & We_n) | Cs_n) & ~Cke; - wire nop_enable = ~Cs_n & Ras_n & Cas_n & We_n ; - wire des_enable = Cs_n ; - wire srr_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n & ~Ba[1] & Ba[0] ; //& (part_size==1024) ; // **** - - // Burst Length Decode -// reg [4:0] burst_length = 1 << (Mode_reg[2:0]); - reg [4:0] burst_length ; - reg read_precharge_truncation; - - // CAS Latency Decode - wire [2:0] cas_latency_x2 = ((2*Mode_reg[6:4])-1); - - - - // DQS Buffer - reg [DQS_BITS - 1 : 0] dqs_delayed ; -// always@* begin -// dqs_delayed <= Dqs_out ; -// end - - assign Dqs = Dqs_out; - - // DQ Buffer - reg [DQ_BITS - 1 : 0] dq_delayed ; - always@* begin - if (Mode_reg[6:4] == 3'b010) begin - dq_delayed <= #tAC2_max Dq_out ; - end else if (Mode_reg[6:4] == 3'b011) begin - dq_delayed <= #tAC3_max Dq_out ; - end else begin - dq_delayed <= #tAC3_max {DQ_BITS{1'bz}} ; - end - end - assign Dq = dq_delayed; - - // Debug message - wire Debug = 1'b0; - - // Timing Check -// realtime MRD_chk; - realtime RFC_chk; - realtime RRD_chk; - realtime RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3; - realtime RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3; - realtime RC_chk0, RC_chk1, RC_chk2, RC_chk3; - realtime RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; - realtime RP_chk0, RP_chk1, RP_chk2, RP_chk3; - realtime WR_chk0, WR_chk1, WR_chk2, WR_chk3; - realtime SRR_chk; - - // - reg [2:0] current_init_state ; - parameter [2:0] begin_init = 3'b000 ; - parameter [2:0] cke_init = 3'b001 ; - parameter [2:0] prech_init = 3'b010 ; - parameter [2:0] begin_mode_init = 3'b011 ; - parameter [2:0] mode_init = 3'b100 ; - parameter [2:0] ext_mode_init = 3'b101 ; - parameter [2:0] mode_done_init = 3'b110 ; - - initial begin - CkeZ = 1'b0; - Sys_clk = 1'b0; - {Pc_b0, Pc_b1, Pc_b2, Pc_b3} = 4'b0000; - {Act_b0, Act_b1, Act_b2, Act_b3} = 4'b1111; - Dqs_int = 1'b0; - Dqs_out = {DQS_BITS{1'bz}}; - Dqs_gen = {DQS_BITS{1'bz}}; - Dq_out = {DQ_BITS{1'bz}}; - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - aref_count = 0; - SelfRefresh = 1'b0; - power_up_done = 0; - ext_mode_load_done = 0; - mode_load_done = 0; - // MRD_chk = 0; - RFC_chk = 0; - RRD_chk = 0; - RAS_chk0 = 0; - RAS_chk1 = 0; - RAS_chk2 = 0; - RAS_chk3 = 0; - RAP_chk0 = 0; - RAP_chk1 = 0; - RAP_chk2 = 0; - RAP_chk3 = 0; - RC_chk0 = 0; - RC_chk1 = 0; - RC_chk2 = 0; - RC_chk3 = 0; - RCD_chk0 = 0; - RCD_chk1 = 0; - RCD_chk2 = 0; - RCD_chk3 = 0; - RP_chk0 = 0; - RP_chk1 = 0; - RP_chk2 = 0; - RP_chk3 = 0; - WR_chk0 = 0; - WR_chk1 = 0; - WR_chk2 = 0; - WR_chk3 = 0; - SRR_chk = 0; - $timeformat (-9, 3, " ns", 12); - pos_clk_time = 0; - neg_clk_time = 0; - enter_DPD = 0; - enter_PD = 0; - enter_APD = 0; - current_init_state = begin_init ; - SRR_read = 1'b0; - MRD_cntr = 8; - SRR_cntr = 8; - SRC_cntr = 8; - Read_precharge[0] = 1'b0 ; - Read_precharge[1] = 1'b0 ; - Read_precharge[2] = 1'b0 ; - Read_precharge[3] = 1'b0 ; - Write_precharge[0] = 1'b0 ; - Write_precharge[1] = 1'b0 ; - Write_precharge[2] = 1'b0 ; - Write_precharge[3] = 1'b0 ; - wr_ap_display_msg = 1'b0 ; - rd_ap_display_msg = 1'b0 ; - Read_precharge_count[0] = 4'hf; - Read_precharge_count[1] = 4'hf; - Read_precharge_count[2] = 4'hf; - Read_precharge_count[3] = 4'hf; - Write_precharge_count[0] = 4'hf; - Write_precharge_count[1] = 4'hf; - Write_precharge_count[2] = 4'hf; - Write_precharge_count[3] = 4'hf; - BEaddr = {full_mem_bits{1'b0}}; - BEwr = {(DQ_BITS/8){1'b0}}; - BEdin = {DQ_BITS{1'b0}}; - BEclear = 1'b0; - BEclrpart = 1'b0; - BEsynco = 0'b0; - end - - //clock Frequency Check - always @(posedge diff_ck) begin - if (clk_pos_edge_cnt > 1) begin - if (Mode_reg[6:4] == 3'b011) begin - if (clk_period < (tCK3_min-0.001)) begin - $display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 3", $realtime); - $display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period); - end - end - if (Mode_reg[6:4] == 3'b010) begin - if (clk_period < (tCK2_min-0.001)) begin - $display ("%m : at time %t ERROR : Illegal clk period for CAS Latency 2", $realtime); - $display ("%m : at time %t CLK PERIOD = %t", $realtime, clk_period); - end - end - end - end - - //SRR reg settings - always @(posedge power_up_done) begin - Srr_reg = 'b0 ; - Srr_reg[3:0] = 4'b1111 ; //Manufacturer(Micron) - Srr_reg[7:4] = 4'b0000 ; //Revision ID(Default to 0 in model) - Srr_reg[10:8] = 3'b100 ; //Refresh Rate(based on temp sensor - will default to 1x in model) - Srr_reg[11] = (DQ_BITS == 32)? 1'b1 : 1'b0 ; //Part width(x32 or x16) - Srr_reg[12] = 1'b0 ; //Device Type (LP DDR) - Srr_reg[15:13] = (part_size == 1024)? 3'b011 : - (part_size == 512 )? 3'b010 : - (part_size == 256 )? 3'b001 : - 3'b000 ; //Density(1024Mb, 512Mb, 256Mb, 128Mb) - end - - // System Clock - always begin - @ (posedge diff_ck) begin - Sys_clk = CkeZ; - CkeZ = Cke; - end - @ (negedge diff_ck) begin - Sys_clk = 1'b0; - end - end - - task store_prev_cmd; - begin - prev_Cs_n <= Cs_n ; - prev_Ras_n <= Ras_n ; - prev_Cas_n <= Cas_n ; - prev_We_n <= We_n ; - prev_Ba[1] <= Ba[1] ; - prev_Ba[0] <= Ba[0] ; - prev_cke <= Cke ; - end - endtask - - task MRD_counter; - begin - if (Cke) begin - if (MRD_cntr < tMRD) begin - MRD_cntr = MRD_cntr + 1'b1; - end - end - end - endtask - - task SRR_counter; - begin - if (Cke) begin - if (SRR_cntr < tSRR) begin - SRR_cntr = SRR_cntr + 1'b1; - end - end - end - endtask - - task SRC_counter; - begin - if (Cke) begin - if (SRC_cntr < ((Mode_reg[6:4])+1)) begin - SRC_cntr = SRC_cntr + 1'b1; - end - end - end - endtask - - task command_counter; - begin - if (Cke) begin - for (i=0; i<4;i=i+1) begin - if (Read_precharge_count[i] < 4'hf) begin - Read_precharge_count[i] = Read_precharge_count[i] + 1'b1; - end - end - for (i=0; i<4;i=i+1) begin - if (Write_precharge_count[i] < 4'hf) begin - Write_precharge_count[i] = Write_precharge_count[i] + 1'b1; - end - end - end - end - endtask - - - task PD_counter; - begin - if (~Cke) begin - if (PD_cntr < tCKE) begin - PD_cntr = PD_cntr + (enter_DPD | enter_PD | DPD_enable | PD_enable); - end - end else begin - PD_cntr = 4'h0 ; - end - end - endtask - - task tXP_check; - begin - if (Cke == 1'b1 && prev_cke == 1'b0) begin - tXP_chk = $realtime ; - end - if (Cke) begin - if (~nop_enable && ~des_enable) begin - if ($realtime-tXP_chk < tXP) begin -`ifdef T25L - $display ("%m: At time %t ERROR: tPDX violation", $realtime); -`else - $display ("%m: At time %t ERROR: tXP violation", $realtime); -`endif - end - end - end - end - endtask - - // DPD pos edge clk cntr - always begin - @ (posedge diff_ck) begin - tXP_check ; - Power_down_chk ; - PD_counter ; - store_prev_cmd ; - end - end - - // Check to make sure that we have a Deselect or NOP command on the bus when CKE is brought high - always @(Cke) begin - if (Cke === 1'b1) begin - if (SelfRefresh === 1'b1) begin - SelfRefresh = 1'b0; - end - if (!((Cs_n) || (~Cs_n & Ras_n & Cas_n & We_n))) begin - $display ("%m: At time %t MEMORY ERROR: You must have a Deselect or NOP command applied", $realtime); - $display ("%m: when the Clock Enable is brought High."); - end - end - end - - //BL Mode Reg settings - always@(Mode_reg[2:0] or mode_load_done) begin - if (mode_load_done) begin - case (Mode_reg[2:0]) - 3'b001 : burst_length = 5'b00010; - 3'b010 : burst_length = 5'b00100; - 3'b011 : burst_length = 5'b01000; - default : burst_length = 5'bxxxxx; - endcase - end - end - -// Init sequence -always @* begin - if (current_init_state == begin_init) begin - if (Cke) begin - current_init_state = cke_init ; - power_up_done = 1'b0 ; - end - end - if (current_init_state == cke_init) begin - if (Prech_enable) begin - current_init_state = prech_init ; - aref_count = 0 ; - end - end - if (current_init_state == prech_init) begin - if (~Prech_enable) begin - current_init_state = begin_mode_init ; - end - end - if (current_init_state == begin_mode_init) begin - if (ext_mode_load_done) begin - current_init_state = ext_mode_init ; - end - if (mode_load_done) begin - current_init_state = mode_init ; - end - end - if (current_init_state == mode_init) begin - if (ext_mode_load_done) begin - current_init_state = mode_done_init ; - end - end - if (current_init_state == ext_mode_init) begin - if (mode_load_done) begin - current_init_state = mode_done_init ; - end - end - if (current_init_state == mode_done_init && aref_count >= 2) begin - power_up_done = 1'b1; - end -end - - task backend_sync; - begin - BEsynco = 1'b1; - wait (BEsynci) BEsynco = 1'b0; - wait (!BEsynci) ; - end - endtask - - - // this task will erase the contents of 0 or more banks - task erase_mem; - input [BA_BITS+1:0] bank_MSB_row; //bank bits + 2 row MSB - input DPD_mode ; //erase all memory locations - integer i,j; - begin - - if (DPD_mode) begin - BEclear = 1'b1; - backend_sync; - BEclear = 1'b0; - backend_sync; - end else begin - for (i={1'b0,bank_MSB_row}+1; i<5'b10000; i=i+1) begin - BEaddr = { i[3:0], {(full_mem_bits-BA_BITS-2){1'b0}} }; - j = full_mem_bits-BA_BITS-2; - BEdin = j[DQ_BITS-1:0]; - BEclrpart = 1'b1; - backend_sync; - BEclrpart = 1'b0; - backend_sync; - end - end // else: !if(DPD_mode) - end - endtask // erase_mem - - // Write Memory - task write_mem; - input [full_mem_bits - 1 : 0] addr; - input [DQ_BITS - 1 : 0] data; - begin - BEaddr = addr; - BEdin = data; - backend_sync; - BEwr = 2'b11; - backend_sync; - BEwr = 2'b00; - backend_sync; - end - endtask // write_mem - - - // Read Memory - task read_mem; - input [full_mem_bits - 1 : 0] addr; - output [DQ_BITS - 1 : 0] data; - begin - BEaddr = addr; - backend_sync; - data = BEdout; - end - endtask - - // Burst Decode - task Burst_Decode; - begin - - // Advance Burst Counter - if (Burst_counter < burst_length) begin - Burst_counter = Burst_counter + 1; - end - - // Burst Type - if (Mode_reg[3] === 1'b0) begin // Sequential Burst - Cols_temp = Cols_addr + 1; - end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst - Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2]; - Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1]; - Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0]; - end - - // Burst Length - if (burst_length === 2) begin - Cols_addr [0] = Cols_temp [0]; - end else if (burst_length === 4) begin - Cols_addr [1 : 0] = Cols_temp [1 : 0]; - end else if (burst_length === 8) begin - Cols_addr [2 : 0] = Cols_temp [2 : 0]; - end else if (burst_length === 16) begin - Cols_addr [3 : 0] = Cols_temp [3 : 0]; - end else begin - Cols_addr = Cols_temp; - end - - // Data Counter - if (Burst_counter >= burst_length) begin - Data_in_enable = 1'b0; - Data_out_enable = 1'b0; - read_precharge_truncation = 1'b0; - //if (SRC_cntr == 2) begin // **** - if (((SRC_cntr == 2) & (Mode_reg[6:4] == 3'b010)) | ((SRC_cntr == 3) & (Mode_reg[6:4] == 3'b011))) begin - SRR_read = 1'b0; - end - end - end - endtask - -// // Burst Decode -// task Burst_Decode; -// begin -// -// // Advance Burst Counter -// if (Burst_counter < burst_length) begin -// Burst_counter = Burst_counter + 1; -// end -// -// // Burst Type -// if (Mode_reg[3] === 1'b0) begin // Sequential Burst -// Cols_temp = Cols_addr + 1; -// end else if (Mode_reg[3] === 1'b1) begin // Interleaved Burst -// Cols_temp[2] = Burst_counter[2] ^ Cols_brst[2]; -// Cols_temp[1] = Burst_counter[1] ^ Cols_brst[1]; -// Cols_temp[0] = Burst_counter[0] ^ Cols_brst[0]; -// end -// -// // Burst Length -// if (burst_length === 2) begin -// Cols_addr [0] = Cols_temp [0]; -// end else if (burst_length === 4) begin -// Cols_addr [1 : 0] = Cols_temp [1 : 0]; -// end else if (burst_length === 8) begin -// Cols_addr [2 : 0] = Cols_temp [2 : 0]; -// end else if (burst_length === 16) begin -// Cols_addr [3 : 0] = Cols_temp [3 : 0]; -// end else begin -// Cols_addr = Cols_temp; -// end -// -// // Data Counter -// if (Burst_counter >= burst_length) begin -// Data_in_enable = 1'b0; -// Data_out_enable = 1'b0; -// read_precharge_truncation = 1'b0; -// SRR_read = 1'b0; -// end -// end -// endtask - - // SRC check - task Timing_chk_SRC; - begin - if (Active_enable || Aref_enable || Sref_enable || Burst_term || - Ext_mode_enable || Mode_reg_enable || Prech_enable || Read_enable || - Write_enable || DPD_enable || PD_enable || srr_enable) begin - if (part_size == 1024) begin - if (SRC_cntr < ((Mode_reg[6:4])+tSRC)) begin - $display ("%m: At time %t ERROR: tSRC Violation", $realtime); - end - end - end - end - endtask - - // Manual Precharge Pipeline - task Manual_Precharge_Pipeline; - begin - // A10 Precharge Pipeline - A10_precharge[0] = A10_precharge[1]; - A10_precharge[1] = A10_precharge[2]; - A10_precharge[2] = A10_precharge[3]; - A10_precharge[3] = A10_precharge[4]; - A10_precharge[4] = A10_precharge[5]; - A10_precharge[5] = A10_precharge[6]; - A10_precharge[6] = 1'b0; - - // Bank Precharge Pipeline - Bank_precharge[0] = Bank_precharge[1]; - Bank_precharge[1] = Bank_precharge[2]; - Bank_precharge[2] = Bank_precharge[3]; - Bank_precharge[3] = Bank_precharge[4]; - Bank_precharge[4] = Bank_precharge[5]; - Bank_precharge[5] = Bank_precharge[6]; - Bank_precharge[6] = 2'b0; - - // Command Precharge Pipeline - Cmnd_precharge[0] = Cmnd_precharge[1]; - Cmnd_precharge[1] = Cmnd_precharge[2]; - Cmnd_precharge[2] = Cmnd_precharge[3]; - Cmnd_precharge[3] = Cmnd_precharge[4]; - Cmnd_precharge[4] = Cmnd_precharge[5]; - Cmnd_precharge[5] = Cmnd_precharge[6]; - Cmnd_precharge[6] = 1'b0; - - // Terminate a Read if same bank or all banks - if (Cmnd_precharge[0] === 1'b1) begin - if (Bank_precharge[0] === Bank_addr || A10_precharge[0] === 1'b1) begin - if (Data_out_enable === 1'b1) begin - Data_out_enable = 1'b0; - read_precharge_truncation = 1'b1; - end - end - end - end - endtask - - // Burst Terminate Pipeline - task Burst_Terminate_Pipeline; - begin - // Command Precharge Pipeline - Cmnd_bst[0] = Cmnd_bst[1]; - Cmnd_bst[1] = Cmnd_bst[2]; - Cmnd_bst[2] = Cmnd_bst[3]; - Cmnd_bst[3] = Cmnd_bst[4]; - Cmnd_bst[4] = Cmnd_bst[5]; - Cmnd_bst[5] = Cmnd_bst[6]; - Cmnd_bst[6] = 1'b0; - - // Terminate a Read regardless of banks - if (Cmnd_bst[0] === 1'b1 && Data_out_enable === 1'b1) begin - Data_out_enable = 1'b0; - end - end - endtask - - // Dq and Dqs Drivers - task Dq_Dqs_Drivers; - begin - // read command pipeline - Read_cmnd [0] = Read_cmnd [1]; - Read_cmnd [1] = Read_cmnd [2]; - Read_cmnd [2] = Read_cmnd [3]; - Read_cmnd [3] = Read_cmnd [4]; - Read_cmnd [4] = Read_cmnd [5]; - Read_cmnd [5] = Read_cmnd [6]; - Read_cmnd [6] = 1'b0; - - // read bank pipeline - Read_bank [0] = Read_bank [1]; - Read_bank [1] = Read_bank [2]; - Read_bank [2] = Read_bank [3]; - Read_bank [3] = Read_bank [4]; - Read_bank [4] = Read_bank [5]; - Read_bank [5] = Read_bank [6]; - Read_bank [6] = 2'b0; - - // read column pipeline - Read_cols [0] = Read_cols [1]; - Read_cols [1] = Read_cols [2]; - Read_cols [2] = Read_cols [3]; - Read_cols [3] = Read_cols [4]; - Read_cols [4] = Read_cols [5]; - Read_cols [5] = Read_cols [6]; - Read_cols [6] = 0; - - // Initialize Read command - if (Read_cmnd [1] === 1'b1) begin - Data_out_enable = 1'b1; - Bank_addr = Read_bank [1]; - Cols_addr = Read_cols [1]; - Cols_brst = Cols_addr [2 : 0]; - if (SRR_read == 1'b1) begin - Burst_counter = burst_length - 2; - end else begin - Burst_counter = 0; - end - - // Row Address Mux - case (Bank_addr) - 2'd0 : Rows_addr = B0_row_addr; - 2'd1 : Rows_addr = B1_row_addr; - 2'd2 : Rows_addr = B2_row_addr; - 2'd3 : Rows_addr = B3_row_addr; - default : $display ("%m: At time %t ERROR: Invalid Bank Address", $realtime); - endcase - end - - // Toggle Dqs during Read command - if (Data_out_enable === 1'b1) begin - Dqs_int = 1'b0; - if (Dqs_gen === {DQS_BITS{1'b0}}) begin - Dqs_gen = {DQS_BITS{1'b1}}; - end else if (Dqs_gen === {DQS_BITS{1'b1}}) begin - Dqs_gen = {DQS_BITS{1'b0}}; - end else if (Dqs_gen === {DQS_BITS{1'b0}}) begin - Dqs_gen = {DQS_BITS{1'b0}}; - end - if (Mode_reg[6:4] == 3'b010) begin - Dqs_out <= #tAC2_max Dqs_gen; - end else if (Mode_reg[6:4] == 3'b011) begin - Dqs_out <= #tAC3_max Dqs_gen; - end - end else if (Data_out_enable === 1'b0 && Dqs_int === 1'b0 && (Dqs_gen !== {DQS_BITS{1'bz}})) begin - Dqs_gen = {DQS_BITS{1'bz}} ; - if (Mode_reg[6:4] == 3'b010) begin - Dqs_out <= #tHZ2_max Dqs_gen; - end else if (Mode_reg[6:4] == 3'b011) begin - Dqs_out <= #tHZ3_max Dqs_gen; - end - end - - // Initialize dqs for Read command - if (Mode_reg[6:4] == 3'b010) begin - if ((Read_enable === 1'b1) && (Sys_clk == 1'b1)) begin - if (Data_out_enable === 1'b0) begin - Dqs_int = 1'b1; - Dqs_gen = {DQS_BITS{1'b0}}; -// Dqs_out <= #2.0 Dqs_gen; // used in place of tLZ for a one clock preamble - Dqs_out <= #tAC2_max Dqs_gen; // used in place of tLZ for a one clock preamble // **** - end - end - end else if (Mode_reg[6:4] == 3'b011) begin - if (Read_cmnd [3] === 1'b1) begin - if (Data_out_enable === 1'b0) begin - Dqs_int = 1'b1; - Dqs_gen = {DQS_BITS{1'b0}}; - Dqs_out <= #tAC3_max Dqs_gen; // used in place of tLZ for a one clock preamble - end - end - end - - // Read latch - if (Data_out_enable === 1'b1) begin - // output data - if (SRR_read == 1'b1) begin - if (Burst_counter == (burst_length-2)) begin - Dq_out <= Srr_reg[DQ_BITS-1:0]; - end else if (Burst_counter == (burst_length-1)) begin - Dq_out <= Srr_reg[2*DQ_BITS-1:DQ_BITS]; - end - end else begin - read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_out); - end - if (Debug) begin - $display ("At time %t %m:READ: Bank = %d, Row = %d, Col = %d, Data = %d", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_out); - end - - end else begin - Dq_out = {DQ_BITS{1'bz}}; - end - end - endtask - - // Write FIFO and DM Mask Logic - task Write_FIFO_DM_Mask_Logic; - begin - // Write command pipeline - Write_cmnd [0] = Write_cmnd [1]; - Write_cmnd [1] = Write_cmnd [2]; - Write_cmnd [2] = Write_cmnd [3]; - Write_cmnd [3] = 1'b0; - - // Write command pipeline - Write_bank [0] = Write_bank [1]; - Write_bank [1] = Write_bank [2]; - Write_bank [2] = Write_bank [3]; - Write_bank [3] = 2'b0; - - // Write column pipeline - Write_cols [0] = Write_cols [1]; - Write_cols [1] = Write_cols [2]; - Write_cols [2] = Write_cols [3]; - Write_cols [3] = {COL_BITS{1'b0}}; - - // Initialize Write command - if (Write_cmnd [0] === 1'b1) begin - Data_in_enable = 1'b1; - Bank_addr = Write_bank [0]; - Cols_addr = Write_cols [0]; - Cols_brst = Cols_addr [2 : 0]; - Burst_counter = 0; - - // Row address mux - case (Bank_addr) - 2'd0 : Rows_addr = B0_row_addr; - 2'd1 : Rows_addr = B1_row_addr; - 2'd2 : Rows_addr = B2_row_addr; - 2'd3 : Rows_addr = B3_row_addr; - default : $display ("%m: At time %t ERROR: Invalid Row Address", $realtime); - endcase - end - - // Write data - if (Data_in_enable === 1'b1) begin - - // Data Buffer - read_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); - - // write negedge Dqs on posedge Sys_clk - if (Sys_clk) begin - if (!dm_fall[0]) begin - Dq_buf [ 7 : 0] = dq_fall [ 7 : 0]; - end - if (!dm_fall[1]) begin - Dq_buf [15 : 8] = dq_fall [15 : 8]; - end - if (!dm_fall[2]) begin - Dq_buf [23 : 16] = dq_fall [23 : 16]; - end - if (!dm_fall[3]) begin - Dq_buf [31 : 24] = dq_fall [31 : 24]; - end - if (~&dm_fall) begin - if (Debug) begin - $display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); - end - end - // write posedge Dqs on negedge Sys_clk - end else begin - if (!dm_rise[0]) begin - Dq_buf [ 7 : 0] = dq_rise [ 7 : 0]; - end - if (!dm_rise[1]) begin - Dq_buf [15 : 8] = dq_rise [15 : 8]; - end - if (!dm_rise[2]) begin - Dq_buf [23 : 16] = dq_rise [23 : 16]; - end - if (!dm_rise[3]) begin - Dq_buf [31 : 24] = dq_rise [31 : 24]; - end - if (~&dm_rise) begin - if (Debug) begin - $display ("At time %t %m:WRITE: Bank = %d, Row = %d, Col = %d, Data = %h", $realtime, Bank_addr, Rows_addr, Cols_addr, Dq_buf[DQ_BITS-1:0]); - end - end - end - - // Write Data - write_mem({Bank_addr, Rows_addr, Cols_addr}, Dq_buf); - - // tWR start and tWTR check - if (Sys_clk && &dm_pair === 1'b0) begin - case (Bank_addr) - 2'd0 : WR_chk0 = $realtime; - 2'd1 : WR_chk1 = $realtime; - 2'd2 : WR_chk2 = $realtime; - 2'd3 : WR_chk3 = $realtime; - default : $display ("%m: At time %t ERROR: Invalid Bank Address (tWR)", $realtime); - endcase - - // tWTR check - if (Read_enable === 1'b1) begin - $display ("%m: At time %t ERROR: tWTR violation during Read", $realtime); - end - end - end - end - endtask - - // Auto Precharge Calculation - task Auto_Precharge_Calculation; - begin - // Precharge counter - if (Read_precharge [0] === 1'b1 || Write_precharge [0] === 1'b1) begin - Count_precharge [0] = Count_precharge [0] + 1; - end - if (Read_precharge [1] === 1'b1 || Write_precharge [1] === 1'b1) begin - Count_precharge [1] = Count_precharge [1] + 1; - end - if (Read_precharge [2] === 1'b1 || Write_precharge [2] === 1'b1) begin - Count_precharge [2] = Count_precharge [2] + 1; - end - if (Read_precharge [3] === 1'b1 || Write_precharge [3] === 1'b1) begin - Count_precharge [3] = Count_precharge [3] + 1; - end - - // Read with AutoPrecharge Calculation - // The device start internal precharge when: - // 1. Meet tRAS requirement - // 2. BL/2 cycles after command - if ((Read_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin - if (Count_precharge[0] >= burst_length/2) begin - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - RP_chk0 = $realtime; - Read_precharge[0] = 1'b0; - end - end - if ((Read_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin - if (Count_precharge[1] >= burst_length/2) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - RP_chk1 = $realtime; - Read_precharge[1] = 1'b0; - end - end - if ((Read_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin - if (Count_precharge[2] >= burst_length/2) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - RP_chk2 = $realtime; - Read_precharge[2] = 1'b0; - end - end - if ((Read_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin - if (Count_precharge[3] >= burst_length/2) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - RP_chk3 = $realtime; - Read_precharge[3] = 1'b0; - end - end - - // Write with AutoPrecharge Calculation - // The device start internal precharge when: - // 1. Meet tRAS requirement - // 2. Two clock after last burst - // Since tWR is time base, the model will compensate tRP - if ((Write_precharge[0] === 1'b1) && ($realtime - RAS_chk0 >= tRAS)) begin - if (Count_precharge[0] >= burst_length/2+3) begin - Pc_b0 = 1'b1; - Act_b0 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk0 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk0 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[0] = 1'b0; - end - end - if ((Write_precharge[1] === 1'b1) && ($realtime - RAS_chk1 >= tRAS)) begin - if (Count_precharge[1] >= burst_length/2+3) begin - Pc_b1 = 1'b1; - Act_b1 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk1 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk1 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[1] = 1'b0; - end - end - if ((Write_precharge[2] === 1'b1) && ($realtime - RAS_chk2 >= tRAS)) begin - if (Count_precharge[2] >= burst_length/2+3) begin - Pc_b2 = 1'b1; - Act_b2 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk2 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk2 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[2] = 1'b0; - end - end - if ((Write_precharge[3] === 1'b1) && ($realtime - RAS_chk3 >= tRAS)) begin - if (Count_precharge[3] >= burst_length/2+3) begin - Pc_b3 = 1'b1; - Act_b3 = 1'b0; - if (Mode_reg[6:4] == 3'b011) begin - RP_chk3 = $realtime - ((2 * tCK3_min) - tWR); - end - if (Mode_reg[6:4] == 3'b010) begin - RP_chk3 = $realtime - ((2 * tCK2_min) - tWR); - end - Write_precharge[3] = 1'b0; - end - end - end - endtask - - task Power_down_chk; - begin - if (DPD_enable == 1'b1 && enter_DPD == 1'b0) begin - if (prev_cke & Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin - erase_mem(4'b0000, 1'b1); - current_init_state = begin_init ; - ext_mode_load_done = 1'b0 ; - mode_load_done = 1'b0 ; - enter_DPD = 1'b1; - $display ("%m: at time %t Entering Deep Power-Down Mode", $realtime); - end - end - if (enter_DPD == 1'b1) begin - if (Cke == 1'b1 && prev_cke == 1'b0) begin - if (PD_cntr < tCKE) begin - $display ("%m: At time %t ERROR: tCKE violation during exiting of Deep Power-Down Mode", $realtime); - end - $display ("%m: at time %t Exiting Deep Power-Down Mode - A 200 us delay is required with either DESELECT or NOP commands present before the initialization sequence may begin", $realtime); - enter_DPD = 1'b0; - end - end - if (PD_enable == 1'b1 && enter_PD == 1'b0) begin - if (prev_cke) begin - if (Pc_b0 & Pc_b1 & Pc_b2 & Pc_b3) begin - $display ("%m: at time %t Entering Power-Down Mode", $realtime); - enter_PD = 1'b1; - end else if (~Pc_b0 | ~Pc_b1 | ~Pc_b2 | ~Pc_b3) begin - $display ("%m: at time %t Entering Active Power-Down Mode", $realtime); - enter_APD = 1'b1; - end - end - end - if (enter_PD == 1'b1 || enter_APD == 1'b1) begin - if (Cke == 1'b1 && prev_cke == 1'b0) begin - if (PD_cntr < tCKE) begin - if (enter_PD == 1'b1) begin - $display ("%m: At time %t ERROR: tCKE violation during exiting of Power-Down Mode", $realtime); - end else if (enter_APD == 1'b1) begin - $display ("%m: At time %t ERROR: tCKE violation during exiting of Active Power-Down Mode", $realtime); - end - end - if (enter_PD == 1'b1) begin - $display ("%m: at time %t Exiting Power-Down Mode", $realtime); - enter_PD = 1'b0 ; - end else if (enter_APD == 1'b1) begin - $display ("%m: at time %t Exiting Active Power-Down Mode", $realtime); - enter_APD = 1'b0 ; - end - end - end - - end - endtask - - // Control Logic - task Control_Logic; - begin - - // Self Refresh - if (Sref_enable === 1'b1) begin - // Partial Array Self Refresh - if (part_size == 128) begin - case (Ext_Mode_reg[2:0]) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end - 3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end - 3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b101 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b110 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - endcase - end else begin - case (Ext_Mode_reg[2:0]) - 3'b000 : ;//keep Bank 0-7 - 3'b001 : begin $display("%m: at time %t INFO: Banks 2-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0111, 1'b0); end - 3'b010 : begin $display("%m: at time %t INFO: Banks 1-3 will be lost due to Partial Array Self Refresh", $realtime) ; erase_mem(4'b0011, 1'b0); end - 3'b011 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b100 : begin $display("%m: at time %t INFO: Reserved", $realtime) ; end - 3'b101 : begin $display("%m: at time %t INFO: Banks 1-3 and 1/2 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0001, 1'b0); end - 3'b110 : begin $display("%m: at time %t INFO: Banks 1-3 and 3/4 of bank 0 will be lost due to Partial Array Self Refresh", $realtime); erase_mem(4'b0000, 1'b0); end - endcase - end - SelfRefresh = 1'b1; - end - if (Aref_enable === 1'b1) begin - if (Debug) begin - $display ("Debug: At time %t %m:AUTOREFRESH: Auto Refresh", $realtime); - end - // aref_count is to make sure we have met part of the initialization sequence - if (~power_up_done) begin - aref_count = aref_count + 1; - end - - // Auto Refresh to Auto Refresh - if ($realtime - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Auto Refresh", $realtime); - end - - // Precharge to Auto Refresh - if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) || - ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Auto Refresh", $realtime); - end - - // Precharge to Auto Refresh - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: All banks must be Precharged before Auto Refresh", $realtime); - end - - // Record Current tRFC time - RFC_chk = $realtime; - end - - // SRR Register - if (srr_enable == 1'b1) begin - if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1 && - Data_out_enable === 1'b0 && Data_in_enable === 1'b0) begin - SRR_read = 1'b1; - SRR_chk = $realtime; - SRR_cntr = 0; - end - end - - - // Extended Mode Register - if (Ext_mode_enable == 1'b1) begin - if (Debug) begin - $display ("Debug: At time %t %m:EMR : Extended Mode Register", $realtime); - end - - // Register Mode - Ext_Mode_reg = Addr; - - if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin - // ensure that power sequence is met properly - if (~power_up_done) begin - ext_mode_load_done = 1'b1; - end - $display ("At time %t %m:ELMR : Extended Load Mode Register", $realtime); - if (part_size == 128) begin - // Self Refresh Coverage - case (Addr[2 : 0]) - 3'b000 : $display ("%m : Self Refresh Cov = 4 banks"); - 3'b001 : $display ("%m : Self Refresh Cov = 2 banks"); - 3'b010 : $display ("%m : Self Refresh Cov = 1 bank"); - 3'b101 : $display ("%m : PASR = Reserved"); - 3'b110 : $display ("%m : PASR = Reserved"); - default : $display ("%m : PASR = Reserved"); - endcase - end else begin - // Self Refresh Coverage - case (Addr[2 : 0]) - 3'b000 : $display ("%m : Self Refresh Cov = 4 banks"); - 3'b001 : $display ("%m : Self Refresh Cov = 2 banks"); - 3'b010 : $display ("%m : Self Refresh Cov = 1 bank"); - 3'b101 : $display ("%m : Self Refresh Cov = 1/2 bank"); - 3'b110 : $display ("%m : Self Refresh Cov = 1/4 bank"); - default : $display ("%m : PASR = Reserved"); - endcase - end - // Maximum Case Temp - case (Addr[4 : 3]) - 2'b11 : $display ("%m : Maximum Case Temp = 85C"); - 2'b00 : $display ("%m : Maximum Case Temp = 70C"); - 2'b01 : $display ("%m : Maximum Case Temp = 45C"); - 2'b10 : $display ("%m : Maximum Case Temp = 15C"); - endcase - - // Drive Strength - case (Addr[6 : 5]) - 2'b00 : $display ("%m : Drive Strength = Full Strength"); - 2'b01 : $display ("%m : Drive Strength = Half Strength"); - 2'b10 : $display ("%m : Drive Strength = Quarter Strength"); - 2'b11 : $display ("%m : Drive Strength = One Eight Strength"); - endcase - - end else begin - $display ("%m: At time %t ERROR: all banks must be Precharged before Extended Mode Register", $realtime); - end - - // Precharge to EMR - if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) || - ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Extended Mode Register", $realtime); - end - - // LMR/EMR to LMR/EMR -// if ($realtime - MRD_chk < tMRD) begin -// $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime); -// end - - if (MRD_cntr < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Extended Mode Register", $realtime); - end - - // Record current tMRD time -// MRD_chk = $realtime; - MRD_cntr = 0; - end - - // Load Mode Register - if (Mode_reg_enable === 1'b1) begin - if (Debug) begin - $display ("Debug: At time %t %m:LMR : Load Mode Register", $realtime); - end - - // Register Mode - Mode_reg = Addr; - - if (Mode_reg[6:4] == 3'b010) begin - if (tCK2_min == 0) begin - $display ("%m : at time %t ERROR : Illegal CAS Latency of 2 set for current speed grade", $realtime); - end - end - - // Precharge to LMR - if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin - $display ("%m: At time %t ERROR: all banks must be Precharged before Load Mode Register", $realtime); - end - - // Precharge to LMR - if (($realtime - RP_chk0 < tRP) || ($realtime - RP_chk1 < tRP) || - ($realtime - RP_chk2 < tRP) || ($realtime - RP_chk3 < tRP)) begin - $display ("%m: At time %t ERROR: tRP violation during Load Mode Register", $realtime); - end - - // LMR/EMR to LMR/EMR -// if ($realtime - MRD_chk < tMRD) begin -// $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime); -// end - if (MRD_cntr < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Load Mode Register", $realtime); - end - - if (Pc_b0 === 1'b1 && Pc_b1 === 1'b1 && Pc_b2 === 1'b1 && Pc_b3 === 1'b1) begin - // ensure that power sequence is met properly - if (~power_up_done) begin - mode_load_done = 1'b1; - end - // Burst Length - case (Addr [2 : 0]) - 3'b001 : $display ("At time %t %m:LMR : Burst Length = 2", $realtime); - 3'b010 : $display ("At time %t %m:LMR : Burst Length = 4", $realtime); - 3'b011 : $display ("At time %t %m:LMR : Burst Length = 8", $realtime); - default : - begin - $display ("%m: At time %t ERROR: Undefined burst length selection", $realtime); - $stop; - end - endcase - - // CAS Latency - case (Addr [6 : 4]) - 3'b010 : $display ("At time %t %m:LMR : CAS Latency = 2", $realtime); - 3'b011 : $display ("At time %t %m:LMR : CAS Latency = 3", $realtime); - default : begin - $display ("%m: At time %t ERROR: CAS Latency not supported", $realtime); - $stop; - end - endcase - - end - // Record current tMRD time -// MRD_chk = $realtime; - MRD_cntr = 0; - end - - // Activate Block - if (Active_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Activate command", $realtime); - end - // Display Debug Message - if (Debug) begin - $display ("Debug: At time %t %m:ACTIVATE: Bank = %d, Row = %d", $realtime, Ba, Addr); - end - - // Activating an open bank can cause corruption. - if ((Ba === 2'b00 && Pc_b0 === 1'b0) || (Ba === 2'b01 && Pc_b1 === 1'b0) || - (Ba === 2'b10 && Pc_b2 === 1'b0) || (Ba === 2'b11 && Pc_b3 === 1'b0)) begin - $display ("%m: At time %t ERROR: Bank = %d is already activated - data can be corrupted", $realtime, Ba); - end - - // Activate Bank 0 - if (Ba === 2'b00 && Pc_b0 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk0 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk0 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b0 = 1'b1; - Pc_b0 = 1'b0; - B0_row_addr = Addr; - RC_chk0 = $realtime; - RCD_chk0 = $realtime; - RAS_chk0 = $realtime; - RAP_chk0 = $realtime; - end - - // Activate Bank 1 - if (Ba === 2'b01 && Pc_b1 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk1 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk1 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b1 = 1'b1; - Pc_b1 = 1'b0; - B1_row_addr = Addr; - RC_chk1 = $realtime; - RCD_chk1 = $realtime; - RAS_chk1 = $realtime; - RAP_chk1 = $realtime; - end - - // Activate Bank 2 - if (Ba === 2'b10 && Pc_b2 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk2 < tRC) begin - $display ("%m: At time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk2 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b2 = 1'b1; - Pc_b2 = 1'b0; - B2_row_addr = Addr; - RC_chk2 = $realtime; - RCD_chk2 = $realtime; - RAS_chk2 = $realtime; - RAP_chk2 = $realtime; - end - - // Activate Bank 3 - if (Ba === 2'b11 && Pc_b3 === 1'b1) begin - // Activate to Activate (same bank) - if ($realtime - RC_chk3 < tRC) begin - $display ("%m: t time %t ERROR: tRC violation during Activate bank %d", $realtime, Ba); - end - - // Precharge to Activate - if ($realtime - RP_chk3 < tRP) begin - $display ("%m: At time %t ERROR: tRP violation during Activate bank %d", $realtime, Ba); - end - - // Record variables for checking violation - Act_b3 = 1'b1; - Pc_b3 = 1'b0; - B3_row_addr = Addr; - RC_chk3 = $realtime; - RCD_chk3 = $realtime; - RAS_chk3 = $realtime; - RAP_chk3 = $realtime; - end - - // Activate to Activate (different bank) - if ((Prev_bank != Ba) && ($realtime - RRD_chk < tRRD)) begin - $display ("%m: At time %t ERROR: tRRD violation during Activate bank = %d", $realtime, Ba); - end - - // AutoRefresh to Activate - if ($realtime - RFC_chk < tRFC) begin - $display ("%m: At time %t ERROR: tRFC violation during Activate bank %d", $realtime, Ba); - end - - // Record variable for checking violation - RRD_chk = $realtime; - Prev_bank = Ba; - end - - // Precharge Block - consider NOP if bank already precharged or in process of precharging - if (Prech_enable === 1'b1) begin - // Display Debug Message - if (Debug) begin - $display ("Debug: At time %t %m:PRE: Addr[10] = %b, Bank = %b", $realtime, Addr[10], Ba); - end - - // EMR or LMR to Precharge -// if ($realtime - MRD_chk < tMRD) begin -// $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime); -// end - if (MRD_cntr < tMRD) begin - $display ("%m: At time %t ERROR: tMRD violation during Precharge", $realtime); - end - - // Precharge bank 0 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin - Act_b0 = 1'b0; - Pc_b0 = 1'b1; - RP_chk0 = $realtime; - - // Activate to Precharge Bank - if ($realtime - RAS_chk0 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk0 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Precharge bank 1 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin - Act_b1 = 1'b0; - Pc_b1 = 1'b1; - RP_chk1 = $realtime; - - // Activate to Precharge Bank 1 - if ($realtime - RAS_chk1 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk1 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Precharge bank 2 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin - Act_b2 = 1'b0; - Pc_b2 = 1'b1; - RP_chk2 = $realtime; - - // Activate to Precharge Bank 2 - if ($realtime - RAS_chk2 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk2 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Precharge bank 3 - if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin - Act_b3 = 1'b0; - Pc_b3 = 1'b1; - RP_chk3 = $realtime; - - // Activate to Precharge Bank 3 - if ($realtime - RAS_chk3 < tRAS) begin - $display ("%m: At time %t ERROR: tRAS violation during Precharge", $realtime); - end - - // tWR violation check for Write - if ($realtime - WR_chk3 < tWR) begin - $display ("%m: At time %t ERROR: tWR violation during Precharge", $realtime); - end - end - - // Pipeline for READ - A10_precharge [cas_latency_x2] = Addr[10]; - Bank_precharge[cas_latency_x2] = Ba; - Cmnd_precharge[cas_latency_x2] = 1'b1; - end - - // Burst terminate - if (Burst_term === 1'b1) begin - // Display Debug Message - if (Debug) begin - $display ("Debug: %m: At time %t BURST_TERMINATE): Burst Terminate",$realtime); - end - - // Burst Terminate Command Pipeline for Read - Cmnd_bst[cas_latency_x2-1] = 1'b1; - - // Illegal to burst terminate a Write - if (Data_in_enable === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to burst terminate a Write", $realtime); - end - - // Illegal to burst terminate a Read with Auto Precharge - if (Read_precharge[0] === 1'b1 || Read_precharge[1] === 1'b1 || - Read_precharge[2] === 1'b1 || Read_precharge[3] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to burst terminate a Read with Auto Precharge", $realtime); - end - end - - // Read Command - if (Read_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Read Command", $realtime); - end - // Display Debug Message - if (Debug) begin - $display ("Debug: At time %t %m:READ: Bank = %d, Col = %d", $realtime, Ba, {Addr [11], Addr [9 : 0]}); - end - if (part_size == 1024) begin - if (SRR_read == 1'b1) begin - if (SRR_cntr < tSRR) begin - $display ("%m: At time %t ERROR: tSRR Violation", $realtime); - end - SRC_cntr = 0 ; - end - end else begin - if (SRR_read == 1'b1) begin - if ($realtime - SRR_chk < tSRR-0.01) begin - $display ("%m: At time %t ERROR: tSRR Violation", $realtime); - end - SRC_cntr = 0; - end - end - // CAS Latency pipeline - Read_cmnd[cas_latency_x2] = 1'b1; - Read_bank[cas_latency_x2] = Ba; - Read_cols[cas_latency_x2] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - - // Terminate a Write - if (Data_in_enable === 1'b1) begin - Data_in_enable = 1'b0; - end - - // Interrupt a Read with Auto Precharge - if (Read_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime); - end else if ((Read_precharge [0] === 1'b1) | - (Read_precharge [1] === 1'b1) | - (Read_precharge [2] === 1'b1) | - (Read_precharge [3] === 1'b1) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (different banks)", $realtime); - end - - // Interrupt a Write with Auto Precharge - if (Write_precharge [Ba] === 1'b1) begin -// $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same banks)", $realtime); - end else if ((Write_precharge_count [0] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [1] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [2] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [3] < (burst_length/2 )) & (Mode_reg[6:4] == 3'b010) | - (Write_precharge_count [0] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) | - (Write_precharge_count [1] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) | - (Write_precharge_count [2] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) | - (Write_precharge_count [3] < (burst_length/2-1)) & (Mode_reg[6:4] == 3'b011) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Write with Auto Precharge (different banks)", $realtime); - end - - // Activate to Read - if (((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) && - (SRR_read == 1'b0)) begin - $display("%m: At time %t ERROR: Bank is not Activated for Read", $realtime); - end - - // Activate to Read without Auto Precharge - if ((Addr [10] === 1'b0 && Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) || - (Addr [10] === 1'b0 && Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin - $display("%m: At time %t ERROR: tRCD violation during Read", $realtime); - end - - // Auto Precharge - if (Addr[10] === 1'b1) begin - Read_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - Read_precharge_count[Ba] = 4'h0; - end - end - - // Write Command - if (Write_enable === 1'b1) begin - if (!(power_up_done)) begin - $display ("%m: At time %t ERROR: Power Up and Initialization Sequence not completed before executing Write Command", $realtime); - end - // display debug message - if (Debug) begin - $display ("Debug: At time %t %m:WRITE: Bank = %d, Col = %d", $realtime, Ba, {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}); - end - - // Pipeline for Write - Write_cmnd [3] = 1'b1; - Write_bank [3] = Ba; - Write_cols [3] = {Addr [ADDR_BITS - 1 : 11], Addr [9 : 0]}; - - // Interrupt a Write with Auto Precharge (same bank only) - if (Write_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge", $realtime); - end - - // Activate to Write - if ((Ba === 2'b00 && Pc_b0 === 1'b1) || (Ba === 2'b01 && Pc_b1 === 1'b1) || - (Ba === 2'b10 && Pc_b2 === 1'b1) || (Ba === 2'b11 && Pc_b3 === 1'b1)) begin - $display("%m: At time %t ERROR: Bank is not Activated for Write", $realtime); - end - - // Activate to Write - if ((Ba === 2'b00 && $realtime - RCD_chk0 < tRCD) || - (Ba === 2'b01 && $realtime - RCD_chk1 < tRCD) || - (Ba === 2'b10 && $realtime - RCD_chk2 < tRCD) || - (Ba === 2'b11 && $realtime - RCD_chk3 < tRCD)) begin - $display("%m: At time %t ERROR: tRCD violation during Write to Bank %d", $realtime, Ba); - end - - // Read to Write - if (Read_cmnd[0] || Read_cmnd[1] || Read_cmnd[2] || Read_cmnd[3] || - Read_cmnd[4] || Read_cmnd[5] || Read_cmnd[6] || (Burst_counter_dly < burst_length)) begin - if (Data_out_enable_dly || read_precharge_truncation) begin - $display("%m: At time %t ERROR: Read to Write violation", $realtime); - end - end - - // Interrupt a Write with Auto Precharge - if (Write_precharge [Ba] === 1'b1) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (same bank)", $realtime); - end else if (((Write_precharge [0] === 1'b1) & (Count_precharge[0] < (burst_length/2))) | - ((Write_precharge [1] === 1'b1) & (Count_precharge[1] < (burst_length/2))) | - ((Write_precharge [2] === 1'b1) & (Count_precharge[2] < (burst_length/2))) | - ((Write_precharge [3] === 1'b1) & (Count_precharge[3] < (burst_length/2))) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a Write with Auto Precharge (different bank)", $realtime); - end - - // Interrupt a Read with Auto Precharge - if (((Read_precharge_count [Ba] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [Ba] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin -// $display ("%m: At time %t ERROR: It's illegal to interrupt a Read with Auto Precharge (same bank)", $realtime); - end else if (((Read_precharge_count [0] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [1] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [2] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [3] < (4'h2 + (burst_length/2))) & (Mode_reg[6:4] == 3'b010)) | - ((Read_precharge_count [0] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) | - ((Read_precharge_count [1] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) | - ((Read_precharge_count [2] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) | - ((Read_precharge_count [3] < (4'h3 + (burst_length/2))) & (Mode_reg[6:4] == 3'b011)) ) begin - $display ("%m: At time %t ERROR: It's illegal to interrupt a data transfer on a Read with Auto Precharge (different bank)", $realtime); - end - - // Auto Precharge - if (Addr[10] === 1'b1) begin - Write_precharge [Ba]= 1'b1; - Count_precharge [Ba]= 0; - Write_precharge_count[Ba] = 4'h0; - end - end - - end - endtask - - // Main Logic - always @ (posedge Sys_clk) begin - Manual_Precharge_Pipeline; - Burst_Terminate_Pipeline; - Dq_Dqs_Drivers; - Write_FIFO_DM_Mask_Logic; - Burst_Decode; - Auto_Precharge_Calculation; - Timing_chk_SRC; - Control_Logic; - MRD_counter; - SRR_counter; - SRC_counter; - command_counter; - end - - always @ (negedge Sys_clk) begin - Manual_Precharge_Pipeline; - Burst_Terminate_Pipeline; - Dq_Dqs_Drivers; - Write_FIFO_DM_Mask_Logic; - Burst_Decode; - end - - // Dqs Receiver - always @ (posedge Dqs_in[0]) begin - // Latch data at posedge Dqs - dq_rise[7 : 0] = Dq_in[7 : 0]; - dm_rise[0] = Dm_in[0]; - expect_pos_dqs[0] = 0; - end - - always @ (posedge Dqs_in[1]) begin - // Latch data at posedge Dqs - dq_rise[15 : 8] = Dq_in[15 : 8]; - dm_rise[1] = Dm_in [1]; - expect_pos_dqs[1] = 0; - end - -`ifdef x32 - always @ (posedge Dqs_in[2]) begin - // Latch data at posedge Dqs - dq_rise[23 : 16] = Dq_in[23 : 16]; - dm_rise[2] = Dm_in [2]; - expect_pos_dqs[2] = 0; - end - - always @ (posedge Dqs_in[3]) begin - // Latch data at posedge Dqs - dq_rise[31 : 24] = Dq_in[31 : 24]; - dm_rise[3] = Dm_in [3]; - expect_pos_dqs[3] = 0; - end -`endif - - always @ (negedge Dqs_in[0]) begin - // Latch data at negedge Dqs - dq_fall[7 : 0] = Dq_in[7 : 0]; - dm_fall[0] = Dm_in[0]; - dm_pair[1:0] = {dm_rise[0], dm_fall[0]}; - expect_neg_dqs[0] = 0; - end - - always @ (negedge Dqs_in[1]) begin - // Latch data at negedge Dqs - dq_fall[15: 8] = Dq_in[15 : 8]; - dm_fall[1] = Dm_in[1]; - dm_pair[3:2] = {dm_rise[1], dm_fall[1]}; - expect_neg_dqs[1] = 0; - end - -`ifdef x32 - always @ (negedge Dqs_in[2]) begin - // Latch data at negedge Dqs - dq_fall[23: 16] = Dq_in[23 : 16]; - dm_fall[2] = Dm_in[2]; - dm_pair[5:4] = {dm_rise[2], dm_fall[2]}; - expect_neg_dqs[2] = 0; - end - - always @ (negedge Dqs_in[3]) begin - // Latch data at negedge Dqs - dq_fall[31: 24] = Dq_in[31 : 24]; - dm_fall[3] = Dm_in[3]; - dm_pair[7:6] = {dm_rise[3], dm_fall[3]}; - expect_neg_dqs[3] = 0; - end -`endif - - // Dqs edge checking - always @ (posedge Sys_clk) begin - if (Write_cmnd[2] || Write_cmnd[1] || Data_in_enable) begin - for (i=0; i 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (cols_bits-1 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- Load and Dumb variables - FILE file_load : TEXT open read_mode is fname; -- Data load - FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump - VARIABLE Bank_Load : std_logic_vector ( 1 DOWNTO 0); - VARIABLE Rows_Load : std_logic_vector (addr_bits-1 DOWNTO 0); - VARIABLE Cols_Load : std_logic_vector ( cols_bits-1 DOWNTO 0); - VARIABLE Data_Load : std_logic_vector (15 DOWNTO 0); - VARIABLE i, j : INTEGER; - VARIABLE good_load : BOOLEAN; - VARIABLE l : LINE; - variable file_loaded : boolean := false; - variable dump : std_logic := '0'; - variable ch : character; - variable rectype : std_logic_vector(3 downto 0); - variable recaddr : std_logic_vector(31 downto 0); - variable reclen : std_logic_vector(7 downto 0); - variable recdata : std_logic_vector(0 to 16*8-1); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF conv_integer(Burst_counter) >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF conv_integer(Burst_counter) >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF conv_integer(Burst_counter) >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) or (not chktiming) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) or (not chktiming) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) or (not chktiming) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) or (not chktiming) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) or (not chktiming) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) or (not chktiming) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) or (not chktiming) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) or (not chktiming) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) or (not chktiming) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) or (not chktiming) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) or (not chktiming) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) or (not chktiming) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) or (not chktiming) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) or (not chktiming) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) or (not chktiming) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) or (not chktiming) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) or (not chktiming) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) or (not chktiming) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) or (not chktiming) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) or (not chktiming) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) or (not chktiming) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) or (not chktiming) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) or (not chktiming) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) or (not chktiming) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) or (not chktiming) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (cols_bits-1 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (cols_bits-1 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (cols_bits-1 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (cols_bits-1 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (cols_bits-1 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) or (not chktiming) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) or (not chktiming) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (cols_bits-1 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) or (not chktiming) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - - IF (now >= (fdelay * 1 us)) and not file_loaded THEN --' - file_loaded := true; - WHILE NOT endfile(file_load) LOOP - readline(file_load, l); - read(l, ch); - if (ch /= 'S') or (ch /= 's') then - hread(l, rectype); - hread(l, reclen); - recaddr := (others => '0'); - case rectype is - when "0001" => - hread(l, recaddr(15 downto 0)); - when "0010" => - hread(l, recaddr(23 downto 0)); - when "0011" => - hread(l, recaddr); - when "0111" => - hread(l, recaddr); --- if (index = 0) then print("Start address : " & tost(recaddr)); end if; - next; - when others => next; - end case; - case bbits is - when 64 => -- 64-bit bank with four 16-bit DDRs - recaddr(31 downto 18+cols_bits) := (others => '0'); - hread(l, recdata); - Bank_Load := recaddr(17+cols_bits downto 16+cols_bits); - Rows_Load := recaddr(15+cols_bits downto 3+cols_bits); - Cols_Load := recaddr(2+cols_bits downto 3); - Init_mem (Bank_Load, To_Integer(Rows_Load)); - IF Bank_Load = "00" THEN - for i in 0 to 1 loop - Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); - end loop; - ELSIF Bank_Load = "01" THEN - for i in 0 to 1 loop - Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); - end loop; - ELSIF Bank_Load = "10" THEN - for i in 0 to 1 loop - Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); - end loop; - ELSIF Bank_Load = "11" THEN - for i in 0 to 1 loop - Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*64+index*16 to i*64+index*16+15)); - end loop; - END IF; - - when 32 => -- 32-bit bank with two 16-bit DDRs - recaddr(31 downto 17+cols_bits) := (others => '0'); - hread(l, recdata); - Bank_Load := recaddr(16+cols_bits downto 15+cols_bits); - Rows_Load := recaddr(14+cols_bits downto 2+cols_bits); - Cols_Load := recaddr(1+cols_bits downto 2); - Init_mem (Bank_Load, To_Integer(Rows_Load)); - - IF Bank_Load = "00" THEN - for i in 0 to 3 loop - Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); - end loop; - ELSIF Bank_Load = "01" THEN - for i in 0 to 3 loop - Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); - end loop; - ELSIF Bank_Load = "10" THEN - for i in 0 to 3 loop - Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); - end loop; - ELSIF Bank_Load = "11" THEN - for i in 0 to 3 loop - Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*32+index*16 to i*32+index*16+15)); - end loop; - END IF; - - when others => -- 16-bit bank with one 16-bit DDR - hread(l, recdata); - recaddr(31 downto 16+cols_bits) := (others => '0'); - Bank_Load := recaddr(15+cols_bits downto 14+cols_bits); - Rows_Load := recaddr(13+cols_bits downto 1+cols_bits); - Cols_Load := recaddr(cols_bits downto 1); - Init_mem (Bank_Load, To_Integer(Rows_Load)); - - IF Bank_Load = "00" THEN - for i in 0 to 3 loop - Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); - Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); - end loop; - ELSIF Bank_Load = "01" THEN - for i in 0 to 3 loop - Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); - Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); - end loop; - ELSIF Bank_Load = "10" THEN - for i in 0 to 3 loop - Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); - Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); - end loop; - ELSIF Bank_Load = "11" THEN - for i in 0 to 3 loop - Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := (recdata(i*16 to i*16+15)); - Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i+4) := (recdata((i+4)*16 to (i+4)*16+15)); - end loop; - END IF; - - END case; - END IF; - END LOOP; - END IF; - - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) or (not chktiming) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) or (not chktiming) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) or (not chktiming) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) or (not chktiming) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) or (not chktiming) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) or (not chktiming) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) or (not chktiming) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) or (not chktiming) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) or (not chktiming) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) or (not chktiming) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) or (not chktiming) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) or (not chktiming) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) or (not chktiming) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) or (not chktiming) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/micron/ddr_sdram/vhdlsim.txt b/lib/micron/ddr_sdram/vhdlsim.txt deleted file mode 100644 index 6d037bcc..00000000 --- a/lib/micron/ddr_sdram/vhdlsim.txt +++ /dev/null @@ -1,4 +0,0 @@ -mt46v16m16.vhd -mobile_ddr_febe.vhd -mobile_ddr2_febe.vhd - diff --git a/lib/micron/ddr_sdram/vlogsim.txt b/lib/micron/ddr_sdram/vlogsim.txt deleted file mode 100644 index eaa235f6..00000000 --- a/lib/micron/ddr_sdram/vlogsim.txt +++ /dev/null @@ -1,9 +0,0 @@ -ddr256m32x8.v -ddr.v -ddr2.v -mobile_ddr.v -HYx18M256xxxCx.v -ddr3.v -mobile_ddr_fe.v -ddr3_model.v -mobile_ddr2_fe.v diff --git a/lib/openchip/charlcd/apbcharlcd.vhd b/lib/openchip/charlcd/apbcharlcd.vhd deleted file mode 100644 index dd3a4959..00000000 --- a/lib/openchip/charlcd/apbcharlcd.vhd +++ /dev/null @@ -1,140 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2004 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- Entity: charlcd --- File: apbcharlcd.vhd --- Author: Antti Lukats, OpenChip --- Description: Character LCD --- ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; - -library openchip; -use openchip.charlcd.all; - ---pragma translate_off -use std.textio.all; ---pragma translate_on - -entity apbcharlcd is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - lcdi : in charlcd_in_type; - lcdo : out charlcd_out_type); -end; - -architecture rtl of apbcharlcd is - -constant REVISION : integer := 0; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBCHARLCD, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); - -type charlcdregs is record - outreg : std_logic_vector(31 downto 0); -- Output Latch Data/Control - inreg : std_logic_vector(7 downto 0); -- Input Latch, not used - irq : std_ulogic; -- interrupt (internal), not used -end record; - -signal r, rin : charlcdregs; - -begin - - comb : process(rst, r, apbi, lcdi ) - - variable rdata : std_logic_vector(31 downto 0); - variable irq : std_logic_vector(NAHBIRQ-1 downto 0); - variable v : charlcdregs; - - begin - v := r; - v.inreg := lcdi.d_in; - - irq := (others => '0'); - --irq(pirq) := r.irq; - v.irq := '0'; - rdata := (others => '0'); - --- read/write registers - - case apbi.paddr(3 downto 2) is - when "00" => - rdata(31 downto 0) := r.outreg; -- read Control Reg - when "01" => - rdata(7 downto 0) := r.inreg; -- read back if bidir? - when others => - end case; - - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(3 downto 2) is - when "00" => - v.outreg := apbi.pwdata(31 downto 0); - when others => - end case; - end if; - --- reset operation - - if rst = '0' then - v.outreg := (others => '0'); - end if; - --- update registers - - rin <= v; - --- drive outputs - - lcdo.d_out <= r.outreg(7 downto 0); - lcdo.en <= r.outreg(11 downto 8); - lcdo.rs <= r.outreg(12); - lcdo.r_wn <= r.outreg(13); - lcdo.backlight_en <= r.outreg(14); - lcdo.d_out_oe <= r.outreg(15); - - apbo.prdata <= rdata; - apbo.pirq <= irq; - apbo.pindex <= pindex; - - end process; - - apbo.pconfig <= pconfig; - - regs : process(clk) - begin - if rising_edge(clk) then - r <= rin; - end if; - end process; - --- pragma translate_off - bootmsg : report_version - generic map ("apbcharlcd" & tost(pindex) & - ": Character LCD rev " & tost(REVISION) & ", irq " & tost(pirq)); --- pragma translate_on - -end; diff --git a/lib/openchip/charlcd/charlcd.vhd b/lib/openchip/charlcd/charlcd.vhd deleted file mode 100644 index d31291b8..00000000 --- a/lib/openchip/charlcd/charlcd.vhd +++ /dev/null @@ -1,55 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2004 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- package: charlcd --- File: charlcd.vhd --- Author: Antti Lukats, OpenChip --- Description: Character LCD types and components ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; - -package charlcd is - -type charlcd_in_type is record - d_in : std_logic_vector(7 downto 0); -end record; - -type charlcd_out_type is record - d_out : std_logic_vector(7 downto 0); - d_out_oe : std_logic; - en : std_logic_vector(3 downto 0); - rs : std_logic; - r_wn : std_logic; - backlight_en : std_logic; - -end record; - -component apbcharlcd - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - lcdi : in charlcd_in_type; - lcdo : out charlcd_out_type); -end component; - -end; diff --git a/lib/openchip/charlcd/vhdlsyn.txt b/lib/openchip/charlcd/vhdlsyn.txt deleted file mode 100644 index 3e703077..00000000 --- a/lib/openchip/charlcd/vhdlsyn.txt +++ /dev/null @@ -1 +0,0 @@ -charlcd.vhd apbcharlcd.vhd diff --git a/lib/openchip/dirs.txt b/lib/openchip/dirs.txt deleted file mode 100644 index b2cc0b55..00000000 --- a/lib/openchip/dirs.txt +++ /dev/null @@ -1 +0,0 @@ -gpio charlcd sui diff --git a/lib/openchip/doc/readme.txt b/lib/openchip/doc/readme.txt deleted file mode 100644 index 9b501018..00000000 --- a/lib/openchip/doc/readme.txt +++ /dev/null @@ -1,122 +0,0 @@ -OpenChip IP-Cores for GRLIB - - -implemented in this release: - -APBGPIO -APBSUI - -both tested on Memec S3-1500MB board. - - -Generic note about the IP Cores: -All REV 0 IPcores implement only minimal "software assisted" -functionality, so they are basically just like specialized -IO ports that connect to the extenal peripherals. - -Next REVision will include dedicated hardware, but will be -backwards compatible and continue supporting the "software" -mode where the software has direct access to the peripherals. - - - -APBGPIO -======= -Simple 32bit General Purpose Input Output port - -address map (REV 0) - -base+0 write : data output -base+4 write : tristate register - -base+0 read : data input (external pins readback) - - -tristate buffer should be instantiated in toplevel, -if no tristate signals are used the GPIO can be used -as two 32 bit output and one 32 bit input port - -example use in C: - -int *gpio = (int *) 0x80000400; // Set base address! -int temp; - - gpio[0] = 0x12345678; // Write to DATA - gpio[1] = 0xFFFFFFFF; // Write to Direction - temp = gpio[0]; // Read input data - - - -APBSUI -====== -Simple User Interface - -combines in one peripheral -* Switches, use for DIP switches) -* Buttons, use for Push Buttons -* LED's, use for single LED's -* 7 Segment LED', connect to Segment LED's -* Buzzer, connect to Piezo or Speaker -* Character LCD, connect to typical Character mode LCD - - -address map (REV 0) -base+0 write : single LED's -base+1 write : 7 Segment LED's (4 digits, non multiplexed) -base+2 write : LCD -base+3 write : d0 - buzzer - - -base+4 read : Switches -base+5 read : Buttons - - -example use in vhdl top: ------------------------------------------------------------- - sui0 : apbsui - generic map ( - pindex => 4, - paddr => 4, - pirq => 5, - ledact => 0, - led7act => 0 - ) - port map ( - rstn, - clkm, - apbi, - apbo(4), - suii, - suio - ); - - suii.switch_in(7 downto 0) <= switch(7 downto 0); - suii.button_in(0) <= push1; - - led(3 downto 0) <= suio.led_out(3 downto 0); - - led1_a <= suio.led_a_out(0); - led1_b <= suio.led_b_out(0); - led1_c <= suio.led_c_out(0); - led1_d <= suio.led_d_out(0); - led1_e <= suio.led_e_out(0); - led1_f <= suio.led_f_out(0); - led1_g <= suio.led_g_out(0); - led1_dp <= suio.led_dp_out(0); - - led2_a <= suio.led_a_out(1); - led2_b <= suio.led_b_out(1); - led2_c <= suio.led_c_out(1); - led2_d <= suio.led_d_out(1); - led2_e <= suio.led_e_out(1); - led2_f <= suio.led_f_out(1); - led2_g <= suio.led_g_out(1); - led2_dp <= suio.led_dp_out(1); - - lcd_data <= suio.lcd_out; - lcd_en <= suio.lcd_en(0); - lcd_rs <= suio.lcd_rs; - piezo <= suio.buzzer; - ------------------------------------------------------------- - diff --git a/lib/openchip/doc/suidemo.c b/lib/openchip/doc/suidemo.c deleted file mode 100644 index 3d1d4efe..00000000 --- a/lib/openchip/doc/suidemo.c +++ /dev/null @@ -1,99 +0,0 @@ - -// Set Base address -int *sui = (int *) 0x80000400; - - -void delay(n) { - int i; - for (i=0;i>4 & 0x000F]<<8); - led_val ^= 0xFFFFFFFF; - - sui[1] = led_val; - -} - - - -main() { - int val; - - // Say hello on LCD - lcd_init(); - lcd_write("Testing SPARC V8 LCD"); - - // write something to 7 Segment LED's - led7_write_int(0x1234); - - // Blink single LEDs - while (1) { - sui[0] = val; - val++; - delay(100000); - } -} diff --git a/lib/openchip/gpio/apbgpio.vhd b/lib/openchip/gpio/apbgpio.vhd deleted file mode 100644 index 688e019d..00000000 --- a/lib/openchip/gpio/apbgpio.vhd +++ /dev/null @@ -1,141 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2004 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- Entity: gpio --- File: apbgpio.vhd --- Author: Antti Lukats, OpenChip --- Description: General Purpose I/O --- ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; - -library openchip; -use openchip.gpio.all; - ---pragma translate_off -use std.textio.all; ---pragma translate_on - -entity apbgpio is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - gpioi : in gpio_in_type; - gpioo : out gpio_out_type); -end; - -architecture rtl of apbgpio is - -constant REVISION : integer := 0; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBGPIO, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); - -type gpioregs is record - outreg : std_logic_vector(31 downto 0); -- Output Latch - dirreg : std_logic_vector(31 downto 0); -- Direction Register - inreg : std_logic_vector(31 downto 0); -- Input Latch - irq : std_ulogic; -- interrupt (internal), not used -end record; - -signal r, rin : gpioregs; - -begin - - comb : process(rst, r, apbi, gpioi ) - - variable rdata : std_logic_vector(31 downto 0); - variable irq : std_logic_vector(NAHBIRQ-1 downto 0); - variable v : gpioregs; - - begin - v := r; - v.inreg := gpioi.d_in; - - irq := (others => '0'); - --irq(pirq) := r.irq; - v.irq := '0'; - rdata := (others => '0'); - --- read/write registers - - case apbi.paddr(3 downto 2) is - when "00" => - rdata(31 downto 0) := r.inreg; -- read IO pin - when "01" => - rdata(31 downto 0) := r.dirreg; -- read back of direction reg ? - when others => - end case; - - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(3 downto 2) is - when "00" => - v.outreg := apbi.pwdata(31 downto 0); - when "01" => - v.dirreg := apbi.pwdata(31 downto 0); - when others => - end case; - end if; - --- reset operation - - if rst = '0' then - v.outreg := (others => '0'); - v.dirreg := (others => '0'); - end if; - --- update registers - - rin <= v; - --- drive outputs - - - gpioo.d_out <= r.outreg; - gpioo.t_out <= r.dirreg; - - apbo.prdata <= rdata; - apbo.pirq <= irq; - apbo.pindex <= pindex; - - end process; - - apbo.pconfig <= pconfig; - - regs : process(clk) - begin - if rising_edge(clk) then - r <= rin; - end if; - end process; - --- pragma translate_off - bootmsg : report_version - generic map ("apbgpio" & tost(pindex) & - ": Generic GPIO rev " & tost(REVISION) & ", irq " & tost(pirq)); --- pragma translate_on - -end; diff --git a/lib/openchip/gpio/gpio.vhd b/lib/openchip/gpio/gpio.vhd deleted file mode 100644 index 527d5c8c..00000000 --- a/lib/openchip/gpio/gpio.vhd +++ /dev/null @@ -1,50 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2004 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- package: gpio --- File: gpio.vhd --- Author: Antti Lukats, OpenChip --- Description: GPIO types and components ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; - -package gpio is - -type gpio_in_type is record - d_in : std_logic_vector(31 downto 0); -end record; - -type gpio_out_type is record - d_out : std_logic_vector(31 downto 0); - t_out : std_logic_vector(31 downto 0); -end record; - -component apbgpio - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0); - port ( - rst : in std_ulogic; - clk : in std_ulogic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - gpioi : in gpio_in_type; - gpioo : out gpio_out_type); -end component; - -end; diff --git a/lib/openchip/gpio/vhdlsyn.txt b/lib/openchip/gpio/vhdlsyn.txt deleted file mode 100644 index 7da17387..00000000 --- a/lib/openchip/gpio/vhdlsyn.txt +++ /dev/null @@ -1 +0,0 @@ -gpio.vhd apbgpio.vhd diff --git a/lib/openchip/libs.txt b/lib/openchip/libs.txt deleted file mode 100644 index 18d70579..00000000 --- a/lib/openchip/libs.txt +++ /dev/null @@ -1 +0,0 @@ -openchip diff --git a/lib/openchip/sui/apbsui.vhd b/lib/openchip/sui/apbsui.vhd deleted file mode 100644 index a81facd3..00000000 --- a/lib/openchip/sui/apbsui.vhd +++ /dev/null @@ -1,231 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2004 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- Entity: sui --- File: apbsui.vhd --- Author: Antti Lukats, OpenChip --- Description: Simple User Interface --- --- Single Peripheral containting the following: --- Input: --- Switches 0..31 --- Buttons 0..31 --- Output --- LED 7 Segment, 4 digits non multiplexed, 32 digits in multiplexed mode --- Single LED 0..31 --- Buzzer --- Character LCD --- --- Version 0: All functions are software assisted, IP Core has minimal --- intelligence providing bit-bang access to all the connected hardware --- --- --- --- --- --- --- --- ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; -use grlib.stdlib.all; -use grlib.devices.all; - -library openchip; -use openchip.sui.all; - ---pragma translate_off -use std.textio.all; ---pragma translate_on - -entity apbsui is - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; - - --- active level for Segment LED segments - led7act : integer := 1; --- active level for single LED's - ledact : integer := 1); - - port ( - rst : in std_ulogic; - clk : in std_ulogic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - suii : in sui_in_type; - suio : out sui_out_type); -end; - -architecture rtl of apbsui is - -constant REVISION : integer := 0; - -constant pconfig : apb_config_type := ( - 0 => ahb_device_reg ( VENDOR_OPENCHIP, OPENCHIP_APBSUI, 0, REVISION, pirq), - 1 => apb_iobar(paddr, pmask)); - -type suiregs is record - ledreg : std_logic_vector(31 downto 0); -- Output Latch, single LEDs - led7reg : std_logic_vector(31 downto 0); -- Output Latch, 7 Seg LEDs - lcdreg : std_logic_vector(15 downto 0); -- Output Latch LCD - buzreg : std_logic_vector(0 downto 0); -- Buzzer - - sw_inreg : std_logic_vector(31 downto 0); -- Switches in - btn_inreg : std_logic_vector(31 downto 0); -- Buttons in - - - irq : std_ulogic; -- interrupt (internal), not used -end record; - -signal r, rin : suiregs; - -begin - - comb : process(rst, r, apbi, suii ) - - variable rdata : std_logic_vector(31 downto 0); - variable irq : std_logic_vector(NAHBIRQ-1 downto 0); - variable v : suiregs; - - - - begin - v := r; - v.sw_inreg := suii.switch_in; - v.btn_inreg := suii.button_in; - - irq := (others => '0'); - --irq(pirq) := r.irq; - v.irq := '0'; - rdata := (others => '0'); - --- read/write registers - - case apbi.paddr(4 downto 2) is - when "100" => - rdata(31 downto 0) := r.sw_inreg; -- read switches - when "101" => - rdata(31 downto 0) := r.btn_inreg; -- read buttons - when others => - end case; - - if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then - case apbi.paddr(4 downto 2) is - when "000" => - v.ledreg := apbi.pwdata(31 downto 0); - when "001" => - v.led7reg := apbi.pwdata(31 downto 0); - when "010" => - v.lcdreg(15 downto 0) := apbi.pwdata(15 downto 0); - when "011" => - v.buzreg(0) := apbi.pwdata(0); - - when others => - end case; - end if; - --- reset operation - - if rst = '0' then - v.ledreg := (others => '0'); - v.led7reg := (others => '0'); - end if; - --- update registers - - rin <= v; - --- drive outputs - - suio.lcd_out <= r.lcdreg(7 downto 0); - suio.lcd_en <= r.lcdreg(11 downto 8); - suio.lcd_rs <= r.lcdreg(12); - suio.lcd_r_wn <= r.lcdreg(13); - suio.lcd_backlight <= r.lcdreg(14); - suio.lcd_oe <= r.lcdreg(15); - - suio.buzzer <= r.buzreg(0); - suio.led_out <= r.ledreg; - - - - suio.led_a_out(0) <= r.led7reg(0); - suio.led_b_out(0) <= r.led7reg(1); - suio.led_c_out(0) <= r.led7reg(2); - suio.led_d_out(0) <= r.led7reg(3); - suio.led_e_out(0) <= r.led7reg(4); - suio.led_f_out(0) <= r.led7reg(5); - suio.led_g_out(0) <= r.led7reg(6); - suio.led_dp_out(0) <= r.led7reg(7); - - suio.led_a_out(1) <= r.led7reg(8); - suio.led_b_out(1) <= r.led7reg(9); - suio.led_c_out(1) <= r.led7reg(10); - suio.led_d_out(1) <= r.led7reg(11); - suio.led_e_out(1) <= r.led7reg(12); - suio.led_f_out(1) <= r.led7reg(13); - suio.led_g_out(1) <= r.led7reg(14); - suio.led_dp_out(1) <= r.led7reg(15); - - suio.led_a_out(2) <= r.led7reg(16); - suio.led_b_out(2) <= r.led7reg(17); - suio.led_c_out(2) <= r.led7reg(18); - suio.led_d_out(2) <= r.led7reg(19); - suio.led_e_out(2) <= r.led7reg(20); - suio.led_f_out(2) <= r.led7reg(21); - suio.led_g_out(2) <= r.led7reg(22); - suio.led_dp_out(2) <= r.led7reg(23); - - suio.led_a_out(3) <= r.led7reg(24); - suio.led_b_out(3) <= r.led7reg(25); - suio.led_c_out(3) <= r.led7reg(26); - suio.led_d_out(3) <= r.led7reg(27); - suio.led_e_out(3) <= r.led7reg(28); - suio.led_f_out(3) <= r.led7reg(29); - suio.led_g_out(3) <= r.led7reg(30); - suio.led_dp_out(3) <= r.led7reg(31); - - - - - - - apbo.prdata <= rdata; - apbo.pirq <= irq; - apbo.pindex <= pindex; - - end process; - - apbo.pconfig <= pconfig; - - regs : process(clk) - begin - if rising_edge(clk) then - r <= rin; - end if; - end process; - --- pragma translate_off - bootmsg : report_version - generic map ("apbsui" & tost(pindex) & - ": SUI rev " & tost(REVISION) & ", irq " & tost(pirq)); --- pragma translate_on - -end; diff --git a/lib/openchip/sui/sui.vhd b/lib/openchip/sui/sui.vhd deleted file mode 100644 index 3995284d..00000000 --- a/lib/openchip/sui/sui.vhd +++ /dev/null @@ -1,78 +0,0 @@ ----------------------------------------------------------------------------- --- This file is a part of the GRLIB VHDL IP LIBRARY --- Copyright (C) 2004 GAISLER RESEARCH --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 2 of the License, or --- (at your option) any later version. --- --- See the file COPYING for the full details of the license. --- ------------------------------------------------------------------------------ --- package: sui --- File: sui.vhd --- Author: Antti Lukats, OpenChip --- Description: Simple User Interface types and components ------------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -library grlib; -use grlib.amba.all; - -package sui is - -type sui_in_type is record - post_code_in : std_logic_vector(7 downto 0); - switch_in : std_logic_vector(31 downto 0); - button_in : std_logic_vector(31 downto 0); - - lcd_in : std_logic_vector(7 downto 0); -end record; - -type sui_out_type is record - led_a_out : std_logic_vector(3 downto 0); - led_b_out : std_logic_vector(3 downto 0); - led_c_out : std_logic_vector(3 downto 0); - led_d_out : std_logic_vector(3 downto 0); - led_e_out : std_logic_vector(3 downto 0); - led_f_out : std_logic_vector(3 downto 0); - led_g_out : std_logic_vector(3 downto 0); - led_dp_out : std_logic_vector(3 downto 0); - led_com_out : std_logic_vector(31 downto 0); - - led_out : std_logic_vector(31 downto 0); - - lcd_out : std_logic_vector(7 downto 0); - lcd_oe : std_logic; - lcd_en : std_logic_vector(3 downto 0); - lcd_rs : std_logic; - lcd_r_wn : std_logic; - lcd_backlight : std_logic; - - - buzzer : std_logic; -end record; - -component apbsui - generic ( - pindex : integer := 0; - paddr : integer := 0; - pmask : integer := 16#fff#; - pirq : integer := 0; --- active level for Segment LED segments - led7act : integer := 1; --- active level for single LED's - ledact : integer := 1); - - port ( - rst : in std_ulogic; - clk : in std_ulogic; - apbi : in apb_slv_in_type; - apbo : out apb_slv_out_type; - suii : in sui_in_type; - suio : out sui_out_type); -end component; - -end; diff --git a/lib/openchip/sui/vhdlsyn.txt b/lib/openchip/sui/vhdlsyn.txt deleted file mode 100644 index f8fcb9d2..00000000 --- a/lib/openchip/sui/vhdlsyn.txt +++ /dev/null @@ -1 +0,0 @@ -sui.vhd apbsui.vhd diff --git a/lib/opencores/dirs.txt b/lib/opencores/dirs.txt index d909198b..f4b6f664 100644 --- a/lib/opencores/dirs.txt +++ b/lib/opencores/dirs.txt @@ -1 +1 @@ -can i2c +can i2c ge_1000baseX diff --git a/lib/spw/comp/spwcomp.vhd b/lib/spw/comp/spwcomp.vhd index 8cfcfef5..2a0f1541 100644 --- a/lib/spw/comp/spwcomp.vhd +++ b/lib/spw/comp/spwcomp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -23,21 +23,36 @@ use ieee.std_logic_1164.all; package spwcomp is component grspwc2 is generic( - rmap : integer range 0 to 2 := 0; - rmapcrc : integer range 0 to 1 := 0; - fifosize1 : integer range 4 to 32 := 32; - fifosize2 : integer range 16 to 64 := 64; - rxunaligned : integer range 0 to 1 := 0; - rmapbufs : integer range 2 to 8 := 4; - scantest : integer range 0 to 1 := 0; - ports : integer range 1 to 2 := 1; - dmachan : integer range 1 to 4 := 1; - tech : integer; - input_type : integer range 0 to 4 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - nodeaddr : integer range 0 to 255 := 254; - destkey : integer range 0 to 255 := 0); + rmap : integer range 0 to 2 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 64 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + scantest : integer range 0 to 1 := 0; + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; + tech : integer; + input_type : integer range 0 to 4 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + nodeaddr : integer range 0 to 255 := 254; + destkey : integer range 0 to 255 := 0; + interruptdist : integer range 0 to 32 := 0; + intscalerbits : integer range 0 to 31 := 0; + intisrtimerbits : integer range 0 to 31 := 0; + intiatimerbits : integer range 0 to 31 := 0; + intctimerbits : integer range 0 to 31 := 0; + tickinasync : integer range 0 to 1 := 0; + pnp : integer range 0 to 2 := 0; + pnpvendid : integer range 0 to 16#FFFF# := 0; + pnpprodid : integer range 0 to 16#FFFF# := 0; + pnpmajorver : integer range 0 to 16#FF# := 0; + pnpminorver : integer range 0 to 16#FF# := 0; + pnppatch : integer range 0 to 16#FF# := 0; + num_txdesc : integer range 64 to 512 := 64; + num_rxdesc : integer range 128 to 1024 := 128 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -90,19 +105,19 @@ package spwcomp is --rmapen rmapen : in std_ulogic; rmapnodeaddr : in std_logic_vector(7 downto 0); - --rx ahb fifo + --rx ahb fifo rxrenable : out std_ulogic; - rxraddress : out std_logic_vector(4 downto 0); + rxraddress : out std_logic_vector(5 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); - rxwaddress : out std_logic_vector(4 downto 0); + rxwaddress : out std_logic_vector(5 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; - txraddress : out std_logic_vector(4 downto 0); + txraddress : out std_logic_vector(5 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); - txwaddress : out std_logic_vector(4 downto 0); + txwaddress : out std_logic_vector(5 downto 0); txrdata : in std_logic_vector(31 downto 0); --nchar fifo ncrenable : out std_ulogic; @@ -124,7 +139,18 @@ package spwcomp is --parallel rx data out rxdav : out std_ulogic; rxdataout : out std_logic_vector(8 downto 0); - loopback : out std_ulogic + loopback : out std_ulogic; + -- interrupt dist. default values + intpreload : in std_logic_vector(30 downto 0); + inttreload : in std_logic_vector(30 downto 0); + intiareload : in std_logic_vector(30 downto 0); + intcreload : in std_logic_vector(30 downto 0); + irqtxdefault : in std_logic_vector(4 downto 0); + -- SpW PnP enable + pnpen : in std_ulogic; + pnpuvendid : in std_logic_vector(15 downto 0); + pnpuprodid : in std_logic_vector(15 downto 0); + pnpusn : in std_logic_vector(31 downto 0) ); end component; @@ -482,7 +508,8 @@ package spwcomp is rxtx_sameclk : integer range 0 to 1 := 0; fifosize : integer range 16 to 2048 := 64; tech : integer; - scantest : integer range 0 to 1 := 0 + scantest : integer range 0 to 1 := 0; + inputtest : integer range 0 to 1 := 0 ); port( rst : in std_ulogic; @@ -548,31 +575,56 @@ package spwcomp is tickin : in std_ulogic; timein : in std_logic_vector(7 downto 0); tickin_done : out std_ulogic; + tickin_busy : out std_ulogic; tickout : out std_ulogic; - timeout : out std_logic_vector(7 downto 0) + timeout : out std_logic_vector(7 downto 0); + credcnt : out std_logic_vector(5 downto 0); + ocredcnt : out std_logic_vector(5 downto 0); + --misc + powerdown : out std_ulogic; + powerdownrx : out std_ulogic; + -- input timing testing + testdi : in std_logic_vector(1 downto 0) := "00"; + testsi : in std_logic_vector(1 downto 0) := "00"; + testinput : in std_ulogic := '0' ); end component; component grspw2_gen is generic( - rmap : integer range 0 to 2 := 0; - rmapcrc : integer range 0 to 1 := 0; - fifosize1 : integer range 4 to 32 := 32; - fifosize2 : integer range 16 to 64 := 64; - rxunaligned : integer range 0 to 1 := 0; - rmapbufs : integer range 2 to 8 := 4; - scantest : integer range 0 to 1 := 0; - ports : integer range 1 to 2 := 1; - dmachan : integer range 1 to 4 := 1; - tech : integer; - input_type : integer range 0 to 4 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - ft : integer range 0 to 2 := 0; - techfifo : integer range 0 to 1 := 1; - memtech : integer := 0; - nodeaddr : integer range 0 to 255 := 254; - destkey : integer range 0 to 255 := 0); + rmap : integer range 0 to 2 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 64 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + scantest : integer range 0 to 1 := 0; + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; + tech : integer; + input_type : integer range 0 to 4 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + ft : integer range 0 to 2 := 0; + techfifo : integer range 0 to 1 := 1; + memtech : integer := 0; + nodeaddr : integer range 0 to 255 := 254; + destkey : integer range 0 to 255 := 0; + interruptdist : integer range 0 to 32 := 0; + intscalerbits : integer range 0 to 31 := 0; + intisrtimerbits : integer range 0 to 31 := 0; + intiatimerbits : integer range 0 to 31 := 0; + intctimerbits : integer range 0 to 31 := 0; + tickinasync : integer range 0 to 1 := 0; + pnp : integer range 0 to 2 := 0; + pnpvendid : integer range 0 to 16#FFFF# := 0; + pnpprodid : integer range 0 to 16#FFFF# := 0; + pnpmajorver : integer range 0 to 16#FF# := 0; + pnpminorver : integer range 0 to 16#FF# := 0; + pnppatch : integer range 0 to 16#FF# := 0; + num_txdesc : integer range 64 to 512 := 64; + num_rxdesc : integer range 128 to 1024 := 128 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -630,7 +682,19 @@ package spwcomp is rmapnodeaddr : in std_logic_vector(7 downto 0); --parallel rx data out rxdav : out std_ulogic; - rxdataout : out std_logic_vector(8 downto 0) + rxdataout : out std_logic_vector(8 downto 0); + loopback : out std_ulogic; + -- interrupt dist. default values + intpreload : in std_logic_vector(30 downto 0); + inttreload : in std_logic_vector(30 downto 0); + intiareload : in std_logic_vector(30 downto 0); + intcreload : in std_logic_vector(30 downto 0); + irqtxdefault : in std_logic_vector(4 downto 0); + -- SpW PnP enable + pnpen : in std_ulogic; + pnpuvendid : in std_logic_vector(15 downto 0); + pnpuprodid : in std_logic_vector(15 downto 0); + pnpusn : in std_logic_vector(31 downto 0) ); end component; diff --git a/lib/spw/wrapper/grspw2_gen.vhd b/lib/spw/wrapper/grspw2_gen.vhd index b1aa3231..a9eeba8e 100644 --- a/lib/spw/wrapper/grspw2_gen.vhd +++ b/lib/spw/wrapper/grspw2_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -33,24 +33,38 @@ use spw.spwcomp.all; entity grspw2_gen is generic( - rmap : integer range 0 to 2 := 0; - rmapcrc : integer range 0 to 1 := 0; - fifosize1 : integer range 4 to 32 := 32; - fifosize2 : integer range 16 to 64 := 64; - rxunaligned : integer range 0 to 1 := 0; - rmapbufs : integer range 2 to 8 := 4; - scantest : integer range 0 to 1 := 0; - ports : integer range 1 to 2 := 1; - dmachan : integer range 1 to 4 := 1; - tech : integer; - input_type : integer range 0 to 3 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - ft : integer range 0 to 2 := 0; - techfifo : integer range 0 to 1 := 1; - memtech : integer := 0; - nodeaddr : integer range 0 to 255 := 254; - destkey : integer range 0 to 255 := 0 + rmap : integer range 0 to 2 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 64 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + scantest : integer range 0 to 1 := 0; + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; + tech : integer; + input_type : integer range 0 to 3 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + ft : integer range 0 to 2 := 0; + techfifo : integer range 0 to 1 := 1; + memtech : integer := 0; + nodeaddr : integer range 0 to 255 := 254; + destkey : integer range 0 to 255 := 0; + interruptdist : integer range 0 to 32 := 0; + intscalerbits : integer range 0 to 31 := 0; + intisrtimerbits : integer range 0 to 31 := 0; + intiatimerbits : integer range 0 to 31 := 0; + intctimerbits : integer range 0 to 31 := 0; + tickinasync : integer range 0 to 1 := 0; + pnp : integer range 0 to 2 := 0; + pnpvendid : integer range 0 to 16#FFFF# := 0; + pnpprodid : integer range 0 to 16#FFFF# := 0; + pnpmajorver : integer range 0 to 16#FF# := 0; + pnpminorver : integer range 0 to 16#FF# := 0; + pnppatch : integer range 0 to 16#FF# := 0; + num_txdesc : integer range 64 to 512 := 64; + num_rxdesc : integer range 128 to 1024 := 128 ); port( rst : in std_ulogic; @@ -110,7 +124,18 @@ entity grspw2_gen is --parallel rx data out rxdav : out std_ulogic; rxdataout : out std_logic_vector(8 downto 0); - loopback : out std_ulogic + loopback : out std_ulogic; + -- interrupt dist. default values + intpreload : in std_logic_vector(30 downto 0); + inttreload : in std_logic_vector(30 downto 0); + intiareload : in std_logic_vector(30 downto 0); + intcreload : in std_logic_vector(30 downto 0); + irqtxdefault : in std_logic_vector(4 downto 0); + --SpW PnP enable + pnpen : in std_ulogic; + pnpuvendid : in std_logic_vector(15 downto 0); + pnpuprodid : in std_logic_vector(15 downto 0); + pnpusn : in std_logic_vector(31 downto 0) ); end entity; @@ -123,17 +148,17 @@ architecture rtl of grspw2_gen is --rx ahb fifo signal rxrenable : std_ulogic; - signal rxraddress : std_logic_vector(4 downto 0); + signal rxraddress : std_logic_vector(5 downto 0); signal rxwrite : std_ulogic; signal rxwdata : std_logic_vector(31 downto 0); - signal rxwaddress : std_logic_vector(4 downto 0); + signal rxwaddress : std_logic_vector(5 downto 0); signal rxrdata : std_logic_vector(31 downto 0); --tx ahb fifo signal txrenable : std_ulogic; - signal txraddress : std_logic_vector(4 downto 0); + signal txraddress : std_logic_vector(5 downto 0); signal txwrite : std_ulogic; signal txwdata : std_logic_vector(31 downto 0); - signal txwaddress : std_logic_vector(4 downto 0); + signal txwaddress : std_logic_vector(5 downto 0); signal txrdata : std_logic_vector(31 downto 0); --nchar fifo signal ncrenable : std_ulogic; @@ -163,21 +188,35 @@ begin grspwc0: grspwc2 generic map( - rmap => rmap, - rmapcrc => rmapcrc, - fifosize1 => fifosize1, - fifosize2 => fifosize2, - rxunaligned => rxunaligned, - rmapbufs => rmapbufs, - scantest => scantest, - ports => ports, - dmachan => dmachan, - tech => tech, - input_type => input_type, - output_type => output_type, - rxtx_sameclk => rxtx_sameclk, - nodeaddr => nodeaddr, - destkey => destkey) + rmap => rmap, + rmapcrc => rmapcrc, + fifosize1 => fifosize1, + fifosize2 => fifosize2, + rxunaligned => rxunaligned, + rmapbufs => rmapbufs, + scantest => scantest, + ports => ports, + dmachan => dmachan, + tech => tech, + input_type => input_type, + output_type => output_type, + rxtx_sameclk => rxtx_sameclk, + nodeaddr => nodeaddr, + destkey => destkey, + interruptdist => interruptdist, + intscalerbits => intscalerbits, + intisrtimerbits => intisrtimerbits, + intiatimerbits => intiatimerbits, + intctimerbits => intctimerbits, + tickinasync => tickinasync, + pnp => pnp, + pnpvendid => pnpvendid, + pnpprodid => pnpprodid, + pnpmajorver => pnpmajorver, + pnpminorver => pnpminorver, + pnppatch => pnppatch, + num_txdesc => num_txdesc, + num_rxdesc => num_rxdesc) port map( rst => rst, clk => clk, @@ -264,7 +303,19 @@ begin --parallel rx data out rxdav => rxdav, rxdataout => rxdataout, - loopback => loopback); + loopback => loopback, + -- interrupt dist. default values + intpreload => intpreload, + inttreload => inttreload, + intiareload => intiareload, + intcreload => intcreload, + irqtxdefault => irqtxdefault, + -- SpW PnP enable + pnpen => pnpen, + pnpuvendid => pnpuvendid, + pnpuprodid => pnpuprodid, + pnpusn => pnpusn + ); ------------------------------------------------------------------------------ -- FIFOS --------------------------------------------------------------------- diff --git a/lib/spw/wrapper/grspw_codec_gen.vhd b/lib/spw/wrapper/grspw_codec_gen.vhd index 8861a106..2409a245 100644 --- a/lib/spw/wrapper/grspw_codec_gen.vhd +++ b/lib/spw/wrapper/grspw_codec_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/spw/wrapper/grspw_gen.vhd b/lib/spw/wrapper/grspw_gen.vhd index 58537891..760e0460 100644 --- a/lib/spw/wrapper/grspw_gen.vhd +++ b/lib/spw/wrapper/grspw_gen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/altera_mf/simprims/altera_mf_components.vhd b/lib/tech/altera_mf/simprims/altera_mf_components.vhd index ee0ced6f..84c9a057 100644 --- a/lib/tech/altera_mf/simprims/altera_mf_components.vhd +++ b/lib/tech/altera_mf/simprims/altera_mf_components.vhd @@ -112,25 +112,26 @@ end component; component altlvds_rx generic ( - number_of_channels : natural; - deserialization_factor : natural; - inclock_boost : natural:= 0; - registered_output : string := "ON"; - inclock_period : natural; - cds_mode : string := "UNUSED"; - intended_device_family : string := "APEX20KE"; - input_data_rate : natural:= 0; - inclock_data_alignment : string := "EDGE_ALIGNED"; - registered_data_align_input : string :="ON"; - common_rx_tx_pll : string :="ON"; - enable_dpa_mode : string := "OFF"; + number_of_channels : natural; -- Required parameter + deserialization_factor : natural; -- Required parameter + registered_output : string := "ON"; + inclock_period : natural := 10000; -- Required parameter + inclock_boost : natural := 0; + cds_mode : string := "UNUSED"; + intended_device_family : string := "APEX20KE"; + input_data_rate : natural := 0; + inclock_data_alignment : string := "EDGE_ALIGNED"; + registered_data_align_input : string := "ON"; + common_rx_tx_pll : string := "ON"; + enable_dpa_mode : string := "OFF"; enable_dpa_pll_calibration : string := "OFF"; - enable_dpa_fifo : string := "ON"; - use_dpll_rawperror : string := "OFF"; - use_coreclock_input : string := "OFF"; - dpll_lock_count : natural:= 0; - dpll_lock_window : natural:= 0; - outclock_resource : string := "AUTO"; + enable_dpa_calibration : string := "ON"; + enable_dpa_fifo : string := "ON"; + use_dpll_rawperror : string := "OFF"; + use_coreclock_input : string := "OFF"; + dpll_lock_count : natural := 0; + dpll_lock_window : natural := 0; + outclock_resource : string := "AUTO"; data_align_rollover : natural := 10; lose_lock_on_one_change : string := "OFF"; reset_fifo_at_first_lock : string := "ON"; @@ -152,61 +153,107 @@ component altlvds_rx enable_dpa_initial_phase_selection : string := "OFF"; dpa_initial_phase_value :natural := 0; pll_self_reset_on_loss_lock : string := "OFF"; - lpm_hint : string := "UNUSED"; - lpm_type : string := "altlvds_rx"; - clk_src_is_pll : string := "off" ); + lpm_hint : string := "UNUSED"; + lpm_type : string := "altlvds_rx"; + -- Specifies whether the source of the input clock is from the PLL + clk_src_is_pll : string := "off" ); + +-- PORT DECLARATION port ( - rx_in : in std_logic_vector(number_of_channels-1 downto 0); +--INPUT PORT DECLARATION + rx_in : in std_logic_vector(number_of_channels-1 downto 0); --Required port rx_inclock : in std_logic := '0'; rx_syncclock : in std_logic := '0'; rx_readclock : in std_logic := '0'; - rx_enable : in std_logic := '1'; + rx_enable : in std_logic := '0'; rx_deskew : in std_logic := '0'; rx_pll_enable : in std_logic := '1'; - rx_data_align : in std_logic := '0'; + rx_data_align : in std_logic := 'Z'; rx_data_align_reset : in std_logic := '0'; - rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); - rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0'); + rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0):= (others => '0'); rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1'); rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); - rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); + rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => 'Z'); rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); pll_areset : in std_logic := '0'; dpa_pll_recal : in std_logic := '0'; pll_phasedone : in std_logic := '1'; rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0'); - rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); - rx_outclock : out std_logic; - rx_locked : out std_logic; - rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); - rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0); - rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0); + + +-- OUTPUT PORT DECLARATION + rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + rx_outclock : out std_logic; + rx_locked : out std_logic; + rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0); + rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0); + rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0); dpa_pll_cal_busy : out std_logic; pll_phasestep : out std_logic; pll_phaseupdown : out std_logic; pll_phasecounterselect: out std_logic_Vector(3 downto 0); - pll_scanclk : out std_logic); + pll_scanclk : out std_logic + ); + end component; component altlvds_tx generic ( + -- Specifies the number of LVDS channels (required) number_of_channels : natural; - deserialization_factor : natural:= 4; - inclock_boost : natural := 0; - outclock_divide_by : positive:= 1; - registered_input : string := "ON"; - multi_clock : string := "OFF"; - inclock_period : natural; - center_align_msb : string := "UNUSED"; - intended_device_family : string := "APEX20KE"; - output_data_rate : natural:= 0; - outclock_resource : string := "AUTO"; - common_rx_tx_pll : string := "ON"; - inclock_data_alignment : string := "EDGE_ALIGNED"; - outclock_alignment : string := "EDGE_ALIGNED"; - use_external_pll : string := "OFF"; + + -- Specifies the number of bits per channel (required) + deserialization_factor : natural := 4; + + -- Indicates whether the tx_in[] and tx_outclock ports should be + -- registered. Choices for STRATIX are ON, OFF, TX_CLKIN or TX_CORECLK + registered_input : string := "ON"; + + -- "ON" means that sync_inclock is also used + -- (not used for Stratix and Stratix GX.) + multi_clock : string := "OFF"; + + -- Specifies the period of the input clock in ps (Required) + inclock_period : natural := 10000; + + -- Specifies the period of the tx_outclock port as + -- [INCLOCK_PERIOD * OUTCLOCK_DIVIDE_BY] + outclock_divide_by : positive := 1; + + -- The effective clock period used to sample output data + inclock_boost : natural := 0; + + -- Aligns the Most Significant Bit(MSB) to the falling edge of the + -- clock instead of the rising edge (only for APEX II devices) + center_align_msb : string := "OFF"; + + -- Specifies the device family to be used + intended_device_family : string := "APEX20KE"; + + -- Specifies the data rate out of the PLL. + -- (required and only for Stratix and Stratix GX devices) + output_data_rate : natural := 0; + + -- Specifies the alignment of the input data with respect to the + -- tx_inclock port. (required and only available for Stratix and + -- Stratix GX devices) + inclock_data_alignment : string := "EDGE_ALIGNED"; + + -- Specifies the alignment of the output data with respect to the + -- tx_outclock port. (required and only available for Stratix and + -- Stratix GX devices) + outclock_alignment : string := "EDGE_ALIGNED"; + + -- Specifies whether the compiler uses the same PLL for both the LVDS + -- receiver and the LVDS transmitter + common_rx_tx_pll : string := "ON"; + + outclock_resource : string := "AUTO"; + + use_external_pll : string := "OFF"; implement_in_les : STRING := "OFF"; preemphasis_setting : natural := 0; vod_setting : natural := 0; @@ -218,21 +265,55 @@ component altlvds_tx outclock_phase_shift : integer := 0; use_no_phase_shift : string := "ON"; pll_self_reset_on_loss_lock : string := "OFF"; + lpm_type : string := "altlvds_tx"; lpm_hint : string := "UNUSED"; - lpm_type : string := "altlvds_tx"; - clk_src_is_pll : string := "off" ); + + -- Specifies whether the source of the input clock is from the PLL + clk_src_is_pll : string := "off" ); + +-- PORT DECLARATION port ( - tx_in : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0); + +-- INPUT PORT DECLARATION + -- Input data (required) + tx_in : in std_logic_vector(deserialization_factor* + number_of_channels -1 downto 0); + + -- Input clock (required) tx_inclock : in std_logic := '0'; + tx_syncclock : in std_logic := '0'; + tx_enable : in std_logic := '1'; + + -- Optional clock for input registers (Required if "multi_clock" + -- parameters is turned on) sync_inclock : in std_logic := '0'; + + -- Enable control for the LVDS PLL tx_pll_enable : in std_logic := '1'; + + -- Asynchronously resets all counters to initial values (only for + --Stratix and Stratix GX devices) pll_areset : in std_logic := '0'; - tx_out : out std_logic_vector(number_of_channels-1 downto 0); + + +-- OUTPUT PORT DECLARATION + -- Serialized data signal(required) + tx_out : out std_logic_vector(number_of_channels-1 downto 0) + := (others => '0'); + + -- External reference clock tx_outclock : out std_logic; + + -- Output clock used to feed non-peripheral logic. + -- Only available for Stratix, and Stratix GX devices only. tx_coreclock : out std_logic; - tx_locked : out std_logic ); + + -- Gives the status of the LVDS PLL + -- (when the PLL is locked, this signal is VCC. GND otherwise) + tx_locked : out std_logic + ); end component; component altdpram diff --git a/lib/tech/atc18/components/atmel_components.vhd b/lib/tech/atc18/components/atmel_components.vhd index 67d4ed1a..3c8c96f8 100644 --- a/lib/tech/atc18/components/atmel_components.vhd +++ b/lib/tech/atc18/components/atmel_components.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/atc18/components/atmel_simprims.vhd b/lib/tech/atc18/components/atmel_simprims.vhd index 5329f4bc..ea49d0d2 100644 --- a/lib/tech/atc18/components/atmel_simprims.vhd +++ b/lib/tech/atc18/components/atmel_simprims.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/umc18/components/umc_components.vhd b/lib/tech/umc18/components/umc_components.vhd index c55151a1..1e37b991 100644 --- a/lib/tech/umc18/components/umc_components.vhd +++ b/lib/tech/umc18/components/umc_components.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/umc18/components/umc_simprims.vhd b/lib/tech/umc18/components/umc_simprims.vhd index c844d1a7..5b1094b5 100644 --- a/lib/tech/umc18/components/umc_simprims.vhd +++ b/lib/tech/umc18/components/umc_simprims.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/unisim/gr/unisim_VCOMP.vhd b/lib/tech/unisim/gr/unisim_VCOMP.vhd index 61d42eb9..09a2d5b0 100644 --- a/lib/tech/unisim/gr/unisim_VCOMP.vhd +++ b/lib/tech/unisim/gr/unisim_VCOMP.vhd @@ -2,7 +2,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/unisim/gr/unisim_VITAL.vhd b/lib/tech/unisim/gr/unisim_VITAL.vhd index 2b988957..323cf793 100644 --- a/lib/tech/unisim/gr/unisim_VITAL.vhd +++ b/lib/tech/unisim/gr/unisim_VITAL.vhd @@ -238,13 +238,13 @@ entity IBUFG is generic ( IBUF_LOW_PWR : boolean := TRUE; IOSTANDARD : string := "LVCMOS25"); port (O : out std_logic; I : in std_logic); end; -architecture beh of IBUFG is begin o <= to_X01(i) after 1 ns; end; +architecture beh of IBUFG is begin o <= to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; entity IBUF is generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25"); port (O : out std_logic; I : in std_logic); end; -architecture beh of IBUF is begin o <= to_X01(i) after 1 ns; end; +architecture beh of IBUF is begin o <= to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -253,7 +253,7 @@ entity OBUF is generic ( IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW"); port (O : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUF is -begin o <= to_X01(i) after 2 ns when slew = "SLOW" else to_X01(i) after 1 ns; end; +begin o <= to_X01(i) after 0 ns when slew = "SLOW" else to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -266,10 +266,10 @@ entity IOBUF is generic ( end; architecture beh of IOBUF is begin - io <= 'X' after 2 ns when to_X01(t) = 'X' else - I after 2 ns when (to_X01(t) = '0') else - 'Z' after 2 ns when to_X01(t) = '1'; - o <= to_X01(io) after 1 ns; + io <= 'X' after 0 ns when to_X01(t) = 'X' else + I after 0 ns when (to_X01(t) = '0') else + 'Z' after 0 ns when to_X01(t) = '1'; + o <= to_X01(io) after 0 ns; end; library ieee; @@ -281,13 +281,13 @@ entity IOBUFDS is generic ( end; architecture beh of IOBUFDS is begin - io <= 'X' after 2 ns when to_X01(t) = 'X' else - I after 2 ns when (to_X01(t) = '0') else - 'Z' after 2 ns when to_X01(t) = '1'; - iob <= 'X' after 2 ns when to_X01(t) = 'X' else - not I after 2 ns when (to_X01(t) = '0') else - 'Z' after 2 ns when to_X01(t) = '1'; - o <= to_X01(io) after 1 ns; + io <= 'X' after 0 ns when to_X01(t) = 'X' else + I after 0 ns when (to_X01(t) = '0') else + 'Z' after 0 ns when to_X01(t) = '1'; + iob <= 'X' after 0 ns when to_X01(t) = 'X' else + not I after 0 ns when (to_X01(t) = '0') else + 'Z' after 0 ns when to_X01(t) = '1'; + o <= to_X01(io) after 0 ns; end; library ieee; @@ -299,9 +299,9 @@ entity OBUFT is generic ( end; architecture beh of OBUFT is begin - o <= I after 2 ns when to_X01(t) = '0' else - 'Z' after 2 ns when to_X01(t) = '1' else - 'X' after 2 ns ; + o <= I after 0 ns when to_X01(t) = '0' else + 'Z' after 0 ns when to_X01(t) = '1' else + 'X' after 0 ns ; end; library ieee; use ieee.std_logic_1164.all; @@ -314,8 +314,8 @@ architecture beh of IBUFDS is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -326,8 +326,8 @@ architecture beh of IBUFDS_LVDS_25 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -338,8 +338,8 @@ architecture beh of IBUFDS_LVDS_33 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -350,8 +350,8 @@ architecture beh of IBUFGDS_LVDS_15 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -362,8 +362,8 @@ architecture beh of IBUFGDS_LVDS_18 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -374,8 +374,8 @@ architecture beh of IBUFGDS_LVDS_25 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -386,8 +386,8 @@ architecture beh of IBUFGDS_LVDS_33 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -402,8 +402,8 @@ architecture beh of IBUFGDS is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -415,8 +415,8 @@ entity OBUFDS is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS is begin - o <= to_X01(i) after 2 ns when SLEW = "SLOW" else to_X01(i) after 1 ns; - ob <= not to_X01(i) after 2 ns when SLEW = "SLOW" else not to_X01(i) after 1 ns; + o <= to_X01(i) after 0 ns when SLEW = "SLOW" else to_X01(i) after 0 ns; + ob <= not to_X01(i) after 0 ns when SLEW = "SLOW" else not to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -424,7 +424,7 @@ entity OBUFDS_LVDS_25 is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS_LVDS_25 is begin - o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; + o <= to_X01(i) after 0 ns; ob <= not to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -432,7 +432,7 @@ entity OBUFDS_LVDS_33 is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS_LVDS_33 is begin - o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; + o <= to_X01(i) after 0 ns; ob <= not to_X01(i) after 1 ns; end; ----- CELL BUFGCE ----- @@ -4802,7 +4802,7 @@ architecture IDELAY_V OF IDELAY is end; ----------------------------------------------------------- - constant SYNC_PATH_DELAY : time := 100 ps; + constant SYNC_PATH_DELAY : time := 0 ps; constant MIN_TAP_COUNT : integer := 0; constant MAX_TAP_COUNT : integer := 63; diff --git a/lib/tech/unisim/ise/unisim_VCOMP.vhd b/lib/tech/unisim/ise/unisim_VCOMP.vhd index 61d42eb9..09a2d5b0 100644 --- a/lib/tech/unisim/ise/unisim_VCOMP.vhd +++ b/lib/tech/unisim/ise/unisim_VCOMP.vhd @@ -2,7 +2,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/unisim/ise/unisim_VITAL.vhd b/lib/tech/unisim/ise/unisim_VITAL.vhd index 2b988957..323cf793 100644 --- a/lib/tech/unisim/ise/unisim_VITAL.vhd +++ b/lib/tech/unisim/ise/unisim_VITAL.vhd @@ -238,13 +238,13 @@ entity IBUFG is generic ( IBUF_LOW_PWR : boolean := TRUE; IOSTANDARD : string := "LVCMOS25"); port (O : out std_logic; I : in std_logic); end; -architecture beh of IBUFG is begin o <= to_X01(i) after 1 ns; end; +architecture beh of IBUFG is begin o <= to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; entity IBUF is generic ( CAPACITANCE : string := "DONT_CARE"; IOSTANDARD : string := "LVCMOS25"); port (O : out std_logic; I : in std_logic); end; -architecture beh of IBUF is begin o <= to_X01(i) after 1 ns; end; +architecture beh of IBUF is begin o <= to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -253,7 +253,7 @@ entity OBUF is generic ( IOSTANDARD : string := "LVCMOS25"; SLEW : string := "SLOW"); port (O : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUF is -begin o <= to_X01(i) after 2 ns when slew = "SLOW" else to_X01(i) after 1 ns; end; +begin o <= to_X01(i) after 0 ns when slew = "SLOW" else to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -266,10 +266,10 @@ entity IOBUF is generic ( end; architecture beh of IOBUF is begin - io <= 'X' after 2 ns when to_X01(t) = 'X' else - I after 2 ns when (to_X01(t) = '0') else - 'Z' after 2 ns when to_X01(t) = '1'; - o <= to_X01(io) after 1 ns; + io <= 'X' after 0 ns when to_X01(t) = 'X' else + I after 0 ns when (to_X01(t) = '0') else + 'Z' after 0 ns when to_X01(t) = '1'; + o <= to_X01(io) after 0 ns; end; library ieee; @@ -281,13 +281,13 @@ entity IOBUFDS is generic ( end; architecture beh of IOBUFDS is begin - io <= 'X' after 2 ns when to_X01(t) = 'X' else - I after 2 ns when (to_X01(t) = '0') else - 'Z' after 2 ns when to_X01(t) = '1'; - iob <= 'X' after 2 ns when to_X01(t) = 'X' else - not I after 2 ns when (to_X01(t) = '0') else - 'Z' after 2 ns when to_X01(t) = '1'; - o <= to_X01(io) after 1 ns; + io <= 'X' after 0 ns when to_X01(t) = 'X' else + I after 0 ns when (to_X01(t) = '0') else + 'Z' after 0 ns when to_X01(t) = '1'; + iob <= 'X' after 0 ns when to_X01(t) = 'X' else + not I after 0 ns when (to_X01(t) = '0') else + 'Z' after 0 ns when to_X01(t) = '1'; + o <= to_X01(io) after 0 ns; end; library ieee; @@ -299,9 +299,9 @@ entity OBUFT is generic ( end; architecture beh of OBUFT is begin - o <= I after 2 ns when to_X01(t) = '0' else - 'Z' after 2 ns when to_X01(t) = '1' else - 'X' after 2 ns ; + o <= I after 0 ns when to_X01(t) = '0' else + 'Z' after 0 ns when to_X01(t) = '1' else + 'X' after 0 ns ; end; library ieee; use ieee.std_logic_1164.all; @@ -314,8 +314,8 @@ architecture beh of IBUFDS is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -326,8 +326,8 @@ architecture beh of IBUFDS_LVDS_25 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -338,8 +338,8 @@ architecture beh of IBUFDS_LVDS_33 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -350,8 +350,8 @@ architecture beh of IBUFGDS_LVDS_15 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -362,8 +362,8 @@ architecture beh of IBUFGDS_LVDS_18 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -374,8 +374,8 @@ architecture beh of IBUFGDS_LVDS_25 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -386,8 +386,8 @@ architecture beh of IBUFGDS_LVDS_33 is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -402,8 +402,8 @@ architecture beh of IBUFGDS is signal old : std_ulogic; begin - old <= '1' after 1 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else - '0' after 1 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; + old <= '1' after 0 ns when (to_X01(I) = '1') and (to_X01(IB) = '0') else + '0' after 0 ns when (to_X01(I) = '0') and (to_X01(IB) = '1') else old; o <= old; end; @@ -415,8 +415,8 @@ entity OBUFDS is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS is begin - o <= to_X01(i) after 2 ns when SLEW = "SLOW" else to_X01(i) after 1 ns; - ob <= not to_X01(i) after 2 ns when SLEW = "SLOW" else not to_X01(i) after 1 ns; + o <= to_X01(i) after 0 ns when SLEW = "SLOW" else to_X01(i) after 0 ns; + ob <= not to_X01(i) after 0 ns when SLEW = "SLOW" else not to_X01(i) after 0 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -424,7 +424,7 @@ entity OBUFDS_LVDS_25 is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS_LVDS_25 is begin - o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; + o <= to_X01(i) after 0 ns; ob <= not to_X01(i) after 1 ns; end; library ieee; use ieee.std_logic_1164.all; @@ -432,7 +432,7 @@ entity OBUFDS_LVDS_33 is port (O, OB : out std_ulogic; I : in std_ulogic); end; architecture beh of OBUFDS_LVDS_33 is begin - o <= to_X01(i) after 1 ns; ob <= not to_X01(i) after 1 ns; + o <= to_X01(i) after 0 ns; ob <= not to_X01(i) after 1 ns; end; ----- CELL BUFGCE ----- @@ -4802,7 +4802,7 @@ architecture IDELAY_V OF IDELAY is end; ----------------------------------------------------------- - constant SYNC_PATH_DELAY : time := 100 ps; + constant SYNC_PATH_DELAY : time := 0 ps; constant MIN_TAP_COUNT : integer := 0; constant MAX_TAP_COUNT : integer := 63; diff --git a/lib/tech/virage/simprims/virage_simprims.vhd b/lib/tech/virage/simprims/virage_simprims.vhd index cc0c6710..07cbc14f 100644 --- a/lib/tech/virage/simprims/virage_simprims.vhd +++ b/lib/tech/virage/simprims/virage_simprims.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/tech/virage/vcomponents/virage_vcomponents.vhd b/lib/tech/virage/vcomponents/virage_vcomponents.vhd index 453220da..a25316e8 100644 --- a/lib/tech/virage/vcomponents/virage_vcomponents.vhd +++ b/lib/tech/virage/vcomponents/virage_vcomponents.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/altera_mf/clkgen_altera_mf.vhd b/lib/techmap/altera_mf/clkgen_altera_mf.vhd index 0c9bf62d..a5e32a27 100644 --- a/lib/techmap/altera_mf/clkgen_altera_mf.vhd +++ b/lib/techmap/altera_mf/clkgen_altera_mf.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/altera_mf/memory_altera_mf.vhd b/lib/techmap/altera_mf/memory_altera_mf.vhd index bb016b23..e62dc887 100644 --- a/lib/techmap/altera_mf/memory_altera_mf.vhd +++ b/lib/techmap/altera_mf/memory_altera_mf.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -266,5 +266,105 @@ begin byteena_a => enablex ); end; +library ieee; +use ieee.std_logic_1164.all; +-- pragma translate_off +library altera_mf; +use altera_mf.dcfifo; +-- pragma translate_on + +entity altera_fifo_dp is + generic ( + tech : integer := 0; + abits : integer := 4; + dbits : integer := 32 + ); + port ( + rdclk : in std_logic; + rdreq : in std_logic; + rdfull : out std_logic; + rdempty : out std_logic; + rdusedw : out std_logic_vector(abits-1 downto 0); + q : out std_logic_vector(dbits-1 downto 0); + wrclk : in std_logic; + wrreq : in std_logic; + wrfull : out std_logic; + wrempty : out std_logic; + wrusedw : out std_logic_vector(abits-1 downto 0); + data : in std_logic_vector(dbits-1 downto 0); + aclr : in std_logic := '0'); +end; + +architecture behav of altera_fifo_dp is + + component dcfifo + generic ( + lpm_width : natural; + lpm_widthu : natural; + lpm_numwords : natural; + lpm_showahead : string := "OFF"; + lpm_hint : string := "USE_EAB=ON"; + overflow_checking : string := "ON"; + underflow_checking : string := "ON"; + delay_rdusedw : natural := 1; + delay_wrusedw : natural := 1; + rdsync_delaypipe : natural := 0; + wrsync_delaypipe : natural := 0; + use_eab : string := "ON"; + add_ram_output_register : string := "OFF"; + add_width : natural := 1; + clocks_are_synchronized : string := "FALSE"; + ram_block_type : string := "AUTO"; + add_usedw_msb_bit : string := "OFF"; + write_aclr_synch : string := "OFF"; + lpm_type : string := "dcfifo"; + intended_device_family : string := "NON_STRATIX" ); + port ( + data : in std_logic_vector(lpm_width-1 downto 0); + rdclk : in std_logic; + wrclk : in std_logic; + wrreq : in std_logic; + rdreq : in std_logic; + aclr : in std_logic := '0'; + rdfull : out std_logic; + wrfull : out std_logic; + wrempty : out std_logic; + rdempty : out std_logic; + q : out std_logic_vector(lpm_width-1 downto 0); + rdusedw : out std_logic_vector(lpm_widthu-1 downto 0); + wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) ); + end component; +begin + + u0 : dcfifo + generic map ( + intended_device_family => "STRATIX IV", + lpm_numwords => 2**abits, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => dbits, + lpm_widthu => abits, + overflow_checking => "ON", + rdsync_delaypipe => 4, + underflow_checking => "ON", + use_eab => "ON", + wrsync_delaypipe => 4 + ) + port map ( + rdclk => rdclk, + rdreq => rdreq, + rdfull => rdfull, + rdempty => rdempty, + rdusedw => rdusedw, + q => q, + wrclk => wrclk, + wrreq => wrreq, + wrfull => wrfull, + wrempty => wrempty, + wrusedw => wrusedw, + data => data, + aclr => aclr + ); +end; diff --git a/lib/techmap/altera_mf/tap_altera_mf.vhd b/lib/techmap/altera_mf/tap_altera_mf.vhd index bb9ae47c..119059d6 100644 --- a/lib/techmap/altera_mf/tap_altera_mf.vhd +++ b/lib/techmap/altera_mf/tap_altera_mf.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/atc18/pads_atc18.vhd b/lib/techmap/atc18/pads_atc18.vhd index 08094d31..f18c0651 100644 --- a/lib/techmap/atc18/pads_atc18.vhd +++ b/lib/techmap/atc18/pads_atc18.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd b/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd index 880c5e56..ba0068de 100644 --- a/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd +++ b/lib/techmap/cycloneiii/cycloneiii_clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd b/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd index ef9b5ac8..1710c474 100644 --- a/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd +++ b/lib/techmap/cycloneiii/cycloneiii_ddr_phy.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/dware/mul_dware.vhd b/lib/techmap/dware/mul_dware.vhd index 08a9ae3b..0c8f3d0d 100644 --- a/lib/techmap/dware/mul_dware.vhd +++ b/lib/techmap/dware/mul_dware.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/ec/ddr_ec.vhd b/lib/techmap/ec/ddr_ec.vhd index 8f25ba72..3e5c442d 100644 --- a/lib/techmap/ec/ddr_ec.vhd +++ b/lib/techmap/ec/ddr_ec.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/ec/memory_ec.vhd b/lib/techmap/ec/memory_ec.vhd index 991bffe4..7b152b38 100644 --- a/lib/techmap/ec/memory_ec.vhd +++ b/lib/techmap/ec/memory_ec.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/eclipsee/memory_eclipse.vhd b/lib/techmap/eclipsee/memory_eclipse.vhd index 94aae86a..e1736b51 100644 --- a/lib/techmap/eclipsee/memory_eclipse.vhd +++ b/lib/techmap/eclipsee/memory_eclipse.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/gencomp/gencomp.vhd b/lib/techmap/gencomp/gencomp.vhd index b91823ca..88f0508b 100644 --- a/lib/techmap/gencomp/gencomp.vhd +++ b/lib/techmap/gencomp/gencomp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -182,6 +182,10 @@ constant has_sram_2pbw : tech_ability_type := ( constant has_srambw : tech_ability_type := (easic45 => 1, others => 0); +constant has_2pfifo : tech_ability_type := ( + altera => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1, + stratix4 => 1, others => 0); + -- ram_raw_latency - describes how many edges on the write-port clock that -- must pass before data is commited to memory. for example, if the write data -- is commited to memory on the falling edge after a write cycle, and is @@ -696,6 +700,28 @@ constant dci : integer := 5; data: out std_logic_vector(7 downto 0)); end component; + component syncfifo_2p is + generic ( + tech : integer := 0; + abits : integer := 6; + dbits : integer := 8 + ); + port ( + rclk : in std_logic; + renable : in std_logic; + rfull : out std_logic; + rempty : out std_logic; + rusedw : out std_logic_vector(abits-1 downto 0); + datain : in std_logic_vector(dbits-1 downto 0); + wclk : in std_logic; + write : in std_logic; + wfull : out std_logic; + wempty : out std_logic; + wusedw : out std_logic_vector(abits-1 downto 0); + dataout : out std_logic_vector(dbits-1 downto 0) + ); + end component; + --------------------------------------------------------------------------- -- PADS --------------------------------------------------------------------------- @@ -943,7 +969,9 @@ component lvds_combo is odval, osval, en : in std_logic_vector(0 to width-1); idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1); idval, isval : out std_logic_vector(0 to width-1); - lvdsref : in std_logic := '1' + powerdown : in std_logic_vector(0 to width-1) := (others => '0'); + powerdownrx : in std_logic_vector(0 to width-1) := (others => '0'); + lvdsref : in std_logic := '1'; lvdsrefo : out std_logic ); end component; @@ -1959,5 +1987,30 @@ component sdram_phy ); end component; +------------------------------------------------------------------------------- +-- GIGABIT ETHERNET SERDES +------------------------------------------------------------------------------- + +component serdes is + generic ( + tech : integer + ); + port ( + clk_125 : in std_logic; + rst_125 : in std_logic; + rx_in : in std_logic; -- SER IN + rx_out : out std_logic_vector(9 downto 0); -- PAR OUT + rx_clk : out std_logic; + rx_rstn : out std_logic; + rx_pll_clk : out std_logic; + rx_pll_rstn : out std_logic; + tx_pll_clk : out std_logic; + tx_pll_rstn : out std_logic; + tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN + tx_out : out std_logic; -- SER OUT + bitslip : in std_logic + ); +end component; + end; diff --git a/lib/techmap/gencomp/netcomp.vhd b/lib/techmap/gencomp/netcomp.vhd index 2c105e17..8103a366 100644 --- a/lib/techmap/gencomp/netcomp.vhd +++ b/lib/techmap/gencomp/netcomp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -306,22 +306,36 @@ end component; component grspwc2_net is generic( - rmap : integer range 0 to 2 := 0; - rmapcrc : integer range 0 to 1 := 0; - fifosize1 : integer range 4 to 32 := 32; - fifosize2 : integer range 16 to 64 := 64; - rxunaligned : integer range 0 to 1 := 0; - rmapbufs : integer range 2 to 8 := 4; - scantest : integer range 0 to 1 := 0; - ports : integer range 1 to 2 := 1; - dmachan : integer range 1 to 4 := 1; - tech : integer; - input_type : integer range 0 to 4 := 0; - output_type : integer range 0 to 2 := 0; - rxtx_sameclk : integer range 0 to 1 := 0; - nodeaddr : integer range 0 to 255 := 254; - destkey : integer range 0 to 255 := 0 - ); + rmap : integer range 0 to 2 := 0; + rmapcrc : integer range 0 to 1 := 0; + fifosize1 : integer range 4 to 32 := 32; + fifosize2 : integer range 16 to 64 := 64; + rxunaligned : integer range 0 to 1 := 0; + rmapbufs : integer range 2 to 8 := 4; + scantest : integer range 0 to 1 := 0; + ports : integer range 1 to 2 := 1; + dmachan : integer range 1 to 4 := 1; + tech : integer; + input_type : integer range 0 to 4 := 0; + output_type : integer range 0 to 2 := 0; + rxtx_sameclk : integer range 0 to 1 := 0; + nodeaddr : integer range 0 to 255 := 254; + destkey : integer range 0 to 255 := 0; + interruptdist : integer range 0 to 32 := 0; + intscalerbits : integer range 0 to 31 := 0; + intisrtimerbits : integer range 0 to 31 := 0; + intiatimerbits : integer range 0 to 31 := 0; + intctimerbits : integer range 0 to 31 := 0; + tickinasync : integer range 0 to 1 := 0; + pnp : integer range 0 to 2 := 0; + pnpvendid : integer range 0 to 16#FFFF# := 0; + pnpprodid : integer range 0 to 16#FFFF# := 0; + pnpmajorver : integer range 0 to 16#FF# := 0; + pnpminorver : integer range 0 to 16#FF# := 0; + pnppatch : integer range 0 to 16#FF# := 0; + num_txdesc : integer range 64 to 512 := 64; + num_rxdesc : integer range 128 to 1024 := 128 + ); port( rst : in std_ulogic; clk : in std_ulogic; @@ -377,17 +391,17 @@ component grspwc2_net is rmapnodeaddr : in std_logic_vector(7 downto 0); --rx ahb fifo rxrenable : out std_ulogic; - rxraddress : out std_logic_vector(4 downto 0); + rxraddress : out std_logic_vector(5 downto 0); rxwrite : out std_ulogic; rxwdata : out std_logic_vector(31 downto 0); - rxwaddress : out std_logic_vector(4 downto 0); + rxwaddress : out std_logic_vector(5 downto 0); rxrdata : in std_logic_vector(31 downto 0); --tx ahb fifo txrenable : out std_ulogic; - txraddress : out std_logic_vector(4 downto 0); + txraddress : out std_logic_vector(5 downto 0); txwrite : out std_ulogic; txwdata : out std_logic_vector(31 downto 0); - txwaddress : out std_logic_vector(4 downto 0); + txwaddress : out std_logic_vector(5 downto 0); txrdata : in std_logic_vector(31 downto 0); --nchar fifo ncrenable : out std_ulogic; @@ -409,7 +423,18 @@ component grspwc2_net is testen : in std_logic; rxdav : out std_logic; rxdataout : out std_logic_vector(8 downto 0); - loopback : out std_logic + loopback : out std_logic; + -- interrupt dist. default values + intpreload : in std_logic_vector(30 downto 0); + inttreload : in std_logic_vector(30 downto 0); + intiareload : in std_logic_vector(30 downto 0); + intcreload : in std_logic_vector(30 downto 0); + irqtxdefault : in std_logic_vector(4 downto 0); + --SpW PnP enable + pnpen : in std_ulogic; + pnpuvendid : in std_logic_vector(15 downto 0); + pnpuprodid : in std_logic_vector(15 downto 0); + pnpusn : in std_logic_vector(31 downto 0) ); end component; @@ -690,89 +715,6 @@ end component; end component; -component ftmctrl_net - generic ( - hindex : integer := 0; - pindex : integer := 0; - romaddr : integer := 16#000#; - rommask : integer := 16#E00#; - ioaddr : integer := 16#200#; - iomask : integer := 16#E00#; - ramaddr : integer := 16#400#; - rammask : integer := 16#C00#; - paddr : integer := 0; - pmask : integer := 16#fff#; - wprot : integer := 0; - invclk : integer := 0; - fast : integer := 0; - romasel : integer := 28; - sdrasel : integer := 29; - srbanks : integer := 4; - ram8 : integer := 0; - ram16 : integer := 0; - sden : integer := 0; - sepbus : integer := 0; - sdbits : integer := 32; - sdlsb : integer := 2; -- set to 12 for the GE-HPE board - oepol : integer := 0; - edac : integer := 0; - syncrst : integer := 0; - pageburst : integer := 0; - scantest : integer := 0; - writefb : integer := 0; - wsshift : integer := 0; - tech : integer := 0 - ); - port ( - rst: in Std_ULogic; - clk: in Std_ULogic; - ahbsi: in ahb_slv_in_type; - ahbso: out ahb_slv_out_type; - apbi: in apb_slv_in_type; - apbo: out apb_slv_out_type; - memi_data: in Std_Logic_Vector(31 downto 0); - memi_brdyn: in Std_Logic; - memi_bexcn: in Std_Logic; - memi_writen: in Std_Logic; - memi_wrn: in Std_Logic_Vector(3 downto 0); - memi_bwidth: in Std_Logic_Vector(1 downto 0); - memi_sd: in Std_Logic_Vector(63 downto 0); - memi_cb: in Std_Logic_Vector(15 downto 0); - memi_scb: in Std_Logic_Vector(15 downto 0); - memi_edac: in Std_Logic; - memo_address: out Std_Logic_Vector(31 downto 0); - memo_data: out Std_Logic_Vector(31 downto 0); - memo_sddata: out Std_Logic_Vector(63 downto 0); - memo_ramsn: out Std_Logic_Vector(7 downto 0); - memo_ramoen: out Std_Logic_Vector(7 downto 0); - memo_ramn: out Std_ULogic; - memo_romn: out Std_ULogic; - memo_mben: out Std_Logic_Vector(3 downto 0); - memo_iosn: out Std_Logic; - memo_romsn: out Std_Logic_Vector(7 downto 0); - memo_oen: out Std_Logic; - memo_writen: out Std_Logic; - memo_wrn: out Std_Logic_Vector(3 downto 0); - memo_bdrive: out Std_Logic_Vector(3 downto 0); - memo_vbdrive: out Std_Logic_Vector(31 downto 0); - memo_svbdrive: out Std_Logic_Vector(63 downto 0); - memo_read: out Std_Logic; - memo_sa: out Std_Logic_Vector(14 downto 0); - memo_cb: out Std_Logic_Vector(15 downto 0); - memo_scb: out Std_Logic_Vector(15 downto 0); - memo_vcdrive: out Std_Logic_Vector(15 downto 0); - memo_svcdrive: out Std_Logic_Vector(15 downto 0); - memo_ce: out Std_ULogic; - sdo_sdcke: out Std_Logic_Vector( 1 downto 0); - sdo_sdcsn: out Std_Logic_Vector( 1 downto 0); - sdo_sdwen: out Std_ULogic; - sdo_rasn: out Std_ULogic; - sdo_casn: out Std_ULogic; - sdo_dqm: out Std_Logic_Vector( 7 downto 0); - wpo_wprothit: in Std_ULogic); - -end component; - component ssrctrl_net generic ( tech: Integer := 0; diff --git a/lib/techmap/grdware/mul_dware.vhd b/lib/techmap/grdware/mul_dware.vhd index 90ddc2ab..5e641429 100644 --- a/lib/techmap/grdware/mul_dware.vhd +++ b/lib/techmap/grdware/mul_dware.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/inferred/ddr_inferred.vhd b/lib/techmap/inferred/ddr_inferred.vhd index 5db3c8e8..df619bd3 100644 --- a/lib/techmap/inferred/ddr_inferred.vhd +++ b/lib/techmap/inferred/ddr_inferred.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/inferred/ddr_phy_inferred.vhd b/lib/techmap/inferred/ddr_phy_inferred.vhd index 1a8253cf..a1cec6ca 100644 --- a/lib/techmap/inferred/ddr_phy_inferred.vhd +++ b/lib/techmap/inferred/ddr_phy_inferred.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/inferred/ddrphy_datapath.vhd b/lib/techmap/inferred/ddrphy_datapath.vhd index 811d45f5..01b1bfda 100644 --- a/lib/techmap/inferred/ddrphy_datapath.vhd +++ b/lib/techmap/inferred/ddrphy_datapath.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/inferred/lpddr2_phy_inferred.vhd b/lib/techmap/inferred/lpddr2_phy_inferred.vhd index 4c5e90fe..ee4ce123 100644 --- a/lib/techmap/inferred/lpddr2_phy_inferred.vhd +++ b/lib/techmap/inferred/lpddr2_phy_inferred.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -182,7 +182,10 @@ begin ddr_dqs_out <= (others => dqsout); ddr_dqs_oen <= (others => dqsoen); - ddr_dq_oen <= (others => dqoen); + ddr_dqs_oen <= (others => dqsoen or (not rst) or (not llock)) when oepol=0 else + (others => (not dqsoen) and rst and llock); + ddr_dq_oen <= (others => dqoen or (not rst) or (not llock)) when oepol=0 else + (others => (not dqoen) and rst and llock); ddr_clk <= (others => gextclk); ddr_clkb <= (others => gextclkn); dqsiend <= dqsien after tdqsck; diff --git a/lib/techmap/inferred/memory_inferred.vhd b/lib/techmap/inferred/memory_inferred.vhd index a084838d..3e06ead5 100644 --- a/lib/techmap/inferred/memory_inferred.vhd +++ b/lib/techmap/inferred/memory_inferred.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/inferred/mul_inferred.vhd b/lib/techmap/inferred/mul_inferred.vhd index 23a4bf68..eb5225d3 100644 --- a/lib/techmap/inferred/mul_inferred.vhd +++ b/lib/techmap/inferred/mul_inferred.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/inferred/sim_pll.vhd b/lib/techmap/inferred/sim_pll.vhd index 9987b377..22d0685e 100644 --- a/lib/techmap/inferred/sim_pll.vhd +++ b/lib/techmap/inferred/sim_pll.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/allclkgen.vhd b/lib/techmap/maps/allclkgen.vhd index ba197431..ab7d8a11 100644 --- a/lib/techmap/maps/allclkgen.vhd +++ b/lib/techmap/maps/allclkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -545,13 +545,6 @@ component clkand_dare ); end component; -component clkmux_dare - port ( - i0, i1 : in std_ulogic; - sel : in std_ulogic; - o : out std_ulogic); -end component; - component clkmux_rhumc port ( i0, i1 : in std_ulogic; @@ -595,6 +588,14 @@ end component; lock : out std_ulogic); end component; +component clkmux_dare + port( + i0 : in std_ulogic; + i1 : in std_ulogic; + sel : in std_ulogic; + o : out std_ulogic); +end component; + component clkmux_rhlib18t port( i0 : in std_ulogic; @@ -666,6 +667,8 @@ component clkgen_ut130hbd clk : out std_ulogic; -- main clock clkn : out std_ulogic; -- inverted main clock clk2x : out std_ulogic; -- double clock + clk4x : out std_ulogic; + clk8x : out std_ulogic; sdclk : out std_ulogic; -- SDRAM clock pciclk : out std_ulogic; -- PCI clock cgi : in clkgen_in_type; diff --git a/lib/techmap/maps/allddr.vhd b/lib/techmap/maps/allddr.vhd index 5cfb57cf..bfb8017a 100644 --- a/lib/techmap/maps/allddr.vhd +++ b/lib/techmap/maps/allddr.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -30,6 +30,19 @@ use techmap.gencomp.all; package allddr is +component rhumc_iddr_reg is + port( + Q1 : out std_ulogic; + Q2 : out std_ulogic; + C1 : in std_ulogic; + C2 : in std_ulogic; + CE : in std_ulogic; + D : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic + ); +end component; + component unisim_iddr_reg is generic ( tech : integer := virtex4; arch : integer := 0); port( @@ -56,6 +69,18 @@ component gen_iddr_reg S : in std_ulogic); end component; +component rhumc_oddr_reg + port ( + Q : out std_ulogic; + C1 : in std_ulogic; + C2 : in std_ulogic; + CE : in std_ulogic; + D1 : in std_ulogic; + D2 : in std_ulogic; + R : in std_ulogic; + S : in std_ulogic); +end component; + component ec_oddr_reg port ( Q : out std_ulogic; diff --git a/lib/techmap/maps/allmem.vhd b/lib/techmap/maps/allmem.vhd index 60cef4e3..a462799e 100644 --- a/lib/techmap/maps/allmem.vhd +++ b/lib/techmap/maps/allmem.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -449,6 +449,24 @@ component altera_syncram_dp ); end component; +component altera_fifo_dp is + generic (tech : integer := 0; abits : integer := 4; dbits : integer := 32); + port ( + rdclk : in std_logic; + rdreq : in std_logic; + rdfull : out std_logic; + rdempty : out std_logic; + rdusedw : out std_logic_vector(abits-1 downto 0); + q : out std_logic_vector(dbits-1 downto 0); + wrclk : in std_logic; + wrreq : in std_logic; + wrfull : out std_logic; + wrempty : out std_logic; + wrusedw : out std_logic_vector(abits-1 downto 0); + data : in std_logic_vector(dbits-1 downto 0); + aclr : in std_logic := '0'); +end component; + component generic_syncram generic (abits : integer := 10; dbits : integer := 8 ); port ( diff --git a/lib/techmap/maps/allmul.vhd b/lib/techmap/maps/allmul.vhd index 506712e8..e484e74d 100644 --- a/lib/techmap/maps/allmul.vhd +++ b/lib/techmap/maps/allmul.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/allpads.vhd b/lib/techmap/maps/allpads.vhd index f91950b5..3b92c0bf 100644 --- a/lib/techmap/maps/allpads.vhd +++ b/lib/techmap/maps/allpads.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -652,7 +652,10 @@ component ut130hbd_lvds_combo port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1); odval, osval, en : in std_logic_vector(0 to width-1); idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1); - idval, isval : out std_logic_vector(0 to width-1)); + idval, isval : out std_logic_vector(0 to width-1); + powerdown : in std_logic_vector(0 to width-1); + powerdownrx : in std_logic_vector(0 to width-1); + lvdsref : out std_logic); end component; component ut90nhbd_inpad is @@ -710,7 +713,9 @@ component rhumc_lvds_combo odval, osval, en : in std_logic_vector(0 to width-1); idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1); idval, isval : out std_logic_vector(0 to width-1); - lvdsref : in std_logic); + powerdown : in std_logic_vector(0 to width-1); + powerdownrx : in std_logic_vector(0 to width-1); + lvdsref : out std_logic); end component; component umc_lvds_combo diff --git a/lib/techmap/maps/alltap.vhd b/lib/techmap/maps/alltap.vhd index 2eb4fc38..0324a432 100644 --- a/lib/techmap/maps/alltap.vhd +++ b/lib/techmap/maps/alltap.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/clkand.vhd b/lib/techmap/maps/clkand.vhd index 9eb7f035..400a83fc 100644 --- a/lib/techmap/maps/clkand.vhd +++ b/lib/techmap/maps/clkand.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/clkgen.vhd b/lib/techmap/maps/clkgen.vhd index c2110257..908e1bce 100644 --- a/lib/techmap/maps/clkgen.vhd +++ b/lib/techmap/maps/clkgen.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -225,7 +225,7 @@ begin ut13 : if (tech = ut130) generate v : clkgen_ut130hbd generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel) - port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu); + port map (clkin, pciclkin, clk, clkn, clk2x, clk4x, clk8x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu); end generate; ut90nhbd : if (tech = ut90) generate v : clkgen_ut90nhbd diff --git a/lib/techmap/maps/clkinv.vhd b/lib/techmap/maps/clkinv.vhd index 57ec4457..da6c6823 100644 --- a/lib/techmap/maps/clkinv.vhd +++ b/lib/techmap/maps/clkinv.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -17,9 +17,9 @@ -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----------------------------------------------------------------------------- --- Entity: clkinv --- File: clkinv.vhd --- Author: Fredrik Ringhage - Aeroflex Gaisler Research +-- Entity: clkinv +-- File: clkinv.vhd +-- Author: Fredrik Ringhage - Aeroflex Gaisler Research -- Description: SET protected inverters for clock tree ------------------------------------------------------------------------------ diff --git a/lib/techmap/maps/clkmux.vhd b/lib/techmap/maps/clkmux.vhd index 5f5b1637..9caf7745 100644 --- a/lib/techmap/maps/clkmux.vhd +++ b/lib/techmap/maps/clkmux.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/clkpad.vhd b/lib/techmap/maps/clkpad.vhd index a14c7674..6c04b362 100644 --- a/lib/techmap/maps/clkpad.vhd +++ b/lib/techmap/maps/clkpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -69,7 +69,7 @@ begin u0 : umc_inpad generic map (level, voltage) port map (pad, o); lock <= '1'; end generate; rhu : if (tech = rhumc) generate - u0 : rhumc_inpad generic map (level, voltage) port map (pad, o); lock <= '1'; + u0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o); lock <= '1'; end generate; saed : if (tech = saed32) generate u0 : saed32_inpad generic map (level, voltage) port map (pad, o); lock <= '1'; diff --git a/lib/techmap/maps/clkpad_ds.vhd b/lib/techmap/maps/clkpad_ds.vhd index 44b0037c..643afde4 100644 --- a/lib/techmap/maps/clkpad_ds.vhd +++ b/lib/techmap/maps/clkpad_ds.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/cpu_disas_net.vhd b/lib/techmap/maps/cpu_disas_net.vhd index 0d7af9bb..cecf3c15 100644 --- a/lib/techmap/maps/cpu_disas_net.vhd +++ b/lib/techmap/maps/cpu_disas_net.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/ddr_ireg.vhd b/lib/techmap/maps/ddr_ireg.vhd index dddb576e..ea604a42 100644 --- a/lib/techmap/maps/ddr_ireg.vhd +++ b/lib/techmap/maps/ddr_ireg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -44,7 +44,8 @@ architecture rtl of ddr_ireg is begin inf : if not((is_unisim(tech) = 1) or (tech = axcel) or - (tech = axdsp) or (tech = apa3) or (tech = apa3e) or (tech = apa3l)) generate + (tech = axdsp) or (tech = apa3) or (tech = apa3e) or + (tech = apa3l) or (tech = rhumc)) generate inf0 : gen_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S); end generate; @@ -68,6 +69,10 @@ begin xil0 : unisim_iddr_reg generic map (tech, arch) port map (Q1, Q2, C1, C2, CE, D, R, S); end generate; + rhu : if (tech = rhumc) generate + rhu0: rhumc_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S); + end generate; + --pragma translate_off assert (tech /= easic45) and (tech /= easic90) report "ddr_ireg: Not supported on eASIC. Use DDR pad instead." diff --git a/lib/techmap/maps/ddr_oreg.vhd b/lib/techmap/maps/ddr_oreg.vhd index 8d2f7661..9ed4d094 100644 --- a/lib/techmap/maps/ddr_oreg.vhd +++ b/lib/techmap/maps/ddr_oreg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/ddrphy.vhd b/lib/techmap/maps/ddrphy.vhd index 111f562c..3ce0ae9e 100644 --- a/lib/techmap/maps/ddrphy.vhd +++ b/lib/techmap/maps/ddrphy.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/grfpw_net.vhd b/lib/techmap/maps/grfpw_net.vhd index 51e56188..fb91f536 100644 --- a/lib/techmap/maps/grfpw_net.vhd +++ b/lib/techmap/maps/grfpw_net.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/grgates.vhd b/lib/techmap/maps/grgates.vhd index 6ac0f966..dd347085 100644 --- a/lib/techmap/maps/grgates.vhd +++ b/lib/techmap/maps/grgates.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/grlfpw_net.vhd b/lib/techmap/maps/grlfpw_net.vhd index 251bde4e..c840ecfc 100644 --- a/lib/techmap/maps/grlfpw_net.vhd +++ b/lib/techmap/maps/grlfpw_net.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/inpad.vhd b/lib/techmap/maps/inpad.vhd index 320f5359..c5ebf58c 100644 --- a/lib/techmap/maps/inpad.vhd +++ b/lib/techmap/maps/inpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/inpad_ddr.vhd b/lib/techmap/maps/inpad_ddr.vhd index 91aa4777..7711ba5e 100644 --- a/lib/techmap/maps/inpad_ddr.vhd +++ b/lib/techmap/maps/inpad_ddr.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/inpad_ds.vhd b/lib/techmap/maps/inpad_ds.vhd index 1d808e5b..b910ef33 100644 --- a/lib/techmap/maps/inpad_ds.vhd +++ b/lib/techmap/maps/inpad_ds.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/iodpad.vhd b/lib/techmap/maps/iodpad.vhd index ce110692..984f8dcb 100644 --- a/lib/techmap/maps/iodpad.vhd +++ b/lib/techmap/maps/iodpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/iopad.vhd b/lib/techmap/maps/iopad.vhd index 1cac2ac4..6e3e3613 100644 --- a/lib/techmap/maps/iopad.vhd +++ b/lib/techmap/maps/iopad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/iopad_ddr.vhd b/lib/techmap/maps/iopad_ddr.vhd index 12466634..cdbd346d 100644 --- a/lib/techmap/maps/iopad_ddr.vhd +++ b/lib/techmap/maps/iopad_ddr.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/iopad_ds.vhd b/lib/techmap/maps/iopad_ds.vhd index 2ce01080..db016778 100644 --- a/lib/techmap/maps/iopad_ds.vhd +++ b/lib/techmap/maps/iopad_ds.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/leon4_net.vhd b/lib/techmap/maps/leon4_net.vhd index ef011e4b..68660741 100644 --- a/lib/techmap/maps/leon4_net.vhd +++ b/lib/techmap/maps/leon4_net.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/lvds_combo.vhd b/lib/techmap/maps/lvds_combo.vhd index 8f292a15..d848f5e4 100644 --- a/lib/techmap/maps/lvds_combo.vhd +++ b/lib/techmap/maps/lvds_combo.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -36,7 +36,10 @@ entity lvds_combo is odval, osval, en : in std_logic_vector(0 to width-1); idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1); idval, isval : out std_logic_vector(0 to width-1); - lvdsref : in std_logic := '1' + powerdown : in std_logic_vector(0 to width-1) := (others => '0'); + powerdownrx : in std_logic_vector(0 to width-1) := (others => '0'); + lvdsref : in std_logic := '1'; + lvdsrefo : out std_logic ); end ; @@ -64,7 +67,7 @@ begin ut13 : if tech = ut130 generate u0: ut130hbd_lvds_combo generic map (voltage, width) port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen, - idpadp, idpadn, ispadp, ispadn, idval, isval); + idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo); end generate; um : if tech = umc generate u0: umc_lvds_combo generic map (voltage, width) @@ -74,7 +77,7 @@ begin rhu : if tech = rhumc generate u0: rhumc_lvds_combo generic map (voltage, width) port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen, - idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref); + idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo); end generate; end generate; end; diff --git a/lib/techmap/maps/mul_61x61.vhd b/lib/techmap/maps/mul_61x61.vhd index 31545783..83db7b65 100644 --- a/lib/techmap/maps/mul_61x61.vhd +++ b/lib/techmap/maps/mul_61x61.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/nandtree.vhd b/lib/techmap/maps/nandtree.vhd index 061d13a6..0595e19a 100644 --- a/lib/techmap/maps/nandtree.vhd +++ b/lib/techmap/maps/nandtree.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/odpad.vhd b/lib/techmap/maps/odpad.vhd index da885969..11ac7569 100644 --- a/lib/techmap/maps/odpad.vhd +++ b/lib/techmap/maps/odpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/outpad.vhd b/lib/techmap/maps/outpad.vhd index ac650164..4f389191 100644 --- a/lib/techmap/maps/outpad.vhd +++ b/lib/techmap/maps/outpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/outpad_ddr.vhd b/lib/techmap/maps/outpad_ddr.vhd index e353fd6d..6e0e4e48 100644 --- a/lib/techmap/maps/outpad_ddr.vhd +++ b/lib/techmap/maps/outpad_ddr.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/outpad_ds.vhd b/lib/techmap/maps/outpad_ds.vhd index 6654bd30..9cf4484a 100644 --- a/lib/techmap/maps/outpad_ds.vhd +++ b/lib/techmap/maps/outpad_ds.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/regfile_3p.vhd b/lib/techmap/maps/regfile_3p.vhd index 7c3310f1..513d1467 100644 --- a/lib/techmap/maps/regfile_3p.vhd +++ b/lib/techmap/maps/regfile_3p.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/ringosc.vhd b/lib/techmap/maps/ringosc.vhd index d8a5caf3..3af42534 100644 --- a/lib/techmap/maps/ringosc.vhd +++ b/lib/techmap/maps/ringosc.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -41,14 +41,24 @@ architecture rtl of ringosc is roout : out Std_ULogic); end component; + component ringosc_ut130hbd + port ( + roen : in Std_ULogic; + roout : out Std_ULogic); + end component; + begin dr : if tech = rhumc generate drx : ringosc_rhumc port map (roen, roout); end generate; + ut130r : if tech = ut130 generate + ut130rx : ringosc_ut130hbd port map (roen, roout); + end generate; + -- pragma translate_off - gen : if tech /= rhumc generate + gen : if tech /= rhumc and tech /= ut130 generate signal tmp : std_ulogic := '0'; begin tmp <= not tmp after 1 ns when roen = '1' else '0'; @@ -56,4 +66,4 @@ begin end generate; -- pragma translate_on -end architecture rtl; \ No newline at end of file +end architecture rtl; diff --git a/lib/techmap/maps/scanreg.vhd b/lib/techmap/maps/scanreg.vhd index 3dbc7359..c727c8e1 100644 --- a/lib/techmap/maps/scanreg.vhd +++ b/lib/techmap/maps/scanreg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/sdram_phy.vhd b/lib/techmap/maps/sdram_phy.vhd index b8348ec2..b39fd43d 100644 --- a/lib/techmap/maps/sdram_phy.vhd +++ b/lib/techmap/maps/sdram_phy.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/skew_outpad.vhd b/lib/techmap/maps/skew_outpad.vhd index 8af9077d..5bf0fedf 100644 --- a/lib/techmap/maps/skew_outpad.vhd +++ b/lib/techmap/maps/skew_outpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/spictrl_net.vhd b/lib/techmap/maps/spictrl_net.vhd index e206dce5..05d3d148 100644 --- a/lib/techmap/maps/spictrl_net.vhd +++ b/lib/techmap/maps/spictrl_net.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncfifo_2p.vhd b/lib/techmap/maps/syncfifo_2p.vhd new file mode 100644 index 00000000..4c710a22 --- /dev/null +++ b/lib/techmap/maps/syncfifo_2p.vhd @@ -0,0 +1,97 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: syncfifo_2p +-- File: syncfifo_2p.vhd +-- Author: Andrea Gianarro - Aeroflex Gaisler AB +-- Description: Syncronous 2-port fifo with tech selection +------------------------------------------------------------------------------ + +library ieee; +library techmap; +use ieee.std_logic_1164.all; +use techmap.gencomp.all; +use work.allmem.all; +library grlib; +use grlib.config.all; +use grlib.config_types.all; +use grlib.stdlib.all; + +entity syncfifo_2p is + generic ( + tech : integer := 0; + abits : integer := 6; + dbits : integer := 8 + ); + port ( + rclk : in std_logic; + renable : in std_logic; + rfull : out std_logic; + rempty : out std_logic; + rusedw : out std_logic_vector(abits-1 downto 0); + dataout : out std_logic_vector(dbits-1 downto 0); + wclk : in std_logic; + write : in std_logic; + wfull : out std_logic; + wempty : out std_logic; + wusedw : out std_logic_vector(abits-1 downto 0); + datain : in std_logic_vector(dbits-1 downto 0) + ); +end; + +architecture rtl of syncfifo_2p is +begin + + -- TO BE IMPLEMENTED +-- inf : if tech = inferred generate +-- x0 : generic_syncfifo_2p generic map (abits, dbits) +-- port map (rclk, renable, rfull, rempty, rusedw, dataout, wclk, +-- write, wfull, wempty, wusedw, datain); +-- end generate; + + alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or + (tech = stratix3) or (tech = stratix4) generate + x0 : altera_fifo_dp generic map (tech, abits, dbits) + port map (rclk, renable, rfull, rempty, rusedw, dataout, wclk, + write, wfull, wempty, wusedw, datain); + end generate; + +-- pragma translate_off + nofifo : if has_2pfifo(tech) = 0 generate + x : process + begin + assert false report "syncfifo_2p: technology " & tech_table(tech) & + " not supported" + severity failure; + wait; + end process; + end generate; + dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate + x : process + begin + assert false report "syncfifo_2p: " & tost(2**abits) & "x" & tost(dbits) & + " (" & tech_table(tech) & ")" + severity note; + wait; + end process; + end generate; +-- pragma translate_on + +end; + diff --git a/lib/techmap/maps/syncram.vhd b/lib/techmap/maps/syncram.vhd index e4c9d728..79232d2a 100644 --- a/lib/techmap/maps/syncram.vhd +++ b/lib/techmap/maps/syncram.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram128.vhd b/lib/techmap/maps/syncram128.vhd index 2fee44f2..0444cb15 100644 --- a/lib/techmap/maps/syncram128.vhd +++ b/lib/techmap/maps/syncram128.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram128bw.vhd b/lib/techmap/maps/syncram128bw.vhd index 94677859..2d709f34 100644 --- a/lib/techmap/maps/syncram128bw.vhd +++ b/lib/techmap/maps/syncram128bw.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram156bw.vhd b/lib/techmap/maps/syncram156bw.vhd index 87bd5146..1b3b64db 100644 --- a/lib/techmap/maps/syncram156bw.vhd +++ b/lib/techmap/maps/syncram156bw.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram256bw.vhd b/lib/techmap/maps/syncram256bw.vhd index 7024f2b4..41c2eac8 100644 --- a/lib/techmap/maps/syncram256bw.vhd +++ b/lib/techmap/maps/syncram256bw.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram64.vhd b/lib/techmap/maps/syncram64.vhd index 32fdffc0..3469b30d 100644 --- a/lib/techmap/maps/syncram64.vhd +++ b/lib/techmap/maps/syncram64.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram_2p.vhd b/lib/techmap/maps/syncram_2p.vhd index ea2cce22..7dd4c81e 100644 --- a/lib/techmap/maps/syncram_2p.vhd +++ b/lib/techmap/maps/syncram_2p.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram_2pbw.vhd b/lib/techmap/maps/syncram_2pbw.vhd index 22809484..ac6c3a1d 100644 --- a/lib/techmap/maps/syncram_2pbw.vhd +++ b/lib/techmap/maps/syncram_2pbw.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncram_dp.vhd b/lib/techmap/maps/syncram_dp.vhd index 63093d3b..e67f2589 100644 --- a/lib/techmap/maps/syncram_dp.vhd +++ b/lib/techmap/maps/syncram_dp.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncrambw.vhd b/lib/techmap/maps/syncrambw.vhd index 81b3b279..1f823b89 100644 --- a/lib/techmap/maps/syncrambw.vhd +++ b/lib/techmap/maps/syncrambw.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/syncreg.vhd b/lib/techmap/maps/syncreg.vhd index 7658f72b..27a36387 100644 --- a/lib/techmap/maps/syncreg.vhd +++ b/lib/techmap/maps/syncreg.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/system_monitor.vhd b/lib/techmap/maps/system_monitor.vhd index dc5ba185..216c8a10 100644 --- a/lib/techmap/maps/system_monitor.vhd +++ b/lib/techmap/maps/system_monitor.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/tap.vhd b/lib/techmap/maps/tap.vhd index 8a86190a..6b57753a 100644 --- a/lib/techmap/maps/tap.vhd +++ b/lib/techmap/maps/tap.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/techbuf.vhd b/lib/techmap/maps/techbuf.vhd index a5609d8d..028c70e0 100644 --- a/lib/techmap/maps/techbuf.vhd +++ b/lib/techmap/maps/techbuf.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/techmult.vhd b/lib/techmap/maps/techmult.vhd index ff555813..d138b94a 100644 --- a/lib/techmap/maps/techmult.vhd +++ b/lib/techmap/maps/techmult.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/toutpad.vhd b/lib/techmap/maps/toutpad.vhd index 781fcea6..57271e60 100644 --- a/lib/techmap/maps/toutpad.vhd +++ b/lib/techmap/maps/toutpad.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/toutpad_ds.vhd b/lib/techmap/maps/toutpad_ds.vhd index bb67f739..7e2d3953 100644 --- a/lib/techmap/maps/toutpad_ds.vhd +++ b/lib/techmap/maps/toutpad_ds.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/maps/vhdlsyn.txt b/lib/techmap/maps/vhdlsyn.txt index 5d7d3be7..324b1d39 100644 --- a/lib/techmap/maps/vhdlsyn.txt +++ b/lib/techmap/maps/vhdlsyn.txt @@ -6,6 +6,7 @@ allpads.vhd alltap.vhd clkgen.vhd clkmux.vhd +clkinv.vhd clkand.vhd ddr_ireg.vhd ddr_oreg.vhd @@ -17,6 +18,7 @@ syncram_dp.vhd syncramft.vhd syncram_2pft.vhd syncrambwft.vhd +syncfifo_2p.vhd regfile_3p.vhd tap.vhd techbuf.vhd @@ -36,7 +38,6 @@ cpu_disas_net.vhd grusbhc_net.vhd ringosc.vhd ssrctrl_net.vhd -ftmctrl_net.vhd ftsrctrl_net.vhd corepcif_net.vhd pci_arb_net.vhd @@ -57,4 +58,5 @@ sdram_phy.vhd from.vhd syncreg.vhd clkinv.vhd +serdes.vhd diff --git a/lib/techmap/saed32/clkgen_saed32.vhd b/lib/techmap/saed32/clkgen_saed32.vhd index 17e7aad1..f07c30a9 100644 --- a/lib/techmap/saed32/clkgen_saed32.vhd +++ b/lib/techmap/saed32/clkgen_saed32.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/saed32/memory_saed32.vhd b/lib/techmap/saed32/memory_saed32.vhd index c0c36ced..343a0118 100644 --- a/lib/techmap/saed32/memory_saed32.vhd +++ b/lib/techmap/saed32/memory_saed32.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -49,36 +49,36 @@ architecture rtl of saed32_syncram is component SRAM1RW64x32 is port ( A : in std_logic_vector( 5 downto 0 ); - O : out std_logic_vector( 31 downto 0 ); - I : in std_logic_vector( 31 downto 0 ); + CE : in std_logic; WEB : in std_logic; - CSB : in std_logic; OEB : in std_logic; - CE : in std_logic + CSB : in std_logic; + I : in std_logic_vector( 31 downto 0 ); + O : out std_logic_vector( 31 downto 0 ) ); end component; component SRAM1RW128x48 is port ( A : in std_logic_vector( 6 downto 0 ); - O : out std_logic_vector( 47 downto 0 ); - I : in std_logic_vector( 47 downto 0 ); + CE : in std_logic; WEB : in std_logic; - CSB : in std_logic; OEB : in std_logic; - CE : in std_logic + CSB : in std_logic; + I : in std_logic_vector( 47 downto 0 ); + O : out std_logic_vector( 47 downto 0 ) ); end component; component SRAM1RW1024x8 is port ( A : in std_logic_vector( 9 downto 0 ); - O : out std_logic_vector( 7 downto 0 ); - I : in std_logic_vector( 7 downto 0 ); + CE : in std_logic; WEB : in std_logic; - CSB : in std_logic; OEB : in std_logic; - CE : in std_logic + CSB : in std_logic; + I : in std_logic_vector( 7 downto 0 ); + O : out std_logic_vector( 7 downto 0 ) ); end component; @@ -92,27 +92,28 @@ begin csn <= not enable; wen <= not write; gnd <= (others => '0'); vcc <= '1'; + + a(17 downto abits) <= (others => '0'); + d(48 downto dbits) <= (others => '0'); + a(abits -1 downto 0) <= address; d(dbits -1 downto 0) <= datain(dbits -1 downto 0); - reg1 : process (clk) begin - dataout <= q(dbits -1 downto 0); - end process; - a6 : if (abits <= 6) generate - id0 : SRAM1RW64x32 port map (a(5 downto 0), q(31 downto 0), d(31 downto 0), wen, csn, '0', '1'); + id0 : SRAM1RW64x32 port map (A => a(5 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(31 downto 0), O => q(31 downto 0)); end generate; a7 : if (abits = 7) generate - id0 : SRAM1RW128x48 port map (a(6 downto 0), q(47 downto 0), d(47 downto 0), wen, csn, '0', '1'); + id0 : SRAM1RW128x48 port map (A => a(6 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(47 downto 0), O => q(47 downto 0)); end generate; - a10 : if (abits = 10) generate + a10 : if (abits >= 8 and abits <= 10) generate x : for i in 0 to ((dbits-1)/8) generate - id0 : SRAM1RW1024x8 port map (a(9 downto 0), q(((i+1)*8)-1 downto i*8), d(((i+1)*8)-1 downto i*8), csn, wen, gnd(0), '1'); + id0 : SRAM1RW1024x8 port map (A => a(9 downto 0), CE => clk, WEB => wen, OEB => gnd(0), CSB => csn, I => d(((i+1)*8)-1 downto i*8), O => q(((i+1)*8)-1 downto i*8)); end generate; end generate; + dataout <= q(dbits -1 downto 0); -- pragma translate_off a_to_high : if (abits > 10) or (dbits > 32) generate diff --git a/lib/techmap/saed32/pads_saed32.vhd b/lib/techmap/saed32/pads_saed32.vhd index 9f4347d4..b8df90f0 100644 --- a/lib/techmap/saed32/pads_saed32.vhd +++ b/lib/techmap/saed32/pads_saed32.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -128,17 +128,15 @@ begin localen <= not en; f4 : if (strength <= 4) generate - op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); + op : B4ISH1025_NS port map (DIN => i,PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); end generate; f12 : if (strength > 4) and (strength <= 12) generate - op : B12ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); + op : B12ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); end generate; f16 : if (strength > 12) generate - op : B16ISH1025_NS port map (DIN => i, PADIO => localpad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); + op : B16ISH1025_NS port map (DIN => i, PADIO => pad, DOUT => o, VSS => OPEN, R_EN => localen, EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); end generate; - pad <= localpad; - end; library ieee; @@ -210,7 +208,6 @@ architecture rtl of saed32_toutpad is begin - f4 : if (strength <= 4) generate op : B4ISH1025_NS port map (DIN => i,PADIO => localpad, DOUT => OPEN, VSS => OPEN, R_EN => '0', EN => en, VDDIO => OPEN, VDD => OPEN, VSSIO => OPEN, PULL_UP => '0', PULL_DOWN => '0'); end generate; diff --git a/lib/techmap/stratixii/clkgen_stratixii.vhd b/lib/techmap/stratixii/clkgen_stratixii.vhd index 82f77d6c..caf5b2c5 100644 --- a/lib/techmap/stratixii/clkgen_stratixii.vhd +++ b/lib/techmap/stratixii/clkgen_stratixii.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/stratixii/stratixii_ddr_phy.vhd b/lib/techmap/stratixii/stratixii_ddr_phy.vhd index b43ad7f1..fb23b42b 100644 --- a/lib/techmap/stratixii/stratixii_ddr_phy.vhd +++ b/lib/techmap/stratixii/stratixii_ddr_phy.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/stratixiii/clkgen_stratixiii.vhd b/lib/techmap/stratixiii/clkgen_stratixiii.vhd index d420b18d..f9d256c4 100644 --- a/lib/techmap/stratixiii/clkgen_stratixiii.vhd +++ b/lib/techmap/stratixiii/clkgen_stratixiii.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/stratixiii/serdes_stratixiii.vhd b/lib/techmap/stratixiii/serdes_stratixiii.vhd new file mode 100644 index 00000000..3b299c16 --- /dev/null +++ b/lib/techmap/stratixiii/serdes_stratixiii.vhd @@ -0,0 +1,266 @@ +------------------------------------------------------------------------------ +-- This file is a part of the GRLIB VHDL IP LIBRARY +-- Copyright (C) 2003 - 2008, Gaisler Research +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +----------------------------------------------------------------------------- +-- Entity: serdes_stratixiii +-- File: serdes_stratixiii.vhd +-- Author: Andrea Gianarro - Aeroflex Gaisler AB +-- Description: Stratix III and IV SGMII Gigabit Ethernet Serdes +------------------------------------------------------------------------------ +library ieee; +use ieee.std_logic_1164.all; +library grlib; +use grlib.stdlib.all; +library techmap; +use techmap.gencomp.all; +library altera_mf; +use altera_mf.altera_mf_components.all; + +entity serdes_stratixiii is + port ( + clk_125 : in std_logic; + rst_125 : in std_logic; + rx_in : in std_logic; -- SER IN + rx_out : out std_logic_vector(9 downto 0); -- PAR OUT + rx_clk : out std_logic; + rx_rstn : out std_logic; + rx_pll_clk : out std_logic; + rx_pll_rstn : out std_logic; + tx_pll_clk : out std_logic; + tx_pll_rstn : out std_logic; + tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN + tx_out : out std_logic; -- SER OUT + bitslip : in std_logic + ); +end entity; + +architecture rtl of serdes_stratixiii is + component altera_tse_lvds_reset_sequencer is + port ( + clk : in std_logic; + reset : in std_logic; + rx_locked : in std_logic; + rx_channel_data_align : out std_logic; + pll_areset : out std_logic; -- can be ignored + rx_reset : out std_logic; + rx_cda_reset : out std_logic; + rx_reset_sequence_done : out std_logic + ); + end component; + + signal rx_clk_int, rx_pll_clk_int, tx_pll_clk_int, rst_int, pll_areset_int, rx_locked_int, rx_rstn_int_0, tx_locked_int : std_logic; + signal rx_cda_reset_int, bitslip_int, rx_in_int, rx_rst_int, rx_divfwdclk_int, tx_out_int : std_logic_vector(0 downto 0) ; + signal rx_clk_rstn_int, rx_pll_rstn_int, tx_pll_rstn_int, rx_cda_reset_int_0 : std_logic; + signal rx_out_int, tx_in_int : std_logic_vector(9 downto 0) ; + + signal r0, r1, r2 : std_logic_vector(4 downto 0); + signal r3 : std_logic_vector(5 downto 0); + signal r4 : std_logic_vector(1 downto 0); +begin + + bitslip_int(0) <= bitslip; + rx_in_int(0) <= rx_in; + tx_in_int <= tx_in; + rx_out <= rx_out_int; + tx_out <= tx_out_int(0); + -- output clocks + rx_clk <= rx_clk_int; + rx_pll_clk <= rx_pll_clk_int; + tx_pll_clk <= tx_pll_clk_int; + -- output synchronized resets + rx_rstn <= rx_clk_rstn_int; + rx_pll_rstn <= rx_pll_rstn_int; + tx_pll_rstn <= tx_pll_rstn_int; + + --rx_cda_reset_int(0) <= rx_cda_reset_int_0; + rx_rst_int(0) <= not rx_rstn_int_0; + rx_clk_int <= rx_divfwdclk_int(0); + + -- reset synchronizers + rst0 : process (rx_clk_int, rst_125) begin + if rising_edge(rx_clk_int) then + r0 <= r0(3 downto 0) & rx_locked_int; + rx_clk_rstn_int <= r0(4) and r0(3) and r0(2); + end if; + if (rst_125 = '1') then r0 <= "00000"; rx_clk_rstn_int <= '0'; end if; + end process; + + rst1 : process (rx_pll_clk_int, rx_clk_rstn_int) begin + if rising_edge(rx_pll_clk_int) then + r1 <= r1(3 downto 0) & rx_locked_int; + rx_pll_rstn_int <= r1(4) and r1(3) and r1(2); + end if; + if (rx_clk_rstn_int = '0') then r1 <= "00000"; rx_pll_rstn_int <= '0'; end if; + end process; + + rst2 : process (tx_pll_clk_int, rx_clk_rstn_int) begin + if rising_edge(tx_pll_clk_int) then + r2 <= r2(3 downto 0) & tx_locked_int; + tx_pll_rstn_int <= r2(4) and r2(3) and r2(2); + end if; + if (rx_clk_rstn_int = '0') then r2 <= "00000"; tx_pll_rstn_int <= '0'; end if; + end process; + + -- 6 stages reset synchronizer + rst3 : process (clk_125, rst_125) begin + if rising_edge(clk_125) then + r3 <= r3(4 downto 0) & rx_locked_int; + rx_rstn_int_0 <= r3(5) and r3(4) and r3(3); + end if; + if (rst_125 = '1') then r3 <= "000000"; rx_rstn_int_0 <= '0'; end if; + end process; + + lvds_rx0: altlvds_rx + generic map ( + buffer_implementation => "RAM", + cds_mode => "UNUSED", + --clk_src_is_pll => "off", + common_rx_tx_pll => "ON", + data_align_rollover => 10, + --data_rate => "1250.0 Mbps", + deserialization_factor => 10, + dpa_initial_phase_value => 0, + dpll_lock_count => 0, + dpll_lock_window => 0, + --enable_clock_pin_mode => "UNUSED", + enable_dpa_align_to_rising_edge_only => "OFF", + enable_dpa_calibration => "ON", + enable_dpa_fifo => "UNUSED", + enable_dpa_initial_phase_selection => "OFF", + enable_dpa_mode => "ON", + enable_dpa_pll_calibration => "OFF", + enable_soft_cdr_mode => "ON", + implement_in_les => "OFF", + inclock_boost => 0, + inclock_data_alignment => "EDGE_ALIGNED", + inclock_period => 8000, + inclock_phase_shift => 0, + input_data_rate => 1250, + intended_device_family => "Stratix IV", + lose_lock_on_one_change => "UNUSED", + lpm_hint => "UNUSED", + lpm_type => "altlvds_rx", + number_of_channels => 1, + outclock_resource => "AUTO", + pll_operation_mode => "UNUSED", + pll_self_reset_on_loss_lock => "UNUSED", + port_rx_channel_data_align => "PORT_USED", + port_rx_data_align => "PORT_UNUSED", + --refclk_frequency => "125.000000 MHz", + registered_data_align_input => "UNUSED", + registered_output => "ON", + reset_fifo_at_first_lock => "UNUSED", + rx_align_data_reg => "UNUSED", + sim_dpa_is_negative_ppm_drift => "OFF", + sim_dpa_net_ppm_variation => 0, + sim_dpa_output_clock_phase_shift => 0, + use_coreclock_input => "OFF", + use_dpll_rawperror => "OFF", + use_external_pll => "OFF", + use_no_phase_shift => "ON", + x_on_bitslip => "ON" + ) + port map ( + pll_areset => rst_125, --pll_areset_int, + rx_channel_data_align => bitslip_int, + rx_in => rx_in_int, + rx_inclock => clk_125, + rx_reset => rx_rst_int, + rx_divfwdclk => rx_divfwdclk_int, + rx_locked => rx_locked_int, + rx_out => rx_out_int, + rx_outclock => rx_pll_clk_int, + + dpa_pll_cal_busy => open, + dpa_pll_recal => '0', + pll_phasecounterselect => open, + pll_phasedone => '1', + pll_phasestep => open, + pll_phaseupdown => open, + pll_scanclk => open, + rx_cda_max => open, + rx_cda_reset => (others => '0'), + rx_coreclk => (others => '1'), + rx_data_align => '0', + rx_data_align_reset => '0', + --rx_data_reset => '0', + rx_deskew => '0', + rx_dpa_lock_reset => (others => '0'), + rx_dpa_locked => open, + --rx_dpaclock => '0', + rx_dpll_enable => (others => '1'), + rx_dpll_hold => (others => '0'), + rx_dpll_reset => (others => '0'), + rx_enable => '1', + rx_fifo_reset => (others => '0'), + rx_pll_enable => '1', + rx_readclock => '0', + rx_syncclock => '0' + ); + + lvds_tx0: altlvds_tx + generic map ( + center_align_msb => "UNUSED", + --clk_src_is_pll => "off", + common_rx_tx_pll => "ON", + coreclock_divide_by => 1, + --data_rate => "1250.0 Mbps", + deserialization_factor => 10, + differential_drive => 0, + implement_in_les => "OFF", + inclock_boost => 0, + inclock_data_alignment => "EDGE_ALIGNED", + inclock_period => 8000, + inclock_phase_shift => 0, + intended_device_family => "Stratix IV", + lpm_hint => "UNUSED", + lpm_type => "altlvds_tx", + multi_clock => "OFF", + number_of_channels => 1, + outclock_alignment => "EDGE_ALIGNED", + outclock_divide_by => 10, + outclock_duty_cycle => 50, + outclock_multiply_by => 1, + outclock_phase_shift => 0, + outclock_resource => "AUTO", + output_data_rate => 1250, + pll_self_reset_on_loss_lock => "OFF", + preemphasis_setting => 0, + --refclk_frequency => "125.00 MHz", + registered_input => "TX_CORECLK", + use_external_pll => "OFF", + use_no_phase_shift => "ON", + vod_setting => 0 + ) + port map ( + pll_areset => rst_125, --pll_areset_int, + tx_in => tx_in_int, + tx_inclock => clk_125, + tx_out => tx_out_int, + tx_locked => tx_locked_int, + tx_coreclock => tx_pll_clk_int, + + sync_inclock => '0', + --tx_data_reset => '0', + tx_enable => '1', + tx_outclock => open, + tx_pll_enable => '1', + tx_syncclock => '0' + ); + +end architecture ; \ No newline at end of file diff --git a/lib/techmap/stratixiii/vhdlsyn.txt b/lib/techmap/stratixiii/vhdlsyn.txt index 3c90b595..7fcb9b5c 100644 --- a/lib/techmap/stratixiii/vhdlsyn.txt +++ b/lib/techmap/stratixiii/vhdlsyn.txt @@ -7,3 +7,4 @@ adq_dqs/bidir_dq_iobuf_inst.vhd adq_dqs/output_dqs_iobuf_inst.vhd adq_dqs/bidir_dqs_iobuf_inst.vhd ddr_phy_stratixiii.vhd +serdes_stratixiii.vhd diff --git a/lib/techmap/umc18/memory_umc18.vhd b/lib/techmap/umc18/memory_umc18.vhd index 631f2972..111fb20a 100644 --- a/lib/techmap/umc18/memory_umc18.vhd +++ b/lib/techmap/umc18/memory_umc18.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/umc18/pads_umc18.vhd b/lib/techmap/umc18/pads_umc18.vhd index 0636e737..647b2c81 100644 --- a/lib/techmap/umc18/pads_umc18.vhd +++ b/lib/techmap/umc18/pads_umc18.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/buffer_unisim.vhd b/lib/techmap/unisim/buffer_unisim.vhd index 4a868c79..c3f51c93 100644 --- a/lib/techmap/unisim/buffer_unisim.vhd +++ b/lib/techmap/unisim/buffer_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/clkgen_unisim.vhd b/lib/techmap/unisim/clkgen_unisim.vhd index 437fcd3f..07de74b8 100644 --- a/lib/techmap/unisim/clkgen_unisim.vhd +++ b/lib/techmap/unisim/clkgen_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/clkgen_virtex.vhd b/lib/techmap/unisim/clkgen_virtex.vhd index 2aa32adc..756cecd0 100644 --- a/lib/techmap/unisim/clkgen_virtex.vhd +++ b/lib/techmap/unisim/clkgen_virtex.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/ddr_phy_unisim.vhd b/lib/techmap/unisim/ddr_phy_unisim.vhd index 18bad039..ecb181b3 100644 --- a/lib/techmap/unisim/ddr_phy_unisim.vhd +++ b/lib/techmap/unisim/ddr_phy_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/ddr_unisim.vhd b/lib/techmap/unisim/ddr_unisim.vhd index c5dc95ad..633110f4 100644 --- a/lib/techmap/unisim/ddr_unisim.vhd +++ b/lib/techmap/unisim/ddr_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -89,13 +89,13 @@ architecture rtl of unisim_iddr_reg is signal D_delay : std_ulogic; begin - V7 : if (tech = virtex7) or (tech = kintex7) generate - U0 : IDDR generic map( DDR_CLK_EDGE => "SAME_EDGE_PIPELINED") + V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate + U0 : IDDR generic map( DDR_CLK_EDGE => "SAME_EDGE") Port map( Q1 => Q1, Q2 => Q2, C => C1, CE => CE, D => D, R => R, S => S); end generate; - V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate + V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate U0 : IDDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE") Port map( Q1 => Q1, Q2 => preQ2, C => C1, CE => CE, D => D, R => R, S => S); @@ -272,14 +272,14 @@ architecture rtl of unisim_oddr_reg is begin - V7 : if (tech = virtex7) or (tech = kintex7) generate + V7 : if (tech = virtex7) or (tech = kintex7) or (tech = artix7) generate U0 : ODDR generic map( DDR_CLK_EDGE => "SAME_EDGE") port map( Q => Q, C => C1, CE => CE, D1 => D1, D2 => D2, R => R, S => S); end generate; - V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) generate + V4 : if (tech = virtex4) or (tech = virtex5) or (tech = virtex6) or (tech = zynq7000) generate d2r : if arch = 0 generate d2reg : process (C1, D2, R) diff --git a/lib/techmap/unisim/memory_unisim.vhd b/lib/techmap/unisim/memory_unisim.vhd index 8b9967e1..05d84f41 100644 --- a/lib/techmap/unisim/memory_unisim.vhd +++ b/lib/techmap/unisim/memory_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -55,6 +55,7 @@ end; architecture behav of unisim_syncram is component RAMB16_S36_S36 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (31 downto 0); DOB : out std_logic_vector (31 downto 0); @@ -182,7 +183,9 @@ begin a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and (abits <= 8)) generate x : for i in 0 to ((dbits-1)/72) generate - r0 : RAMB16_S36_S36 port map ( + r0 : RAMB16_S36_S36 + generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72), do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32), xa(8 downto 0), ya(8 downto 0), clk, clk, @@ -295,6 +298,7 @@ end; architecture behav of unisim_syncram_dp is component RAMB16_S4_S4 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (3 downto 0); DOB : out std_logic_vector (3 downto 0); @@ -314,6 +318,7 @@ architecture behav of unisim_syncram_dp is end component; component RAMB16_S1_S1 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (0 downto 0); DOB : out std_logic_vector (0 downto 0); @@ -333,6 +338,7 @@ architecture behav of unisim_syncram_dp is end component; component RAMB16_S2_S2 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (1 downto 0); DOB : out std_logic_vector (1 downto 0); @@ -352,6 +358,7 @@ architecture behav of unisim_syncram_dp is end component; component RAMB16_S9_S9 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (7 downto 0); DOB : out std_logic_vector (7 downto 0); @@ -375,6 +382,7 @@ architecture behav of unisim_syncram_dp is end component; component RAMB16_S18_S18 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (15 downto 0); DOB : out std_logic_vector (15 downto 0); @@ -397,6 +405,7 @@ end component; end component; component RAMB16_S36_S36 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (31 downto 0); DOB : out std_logic_vector (31 downto 0); @@ -431,7 +440,9 @@ begin a9 : if abits <= 9 generate x : for i in 0 to ((dbits-1)/36) generate - r0 : RAMB16_S36_S36 port map ( + r0 : RAMB16_S36_S36 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36), do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32), addr1(8 downto 0), addr2(8 downto 0), clk1, clk2, @@ -446,7 +457,9 @@ begin a10 : if abits = 10 generate x : for i in 0 to ((dbits-1)/18) generate - r0 : RAMB16_S18_S18 port map ( + r0 : RAMB16_S18_S18 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18), do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16), addr1(9 downto 0), addr2(9 downto 0), clk1, clk2, @@ -461,7 +474,9 @@ begin a11 : if abits = 11 generate x : for i in 0 to ((dbits-1)/9) generate - r0 : RAMB16_S9_S9 port map ( + r0 : RAMB16_S9_S9 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9), do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8), addr1(10 downto 0), addr2(10 downto 0), clk1, clk2, @@ -476,7 +491,9 @@ begin a12 : if abits = 12 generate x : for i in 0 to ((dbits-1)/4) generate - r0 : RAMB16_S4_S4 port map ( + r0 : RAMB16_S4_S4 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4), addr1(11 downto 0), addr2(11 downto 0), clk1, clk2, di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4), @@ -489,7 +506,9 @@ begin a13 : if abits = 13 generate x : for i in 0 to ((dbits-1)/2) generate - r0 : RAMB16_S2_S2 port map ( + r0 : RAMB16_S2_S2 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2), addr1(12 downto 0), addr2(12 downto 0), clk1, clk2, di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2), @@ -502,7 +521,9 @@ begin a14 : if abits = 14 generate x : for i in 0 to ((dbits-1)/1) generate - r0 : RAMB16_S1_S1 port map ( + r0 : RAMB16_S1_S1 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1), addr1(13 downto 0), addr2(13 downto 0), clk1, clk2, di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1), @@ -639,6 +660,7 @@ component unisim_syncram ); end component; component RAMB16_S36_S36 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (31 downto 0); DOB : out std_logic_vector (31 downto 0); @@ -669,7 +691,9 @@ begin ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1'); a8 : if abits <= 8 generate - r0 : RAMB16_S36_S36 port map ( + r0 : RAMB16_S36_S36 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( dataout(63 downto 32), dataout(31 downto 0), open, open, xa(8 downto 0), ya(8 downto 0), clk, clk, datain(63 downto 32), datain(31 downto 0), gnd, gnd, @@ -752,6 +776,7 @@ component unisim_syncram ); end component; component RAMB16_S9_S9 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( DOA : out std_logic_vector (7 downto 0); DOB : out std_logic_vector (7 downto 0); @@ -784,7 +809,9 @@ begin a11 : if abits <= 10 generate x0 : for i in 0 to 7 generate - r0 : RAMB16_S9_S9 port map ( + r0 : RAMB16_S9_S9 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open, xa(10 downto 0), ya(10 downto 0), clk, clk, datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0), diff --git a/lib/techmap/unisim/memory_virtex.vhd b/lib/techmap/unisim/memory_virtex.vhd index 465643e8..83406bf5 100644 --- a/lib/techmap/unisim/memory_virtex.vhd +++ b/lib/techmap/unisim/memory_virtex.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -101,6 +101,7 @@ architecture behav of virtex_syncram is en, rst, we : in std_ulogic); end component; component RAMB4_S16_S16 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( doa : out std_logic_vector (15 downto 0); dob : out std_logic_vector (15 downto 0); @@ -135,7 +136,9 @@ begin end generate; a7 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and (abits <= 7) and (dbits <= 32)) generate - r0 : RAMB4_S16_S16 port map ( do(31 downto 16), do(15 downto 0), + r0 : RAMB4_S16_S16 + generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do(31 downto 16), do(15 downto 0), xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16), di(15 downto 0), enable, enable, gnd, gnd, write, write); do(dbits+32 downto 32) <= (others => '0'); @@ -217,6 +220,7 @@ end; architecture behav of virtex_syncram_dp is component RAMB4_S1_S1 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( doa : out std_logic_vector (0 downto 0); dob : out std_logic_vector (0 downto 0); @@ -235,6 +239,7 @@ architecture behav of virtex_syncram_dp is ); end component; component RAMB4_S2_S2 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( doa : out std_logic_vector (1 downto 0); dob : out std_logic_vector (1 downto 0); @@ -253,6 +258,7 @@ architecture behav of virtex_syncram_dp is ); end component; component RAMB4_S4_S4 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( doa : out std_logic_vector (3 downto 0); dob : out std_logic_vector (3 downto 0); @@ -271,6 +277,7 @@ architecture behav of virtex_syncram_dp is ); end component; component RAMB4_S8_S8 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( doa : out std_logic_vector (7 downto 0); dob : out std_logic_vector (7 downto 0); @@ -289,6 +296,7 @@ architecture behav of virtex_syncram_dp is ); end component; component RAMB4_S16_S16 + generic (SIM_COLLISION_CHECK : string := "ALL"); port ( doa : out std_logic_vector (15 downto 0); dob : out std_logic_vector (15 downto 0); @@ -320,7 +328,9 @@ begin a8 : if abits <= 8 generate x : for i in 0 to ((dbits-1)/16) generate - r0 : RAMB4_S16_S16 port map ( + r0 : RAMB4_S16_S16 + generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16), addr1(7 downto 0), addr2(7 downto 0), clk1, clk2, di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16), @@ -330,7 +340,9 @@ begin a9 : if abits = 9 generate x : for i in 0 to ((dbits-1)/8) generate - r0 : RAMB4_S8_S8 port map ( + r0 : RAMB4_S8_S8 + generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8), addr1(8 downto 0), addr2(8 downto 0), clk1, clk2, di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8), @@ -340,7 +352,9 @@ begin a10: if abits = 10 generate x : for i in 0 to ((dbits-1)/4) generate - r0 : RAMB4_S4_S4 port map ( + r0 : RAMB4_S4_S4 + generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4), addr1(9 downto 0), addr2(9 downto 0), clk1, clk2, di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4), @@ -350,7 +364,9 @@ begin a11: if abits = 11 generate x : for i in 0 to ((dbits-1)/2) generate - r0 : RAMB4_S2_S2 port map ( + r0 : RAMB4_S2_S2 + generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2), addr1(10 downto 0), addr2(10 downto 0), clk1, clk2, di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2), @@ -360,7 +376,9 @@ begin a12: if abits = 12 generate x : for i in 0 to ((dbits-1)/1) generate - r0 : RAMB4_S1_S1 port map ( + r0 : RAMB4_S1_S1 + generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY") + port map ( do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1), addr1(11 downto 0), addr2(11 downto 0), clk1, clk2, di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1), diff --git a/lib/techmap/unisim/pads_unisim.vhd b/lib/techmap/unisim/pads_unisim.vhd index 99c42045..db5ecb8d 100644 --- a/lib/techmap/unisim/pads_unisim.vhd +++ b/lib/techmap/unisim/pads_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/sysmon_unisim.vhd b/lib/techmap/unisim/sysmon_unisim.vhd index 517cb002..79dac6bb 100644 --- a/lib/techmap/unisim/sysmon_unisim.vhd +++ b/lib/techmap/unisim/sysmon_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/unisim/tap_unisim.vhd b/lib/techmap/unisim/tap_unisim.vhd index bfa66406..8deda46d 100644 --- a/lib/techmap/unisim/tap_unisim.vhd +++ b/lib/techmap/unisim/tap_unisim.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/techmap/virage/memory_virage.vhd b/lib/techmap/virage/memory_virage.vhd index ecc874eb..e2a0ee19 100644 --- a/lib/techmap/virage/memory_virage.vhd +++ b/lib/techmap/virage/memory_virage.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/work/debug/cpu_disas.vhd b/lib/work/debug/cpu_disas.vhd index dae6dbea..b2001e90 100644 --- a/lib/work/debug/cpu_disas.vhd +++ b/lib/work/debug/cpu_disas.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/work/debug/debug.vhd b/lib/work/debug/debug.vhd index fe06da1a..4a0b5a62 100644 --- a/lib/work/debug/debug.vhd +++ b/lib/work/debug/debug.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/lib/work/debug/grtestmod.vhd b/lib/work/debug/grtestmod.vhd index 4c5f4424..a36523d4 100644 --- a/lib/work/debug/grtestmod.vhd +++ b/lib/work/debug/grtestmod.vhd @@ -1,7 +1,7 @@ ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research --- Copyright (C) 2008 - 2013, Aeroflex Gaisler +-- Copyright (C) 2008 - 2014, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by diff --git a/software/leon3/Makefile b/software/leon3/Makefile index a5ddd49f..d2089cc3 100644 --- a/software/leon3/Makefile +++ b/software/leon3/Makefile @@ -3,9 +3,9 @@ XCC=sparc-elf-gcc -I$(GRLIB)/software/leon3 $(BOPT) XAS=sparc-elf-gcc -c -I. -I$(GRLIB)/software/leon3 $(BOPT) XAR=sparc-elf-ar XCFLAGS=-O2 -g -msoft-float -#ifeq ("$(LDFLAGS)","") -#LDFLAGS=-qnoambapp -#endif +ifeq ("$(LDFLAGS)","") +LDFLAGS=-qnoambapp +endif XLDFLAGS=-L./ lib3tests.a $(LDFLAGS) PROGS = report_device apbuart divtest multest regtest \ @@ -19,7 +19,7 @@ PROGS = report_device apbuart divtest multest regtest \ ftahbram ftlib ftsrctrl ftmctrl bch l2timers l2irqctrl leon2_test \ grpwm grhcan brm grusbhc leon4_test base_test4 griommu l4stat ftddr2spa \ router greth_throughput grpci2 gr1553b_test spwrouter \ - cgtest privtest privtest_asm + cgtest privtest privtest_asm mmudmap FPROGS=$(shell for i in $(PROGS); do \ if [ -r $(GRLIB)/software/leon3/$$i.c -o -r $(GRLIB)/software/leon3/$$i.S ]; then \ @@ -78,7 +78,7 @@ systest.exe: systest.c lib3tests.a ram.srec: systest.exe sparc-elf-objcopy -O srec --gap-fill 0 systest.exe ram.srec -soft-clean: gen_hex_clean +soft-clean: -rm -rf *.o *.exe *.a mmusoft: @@ -86,94 +86,3 @@ mmusoft: standalone.exe: systest.c standalone.c lib3tests.a $(XCC) $(XCFLAGS) systest.c $(VPATH)/standalone.c $(XLDFLAGS) -o standalone.exe - -gen_hex: soft - sparc-elf-objdump -D prom.exe > prom.disas - sparc-elf-objdump -D systest.exe > systest.disas - cp ram.srec sdram.hex - sed -i '1d' sdram.hex - sed -i '$$d' sdram.hex - sed -i 's/\(.\{12\}\)//' sdram.hex - sed -i 's ...$$ ' sdram.hex - sed -i -e 's/.\{16\}/&\n/g' sdram.hex - sed -i '/^$$/d' sdram.hex - sed -i '/\n/!G;s/\(.\)\(.*\n\)/&\2\1/;//D;s/.//' sdram.hex - sed -i 's/\(.\)\(.\)/\2\1/g' sdram.hex - -gen_hex_dim: gen_hex - awk '{print}END{for (i=0; i < 9; i++) print "0000000000000000"}' sdram.hex > sdram_ext.hex - sed -n ';1~8p' sdram_ext.hex > sdram_dimm1_tmp.hex - sed -n ';2~8p' sdram_ext.hex > sdram_dimm2_tmp.hex - sed -n ';3~8p' sdram_ext.hex > sdram_dimm3_tmp.hex - sed -n ';4~8p' sdram_ext.hex > sdram_dimm4_tmp.hex - sed -n ';5~8p' sdram_ext.hex > sdram_dimm5_tmp.hex - sed -n ';6~8p' sdram_ext.hex > sdram_dimm6_tmp.hex - sed -n ';7~8p' sdram_ext.hex > sdram_dimm7_tmp.hex - sed -n ';8~8p' sdram_ext.hex > sdram_dimm8_tmp.hex - sed -i 's/../&\n/g' sdram_dimm*_tmp.hex - sed -i '/^$$/d' sdram_dimm*_tmp.hex - pr -tm sdram_dimm8_tmp.hex sdram_dimm7_tmp.hex sdram_dimm6_tmp.hex sdram_dimm5_tmp.hex sdram_dimm4_tmp.hex sdram_dimm3_tmp.hex sdram_dimm2_tmp.hex sdram_dimm1_tmp.hex > sdram_merge.hex - sed -i -e 's/\s\+//g' sdram_merge.hex - sed -i '/^$$/d' sdram_merge.hex - awk 'BEGIN{FS="\n"; OFS="\n"; RS="\n"}{for (i = 0; i <= NF/8-1; i++) print $$(8+i*8),$$(7+i*8),$$(6+i*8),$$(5+i*8),$$(4+i*8),$$(3+i*8),$$(2+i*8),$$(1+i*8)}' sdram_merge.hex > sdram_out.hex - sed -n ';1~8p' sdram_out.hex > sdram_dimm1.hex - sed -n ';2~8p' sdram_out.hex > sdram_dimm2.hex - sed -n ';3~8p' sdram_out.hex > sdram_dimm3.hex - sed -n ';4~8p' sdram_out.hex > sdram_dimm4.hex - sed -n ';5~8p' sdram_out.hex > sdram_dimm5.hex - sed -n ';6~8p' sdram_out.hex > sdram_dimm6.hex - sed -n ';7~8p' sdram_out.hex > sdram_dimm7.hex - sed -n ';8~8p' sdram_out.hex > sdram_dimm8.hex - sed -n ';1~8p' sdram_ext.hex > sdram_dimm16_1.hex - sed -n ';2~8p' sdram_ext.hex > sdram_dimm16_2.hex - sed -n ';3~8p' sdram_ext.hex > sdram_dimm16_3.hex - sed -n ';4~8p' sdram_ext.hex > sdram_dimm16_4.hex - sed -n ';5~8p' sdram_ext.hex > sdram_dimm16_5.hex - sed -n ';6~8p' sdram_ext.hex > sdram_dimm16_6.hex - sed -n ';7~8p' sdram_ext.hex > sdram_dimm16_7.hex - sed -n ';8~8p' sdram_ext.hex > sdram_dimm16_8.hex - pr -tmJ sdram_dimm16_8.hex sdram_dimm16_7.hex sdram_dimm16_6.hex sdram_dimm16_5.hex sdram_dimm16_4.hex sdram_dimm16_3.hex sdram_dimm16_2.hex sdram_dimm16_1.hex > sdram_dimm_merge.hex - sed -i -e 's/\s\+//g' sdram_dimm_merge.hex - sed -i '/^$$/d' sdram_dimm_merge.hex - - -gen_hex16: soft - sparc-elf-objdump -D prom.exe > prom.disas - sparc-elf-objdump -D systest.exe > systest.disas - cp ram.srec sdram.hex - sed -i '1d' sdram.hex - sed -i '$$d' sdram.hex - sed -i 's/\(.\{12\}\)//' sdram.hex - sed -i 's ...$$ ' sdram.hex - sed -i -e 's/.\{16\}/&\n/g' sdram.hex - sed -i '/^$$/d' sdram.hex - sed -i '/\n/!G;s/\(.\)\(.*\n\)/&\2\1/;//D;s/.//' sdram.hex - sed -i 's/\(.\)\(.\)/\2\1/g' sdram.hex -# AHB2MIG_ML605 FIX (Order for Big Endieen isn't not correct) - sed -i 's/\(.\)\(.\)\(.\)\(.\)/\3\4\1\2/g' sdram.hex - -gen_hex_dim16: gen_hex16 - awk '{print}END{for (i=0; i < 128; i++) print "0000000000000000"}' sdram.hex > sdram_ext.hex - sed -i 's/..../&\n/g' sdram_ext.hex - sed -i -e 's/\s\+//g' sdram_ext.hex - sed -i '/^$$/d' sdram_ext.hex - sed -n ';1~4p' sdram_ext.hex > sdram_dimm4_tmp.hex - sed -n ';2~4p' sdram_ext.hex > sdram_dimm3_tmp.hex - sed -n ';3~4p' sdram_ext.hex > sdram_dimm2_tmp.hex - sed -n ';4~4p' sdram_ext.hex > sdram_dimm1_tmp.hex - sed -i '/^$$/d' sdram_dimm*_tmp.hex - awk 'BEGIN{FS="\n"; OFS="\n"; RS="\n"}{for (i = 0; i <= NF/8-1; i++) print $$(8+i*8),$$(7+i*8),$$(6+i*8),$$(5+i*8),$$(4+i*8),$$(3+i*8),$$(2+i*8),$$(1+i*8)}' sdram_dimm4_tmp.hex > sdram_dimm4_test.hex - awk 'BEGIN{FS="\n"; OFS="\n"; RS="\n"}{for (i = 0; i <= NF/8-1; i++) print $$(8+i*8),$$(7+i*8),$$(6+i*8),$$(5+i*8),$$(4+i*8),$$(3+i*8),$$(2+i*8),$$(1+i*8)}' sdram_dimm3_tmp.hex > sdram_dimm3_test.hex - awk 'BEGIN{FS="\n"; OFS="\n"; RS="\n"}{for (i = 0; i <= NF/8-1; i++) print $$(8+i*8),$$(7+i*8),$$(6+i*8),$$(5+i*8),$$(4+i*8),$$(3+i*8),$$(2+i*8),$$(1+i*8)}' sdram_dimm2_tmp.hex > sdram_dimm2_test.hex - awk 'BEGIN{FS="\n"; OFS="\n"; RS="\n"}{for (i = 0; i <= NF/8-1; i++) print $$(8+i*8),$$(7+i*8),$$(6+i*8),$$(5+i*8),$$(4+i*8),$$(3+i*8),$$(2+i*8),$$(1+i*8)}' sdram_dimm1_tmp.hex > sdram_dimm1_test.hex - sed -e :a -e '$!N; s/\n//; ta' sdram_dimm4_test.hex > sdram_dimm_merge1.hex - sed -e :a -e '$!N; s/\n//; ta' sdram_dimm3_test.hex > sdram_dimm_merge2.hex - sed -e :a -e '$!N; s/\n//; ta' sdram_dimm2_test.hex > sdram_dimm_merge3.hex - sed -e :a -e '$!N; s/\n//; ta' sdram_dimm1_test.hex > sdram_dimm_merge4.hex - sed -i 's/.\{32\}/&\n/g' sdram_dimm_merge1.hex - sed -i 's/.\{32\}/&\n/g' sdram_dimm_merge2.hex - sed -i 's/.\{32\}/&\n/g' sdram_dimm_merge3.hex - sed -i 's/.\{32\}/&\n/g' sdram_dimm_merge4.hex - -gen_hex_clean: - -rm -f *.hex *.disas \ No newline at end of file diff --git a/software/leon3/cache.c b/software/leon3/cache.c index e5fff1eb..0d539b0c 100644 --- a/software/leon3/cache.c +++ b/software/leon3/cache.c @@ -147,17 +147,42 @@ extern line3(); #define DTAGMASK (~((1<> 28) & 3) != 3) { /* ic dynamic replacement */ + i = 3; + } + + if (((rsysreg(12) >> 28) & 3) != 3) { /* dc dynamic replacement */ + i = 3; + } + + /* if dynamic replacement then test repl = 3, 2, 1, 0 */ + while (i >= 0) { + wsysreg(8, (rsysreg(8) & ~(3 << 28)) | (i << 28)); + wsysreg(12, (rsysreg(12) & ~(3 << 28)) | (i << 28)); + maintest(); + i--; + } + + wsysreg(8, (rsysreg(8) & ~(3 << 28)) | (1 << 28)); + wsysreg(12, (rsysreg(12) & ~(3 << 28)) | (1 << 28)); wsysreg(0, 0x0081000f); - return(tmp); } + long long int getdw(); void cache_test_init_state() @@ -206,8 +231,6 @@ maintest() int ISETS; int (*line[4])() = {line0, line1, line2, line3}; - report_subtest(CACHE_TEST); - cachectrl = rsysreg(0); wsysreg(0, cachectrl & ~0x0f); do cachectrl = rsysreg(0); while(cachectrl & (CCTRL_IFP | CCTRL_DFP)); flush(); diff --git a/software/leon3/hello.c b/software/leon3/hello.c index 6bd47426..597f86e0 100644 --- a/software/leon3/hello.c +++ b/software/leon3/hello.c @@ -1,4 +1,4 @@ - +#include main() { printf("Hello World\n"); diff --git a/software/leon3/mmudmap.c b/software/leon3/mmudmap.c new file mode 100644 index 00000000..e093fa27 --- /dev/null +++ b/software/leon3/mmudmap.c @@ -0,0 +1,75 @@ +/* Setup MMU 1:1 mapping */ +/* Requires 2kbyte size 2kbyte aligned area for page and context tables */ +/* Cached parameter has same format as leon3 generic */ +void mmudmap(unsigned long *tbladdr, int cached) +{ + unsigned long *pt = tbladdr + 256; + unsigned long *ctxt = tbladdr; + int i; + unsigned long pte; + + /* Create level 1 page table with 1:1 mapping */ + for (i=0; i<256; i++) { + pte = (i << 20) | (3 << 2) | (2 << 0); + /* Decide if cacheable, set C bit if so */ + if ( (cached & 1) != 0 ) + pte |= (1 << 7); + pt[i] = pte; + if ((i & 15) == 15) cached >>= 1; + } + + /* Create context table with context 0 mapped to table above, other + * contexts marked as invalid */ + ctxt[0] = (((unsigned long)pt >> 4)) | (1 << 0); + for (i=1; i<256; i++) ctxt[i]=0; + + /* Compiler barrier for completeness, make sure all table writes above + * have been performed before reg writes below */ + asm volatile ("" ::: "memory"); + + /* Flush I/D/MMUTLB */ + asm volatile ("sta %g0, [%g0] 0x18"); + /* Point MMU context pointer register to context table */ + asm volatile ("sta %0, [%1] 0x19" : : "r"(((unsigned long)ctxt) >> 4),"r"(0x100)); + /* Set MMU context register to context 0 */ + asm volatile ("sta %%g0, [%0] 0x19" : : "r"(0x200)); + /* Enable MMU */ + asm volatile ("sta %0, [%%g0] 0x19" : : "r"(1)); +} + +/* Modify table set up by mmudmap for a 16 MiB virtual address area */ +/* Does not flush TLB. */ +void mmudmap_modify(unsigned long *tbladdr_phys, unsigned long vaddr, + unsigned long physaddr, int cacheable, int acc) +{ + unsigned long pte,idx; + + /* Compute index in page table */ + idx = vaddr >> 24; + /* Compute new PTE entry */ + pte = (((unsigned long)physaddr) >> 4) & (~0xff); + if (cacheable) pte |= 0x80; + pte |= (acc & 7) << 2; + pte |= 2; + + /* Modify page table using MMU bypass insn just in case mapping for + * virtual page containing MMU page table has been changed earlier. */ + asm volatile ("sta %0, [%1] 0x1C" : : "r"(pte),"r"(tbladdr_phys+256+idx)); + + /* Just for completeness, in case this code is inlined in the future */ + asm volatile ("" ::: "memory"); +} + +void mmudmap_flushtlb(void) +{ + /* Flush I/D/MMUTLB */ + asm volatile ("sta %%g0, [%%g0] 0x18" ::: "memory"); +} + +void mmudmap_block(void) +{ + unsigned long tmp; + do { + asm volatile ("lda [%%g0] 2, %0" : "=r"(tmp)); + } while ( (tmp & 0xc000) != 0); +} diff --git a/software/leon3/spwtest.c b/software/leon3/spwtest.c index 1a818a69..42dcac7b 100644 --- a/software/leon3/spwtest.c +++ b/software/leon3/spwtest.c @@ -86,8 +86,8 @@ int spw_test(int addr) tx = (char *) malloc(64); rmaphdr = (char *) malloc(32); rmap = (char *) malloc(64); - rxd = (int *) almalloc(1024); - txd = (int *) almalloc(1024); + rxd = (int *) almalloc(8192); + txd = (int *) almalloc(8192); size = (int *) malloc(sizeof(int)); /*reset link */ diff --git a/software/spw/spw_test_dual.c b/software/spw/spw_test_dual.c index 00933393..39f9f535 100644 --- a/software/spw/spw_test_dual.c +++ b/software/spw/spw_test_dual.c @@ -14,9 +14,9 @@ #define SPW2_ADDR 0x80000b00 #define SPW1_FREQ 200000 /* Frequency of txclk in khz, set to 0 to use reset value */ #define SPW2_FREQ 200000 /* Frequency of txclk in khz, set to 0 to use reset value */ -#define AHBFREQ 50000 /* Set to zero to leave reset values */ +#define AHBFREQ 60000 /* Set to zero to leave reset values */ -#define SPW_CLKDIV 19 +#define SPW_CLKDIV 0 #ifndef SPW_PORT #define SPW_PORT 0 @@ -31,19 +31,19 @@ #define PKTTESTMAX 128 #define DESCPKT 1024 -#define MAXSIZE 16777215 /*must not be set to more than 16777216 (2^24)*/ +#define MAXSIZE 16777215 /*must not be set to more than 16777216 (2^24)*/ #define RMAPSIZE 1024 #define RMAPCRCSIZE 1024 -#define TEST1 0 -#define TEST2 0 -#define TEST3 0 -#define TEST4 0 -#define TEST5 0 -#define TEST6 0 -#define TEST7 0 -#define TEST8 0 -#define TEST9 0 +#define TEST1 1 +#define TEST2 1 +#define TEST3 1 +#define TEST4 1 +#define TEST5 1 +#define TEST6 1 +#define TEST7 1 +#define TEST8 1 +#define TEST9 1 #define TEST10 1 #define TEST11 1 #define TEST12 1 @@ -1225,8 +1225,9 @@ int main(int argc, char *argv[]) rx0 = (char *)malloc(RMAPSIZE+4); rx1 = (char *)malloc(32+RMAPSIZE); rx2 = (char *)malloc(32+RMAPSIZE); + rx3 = (char *)malloc(32+RMAPSIZE); if( (tx0 == NULL) || (tx1 == NULL) || (rx0 == NULL) || - (rx1 == NULL) || (rx2 == NULL) ) { + (rx1 == NULL) || (rx2 == NULL) || (rx3 == NULL) ) { printf("Memory initialization error\n"); exit(1); } @@ -1244,19 +1245,15 @@ int main(int argc, char *argv[]) for(j = 0; j < i; j++) { tx1[j] = ~tx1[j]; } -/* if (m >= 4) { */ -/* cmd->incr = no; */ -/* } else { */ - cmd->incr = yes; -/* } */ + cmd->incr = yes; cmd->type = writecmd; cmd->verify = no; cmd->ack = yes; - cmd->destaddr = 0xFE; - cmd->destkey = 0x00; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = i; - cmd->addr = 0xa0000000+i*m*4; + cmd->addr = (int)rx3; cmd->len = i; cmd->status = 0; cmd->dstspalen = 0; @@ -1270,22 +1267,14 @@ int main(int argc, char *argv[]) reply->type = writerep; reply->verify = no; reply->ack = yes; -/* if (m >= 4) { */ - /* reply->incr = no; */ -/* if ( ((((int)&(rx0[(m%4)])) % 4) != 0) || ((cmd->len % 4) != 0) ) { */ -/* reply->status = 10; */ -/* } else { */ - reply->status = 0; -/* } */ -/* } else { */ - reply->incr = yes; - reply->status = 0; -/* } */ - reply->destaddr = 0xFE; - reply->destkey = 0x00; - reply->srcaddr = 0x1; + reply->status = 0; + reply->incr = yes; + reply->status = 0; + reply->destaddr = spw2->nodeaddr; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = i; - reply->addr = 0xa0000000+i*m*4; + reply->addr = (int)rx3; reply->len = i; reply->dstspalen = 0; reply->dstspa = (char *)NULL; @@ -1316,7 +1305,6 @@ int main(int argc, char *argv[]) exit(0); } for (k = 0; k < 64; k++) {} - /* printf("0x%x\n", spw2->regs->status);*/ iterations++; } if (rxs->truncated) { @@ -1341,46 +1329,19 @@ int main(int argc, char *argv[]) } for(k = 0; k < *replysize; k++) { if (loadb((int)&(rx1[k])) != rx2[k]) { - printf("Compare error 0: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx1[k])), (unsigned)rx2[k]); + printf("Compare error 0: i = %i, m = %i. Data[%i] = %x Expected: %x \n", i, m, k, (unsigned)loadb((int)&(rx1[k])), (unsigned)rx2[k]); exit(1); } } - if (reply->status == 0) { - /* if (m < 4) { */ -/* for(k = 0; k < i; k++) { */ -/* if (loadb((int)&(rx0[k+(m%4)])) != tx1[k]) { */ -/* printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx0[k+(m%4)])), (unsigned)tx1[k]); */ -/* exit(1); */ -/* } */ -/* } */ -/* } else { */ -/* if (i != 0) { */ -/* for(k = 0; k < 4; k++) { */ -/* if (loadb((int)&(rx0[k+(m%4)])) != tx1[k + (i - 4)]) { */ -/* printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx0[k+(m%4)])), (unsigned)tx1[k+(i-4)]); */ -/* exit(1); */ -/* } */ -/* } */ -/* } */ -/* } */ - } - /* if ((i % 512) == 0) { */ -/* printf("Packet %i, alignment %i\n", i, m); */ -/* } */ - - /* if (m >= 4) { */ - /* cmd->incr = no; */ -/* } else { */ - cmd->incr = yes; -/* } */ + cmd->incr = yes; cmd->type = readcmd; cmd->verify = no; cmd->ack = yes; - cmd->destaddr = 0xFE; - cmd->destkey = 0x00; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = i; - cmd->addr = 0xa0000000+i*m*4; + cmd->addr = (int)rx3; cmd->len = i; cmd->status = 0; cmd->dstspalen = 0; @@ -1394,28 +1355,18 @@ int main(int argc, char *argv[]) reply->type = readrep; reply->verify = no; reply->ack = yes; - /* if (m >= 4) { */ -/* reply->incr = no; */ - /* if ( ((((int)&(rx0[(m%4)])) % 4) != 0) || ((cmd->len % 4) != 0) ) { */ - /* if ((cmd->len % 4) != 0) { */ -/* reply->status = 10; */ -/* } else { */ -/* reply->status = 0; */ -/* } */ - /* } else { */ - reply->incr = yes; - reply->status = 0; -/* } */ + reply->incr = yes; + reply->status = 0; if (reply->status == 0) { reply->len = i; } else { reply->len = 0; } - reply->destaddr = 0xFE; - reply->destkey = 0x00; - reply->srcaddr = 0x1; + reply->destaddr = spw2->nodeaddr; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = i; - reply->addr = 0xa0000000+i*m*4; + reply->addr = (int)rx3; reply->dstspalen = 0; reply->dstspa = (char *)NULL; reply->srcspalen = 0; @@ -1445,7 +1396,6 @@ int main(int argc, char *argv[]) exit(0); } for (k = 0; k < 64; k++) {} - /* printf("0x%x\n", spw2->regs->status);*/ iterations++; } if (rxs->truncated) { @@ -1476,11 +1426,10 @@ int main(int argc, char *argv[]) printf("Expected: %i, Got: %i \n", *replysize+2+i, *size); } for(k = 0; k < i; k++) { -/* printf("c"); */ -/* if (loadb((int)&(rx1[*replysize+1+k])) != tx1[k]) { */ - printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx1[*replysize+1+k])), (unsigned)tx1[k]); -/* exit(1); */ -/* } */ + if (loadb((int)&(rx1[*replysize+1+k])) != tx1[k]) { + printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx1[*replysize+1+k])), (unsigned)tx1[k]); + exit(1); + } } } else { @@ -1502,19 +1451,15 @@ int main(int argc, char *argv[]) for(j = 0; j < i; j++) { tx1[j] = ~tx1[j]; } - /* if (m >= 4) { */ -/* cmd->incr = no; */ -/* } else { */ - cmd->incr = yes; -/* } */ + cmd->incr = yes; cmd->type = writecmd; cmd->verify = yes; cmd->ack = yes; - cmd->destaddr = 0xFE; - cmd->destkey = 0x00; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = i; - cmd->addr = 0xa0000000; + cmd->addr = (int)rx3; cmd->len = i; cmd->status = 0; cmd->dstspalen = 0; @@ -1528,29 +1473,19 @@ int main(int argc, char *argv[]) reply->type = writerep; reply->verify = yes; reply->ack = yes; -/* if (m >= 4) { */ -/* reply->incr = no; */ - -/* } else { */ - reply->incr = yes; -/* } */ - /* if ( (((((int)&(rx0[(m%4)])) % 2) != 0) && (cmd->len == 2)) || */ -/* (((((int)&(rx0[(m%4)])) % 4) != 0) && (cmd->len == 4)) || */ -/* (cmd->len == 3) ) { */ -/* reply->status = 10; */ -/* } else { */ - reply->status = 0; - if (cmd->len == 3) { - reply->status = 10; - } - if (cmd->len > 4) { - reply->status = 9; - } - reply->destaddr = 0xFE; - reply->destkey = 0x00; - reply->srcaddr = 0x1; + reply->incr = yes; + reply->status = 0; + if (cmd->len == 3) { + reply->status = 10; + } + if (cmd->len > 4) { + reply->status = 9; + } + reply->destaddr = spw2->nodeaddr; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = i; - reply->addr = 0xa0000000; + reply->addr = (int)rx3; reply->len = i; reply->dstspalen = 0; reply->dstspa = (char *)NULL; @@ -1581,7 +1516,6 @@ int main(int argc, char *argv[]) exit(0); } for (k = 0; k < 64; k++) {} - /* printf("0x%x\n", spw2->regs->status);*/ iterations++; } if (rxs->truncated) { @@ -1611,18 +1545,6 @@ int main(int argc, char *argv[]) exit(1); } } - if (reply->status == 0) { - /* for(k = 0; k < i; k++) { */ -/* if (loadb((int)&(rx0[k+(m%4)])) != tx1[k]) { */ -/* printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx0[k+(m%4)])), (unsigned)tx1[k]); */ -/* exit(1); */ -/* } */ -/* } */ - - } - /* if (((i % 4) == 0) && ((m % 8) == 0)) { */ -/* printf("Packet %i, alignment %i\n", i, m); */ -/* } */ } } printf("\n"); @@ -1634,19 +1556,15 @@ int main(int argc, char *argv[]) for(j = 0; j < i; j++) { tx1[j] = ~tx1[j]; } -/* if (m >= 4) { */ -/* cmd->incr = no; */ -/* } else { */ - cmd->incr = yes; -/* } */ + cmd->incr = yes; cmd->type = rmwcmd; cmd->verify = yes; cmd->ack = yes; - cmd->destaddr = 0xFE; - cmd->destkey = 0x00; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = i; - cmd->addr = 0xa0000000; + cmd->addr = (int)rx3; cmd->len = i; cmd->status = 0; cmd->dstspalen = 0; @@ -1660,37 +1578,26 @@ int main(int argc, char *argv[]) reply->type = rmwrep; reply->verify = yes; reply->ack = yes; - /* if (m >= 4) { */ -/* reply->incr = no; */ - -/* } else { */ - reply->incr = yes; -/* } */ - /* if ( (((((int)&(rx0[(m%4)])) % 2) != 0) && ((cmd->len/2) == 2)) || */ -/* (((((int)&(rx0[(m%4)])) % 4) != 0) && ((cmd->len/2) == 4)) || */ -/* ((cmd->len/2) == 3) ) {*/ - if ((cmd->len/2) == 3) { - reply->status = 10; - } else { - reply->status = 0; - } + reply->incr = yes; + if ((cmd->len/2) == 3) { + reply->status = 10; + } else { + reply->status = 0; + } if ( (cmd->len != 0) && (cmd->len != 2) && (cmd->len != 4) && (cmd->len != 6) && (cmd->len != 8)) { - reply->status = 11; + reply->status = 11; } - /* if (m >= 4) { */ -/* reply->status = 2; */ -/* } */ if (reply->status == 0) { for(k = 0; k < (i/2); k++) { rx2[*replysize+1+k] = loadb((int)&(rx0[k+m])); } } - reply->destaddr = 0xFE; - reply->destkey = 0x00; - reply->srcaddr = 0x1; + reply->destaddr = spw2->nodeaddr; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = i; - reply->addr = 0xa0000000; + reply->addr = (int)rx3; if (reply->status == 0) { reply->len = (i/2); } else { @@ -1725,7 +1632,6 @@ int main(int argc, char *argv[]) exit(0); } for (k = 0; k < 64; k++) {} - /* printf("0x%x\n", spw2->regs->status);*/ iterations++; } if (rxs->truncated) { @@ -1763,24 +1669,6 @@ int main(int argc, char *argv[]) exit(1); } } - if (reply->status == 0) { - /* for(k = *replysize+1; k < *replysize+1+(i/2); k++) { */ -/* if (loadb((int)&(rx1[k])) != rx2[k]) { */ -/* printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx1[k])), (unsigned)rx2[k]); */ -/* exit(1); */ -/* } */ -/* } */ -/* for(k = 0; k < (i/2); k++) { */ -/* if (loadb((int)&(rx0[k+(m%4)])) != ((tx1[k] & tx1[k+(i/2)]) | (rx2[*replysize+1+k] & ~tx1[k+(i/2)]) )) { */ -/* printf("Compare error 2: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx0[k+(m%4)])), (unsigned)tx1[k]); */ -/* exit(1); */ -/* } */ -/* } */ - - } - /* if (((i % 4) == 0) && ((m % 8) == 0)) { */ -/* printf("Packet %i, alignment %i\n", i, m); */ -/* } */ } } printf("\n"); @@ -1792,19 +1680,15 @@ int main(int argc, char *argv[]) for(j = 0; j < i+4; j++) { rx0[j] = ~rx0[j]; } - /* if (m >= 4) { */ - /* cmd->incr = no; */ -/* } else { */ - cmd->incr = yes; -/* } */ + cmd->incr = yes; cmd->type = readcmd; cmd->verify = no; cmd->ack = yes; - cmd->destaddr = 0xFE; - cmd->destkey = 0x00; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = i; - cmd->addr = 0xa0000000; + cmd->addr = (int)rx1; cmd->len = i; cmd->status = 0; cmd->dstspalen = 0; @@ -1818,28 +1702,18 @@ int main(int argc, char *argv[]) reply->type = readrep; reply->verify = no; reply->ack = yes; - /* if (m >= 4) { */ -/* reply->incr = no; */ - /* if ( ((((int)&(rx0[(m%4)])) % 4) != 0) || ((cmd->len % 4) != 0) ) { */ - /* if ((cmd->len % 4) != 0) { */ -/* reply->status = 10; */ -/* } else { */ -/* reply->status = 0; */ -/* } */ - /* } else { */ - reply->incr = yes; - reply->status = 0; -/* } */ + reply->incr = yes; + reply->status = 0; if (reply->status == 0) { reply->len = i; } else { reply->len = 0; } - reply->destaddr = 0xFE; - reply->destkey = 0x00; - reply->srcaddr = 0x1; + reply->destaddr = spw2->nodeaddr; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = i; - reply->addr = 0xa0000000; + reply->addr = (int)rx1; reply->dstspalen = 0; reply->dstspa = (char *)NULL; reply->srcspalen = 0; @@ -1869,7 +1743,6 @@ int main(int argc, char *argv[]) exit(0); } for (k = 0; k < 64; k++) {} - /* printf("0x%x\n", spw2->regs->status);*/ iterations++; } if (rxs->truncated) { @@ -1899,31 +1772,12 @@ int main(int argc, char *argv[]) printf("Received packet has wrong length\n"); printf("Expected: %i, Got: %i \n", *replysize+2+i, *size); } - /* if (cmd->incr == yes) { */ -/* for(k = 0; k < i; k++) { */ -/* if (loadb((int)&(rx1[*replysize+1+k])) != rx0[k+(m%4)]) { */ -/* printf("Compare error 1: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx1[*replysize+1+k])), (unsigned)rx0[k+(m%4)]); */ -/* exit(1); */ -/* } */ -/* } */ -/* } else { */ -/* for(k = 0; k < i; k++) { */ -/* if (loadb((int)&(rx1[*replysize+1+k])) != rx0[(k%4)+(m%4)]) { */ -/* printf("Compare error 2: %u Data: %x Expected: %x \n", k, (unsigned)loadb((int)&(rx1[*replysize+1+k])), (unsigned)rx0[(k%4)+(m%4)]); */ -/* printf("Rx1: %x, Rx0: %x\n", (int)rx1, (int)rx0); */ -/* //exit(1); */ -/* } */ -/* } */ -/* } */ } else { if (*size != (*replysize+2)) { printf("Received packet has wrong length\n"); printf("Expected: %i, Got: %i \n", *replysize+2, *size); } } - /* if ((i % 512) == 0) { */ -/* printf("Packet %i, alignment %i\n", i, m); */ -/* } */ } } printf("\n"); @@ -1939,7 +1793,6 @@ int main(int argc, char *argv[]) } for (j = tmp; j < i; j++) { for (m = 0; m < 3; m++) { -/* printf("Packet %i, type %i, offset: %i\n", i, m, j); */ for(k = 0; k < i; k++) { tx1[k] = ~tx1[k]; } @@ -1961,9 +1814,9 @@ int main(int argc, char *argv[]) } cmd->incr = yes; cmd->ack = yes; - cmd->destaddr = 0x2; - cmd->destkey = 0xBF; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = i; cmd->addr = (int)rx0; cmd->len = i; @@ -2016,9 +1869,9 @@ int main(int argc, char *argv[]) } reply->incr = yes; reply->ack = yes; - reply->destaddr = 0x2; - reply->destkey = 0xBF; - reply->srcaddr = 0x1; + reply->destaddr = spw2->nodeaddr; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = i; reply->addr = (int)rx0; reply->dstspalen = 0; @@ -2055,7 +1908,6 @@ int main(int argc, char *argv[]) exit(0); } for (k = 0; k < 64; k++) {} - /* printf("0x%x\n", spw2->regs->status);*/ iterations++; } if (rxs->truncated) { @@ -2188,17 +2040,18 @@ int main(int argc, char *argv[]) } if (m < 3) { - cmd->destaddr = 0x2; - cmd->srcaddr = 0x1; + cmd->destaddr = spw2->nodeaddr; + cmd->srcaddr = spw1->nodeaddr; + cmd->destkey = spw2->destkey; } else { - cmd->destaddr = 0x1; - cmd->srcaddr = 0x2; + cmd->destaddr = spw1->nodeaddr; + cmd->srcaddr = spw2->nodeaddr; + cmd->destkey = spw1->destkey; } cmd->incr = no; cmd->ack = yes; - cmd->destkey = 0xBF; cmd->tid = i; cmd->addr = (int)(rx0); cmd->len = i; @@ -2348,8 +2201,8 @@ int main(int argc, char *argv[]) cmd->verify = no; cmd->ack = yes; cmd->destaddr = destaddr; - cmd->destkey = 0xBF; - cmd->srcaddr = 0x1; + cmd->destkey = spw2->destkey; + cmd->srcaddr = spw1->nodeaddr; cmd->tid = (i % 65536); cmd->addr = (int)&(rx1[0]); cmd->len = 128; @@ -2371,8 +2224,8 @@ int main(int argc, char *argv[]) reply->incr = yes; } reply->destaddr = destaddr; - reply->destkey = 0xBF; - reply->srcaddr = 0x1; + reply->destkey = spw2->destkey; + reply->srcaddr = spw1->nodeaddr; reply->tid = (i % 65536); reply->addr = (int)&(rx1[0]); reply->len = 0; diff --git a/software/spw/spwapi.c b/software/spw/spwapi.c index a0fb78d6..2b07832a 100644 --- a/software/spw/spwapi.c +++ b/software/spw/spwapi.c @@ -10,8 +10,8 @@ /* See the file COPYING for the full details of the license. */ /*****************************************************************************/ -#include "spwapi.h" #include +#include "spwapi.h" static char *almalloc(int sz) { @@ -42,7 +42,7 @@ static inline int loadmem(int addr) int spw_setparam(int nodeaddr, int clkdiv, int destkey, int timetxen, int timerxen, int spwadr, int khz, struct spwvars *spw, int port, - int clkdivs) + int clkdivs) { if ((nodeaddr < 0) || (nodeaddr > 255)) { return 1; @@ -74,7 +74,8 @@ int spw_setparam(int nodeaddr, int clkdiv, int destkey, return 0; } -int spw_setparam_dma(int dmachan, int addr, int mask, int nospill, int rxmaxlen, struct spwvars *spw) +int spw_setparam_dma(int dmachan, int addr, int mask, int nospill, + int rxmaxlen, struct spwvars *spw) { if ((addr < 0) || (addr > 255)) { return 1; @@ -112,6 +113,16 @@ int spw_init(struct spwvars *spw) spw->rxunaligned = (tmp >> 30) & 1; spw->rmapcrc = (tmp >> 29) & 1; spw->dmachan = ((tmp >> 27) & 3) + 1; + spw->pnp = ((tmp >> 18) & 3); + if ((tmp >> 24) & 1) { + tmp = loadmem((int)&(spw->regs->intdist.ctrl)); + spw->intdist = ((tmp >> 13) & 7); + } else { + spw->intdist = 0; + } + tmp = loadmem((int)&(spw->regs->status)); + spw->ntxdesc = 64 << ((tmp >> 24) & 3); + spw->nrxdesc = 128 << ((tmp >> 26) & 3); /*reset core */ spw->regs->ctrl = (1 << 6); tmp = loadmem((int)&(spw->regs->ctrl)); @@ -133,19 +144,19 @@ int spw_init(struct spwvars *spw) spw->regs->destkey = spw->destkey; } for(i = 0; i < spw->dmachan; i++) { - spw->regs->dma[i].ctrl = 0xFFFE01E0; /*clear status, set ctrl for dma chan*/ + spw->regs->dma[i].ctrl = 0x00CC01E0; /*clear status, set ctrl for dma chan*/ if (loadmem((int)&(spw->regs->dma[i].ctrl)) != 0) { return 2; } /* set tx descriptor pointer*/ - if ((spw->dma[i].txd = (struct txdescriptor *)almalloc(1024)) == NULL) { + if ((spw->dma[i].txd = (struct txdescriptor *)almalloc(spw->ntxdesc*16)) == NULL) { return 3; } spw->dma[i].txpnt = 0; spw->dma[i].txchkpnt = 0; spw->regs->dma[i].txdesc = (int) spw->dma[i].txd; /* set rx descriptor pointer*/ - if (( spw->dma[i].rxd = (struct rxdescriptor *)almalloc(1024)) == NULL) { + if (( spw->dma[i].rxd = (struct rxdescriptor *)almalloc(spw->nrxdesc*8)) == NULL) { return 4; } spw->dma[i].rxpnt = 0; @@ -155,7 +166,7 @@ int spw_init(struct spwvars *spw) spw->regs->status = 0xFFF; /*clear status*/ spw->regs->ctrl = 0x2 | (spw->timetxen << 10) | (spw->timerxen << 11) | (spw->port << 21); /*set ctrl*/ for(i = 0; i < spw->dmachan; i++) { - spw->regs->dma[i].ctrl = loadmem((int)&(spw->regs->dma[i].ctrl)) | (spw->dma[i].nospill << 12); + spw->regs->dma[i].ctrl = loadmem((int)&(spw->regs->dma[i].ctrl)) | (spw->dma[i].nospill << 12); } return 0; } @@ -200,22 +211,22 @@ int set_rxdesc(int dmachan, int pnt, struct spwvars *spw) void spw_disable(struct spwvars *spw) { - spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) | 1; + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) | 0x1; } void spw_enable(struct spwvars *spw) { - spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & 0x220F7E; + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & ~0x1; } void spw_start(struct spwvars *spw) { - spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) | (1 << 1); + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) | 0x2; } void spw_stop(struct spwvars *spw) { - spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & 0x220F7D; + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & ~0x2; } int spw_setclockdiv(struct spwvars *spw) @@ -283,7 +294,7 @@ int spw_tx(int dmachan, int hcrc, int dcrc, int skipcrcsize, int hsize, char *hb spw->dma[dmachan].txd[spw->dma[dmachan].txpnt].haddr = (int)hbuf; spw->dma[dmachan].txd[spw->dma[dmachan].txpnt].dlen = dsize; spw->dma[dmachan].txd[spw->dma[dmachan].txpnt].daddr = (int)dbuf; - if (spw->dma[dmachan].txpnt == 63) { + if (spw->dma[dmachan].txpnt == (spw->ntxdesc-1)) { spw->dma[dmachan].txd[spw->dma[dmachan].txpnt].ctrl = 0x3000 | hsize | (hcrc << 16) | (dcrc << 17) | (skipcrcsize << 8); spw->dma[dmachan].txpnt = 0; } else { @@ -291,7 +302,7 @@ int spw_tx(int dmachan, int hcrc, int dcrc, int skipcrcsize, int hsize, char *hb spw->dma[dmachan].txpnt++; } - spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & 0xFAAA | 1; + spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & 0xF8C6FAAA | 1; return 0; } @@ -302,14 +313,14 @@ int spw_rx(int dmachan, char *buf, struct spwvars *spw) return 1; } spw->dma[dmachan].rxd[spw->dma[dmachan].rxpnt].daddr = (int)buf; - if (spw->dma[dmachan].rxpnt == 127) { + if (spw->dma[dmachan].rxpnt == (spw->nrxdesc-1)) { spw->dma[dmachan].rxd[spw->dma[dmachan].rxpnt].ctrl = 0x6000000; spw->dma[dmachan].rxpnt = 0; } else { spw->dma[dmachan].rxd[spw->dma[dmachan].rxpnt].ctrl = 0x2000000; spw->dma[dmachan].rxpnt++; } - spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & 0xF955 | 2 | (1 << 11); + spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & 0xF8C8F955 | 2 | (1 << 11); return 0; } @@ -323,7 +334,7 @@ int spw_checkrx(int dmachan, int *size, struct rxstatus *rxs, struct spwvars *sp rxs->dcrcerr = (tmp >> 30) & 1; rxs->hcrcerr = (tmp >> 29) & 1; rxs->eep = (tmp >> 28) & 1; - if (spw->dma[dmachan].rxchkpnt == 127) { + if (spw->dma[dmachan].rxchkpnt == (spw->nrxdesc-1)) { spw->dma[dmachan].rxchkpnt = 0; } else { spw->dma[dmachan].rxchkpnt++; @@ -339,7 +350,7 @@ int spw_checktx(int dmachan, struct spwvars *spw) int tmp; tmp = loadmem((int)&(spw->dma[dmachan].txd[spw->dma[dmachan].txchkpnt].ctrl)); if (!((tmp >> 12) & 1)) { - if (spw->dma[dmachan].txchkpnt == 63) { + if (spw->dma[dmachan].txchkpnt == (spw->ntxdesc-1)) { spw->dma[dmachan].txchkpnt = 0; } else { spw->dma[dmachan].txchkpnt++; @@ -368,7 +379,7 @@ int send_time_exp(int ctrl, int time, struct spwvars *spw) int i; int code; if ((time < 0) || (time > 63)) { - printf("Illegal time-value"); + printf("Illegal time-value\n"); return -1; } if (time == 0) { @@ -417,7 +428,17 @@ void spw_rmapen(struct spwvars *spw) void spw_rmapdis(struct spwvars *spw) { - spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & 0x2EFFFF; + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & ~(1 << 16); +} + +void spw_pnpen(struct spwvars *spw) +{ + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) | (1 << 15); +} + +void spw_pnppdis(struct spwvars *spw) +{ + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & ~(1 << 15); } int spw_setdestkey(struct spwvars *spw) @@ -436,7 +457,7 @@ void spw_setsepaddr(int dmachan, struct spwvars *spw) void spw_disablesepaddr(int dmachan, struct spwvars *spw) { - spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & 0xFFFFDFFF; + spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & ~(1 << 13); } @@ -448,16 +469,15 @@ void spw_enablerx(int dmachan, struct spwvars *spw) void spw_disablerx(int dmachan, struct spwvars *spw) { - spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & 0xFFFFFFFD; + spw->regs->dma[dmachan].ctrl = loadmem((int)&(spw->regs->dma[dmachan].ctrl)) & ~0x2; } void spw_disable_promiscuous(struct spwvars *spw) { - spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & 0xFFFFFFDF; + spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) & ~(1 << 5); } void spw_enable_promiscuous(struct spwvars *spw) { spw->regs->ctrl = loadmem((int)&(spw->regs->ctrl)) | (1 << 5); } - diff --git a/software/spw/spwapi.h b/software/spw/spwapi.h index 7cab8ebc..8d802f45 100644 --- a/software/spw/spwapi.h +++ b/software/spw/spwapi.h @@ -20,6 +20,34 @@ struct dmachanregs volatile int unused[3]; }; +struct intdistregs +{ + volatile int ctrl; + volatile int intrx; + volatile int ackrx; + volatile int intto; + volatile int tomask; + volatile int aamask; + volatile int scaler; + volatile int isrtimer; + volatile int iatimer; + volatile int ctimer; + volatile int isr; + volatile int unused; +}; + +struct pnpregs +{ + volatile int vendid; + volatile int linkinfo; + volatile int oa1; + volatile int oa2; + volatile int oa3; + volatile int devid; + volatile int uvendid; + volatile int usn; +}; + struct spwregs { volatile int ctrl; @@ -31,6 +59,9 @@ struct spwregs volatile int timer; volatile int unused; struct dmachanregs dma[4]; + struct intdistregs intdist; + volatile int unused2; + struct pnpregs pnp; }; struct txdescriptor @@ -89,6 +120,13 @@ struct spwvars int destkey; int port; struct dmachanvar dma[4]; + int intdist; + int pnp; + int ntxdesc; + int nrxdesc; + int inttxen; + int intrxen; + int pnpen; }; int spw_init(struct spwvars *spw);