diff --git a/dev/fbcon/fbcon.c b/dev/fbcon/fbcon.c index ce627a3fb..66d4243b5 100755 --- a/dev/fbcon/fbcon.c +++ b/dev/fbcon/fbcon.c @@ -190,6 +190,9 @@ void fbcon_setup(struct fbcon_config *_config) cur_pos.y = 0; max_pos.x = config->width / (FONT_WIDTH+1); max_pos.y = (config->height - 1) / FONT_HEIGHT; +#if !DISPLAY_SPLASH_SCREEN + fbcon_clear(); +#endif } struct fbcon_config* fbcon_display(void) diff --git a/dev/keys/gpio_keypad.c b/dev/keys/gpio_keypad.c index abd894a6f..4fc2e4eef 100644 --- a/dev/keys/gpio_keypad.c +++ b/dev/keys/gpio_keypad.c @@ -542,3 +542,13 @@ void ssbi_keypad_init(struct qwerty_keypad_info *qwerty_kp) event_wait(&qwerty_keypad->full_scan); } +void pmic_write(unsigned address, unsigned data) +{ + write_func wr_function = &i2c_ssbi_write_bytes; + if(wr_function == NULL) + return; + if ((*wr_function)(&data, 1, address)) + dprintf (CRITICAL, "Error in initializing register\n"); + +} + diff --git a/platform/msm7x30/gpio.c b/platform/msm7x30/gpio.c index c9662f2c5..1204944bf 100644 --- a/platform/msm7x30/gpio.c +++ b/platform/msm7x30/gpio.c @@ -2,6 +2,8 @@ * Copyright (c) 2008, Google Inc. * All rights reserved. * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -132,17 +134,16 @@ static gpioregs GPIO_REGS[] = { static gpioregs *find_gpio(unsigned n, unsigned *bit) { - if(n > 164) return 0; - if(n > 152) { - *bit = 1 << (n - 153); + if(n > 150) { + *bit = 1 << (n - 151); return GPIO_REGS + 7; } - if(n > 121) { - *bit = 1 << (n - 122); + if(n > 133) { + *bit = 1 << (n - 134); return GPIO_REGS + 6; } - if(n > 103) { - *bit = 1 << (n - 104); + if(n > 106) { + *bit = 1 << (n - 107); return GPIO_REGS + 5; } if(n > 94) { @@ -153,8 +154,8 @@ static gpioregs *find_gpio(unsigned n, unsigned *bit) *bit = 1 << (n - 68); return GPIO_REGS + 3; } - if(n > 42) { - *bit = 1 << (n - 43); + if(n > 43) { + *bit = 1 << (n - 44); return GPIO_REGS + 2; } if(n > 15) { @@ -218,3 +219,23 @@ void platform_config_interleaved_mode_gpios(void) writel (GPIO_ALT_FUNC_PAGE_REG, 0x73); writel (GPIO_ALT_FUNC_CFG_REG, 0x08); } + +/* Enables all gpios passed in table*/ +int platform_gpios_enable(const struct msm_gpio *table, int size) +{ + int rc; + int i; + const struct msm_gpio *g; + for (i = 0; i < size; i++) { + g = table + i; + /* Enable gpio */ + rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE); + if (rc) { + goto err; + } + } + return 0; +err: + return rc; +} + diff --git a/platform/msm7x30/gpio_hw.h b/platform/msm7x30/gpio_hw.h index e9ff8ed21..692704283 100644 --- a/platform/msm7x30/gpio_hw.h +++ b/platform/msm7x30/gpio_hw.h @@ -2,6 +2,8 @@ * Copyright (c) 2008, Google Inc. * All rights reserved. * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -29,95 +31,149 @@ #ifndef __PLATFORM_MSM7X30_GPIO_HW_H #define __PLATFORM_MSM7X30_GPIO_HW_H -#define MSM_GPIO1_BASE 0xA9000000 -#define MSM_GPIO2_BASE 0xA9100000 +#define MSM_GPIO1_BASE 0xAC001000 +#define MSM_GPIO2_BASE 0xAC101000 -#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off)) -#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off)) +#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off)) +#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off)) /* output value */ #define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */ -#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 42-16 */ -#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-43 */ +#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 43-16 */ +#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-44 */ #define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */ -#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 103-95 */ -#define GPIO_OUT_5 GPIO1_REG(0x10) /* gpio 121-104 */ -#define GPIO_OUT_6 GPIO1_REG(0x14) /* gpio 152-122 */ -#define GPIO_OUT_7 GPIO1_REG(0x18) /* gpio 164-153 */ +#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */ +#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 133-107 */ +#define GPIO_OUT_6 GPIO1_REG(0xC4) /* gpio 150-134 */ +#define GPIO_OUT_7 GPIO1_REG(0x214) /* gpio 181-151 */ /* same pin map as above, output enable */ -#define GPIO_OE_0 GPIO1_REG(0x20) +#define GPIO_OE_0 GPIO1_REG(0x10) #define GPIO_OE_1 GPIO2_REG(0x08) -#define GPIO_OE_2 GPIO1_REG(0x24) -#define GPIO_OE_3 GPIO1_REG(0x28) -#define GPIO_OE_4 GPIO1_REG(0x2C) -#define GPIO_OE_5 GPIO1_REG(0x30) -#define GPIO_OE_6 GPIO1_REG(0x34) -#define GPIO_OE_7 GPIO1_REG(0x38) +#define GPIO_OE_2 GPIO1_REG(0x14) +#define GPIO_OE_3 GPIO1_REG(0x18) +#define GPIO_OE_4 GPIO1_REG(0x1C) +#define GPIO_OE_5 GPIO1_REG(0x54) +#define GPIO_OE_6 GPIO1_REG(0xC8) +#define GPIO_OE_7 GPIO1_REG(0x218) /* same pin map as above, input read */ -#define GPIO_IN_0 GPIO1_REG(0x50) +#define GPIO_IN_0 GPIO1_REG(0x34) #define GPIO_IN_1 GPIO2_REG(0x20) -#define GPIO_IN_2 GPIO1_REG(0x54) -#define GPIO_IN_3 GPIO1_REG(0x58) -#define GPIO_IN_4 GPIO1_REG(0x5C) -#define GPIO_IN_5 GPIO1_REG(0x60) -#define GPIO_IN_6 GPIO1_REG(0x64) -#define GPIO_IN_7 GPIO1_REG(0x68) +#define GPIO_IN_2 GPIO1_REG(0x38) +#define GPIO_IN_3 GPIO1_REG(0x3C) +#define GPIO_IN_4 GPIO1_REG(0x40) +#define GPIO_IN_5 GPIO1_REG(0x44) +#define GPIO_IN_6 GPIO1_REG(0xCC) +#define GPIO_IN_7 GPIO1_REG(0x21C) /* same pin map as above, 1=edge 0=level interrup */ -#define GPIO_INT_EDGE_0 GPIO1_REG(0x70) +#define GPIO_INT_EDGE_0 GPIO1_REG(0x60) #define GPIO_INT_EDGE_1 GPIO2_REG(0x50) -#define GPIO_INT_EDGE_2 GPIO1_REG(0x74) -#define GPIO_INT_EDGE_3 GPIO1_REG(0x78) -#define GPIO_INT_EDGE_4 GPIO1_REG(0x7C) -#define GPIO_INT_EDGE_5 GPIO1_REG(0x80) -#define GPIO_INT_EDGE_6 GPIO1_REG(0x84) -#define GPIO_INT_EDGE_7 GPIO1_REG(0x88) +#define GPIO_INT_EDGE_2 GPIO1_REG(0x64) +#define GPIO_INT_EDGE_3 GPIO1_REG(0x68) +#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C) +#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0) +#define GPIO_INT_EDGE_6 GPIO1_REG(0xD0) +#define GPIO_INT_EDGE_7 GPIO1_REG(0x240) /* same pin map as above, 1=positive 0=negative */ -#define GPIO_INT_POS_0 GPIO1_REG(0x90) +#define GPIO_INT_POS_0 GPIO1_REG(0x70) #define GPIO_INT_POS_1 GPIO2_REG(0x58) -#define GPIO_INT_POS_2 GPIO1_REG(0x94) -#define GPIO_INT_POS_3 GPIO1_REG(0x98) -#define GPIO_INT_POS_4 GPIO1_REG(0x9C) -#define GPIO_INT_POS_5 GPIO1_REG(0xA0) -#define GPIO_INT_POS_6 GPIO1_REG(0xA4) -#define GPIO_INT_POS_7 GPIO1_REG(0xA8) +#define GPIO_INT_POS_2 GPIO1_REG(0x74) +#define GPIO_INT_POS_3 GPIO1_REG(0x78) +#define GPIO_INT_POS_4 GPIO1_REG(0x7C) +#define GPIO_INT_POS_5 GPIO1_REG(0xBC) +#define GPIO_INT_POS_6 GPIO1_REG(0xD4) +#define GPIO_INT_POS_7 GPIO1_REG(0x228) /* same pin map as above, interrupt enable */ -#define GPIO_INT_EN_0 GPIO1_REG(0xB0) +#define GPIO_INT_EN_0 GPIO1_REG(0x80) #define GPIO_INT_EN_1 GPIO2_REG(0x60) -#define GPIO_INT_EN_2 GPIO1_REG(0xB4) -#define GPIO_INT_EN_3 GPIO1_REG(0xB8) -#define GPIO_INT_EN_4 GPIO1_REG(0xBC) -#define GPIO_INT_EN_5 GPIO1_REG(0xC0) -#define GPIO_INT_EN_6 GPIO1_REG(0xC4) -#define GPIO_INT_EN_7 GPIO1_REG(0xC8) +#define GPIO_INT_EN_2 GPIO1_REG(0x84) +#define GPIO_INT_EN_3 GPIO1_REG(0x88) +#define GPIO_INT_EN_4 GPIO1_REG(0x8C) +#define GPIO_INT_EN_5 GPIO1_REG(0xB8) +#define GPIO_INT_EN_6 GPIO1_REG(0xD8) +#define GPIO_INT_EN_7 GPIO1_REG(0x22C) /* same pin map as above, write 1 to clear interrupt */ -#define GPIO_INT_CLEAR_0 GPIO1_REG(0xD0) +#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90) #define GPIO_INT_CLEAR_1 GPIO2_REG(0x68) -#define GPIO_INT_CLEAR_2 GPIO1_REG(0xD4) -#define GPIO_INT_CLEAR_3 GPIO1_REG(0xD8) -#define GPIO_INT_CLEAR_4 GPIO1_REG(0xDC) -#define GPIO_INT_CLEAR_5 GPIO1_REG(0xE0) -#define GPIO_INT_CLEAR_6 GPIO1_REG(0xE4) -#define GPIO_INT_CLEAR_7 GPIO1_REG(0xE8) +#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94) +#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98) +#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C) +#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4) +#define GPIO_INT_CLEAR_6 GPIO1_REG(0xDC) +#define GPIO_INT_CLEAR_7 GPIO1_REG(0x230) /* same pin map as above, 1=interrupt pending */ -#define GPIO_INT_STATUS_0 GPIO1_REG(0xF0) +#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0) #define GPIO_INT_STATUS_1 GPIO2_REG(0x70) -#define GPIO_INT_STATUS_2 GPIO1_REG(0xF4) -#define GPIO_INT_STATUS_3 GPIO1_REG(0xF8) -#define GPIO_INT_STATUS_4 GPIO1_REG(0xFC) -#define GPIO_INT_STATUS_5 GPIO1_REG(0x100) -#define GPIO_INT_STATUS_6 GPIO1_REG(0x103) -#define GPIO_INT_STATUS_7 GPIO1_REG(0x108) +#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4) +#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8) +#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC) +#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0) +#define GPIO_INT_STATUS_6 GPIO1_REG(0xE0) +#define GPIO_INT_STATUS_7 GPIO1_REG(0x234) #define GPIO_OUT_VAL_REG_BASE 0xABC00000 #define GPIO_ALT_FUNC_PAGE_REG (GPIO_OUT_VAL_REG_BASE + 0x20) #define GPIO_ALT_FUNC_CFG_REG (GPIO_OUT_VAL_REG_BASE + 0x24) +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_ENABLE 0 +#define GPIO_DISABLE 1 + +#define GPIO_CFG(gpio, func, dir, pull, drvstr) \ + ((((gpio) & 0x3FF) << 4) | \ + ((func) & 0xf) | \ + (((dir) & 0x1) << 14) | \ + (((pull) & 0x3) << 15) | \ + (((drvstr) & 0xF) << 17)) + +/** + * struct msm_gpio - GPIO pin description + * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config() + * @label - textual label + * + * Usually, GPIO's are operated by sets. + * This struct accumulate all GPIO information in single source + * and facilitete group operations provided by msm_gpios_xxx() + */ +struct msm_gpio { + unsigned gpio_cfg; + const char *label; +}; + +/** + * extract GPIO pin from bit-field used for gpio_tlmm_config + */ +#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff) +#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf) +#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1) +#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3) +#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf) + #endif diff --git a/platform/msm7x30/platform.c b/platform/msm7x30/platform.c index 672d25906..eab68cff3 100644 --- a/platform/msm7x30/platform.c +++ b/platform/msm7x30/platform.c @@ -63,6 +63,11 @@ void platform_init(void) void display_init(void) { - //fb_cfg = lcdc_init(); - //fbcon_setup(fb_cfg); +#if DISPLAY_TYPE_LCDC + struct fbcon_config *fb_cfg; + mdp_clock_init(122880000); + fb_cfg = lcdc_init(); + panel_poweron(); + fbcon_setup(fb_cfg); +#endif } diff --git a/platform/msm7x30/rules.mk b/platform/msm7x30/rules.mk index 83acb567b..4f1f758b6 100644 --- a/platform/msm7x30/rules.mk +++ b/platform/msm7x30/rules.mk @@ -8,7 +8,7 @@ CPU := generic MMC_SLOT := 2 DEFINES += WITH_CPU_EARLY_INIT=1 WITH_CPU_WARM_BOOT=1 \ - MMC_SLOT=$(MMC_SLOT) + MMC_SLOT=$(MMC_SLOT) MDP4=1 INCLUDES += -I$(LOCAL_DIR)/include diff --git a/platform/msm_shared/lcdc.c b/platform/msm_shared/lcdc.c index 7ac4092f3..75dfe0ccb 100755 --- a/platform/msm_shared/lcdc.c +++ b/platform/msm_shared/lcdc.c @@ -2,6 +2,8 @@ * Copyright (c) 2008, Google Inc. * All rights reserved. * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: @@ -33,7 +35,13 @@ #include #include +#if MDP4 +#define MSM_MDP_BASE1 0xA3F00000 +#define LCDC_BASE 0xC0000 +#else #define MSM_MDP_BASE1 0xAA200000 +#define LCDC_BASE 0xE0000 +#endif #define LCDC_PIXCLK_IN_PS 26 #define LCDC_FB_PHYS 0x16600000 @@ -66,6 +74,19 @@ static struct fbcon_config fb_cfg = { void lcdc_clock_init(unsigned rate); +#if MDP4 +void mdp4_display_intf_sel(int intf) +{ + unsigned bits, mask; + bits = readl(MSM_MDP_BASE1 + 0x0038); + mask = 0x03; /* 2 bits */ + intf &= 0x03; /* 2 bits */ + bits &= ~mask; + bits |= intf; + writel(bits, MSM_MDP_BASE1 + 0x0038); /* MDP_DISP_INTF_SEL */ +} +#endif + struct fbcon_config *lcdc_init(void) { dprintf(INFO, "lcdc_init(): panel is %d x %d\n", fb_cfg.width, fb_cfg.height); @@ -91,21 +112,32 @@ struct fbcon_config *lcdc_init(void) int display_vstart= (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES) * hsync_period + LCDC_HSYNC_SKEW_DCLK; int display_vend = vsync_period - (LCDC_VSYNC_FRONT_PORCH_LINES * hsync_period) + LCDC_HSYNC_SKEW_DCLK - 1; - writel((hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK, MSM_MDP_BASE1 + 0xe0004); - writel(vsync_period, MSM_MDP_BASE1 + 0xe0008); - writel(LCDC_VSYNC_PULSE_WIDTH_LINES * hsync_period, MSM_MDP_BASE1 + 0xe000c); - writel(display_hctl, MSM_MDP_BASE1 + 0xe0010); - writel(display_vstart, MSM_MDP_BASE1 + 0xe0014); - writel(display_vend, MSM_MDP_BASE1 + 0xe0018); - writel(0, MSM_MDP_BASE1 + 0xe0028); - writel(0xff, MSM_MDP_BASE1 + 0xe002c); - writel(LCDC_HSYNC_SKEW_DCLK, MSM_MDP_BASE1 + 0xe0030); - writel(0, MSM_MDP_BASE1 + 0xe0038); - writel(0, MSM_MDP_BASE1 + 0xe001c); - writel(0, MSM_MDP_BASE1 + 0xe0020); - writel(0, MSM_MDP_BASE1 + 0xe0024); - - writel(1, MSM_MDP_BASE1 + 0xe0000); + writel((hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK, MSM_MDP_BASE1 + LCDC_BASE + 0x4); + writel(vsync_period, MSM_MDP_BASE1 + LCDC_BASE + 0x8); + writel(LCDC_VSYNC_PULSE_WIDTH_LINES * hsync_period, MSM_MDP_BASE1 + LCDC_BASE + 0xc); + writel(display_hctl, MSM_MDP_BASE1 + LCDC_BASE + 0x10); + writel(display_vstart, MSM_MDP_BASE1 + LCDC_BASE + 0x14); + writel(display_vend, MSM_MDP_BASE1 + LCDC_BASE + 0x18); +#if MDP4 + writel(0xf, MSM_MDP_BASE1 + LCDC_BASE + 0x28); +#else + writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x28); +#endif + writel(0xff, MSM_MDP_BASE1 + LCDC_BASE + 0x2c); + writel(LCDC_HSYNC_SKEW_DCLK, MSM_MDP_BASE1 + LCDC_BASE + 0x30); +#if MDP4 + writel(0x3, MSM_MDP_BASE1 + LCDC_BASE + 0x38); +#else + writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x38); +#endif + writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x1c); + writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x20); + writel(0, MSM_MDP_BASE1 + LCDC_BASE + 0x24); +#if MDP4 + writel(0xB, MSM_MDP_BASE1 + 0x10004); + writel(0xB, MSM_MDP_BASE1 + 0x18004); +#endif + writel(1, MSM_MDP_BASE1 + LCDC_BASE + 0x0); return &fb_cfg; } diff --git a/platform/msm_shared/proc_comm.c b/platform/msm_shared/proc_comm.c index 1c8861bf3..45ced64b0 100644 --- a/platform/msm_shared/proc_comm.c +++ b/platform/msm_shared/proc_comm.c @@ -81,6 +81,9 @@ #define MDP_LCDC_PAD_PCLK_CLK 43 #define MDP_VSYNC_CLK 44 +/* msm7x30 adds... */ +#define MDP_P_CLK 86 + enum { PCOM_CMD_IDLE = 0x0, PCOM_CMD_DONE, @@ -118,6 +121,7 @@ enum { PCOM_GPIO_TLMM_UNCONFIG_GROUP, PCOM_NV_READ_HIGH_BITS, PCOM_NV_WRITE_HIGH_BITS, + PCOM_RPC_GPIO_TLMM_CONFIG_EX = 0x25, PCOM_RESERVED_101 = 0x65, PCOM_MSM_HSUSB_PHY_RESET, PCOM_GET_BATT_MV_LEVEL, @@ -221,15 +225,16 @@ static int clock_get_rate(unsigned id) void lcdc_clock_init(unsigned rate) { - clock_enable(100); - + clock_set_rate(MDP_LCDC_PCLK_CLK, rate); clock_enable(MDP_LCDC_PCLK_CLK); clock_enable(MDP_LCDC_PAD_PCLK_CLK); - - clock_set_rate(MDP_LCDC_PCLK_CLK, rate); - clock_set_rate(MDP_LCDC_PAD_PCLK_CLK, rate); +} +void mdp_clock_init (unsigned rate) +{ + clock_set_rate(MDP_CLK, rate); clock_enable(MDP_CLK); + clock_enable(MDP_P_CLK); } void uart3_clock_init(void) @@ -320,3 +325,26 @@ int mmc_clock_get_rate(unsigned id) return clock_get_rate(id); //Get mmc clock rate } +int gpio_tlmm_config(unsigned config, unsigned disable) +{ + return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable); +} + +int vreg_set_level(unsigned id, unsigned mv) +{ + return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv); +} + +int vreg_enable(unsigned id) +{ + int enable = 1; + return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); + +} + +int vreg_disable(unsigned id) +{ + int enable = 0; + return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); +} + diff --git a/project/msm7630_surf.mk b/project/msm7630_surf.mk index 70b89d60f..d107e94cd 100644 --- a/project/msm7630_surf.mk +++ b/project/msm7630_surf.mk @@ -8,4 +8,4 @@ MODULES += app/aboot #DEFINES += WITH_DEBUG_DCC=1 #DEFINES += WITH_DEBUG_UART=1 -#DEFINES += WITH_DEBUG_FBCON=1 \ No newline at end of file +#DEFINES += WITH_DEBUG_FBCON=1 diff --git a/target/msm7630_surf/include/target/display.h b/target/msm7630_surf/include/target/display.h index 17f05f9cd..69cd4ac52 100644 --- a/target/msm7630_surf/include/target/display.h +++ b/target/msm7630_surf/include/target/display.h @@ -29,19 +29,19 @@ #ifndef _TARGET_MSM7630_SURF_DISPLAY_H #define _TARGET_MSM7630_SURF_DISPLAY_H -#define TARGET_XRES 800 -#define TARGET_YRES 480 +#define TARGET_XRES 480 +#define TARGET_YRES 800 -#define LCDC_FB_WIDTH 800 -#define LCDC_FB_HEIGHT 480 +#define LCDC_FB_WIDTH 480 +#define LCDC_FB_HEIGHT 800 -#define LCDC_HSYNC_PULSE_WIDTH_DCLK 60 -#define LCDC_HSYNC_BACK_PORCH_DCLK 81 -#define LCDC_HSYNC_FRONT_PORCH_DCLK 81 +#define LCDC_HSYNC_PULSE_WIDTH_DCLK 8 +#define LCDC_HSYNC_BACK_PORCH_DCLK 184 +#define LCDC_HSYNC_FRONT_PORCH_DCLK 4 #define LCDC_HSYNC_SKEW_DCLK 0 -#define LCDC_VSYNC_PULSE_WIDTH_LINES 2 -#define LCDC_VSYNC_BACK_PORCH_LINES 20 -#define LCDC_VSYNC_FRONT_PORCH_LINES 27 +#define LCDC_VSYNC_PULSE_WIDTH_LINES 1 +#define LCDC_VSYNC_BACK_PORCH_LINES 2 +#define LCDC_VSYNC_FRONT_PORCH_LINES 3 #endif diff --git a/target/msm7630_surf/panel.c b/target/msm7630_surf/panel.c index c2b56a15f..1683a78e6 100644 --- a/target/msm7630_surf/panel.c +++ b/target/msm7630_surf/panel.c @@ -1,8 +1,45 @@ -/* Copyright 2007, Google Inc. */ +/* + * Copyright (c) 2007, Google Inc. + * All rights reserved. + * + * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Code Aurora nor + * the names of its contributors may be used to endorse or promote + * products derived from this software without specific prior written + * permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ #include #include #include +#include + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#if DISPLAY_TYPE_MDDI #include #define MDDI_CLIENT_CORE_BASE 0x108000 @@ -455,9 +492,11 @@ void panel_init(struct mddi_client_caps *client_caps) break; } } +#endif //mddi void panel_poweron(void) { +#if DISPLAY_TYPE_MDDI gpio_set(88, 0); gpio_config(88, GPIO_OUTPUT); thread_sleep(1); //udelay(10); @@ -465,7 +504,262 @@ void panel_poweron(void) thread_sleep(10); //mdelay(10); //mdelay(1000); // uncomment for second stage boot +#elif DISPLAY_TYPE_LCDC + panel_backlight(1); + lcdc_on(); +#endif } void panel_backlight(int on) -{} +{ + unsigned char reg_data = 0xA0; + if(on) + pmic_write(0x132, reg_data); + else + pmic_write(0x132, 0); +} + +static unsigned wega_reset_gpio = +GPIO_CFG(180, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA); + +#define LDO12_CNTRL 0x015 +#define LDO15_CNTRL 0x089 +#define LDO16_CNTRL 0x08A +#define LDO20_CNTRL 0x11F // PM8058 only +#define LDO_LOCAL_EN_BMSK 0x80 + +static int display_common_power(int on) +{ + int rc = 0, flag_on = !!on; + static int display_common_power_save_on; + unsigned int vreg_ldo12, vreg_ldo15, vreg_ldo20, vreg_ldo16, vreg_ldo8; + if (display_common_power_save_on == flag_on) + return 0; + + display_common_power_save_on = flag_on; + + if (on) { + /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */ + rc = gpio_tlmm_config(wega_reset_gpio, GPIO_ENABLE); + if (rc) { + return rc; + } + + gpio_set(180, 0); /* bring reset line low to hold reset*/ + } + + // Set power for WEGA chip. + // Set LD020 to 1.5V + pmic_write(LDO20_CNTRL, 0x00 | LDO_LOCAL_EN_BMSK); + mdelay(5); + + // Set LD012 to 1.8V + pmic_write(LDO12_CNTRL, 0x06 | LDO_LOCAL_EN_BMSK); + mdelay(5); + + // Set LD016 to 2.6V + pmic_write(LDO16_CNTRL, 0x16 | LDO_LOCAL_EN_BMSK); + mdelay(5); + + // Set LD015 to 3.0V + pmic_write(LDO15_CNTRL, 0x1E | LDO_LOCAL_EN_BMSK); + mdelay(5); + + gpio_set(180, 1); /* bring reset line high */ + mdelay(10); /* 10 msec before IO can be accessed */ + if (rc) { + return rc; + } + + return rc; +} + +#if DISPLAY_TYPE_LCDC +static struct msm_gpio lcd_panel_gpios[] = { + { GPIO_CFG(45, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_clk" }, + { GPIO_CFG(46, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_cs0" }, + { GPIO_CFG(47, 0, GPIO_OUTPUT, GPIO_NO_PULL, GPIO_2MA), "spi_mosi" }, + { GPIO_CFG(48, 0, GPIO_INPUT, GPIO_NO_PULL, GPIO_2MA), "spi_miso" } +}; + +int lcdc_toshiba_panel_power(int on) +{ + int rc, i; + struct msm_gpio *gp; + + rc = display_common_power(on); + if (rc < 0) { + return rc; + } + + if (on) { + rc = platform_gpios_enable(lcd_panel_gpios, + ARRAY_SIZE(lcd_panel_gpios)); + if(rc) + { + return rc; + } + } else { /* off */ + gp = lcd_panel_gpios; + for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) { + /* ouput low */ + gpio_set(GPIO_PIN(gp->gpio_cfg), 0); + gp++; + } + } + + return rc; +} + +#define SPI_SCLK 45 +#define SPI_CS 46 +#define SPI_MOSI 47 +#define SPI_MISO 48 + +static void toshiba_spi_write_byte(char dc, unsigned char data) +{ + unsigned bit; + int bnum; + + gpio_set(SPI_SCLK, 0); /* clk low */ + /* dc: 0 for command, 1 for parameter */ + gpio_set(SPI_MOSI, dc); + mdelay(1); /* at least 20 ns */ + gpio_set(SPI_SCLK, 1); /* clk high */ + mdelay(1); /* at least 20 ns */ + bnum = 8; /* 8 data bits */ + bit = 0x80; + while (bnum) { + gpio_set(SPI_SCLK, 0); /* clk low */ + if (data & bit) + gpio_set(SPI_MOSI, 1); + else + gpio_set(SPI_MOSI, 0); + mdelay(1); + gpio_set(SPI_SCLK, 1); /* clk high */ + mdelay(1); + bit >>= 1; + bnum--; + } +} + +static int toshiba_spi_write (char cmd, unsigned data, int num) +{ + char *bp; + gpio_set(SPI_CS, 1); /* cs high */ + + /* command byte first */ + toshiba_spi_write_byte(0, cmd); + + /* followed by parameter bytes */ + if (num) { + bp = (char *)&data;; + bp += (num - 1); + while (num) { + toshiba_spi_write_byte(1, *bp); + num--; + bp--; + } + } + gpio_set(SPI_CS, 0); /* cs low */ + mdelay(1); + return 0; +} + + +void lcdc_disp_on (void) +{ + gpio_set(SPI_CS, 0); /* low */ + gpio_set(SPI_SCLK, 1); /* high */ + gpio_set(SPI_MOSI, 0); + gpio_set(SPI_MISO, 0); + + if (1) { + toshiba_spi_write(0, 0, 0); + mdelay(7); + toshiba_spi_write(0, 0, 0); + mdelay(7); + toshiba_spi_write(0, 0, 0); + mdelay(7); + toshiba_spi_write(0xba, 0x11, 1); + toshiba_spi_write(0x36, 0x00, 1); + mdelay(1); + toshiba_spi_write(0x3a, 0x60, 1); + toshiba_spi_write(0xb1, 0x5d, 1); + mdelay(1); + toshiba_spi_write(0xb2, 0x33, 1); + toshiba_spi_write(0xb3, 0x22, 1); + mdelay(1); + toshiba_spi_write(0xb4, 0x02, 1); + toshiba_spi_write(0xb5, 0x1e, 1); /* vcs -- adjust brightness */ + mdelay(1); + toshiba_spi_write(0xb6, 0x27, 1); + toshiba_spi_write(0xb7, 0x03, 1); + mdelay(1); + toshiba_spi_write(0xb9, 0x24, 1); + toshiba_spi_write(0xbd, 0xa1, 1); + mdelay(1); + toshiba_spi_write(0xbb, 0x00, 1); + toshiba_spi_write(0xbf, 0x01, 1); + mdelay(1); + toshiba_spi_write(0xbe, 0x00, 1); + toshiba_spi_write(0xc0, 0x11, 1); + mdelay(1); + toshiba_spi_write(0xc1, 0x11, 1); + toshiba_spi_write(0xc2, 0x11, 1); + mdelay(1); + toshiba_spi_write(0xc3, 0x3232, 2); + mdelay(1); + toshiba_spi_write(0xc4, 0x3232, 2); + mdelay(1); + toshiba_spi_write(0xc5, 0x3232, 2); + mdelay(1); + toshiba_spi_write(0xc6, 0x3232, 2); + mdelay(1); + toshiba_spi_write(0xc7, 0x6445, 2); + mdelay(1); + toshiba_spi_write(0xc8, 0x44, 1); + toshiba_spi_write(0xc9, 0x52, 1); + mdelay(1); + toshiba_spi_write(0xca, 0x00, 1); + mdelay(1); + toshiba_spi_write(0xec, 0x02a4, 2); /* 0x02a4 */ + mdelay(1); + toshiba_spi_write(0xcf, 0x01, 1); + mdelay(1); + toshiba_spi_write(0xd0, 0xc003, 2); /* c003 */ + mdelay(1); + toshiba_spi_write(0xd1, 0x01, 1); + mdelay(1); + toshiba_spi_write(0xd2, 0x0028, 2); + mdelay(1); + toshiba_spi_write(0xd3, 0x0028, 2); + mdelay(1); + toshiba_spi_write(0xd4, 0x26a4, 2); + mdelay(1); + toshiba_spi_write(0xd5, 0x20, 1); + mdelay(1); + toshiba_spi_write(0xef, 0x3200, 2); + mdelay(32); + toshiba_spi_write(0xbc, 0x80, 1); /* wvga pass through */ + toshiba_spi_write(0x3b, 0x00, 1); + mdelay(1); + toshiba_spi_write(0xb0, 0x16, 1); + mdelay(1); + toshiba_spi_write(0xb8, 0xfff5, 2); + mdelay(1); + toshiba_spi_write(0x11, 0, 0); + mdelay(5); + toshiba_spi_write(0x29, 0, 0); + mdelay(5); + } +} + +void lcdc_on(void) +{ + lcdc_clock_init(27648000); + lcdc_toshiba_panel_power(1); + lcdc_disp_on(); +} + +#endif diff --git a/target/msm7630_surf/rules.mk b/target/msm7630_surf/rules.mk index a5647aad7..2b0942eef 100644 --- a/target/msm7630_surf/rules.mk +++ b/target/msm7630_surf/rules.mk @@ -1,6 +1,6 @@ LOCAL_DIR := $(GET_LOCAL_DIR) -INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared +INCLUDES += -I$(LOCAL_DIR)/include -I$(LK_TOP_DIR)/platform/msm_shared -I$(LK_TOP_DIR)/platform/msm7x30 PLATFORM := msm7x30 @@ -17,7 +17,9 @@ FASTBOOT_BUF_SIZE := 0x07800000 KEYS_USE_GPIO_KEYPAD := 1 -DEFINES += DISPLAY_TYPE_MDDI=1 +DEFINES += DISPLAY_TYPE_MDDI=0 +DEFINES += DISPLAY_SPLASH_SCREEN=0 +DEFINES += DISPLAY_TYPE_LCDC=0 MODULES += \ dev/keys \ @@ -37,4 +39,5 @@ DEFINES += \ OBJS += \ $(LOCAL_DIR)/init.o \ $(LOCAL_DIR)/atags.o \ - $(LOCAL_DIR)/keypad.o + $(LOCAL_DIR)/keypad.o \ + $(LOCAL_DIR)/panel.o