@@ -216,6 +216,10 @@ Use the following settings to configure the extension to your needs.
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\[ Experimental\] A path to the svls Language Server binary.
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+ - ` verilog.languageServer.svls.arguments' ` (Default: '')
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+
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+ \[ Experimental\] Add custom arguments for the Svls Language Server.
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+
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- ` verilog.languageServer.veridian.enabled ` (Default: ` false ` )
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\[ Experimental\] Enable veridian Language Server for SystemVerilog.
@@ -224,6 +228,10 @@ Use the following settings to configure the extension to your needs.
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\[ Experimental\] A path to the veridian Language Server binary.
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+ - ` verilog.languageServer.veridian.arguments' ` (Default: '')
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+
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+ \[ Experimental\] Add custom arguments for the Veridian Language Server.
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+
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- ` verilog.languageServer.hdlChecker.enabled ` (Default: ` false ` )
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\[ Experimental\] Enable HDL Checker Language Server for Verilog-HDL, SystemVerilog, and VHDL.
@@ -232,6 +240,10 @@ Use the following settings to configure the extension to your needs.
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\[ Experimental\] A path to the HDL Checker Language Server binary.
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+ - ` verilog.languageServer.hdlChecker.arguments' ` (Default: '')
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+
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+ \[ Experimental\] Add custom arguments for the HDL Checker Language Server.
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+
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- ` verilog.languageServer.veribleVerilogLs.enabled ` (Default: ` false ` )
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\[ Experimental\] Enable verible-verilog-ls Language Server for SystemVerilog.
@@ -240,6 +252,10 @@ Use the following settings to configure the extension to your needs.
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\[ Experimental\] A path to the verible-verilog-ls Language Server binary.
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+ - ` verilog.languageServer.veribleVerilogLs.arguments' ` (Default: '')
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+
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+ \[ Experimental\] Add custom arguments for the verible-verilog-ls Language Server.
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+
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- ` verilog.languageServer.rustHdl.enabled ` (Default: ` false ` )
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\[ Experimental\] Enable rust_hdl Language Server for VHDL.
@@ -248,6 +264,10 @@ Use the following settings to configure the extension to your needs.
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\[ Experimental\] A path to the rust_hdl Language Server binary.
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+ - ` verilog.languageServer.rustHdl.arguments' ` (Default: '')
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+ \[ Experimental\] Add custom arguments for the rust_hdl Language Server.
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+
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- ` verilog.formatting.verilogHDL.formatter ` (Default: ` verilog-format ` )
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\[ Experimental\] Choose the Verilog-HDL formatter. Possible values are:
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