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<!DOCTYPE html PUBLIC "-//w3c//dtd html 4.0 transitional//en">
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<title>Pentium and Pentium Pro Architectures</title>
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<body link="#0000FF">
<h1>
A Guide to Programming Intel IA32 PC Architecture</h1>
<font size="4">Kai Li, Princeton University<br>
First draft, 1999<br>
Revised 2003</font><p><a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#IA32">1 Intel IA32 Processors</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#modes">1.1 Modes</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#register">1.2 Register Set</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#addressing">1.3 Addressing</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#reset">1.4 Processor Reset</a></p>
<p><a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#assembly">2 Assembly Programming</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#syntax">2.1 Instruction Syntax</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#memory">2.2 Memory Operands</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#instructions">2.3 Frequently Used Instructions</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#directives">2.4 Assembler Directives</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#inline">2.5 Inline Assembly</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#program">2.6 Program Structure and Calling Convention</a></p>
<p><a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#BIOS">3 BIOS Services</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#display memory">3.1 Display Memory</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#write to display">3.2 Write to Display at Current
Cursor</a><br>
<a href="http://flint.cs.yale.edu/cs422/doc/pc-arch.html#read diskette">3.3 Read from Diskette</a></p>
<p><font size="+0" face="Times New Roman">The goal of this documentation is to
provide a brief description of the Intel IA32 PC architecture, a brief introduction to assembly programming using the Gnu
assembler, and a small set of BIOS services that can be used in the course
projects.</font>
</p><h4><font face="Times New Roman">References:</font></h4>
<ul>
<li><i>IA32 Intel Architecture Software Developer's Manual, Volume 2:
Instruction Set Reference Manual</i>, Intel Corporation, 2003</li>
<li><i>IA32 Intel Architecture Software Developer's Manual, Volume 3:
Operating System Writer's Manual</i>, Intel Corporation, 2003.</li>
<li><a href="http://www.gnu.org/manual/gas-2.9.1/html_mono/as.html">
http://www.gnu.org/manual/gas-2.9.1/html_mono/as.html</a></li>
<li><i>The Undocumented PC: A Programmer's Guide to I/O, CPUs, and Fixed
Memory Areas, 2nd Edition</i>, Frank van Gilluwe, Addison-Wesley Developers
Press, 1997.</li>
</ul>
<h2>
<b><font face="Arial"><a name="IA32"></a>1 Intel </font></b>IA32
<b><font face="Arial">Processor</font></b></h2>
<p>
Intel uses IA32 to refer to Pentium processor family, in order to distinguish
them from their 64-bit architectures.</p>
<h2>
<b><font size="+1"><a name="modes"></a>1.1 Modes</font></b></h2>
<font size="+0">The 1A32 processor has three operating modes:</font>
<ul>
<li>
<font size="+0"><b>Real-address mo</b>d<b>e.</b> This mode lets the processor to
address "real" memory address. It can address up to 1Mbytes of memory (20-bit of
address). It can also be called "unprotected" mode since operating system (such
as DOS) code runs in the same mode as the user applications. 1A32 processors have this mode to be compatible with
early Intel processors such as 8086. The processor is set to this mode
following by a power-up or a reset and can be switched to protected mode
using a single instruction.</font></li>
<li>
<font size="+0"><b>Protected mode.</b> This is the preferred mode for a modern
operating system. It allows applications to use virtual memory addressing
and supports multiple programming environment and protections.</font></li>
<li>
<b>System<font size="+0"> management mode</font>. </b>This mode is designed for
fast state snapshot and resumption. It is useful for power management</li>
</ul>
There is also a virtual-8086 mode that allows the processor to execute
8086 code software in the protected, multi-tasking environment.
<h2>
<b><font size="+1"><a name="register"></a>1.2 Register Set</font></b></h2>
<font size="+0">There are three types of registers: general-purpose data
registers, segment registers, and status and control registers. The following
figure shows these registers:</font>
<p><img src="./Pentium and Pentium Pro Architectures_files/Image7.gif" height="382" width="607">
</p><h4>
<b><font face="Arial"><font size="+0">General-purpose Registers</font></font></b></h4>
<font size="+0">The eight <font face="Times-Roman">32-bit general-purpose
data registers are used to hold operands for logical and arithmetic operations,
operands for address calculations and memory pointers. The following shows
what they are used for:</font></font>
<ul>
<li>
<font size="+0">EAX—Accumulator for operands and results data.</font></li>
<li>
<font size="+0">EBX—Pointer to data in the DS segment.</font></li>
<li>
<font size="+0">ECX—Counter for string and loop operations.</font></li>
<li>
<font size="+0">EDX—I/O pointer.</font></li>
<li>
<font size="+0">ESI—Pointer to data in the segment pointed to by the DS register;
source pointer for string operations.</font></li>
<li>
<font size="+0">EDI—Pointer to data (or destination) in the segment pointed
to by the ES register; destination pointer for string operations.</font></li>
<li>
<font size="+0">EBP—Pointer to data on the stack (in the SS segment).</font></li>
<li>
<font size="+0">ESP—Stack pointer (in the SS segment).</font></li>
</ul>
<font size="+0">The following figure shows the lower 16 bits of the general-purpose
registers can be used with the names AX, BX, CX, DX, BP, SP, SI, and DI
(the names for the corresponding 32-bit ones have a prefix "E" for "extended").
Each of the lower two bytes of the EAX, EBX, ECX, and EDX registers can
be referenced by the names AH, BH, CH, and DH (high bytes) and AL, BL,
CL, and DL (low bytes).</font>
<p><img src="./Pentium and Pentium Pro Architectures_files/Image8.gif" border="0" height="307" width="523">
</p><h4>
<b><font face="Arial"><font size="+0">Segment Registers</font></font></b></h4>
<font face="Times-Roman"><font size="+0">There are six segment registers
that hold 16-bit segment selectors. A segment selector is a special pointer
that identifies a segment in memory. The six segment registers are:</font></font>
<ul>
<li>
<font face="Times-Roman"><font size="+0">CS: code segment register</font></font></li>
<li>
<font face="Times-Roman"><font size="+0">SS: stack segment register</font></font></li>
<li>
<font face="Times-Roman"><font size="+0">DS, ES, FS, GS: data segment registers</font></font></li>
</ul>
<font face="Times-Roman"><font size="+0">Four data segment registers provide
programs with flexible and efficient ways to access data.</font></font>
<p><font size="+0"><font face="Times-Roman">Modern operating system and applications
use the (unsegmented) memory model</font><font face="Symbol">¾</font><font face="Times-Roman">
all the segment registers are loaded with the same segment selector so
that all memory references a program makes are to a single linear-address
space.</font></font>
</p><p>When writing application code, you generally create segment selectors
with assembler directives and symbols. The assembler and/or linker then
creates the actual segment selectors associated with these directives and
symbols. If you are writing system code, you may need to create segment
selectors directly. (A detailed description of the segment-selector data
structure is given in Chapter 3, Protected-Mode Memory Management, of the
<i>IA32 Intel Architecture Software Developer's Manual, Volume 3</i>).
</p><p>Project 1, 2, 3, and 4 all use <font face="Times-Roman"><font size="+0">the real-address
mode and needs to set up the segment registers properly.</font></font> Project 5
and 6 will use unsegmented memory model.</p><h4>
<b><font face="Arial"><font size="+0">EFLAGS Register</font></font></b></h4>
<font face="Times-Roman"><font size="+0">The 32-bit EFLAGS register contains
a group of status flags, a control flag, and a group of system flags. The
following shows the function of EFLAGS register bits:</font></font>
<br>
<center><table border="" cellpadding="4" width="550" height="600">
<tbody><tr>
<td valign="TOP" width="48%">
<center><b><font size="-1">Function</font></b></center>
</td>
<td valign="TOP" width="48%">
<center><b><font size="-1">EFLAG Register bit or bits</font></b></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">ID Flag (ID)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">21 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Virtual Interrupt Pending (VIP)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">20 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Virtual Interrupt Flag (VIF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">19 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Alignment check (AC)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">18 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Virtual 8086 Mode (VM)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">17 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Resume Flag (RF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">16 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Nested Task (NT)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">14 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">I/O Privilege Level (IOPL)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">13 to 12 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Overflow Flag (OF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">11 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Direction Flag (DF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">10 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Interrupt Enable Flag (IF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">9 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Trap Flag (TF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">8 (system)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Sign Flag (SF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">7 (status)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Zero Flag (ZF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">6 (status)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Auxiliary Carry Flag (AF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">4 (status)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Parity Flag (PF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">2 (status)</font></center>
</td>
</tr>
<tr>
<td valign="TOP" width="52%">
<center><font size="-1">Carry Flag (CF)</font></center>
</td>
<td valign="TOP" width="48%">
<center><font size="-1">0 (status)</font></center>
</td>
</tr>
</tbody></table></center>
<p><font size="+0">Bits 1, 3, 5, 15, and 22 through 31 of this register are
reserved. To understand what these fields mean and how to use them,
please see Section 3.6.3 and 3.6.4 in </font> <i>IA32 Intel Architecture
Software Developer's Manual, Volume 1.</i></p><h4>
<b><font face="Arial"><font size="+0">EIP Register (Instruction Pointer)</font></font></b></h4>
<font size="+0">The EIP register (or instruction pointer) can also be called
"program counter." It <font face="Times-Roman">contains the offset in the
current code segment for the next instruction to be executed. It is advanced
from one instruction boundary to the next in straight-line code or it is
moved ahead or backwards by a number of instructions when executing JMP,
Jcc, CALL, RET, and IRET instructions. The EIP cannot be accessed directly
by software; it is controlled implicitly by control-transfer instructions
(such as JMP, J</font><i><font face="Times-Italic">cc</font></i><font face="Times-Roman">,
CALL, and RET), inter-rupts, and exceptions. The EIP register can be loaded
indirectly by modifying the value of a return instruction pointer on the
procedure stack and executing a return instruction (RET or IRET).</font></font>
<p><font size="+0">Note that the value of the EIP may not match with the
current instruction because of instruction prefetching. The only way to
read the EIP is to execute a CALL instruction and then read the value of
the return instruction pointer from the procedure stack.</font>
</p><p><font size="+0">The IA32 processors also have control registers, which can be
found in the Intel/manuals.</font></p><h2>
<b><font size="+1"><a name="addressing"></a>1.3 Addressing</font></b></h2>
<h4>
<b><font face="Arial,Helvetica">Bit and Byte Order</font></b></h4>
<font size="+0">IA32 processors use "little endian" as
their byte order. This means that the bytes of a word are numbered starting
from the least significant byte and that the least significant bit starts
of a word starts in the least significant byte.</font>
<h4>
<b><font size="+0" face="Arial">Data Types</font></b></h4>
<font size="0">IA32</font><font size="+0"> provides four data types: a byte (8
bits), a word (16 bits), a double-word (32 bits), and a quad-word (64 bits).
Note that a word is "word" in Gnu assembler and a double-word is equivalent to "long" in Gnu assembler.</font>
<h4>
<b><font face="Arial"><font size="+0">Memory Addressing</font></font></b></h4>
One can use either flat memory model or segmented memory mode. With
the flat memory model, memory appears to a program as a single, continuous
address space, called a linear address space. Code (a program’s instructions), data, and the procedure stack are all contained in this address space.
The linear address space is byte addressable, with addresses running contiguously
from 0 to 2<sup><font size="-1"> 32 - 1</font></sup>.
<p>With the segmented memory mode, memory appears to a program as a group of
independent address spaces called segments. When using this model, code, data,
and stacks are typically contained in separate segments. To address a byte in a
segment, a program must issue a logical address, which consists of a segment
selector and an offset. (A logical address is often referred to as a far
pointer.) The segment selector identifies the segment to be accessed and the
offset identifies a byte in the address space of the segment. The programs
running on an IA32 processor can address up to 16,383 segments of different sizes and
types. Internally, all the segments that are defined for a system are mapped
into the processor’s linear address space. So, the processor translates
each logical address into a linear address to access a memory location.
This translation is transparent to the application program.
</p><h2>
<font face="Arial" size="4"><a name="reset"></a>1.4 Processor Reset</font></h2>
<font size="+0">A cold boot or a warm boot can reset the CPU. A cold
boot is powering up a system whereas a warm boot means that when three
keys CTRL-ALT-DEL are all pressed together, the keyboard BIOS will set
a special flag and resets the CPU.</font>
<p><font size="+0">Upon reset, the processor sets itself to real-mode with
interrupts disabled and key registers set to a known state. For example,
the state of the EFLAGS register is 00000002H and the memory is unchanged.
Thus, the memory will contain garbage upon a cold boot. The CPU will
jump to the BIOS (Basic Input Output Services) to load the bootstrap loader
program from the diskette drive or the hard disk and begins execution of
the loader. The BIOS loads the bootstrap loader into the fixed address
0:7C00 and jumps to the starting address.</font>
</p><h2>
<b><font face="Arial"><a name="assembly"></a>2 Assembly Programming</font></b></h2>
<font size="+0">It often takes a while to master the techniques to program
in assembly language for a particular machine. On the other hand, it should
not take much time to assembly programming on IA32 processors
if you are familiar with assembly programming for another processor.</font> <font size="+0">This section assumes that you are already familiar with
Gnu assembly syntax (learned from the course <i>Introduction to Programming
Systems </i>or its equivalent). </font>
<h3>
<font face="Times-Roman"><a name="syntax"></a>2.1 Instruction Syntax</font></h3>
<font size="+0">There are two conventions about their syntax and representations:
Intel and AT&T. Most documents
use the Intel convention, whereas the Gnu assembler uses the AT&T convention.
The main differences are:</font>
<br>
<table border="" cellpadding="5" width="811" height="400">
<tbody><tr>
<td valign="TOP" width="246" height="10"> </td>
<td valign="TOP" width="256">
<center><b>Gnu Syntax (AT&T)</b></center>
</td>
<td valign="TOP" width="263">
<center>
<p><b>Intel</b></p>
</center>
</td>
</tr>
<tr>
<td valign="TOP" width="246">Immediate operands</td>
<td valign="TOP" width="256">Preceded by "$"
<br>e.g.<font face="Courier New,Courier">:push $4</font>
<br><font face="Courier New,Courier"> movl $0xd00a, %eax</font></td>
<td valign="TOP" width="263">Undelimited
<br>e.g.: <font face="Courier New,Courier">push 4</font>
<br><font face="Courier New,Courier"> mov ebx, d00ah</font></td>
</tr>
<tr>
<td valign="TOP" width="246">Register operands</td>
<td valign="TOP" width="256">Preceded by "<font face="Arial">%</font>"
<br>e.g.: <font face="Courier New,Courier">%eax</font></td>
<td valign="TOP" width="263">Undelimited
<br>e.g.: <font face="Courier New,Courier">eax</font></td>
</tr>
<tr>
<td valign="TOP" width="246">Argument order (e.g. adds the address of C variable
"foo" to register EAX)</td>
<td valign="TOP" width="256">source1, [source2,] dest
<br>e.g.: <font face="Courier New,Courier">addl $_foo, %eax</font></td>
<td valign="TOP" width="263">dest, source1 [, source2]
<br>e.g.: <font face="Courier New,Courier">add eax, _foo</font></td>
</tr>
<tr>
<td valign="TOP" width="246" height="68">Single-size operands</td>
<td valign="TOP" width="256" height="68">Explicit with operand sizes<br>
opcode{b,w,l}
<br>e.g.:<font face="Courier New,Courier"> movb foo, %al</font></td>
<td valign="TOP" width="263" height="68">Implicit with register name, <b>byte
ptr</b>, <b>word ptr</b>, or <b>dword ptr</b>
<br>e.g.: <font face="Courier New,Courier">mov al, foo</font></td>
</tr>
<tr>
<td width="246">Address a C variable "foo"</td>
<td width="256"><font face="Courier New,Courier">_foo</font></td>
<td width="263"><font face="Courier New,Courier">[_foo]</font></td>
</tr>
<tr>
<td width="246">Address memory pointed by a register (e.g. EAX)</td>
<td width="256"><font face="Courier New,Courier">(%eax)</font></td>