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i386: Introduce V2QImode vector compares [PR103861]
Add V2QImode vector compares with SSE registers. 2022-01-10 Uroš Bizjak <[email protected]> gcc/ChangeLog: PR target/103861 * config/i386/i386-expand.c (ix86_expand_int_sse_cmp): Handle V2QImode. * config/i386/mmx.md (<sat_plusminus:insn><mode>3): Use VI1_16_32 mode iterator. (*eq<mode>3): Ditto. (*gt<mode>3): Ditto. (*xop_maskcmp<mode>3): Ditto. (*xop_maskcmp_uns<mode>3): Ditto. (vec_cmp<mode><mode>): Ditto. (vec_cmpu<mode><mode>): Ditto. gcc/testsuite/ChangeLog: PR target/103861 * gcc.target/i386/pr103861-2.c: New test.
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‎gcc/config/i386/i386-expand.c

+7
Original file line numberDiff line numberDiff line change
@@ -4444,6 +4444,12 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
44444444
else if (code == GT && TARGET_SSE4_1)
44454445
gen = gen_sminv4qi3;
44464446
break;
4447+
case E_V2QImode:
4448+
if (code == GTU && TARGET_SSE2)
4449+
gen = gen_uminv2qi3;
4450+
else if (code == GT && TARGET_SSE4_1)
4451+
gen = gen_sminv2qi3;
4452+
break;
44474453
case E_V8HImode:
44484454
if (code == GTU && TARGET_SSE4_1)
44494455
gen = gen_uminv8hi3;
@@ -4537,6 +4543,7 @@ ix86_expand_int_sse_cmp (rtx dest, enum rtx_code code, rtx cop0, rtx cop1,
45374543
case E_V16QImode:
45384544
case E_V8QImode:
45394545
case E_V4QImode:
4546+
case E_V2QImode:
45404547
case E_V8HImode:
45414548
case E_V4HImode:
45424549
case E_V2HImode:

‎gcc/config/i386/mmx.md

+28-28
Original file line numberDiff line numberDiff line change
@@ -1824,10 +1824,10 @@
18241824
(set_attr "mode" "DI,TI,TI")])
18251825

18261826
(define_insn "*<insn><mode>3"
1827-
[(set (match_operand:VI_32 0 "register_operand" "=x,Yw")
1828-
(sat_plusminus:VI_32
1829-
(match_operand:VI_32 1 "register_operand" "<comm>0,Yw")
1830-
(match_operand:VI_32 2 "register_operand" "x,Yw")))]
1827+
[(set (match_operand:VI_16_32 0 "register_operand" "=x,Yw")
1828+
(sat_plusminus:VI_16_32
1829+
(match_operand:VI_16_32 1 "register_operand" "<comm>0,Yw")
1830+
(match_operand:VI_16_32 2 "register_operand" "x,Yw")))]
18311831
"TARGET_SSE2"
18321832
"@
18331833
p<plusminus_mnemonic><mmxvecsize>\t{%2, %0|%0, %2}
@@ -2418,10 +2418,10 @@
24182418
(set_attr "mode" "DI,TI,TI")])
24192419

24202420
(define_insn "*eq<mode>3"
2421-
[(set (match_operand:VI_32 0 "register_operand" "=x,x")
2422-
(eq:VI_32
2423-
(match_operand:VI_32 1 "register_operand" "%0,x")
2424-
(match_operand:VI_32 2 "register_operand" "x,x")))]
2421+
[(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
2422+
(eq:VI_16_32
2423+
(match_operand:VI_16_32 1 "register_operand" "%0,x")
2424+
(match_operand:VI_16_32 2 "register_operand" "x,x")))]
24252425
"TARGET_SSE2"
24262426
"@
24272427
pcmpeq<mmxvecsize>\t{%2, %0|%0, %2}
@@ -2446,10 +2446,10 @@
24462446
(set_attr "mode" "DI,TI,TI")])
24472447

24482448
(define_insn "*gt<mode>3"
2449-
[(set (match_operand:VI_32 0 "register_operand" "=x,x")
2450-
(gt:VI_32
2451-
(match_operand:VI_32 1 "register_operand" "0,x")
2452-
(match_operand:VI_32 2 "register_operand" "x,x")))]
2449+
[(set (match_operand:VI_16_32 0 "register_operand" "=x,x")
2450+
(gt:VI_16_32
2451+
(match_operand:VI_16_32 1 "register_operand" "0,x")
2452+
(match_operand:VI_16_32 2 "register_operand" "x,x")))]
24532453
"TARGET_SSE2"
24542454
"@
24552455
pcmpgt<mmxvecsize>\t{%2, %0|%0, %2}
@@ -2473,10 +2473,10 @@
24732473
(set_attr "mode" "TI")])
24742474

24752475
(define_insn "*xop_maskcmp<mode>3"
2476-
[(set (match_operand:VI_32 0 "register_operand" "=x")
2477-
(match_operator:VI_32 1 "ix86_comparison_int_operator"
2478-
[(match_operand:VI_32 2 "register_operand" "x")
2479-
(match_operand:VI_32 3 "register_operand" "x")]))]
2476+
[(set (match_operand:VI_16_32 0 "register_operand" "=x")
2477+
(match_operator:VI_16_32 1 "ix86_comparison_int_operator"
2478+
[(match_operand:VI_16_32 2 "register_operand" "x")
2479+
(match_operand:VI_16_32 3 "register_operand" "x")]))]
24802480
"TARGET_XOP"
24812481
"vpcom%Y1<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
24822482
[(set_attr "type" "sse4arg")
@@ -2501,10 +2501,10 @@
25012501
(set_attr "mode" "TI")])
25022502

25032503
(define_insn "*xop_maskcmp_uns<mode>3"
2504-
[(set (match_operand:VI_32 0 "register_operand" "=x")
2505-
(match_operator:VI_32 1 "ix86_comparison_uns_operator"
2506-
[(match_operand:VI_32 2 "register_operand" "x")
2507-
(match_operand:VI_32 3 "register_operand" "x")]))]
2504+
[(set (match_operand:VI_16_32 0 "register_operand" "=x")
2505+
(match_operator:VI_16_32 1 "ix86_comparison_uns_operator"
2506+
[(match_operand:VI_16_32 2 "register_operand" "x")
2507+
(match_operand:VI_16_32 3 "register_operand" "x")]))]
25082508
"TARGET_XOP"
25092509
"vpcom%Y1u<mmxvecsize>\t{%3, %2, %0|%0, %2, %3}"
25102510
[(set_attr "type" "ssecmp")
@@ -2527,10 +2527,10 @@
25272527
})
25282528

25292529
(define_expand "vec_cmp<mode><mode>"
2530-
[(set (match_operand:VI_32 0 "register_operand")
2531-
(match_operator:VI_32 1 ""
2532-
[(match_operand:VI_32 2 "register_operand")
2533-
(match_operand:VI_32 3 "register_operand")]))]
2530+
[(set (match_operand:VI_16_32 0 "register_operand")
2531+
(match_operator:VI_16_32 1 ""
2532+
[(match_operand:VI_16_32 2 "register_operand")
2533+
(match_operand:VI_16_32 3 "register_operand")]))]
25342534
"TARGET_SSE2"
25352535
{
25362536
bool ok = ix86_expand_int_vec_cmp (operands);
@@ -2551,10 +2551,10 @@
25512551
})
25522552

25532553
(define_expand "vec_cmpu<mode><mode>"
2554-
[(set (match_operand:VI_32 0 "register_operand")
2555-
(match_operator:VI_32 1 ""
2556-
[(match_operand:VI_32 2 "register_operand")
2557-
(match_operand:VI_32 3 "register_operand")]))]
2554+
[(set (match_operand:VI_16_32 0 "register_operand")
2555+
(match_operator:VI_16_32 1 ""
2556+
[(match_operand:VI_16_32 2 "register_operand")
2557+
(match_operand:VI_16_32 3 "register_operand")]))]
25582558
"TARGET_SSE2"
25592559
{
25602560
bool ok = ix86_expand_int_vec_cmp (operands);

‎gcc/testsuite/gcc.target/i386/pr103861-2.c

+21
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/* PR target/103861 */
2+
/* { dg-do compile } */
3+
/* { dg-options "-O2 -msse2" } */
4+
5+
typedef char vec __attribute__((vector_size(2)));
6+
7+
vec lt (vec a, vec b) { return a < b; }
8+
vec le (vec a, vec b) { return a <= b; }
9+
vec eq (vec a, vec b) { return a == b; }
10+
vec ne (vec a, vec b) { return a != b; }
11+
vec ge (vec a, vec b) { return a >= b; }
12+
vec gt (vec a, vec b) { return a > b; }
13+
14+
typedef unsigned char uvec __attribute__((vector_size(2)));
15+
16+
vec ltu (uvec a, uvec b) { return a < b; }
17+
vec leu (uvec a, uvec b) { return a <= b; }
18+
vec geu (uvec a, uvec b) { return a >= b; }
19+
vec gtu (uvec a, uvec b) { return a > b; }
20+
21+
/* { dg-final { scan-assembler-not "cmpb" } } */

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