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1 |
| -##### Some_acpphint_curves_with_notes.md |
| 1 | +##### Some\_acpphint\_curves\_with\_notes.md |
2 | 2 | This covers:
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3 | 3 |
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4 | 4 | 0. Cortex-A57 cores with and without smaller cache level(s) being shared
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@@ -36,7 +36,7 @@ Effects of competing for the shared RAM cache level(s) can be seen:
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36 | 36 | (left side of goldenrod vs. blue curves)
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37 | 37 | 1. Computing is somewhat slower.
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38 | 38 | (right side of goldenrod vs. blue curves)
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39 |
| -2. The curve structures show a RAM cache changes at around n*256 KiByte, for n |
| 39 | +2. The curve structures show a RAM cache changes at around n\*256 KiByte, for n |
40 | 40 | being the number of hardware threads in use.
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41 | 41 | 3. The curve structures show a RAM cache change at about 8 MiByte.
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42 | 42 | 4. The 1-hardware-thread curves show a RAM cache change at about 32 KiByte.
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@@ -116,7 +116,7 @@ Notes:
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116 | 116 | 0. The x and y ranges for all the plots for 1950X CCD/CCX 2/4 thread
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117 | 117 | combinations are the same, making comparison/contrast easier.
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118 | 118 | 1. The curves for allowing (hardware) thread migration without SMT involvement
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119 |
| - show very clear evidence of around n*512 KiByte and 16 MiByte RAM cache |
| 119 | + show very clear evidence of around n\*512 KiByte and 16 MiByte RAM cache |
120 | 120 | changes, n being the number of (hardware) threads.
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121 | 121 | 2. The shared smaller cache level(s) for SMT usage have competing usage and make
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122 | 122 | them show messier transitions.
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@@ -154,7 +154,7 @@ Notes:
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154 | 154 | 0. The x and y ranges for all the plots for 1950X CCD/CCX 2/4 thread
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155 | 155 | combinations are the same, making comparison/contrast easier.
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156 | 156 | 1. The curves for allowing (hardware) thread migration without SMT involvement
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157 |
| - show very clear evidence of around n*512 KiByte, 16 MiByte, and 32 MiByte RAM |
| 157 | + show very clear evidence of around n\*512 KiByte, 16 MiByte, and 32 MiByte RAM |
158 | 158 | cache changes, n being the number of (hardware) threads, except for the 2CCD 4CCX case that has more cache per (hardware) thread.
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159 | 159 | 2. The shared smaller cache level(s) for SMT usage have competing usage and make
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160 | 160 | them show messier transitions.
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