-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy paths25_mem_filters.sv
643 lines (590 loc) · 17.4 KB
/
s25_mem_filters.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
// vi:set ft=verilog ts=4 sw=4 expandtab ai si:
// [email protected] 20180809
`default_nettype none
`include "./s00_defines.sv"
// module MemFilter1
// import BwaMemDefines::*;
// (
// input wire clk, rst,
// input wire start,
// input wire stop,
// output logic finish,
// output logic busy,
// Axi4StreamIf.slave s_axis_emin,
// Axi4StreamIf.master m_axis_emout
// );
// logic [2:0] state, nxt_state;
// localparam logic [2:0] S_Idle = 3'd0;
// localparam logic [2:0] S_Wait = 3'd1;
// localparam logic [2:0] S_Judge = 3'd2;
// localparam logic [2:0] S_Output = 3'd3;
// localparam logic [2:0] S_Flush = 3'd4;
// WorkingMem m[4];
// wire in_handsk = s_axis_emin.tready & s_axis_emin.tvalid;
// wire out_handsk = m_axis_emout.tready & m_axis_emout.tvalid;
// always_ff @(posedge clk) begin : proc_m
// if(rst) begin
// m[0] <= '0;
// m[1] <= '0;
// m[2] <= '0;
// m[3] <= '0;
// end
// else if(in_handsk) begin
// m[0] <= s_axis_emin.tdata;
// m[1] <= m[0];
// m[2] <= m[1];
// m[3] <= m[2];
// end
// else if(state == S_Output && nxt_state == S_Wait) begin
// m[1] <= '0;
// m[2] <= '0;
// m[3] <= '0;
// end
// end
// wire ij_diff = m[0].i != m[1].i && m[0].j != m[1].j;
// logic stop_r;
// always_ff @(posedge clk) begin : proc_stop_r
// if(rst) begin
// stop_r <= '0;
// end
// else if(stop) begin
// stop_r <= 1'b1;
// end
// else if(state == S_Flush) begin
// stop_r <= 1'b0;
// end
// end
// logic [1:0] cnt;
// always_ff @(posedge clk) begin : proc_cnt
// if(rst) begin
// cnt <= '0;
// end
// else if(state == S_Judge && nxt_state == S_Output) begin
// cnt <= 1'b0;
// end
// else if(state == S_Wait && nxt_state == S_Flush) begin
// cnt <= 1'b1;
// end
// else if(state == S_Output || state == S_Flush) begin
// if(out_handsk) begin
// cnt <= cnt + 1'b1;
// end
// end
// end
// always_ff @(posedge clk) begin : proc_state
// if(rst) begin
// state <= S_Idle;
// end else begin
// state <= nxt_state;
// end
// end
// always_comb begin
// nxt_state = state;
// case (state)
// S_Idle: begin
// if(start) begin
// nxt_state = S_Wait;
// end
// end // S_Idle:
// S_Wait: begin
// if(in_handsk) begin
// nxt_state = S_Judge;
// end
// else if(stop_r) begin
// nxt_state = S_Flush;
// end
// end // S_Wait:
// S_Judge: begin
// if(ij_diff) begin
// nxt_state = S_Output;
// end // if(ij_diff)
// else begin
// nxt_state = S_Wait;
// end
// end // S_Judge:
// S_Output: begin
// if(cnt == 2'd2 & out_handsk) begin
// nxt_state = S_Wait;
// end
// end
// S_Flush: begin
// if(cnt == 2'd3 & out_handsk) begin
// nxt_state = S_Idle;
// end
// end
// default: begin
// nxt_state = state;
// end
// endcase
// end
// always_ff @(posedge clk) begin : proc_finish
// if(rst) begin
// finish <= 1'b0;
// end
// else if(state == S_Flush && nxt_state == S_Idle) begin
// finish <= 1'b1;
// end
// else begin
// finish <= 1'b0;
// end
// end
// assign busy = state != S_Idle;
// wire WorkingMem emout = m[2'd3 - cnt];
// always_comb s_axis_emin.tready = state == S_Wait;
// always_comb m_axis_emout.tdata = emout;
// always_comb m_axis_emout.tvalid = state == S_Output || state == S_Flush;
// endmodule // MemFilter1
module MemFilter1
import BwaMemDefines::*;
#(
parameter GRP_SIZE = 3
)(
input wire clk, rst,
input wire start,
input wire stop,
output logic finish,
output logic busy,
Axi4StreamIf.slave s_axis_emin,
Axi4StreamIf.master m_axis_emout
);
localparam ROW = GRP_SIZE + 1;
logic [2:0] state, nxt_state;
localparam logic [2:0] S_Idle = 3'd0;
localparam logic [2:0] S_Wait = 3'd1;
localparam logic [2:0] S_Judge = 3'd2;
localparam logic [2:0] S_Output = 3'd3;
localparam logic [2:0] S_Clear = 3'd4;
localparam logic [2:0] S_Flush = 3'd5;
(* ram_style = "registers" *) WorkingMem m[ROW];
wire in_handsk = s_axis_emin.tready & s_axis_emin.tvalid;
wire out_handsk = m_axis_emout.tready & m_axis_emout.tvalid;
genvar r;
always_ff @(posedge clk) begin : proc_m
if(rst) begin
m[0] <= '0;
end
else if(state == S_Idle && start) begin
m[0] <= '0;
end
else if(in_handsk) begin
m[0] <= s_axis_emin.tdata;
end
end
generate
for(r = 1; r < ROW; r++ ) begin
always_ff @(posedge clk) begin : proc_m
if(rst) begin
m[r] <= '0;
end
else if(state == S_Idle && start) begin
m[r] <= '0;
end
else if(in_handsk) begin
m[r] <= m[r - 1];
end
else if(state == S_Clear) begin
m[r] <= '0;
end
end
end
endgenerate
wire ij_diff = m[0].i != m[1].i && m[0].j != m[1].j;
logic stop_r;
always_ff @(posedge clk) begin : proc_stop_r
if(rst) begin
stop_r <= '0;
end
else if(stop) begin
stop_r <= 1'b1;
end
else if(state == S_Flush) begin
stop_r <= 1'b0;
end
end
localparam CW = $clog2(ROW);
logic [CW - 1 : 0] cnt;
always_ff @(posedge clk) begin : proc_cnt
if(rst) begin
cnt <= '0;
end
else if(state == S_Judge && ij_diff) begin
cnt <= CW'(ROW - 1);
end
else if(state == S_Wait && stop_r) begin
cnt <= CW'(ROW - 2);
end
else if(state == S_Output || state == S_Flush) begin
if(out_handsk) begin
if(cnt > 1'b0) begin
cnt <= cnt - 1'b1;
end
end
end
end
always_ff @(posedge clk) begin : proc_state
if(rst) begin
state <= S_Idle;
end else begin
state <= nxt_state;
end
end
always_comb begin
nxt_state = state;
case (state)
S_Idle: begin
if(start) begin
nxt_state = S_Wait;
end
end // S_Idle:
S_Wait: begin
if(in_handsk) begin
nxt_state = S_Judge;
end
else if(stop_r) begin
nxt_state = S_Flush;
end
end // S_Wait:
S_Judge: begin
if(ij_diff) begin
nxt_state = S_Output;
end // if(ij_diff)
else begin
nxt_state = S_Wait;
end
end // S_Judge:
S_Output: begin
if(cnt == 1'd1 & out_handsk) begin
nxt_state = S_Clear;
end
end
S_Clear: begin
nxt_state = S_Wait;
end
S_Flush: begin
if(cnt == 1'd0 & out_handsk) begin
nxt_state = S_Idle;
end
end
default: begin
nxt_state = state;
end
endcase
end
always_ff @(posedge clk) begin : proc_finish
if(rst) begin
finish <= 1'b0;
end
else if(state == S_Flush && (cnt == 1'd0 & out_handsk)) begin
finish <= 1'b1;
end
else begin
finish <= 1'b0;
end
end
assign busy = state != S_Idle;
wire WorkingMem emout = m[cnt];
always_comb s_axis_emin.tready = state == S_Wait;
always_comb m_axis_emout.tdata = emout;
always_comb m_axis_emout.tvalid = state == S_Output || state == S_Flush;
always_comb m_axis_emout.tstrb = '1;
always_comb m_axis_emout.tkeep = '1;
always_comb m_axis_emout.tlast = '0;
endmodule // MemFilter1
module MemFilter2
import BwaMemDefines::*;
#(
parameter GRP_SIZE = 3
)(
input wire clk, rst,
input wire gen_last,
input wire start,
input wire stop,
output logic finish,
output logic busy,
Axi4StreamIf.slave s_axis_emin,
Axi4StreamIf.master m_axis_emout
);
logic [2:0] state, nxt_state;
localparam logic [2:0] S_Idle = 3'd0;
localparam logic [2:0] S_Wait = 3'd1;
localparam logic [2:0] S_Judge = 3'd2;
localparam logic [2:0] S_Output = 3'd3;
localparam logic [2:0] S_Clear = 3'd4;
localparam logic [2:0] S_Flush = 3'd5;
localparam ROW = GRP_SIZE + 1;
localparam COL = GRP_SIZE;
// let idx(r, c) = r * COL + c;
function automatic integer idx (input integer r, input integer c); // "let" is not supported by vivado
idx = r * COL + c;
endfunction
(* ram_style = "registers" *) WorkingMem m[ROW * COL];
WorkingMem m_in[ROW * COL];
wire in_handsk = s_axis_emin.tready & s_axis_emin.tvalid;
wire out_handsk = m_axis_emout.tready & m_axis_emout.tvalid;
wire out_cont = m_axis_emout.tready | ~m_axis_emout.tvalid;
logic glast;
always_ff @(posedge clk) begin : proc_glast
if(rst) begin
glast <= 1'b0;
end
else if(state == S_Idle & start) begin
glast <= gen_last;
end
end
always_comb begin
m_in[0] = s_axis_emin.tdata;
end
genvar r, c;
generate
for(c = 1; c < COL; c++) begin : m_in_row0
always_comb begin
m_in[idx(0, c)] = m[idx(0, c) - 1];
end
end
endgenerate
generate
for(r = 1; r < ROW; r++) begin : m_in_row
for(c = 0; c < COL; c++) begin : m_in_col
always_comb begin
m_in[idx(r, c)] = m[idx(r, c) - 1];
end
end
end
endgenerate
generate
for(c = 0; c < COL; c++) begin : m_row0
always_ff @(posedge clk) begin : proc_m
if(rst) begin
m[idx(0, c)] <= '0;
end
else if(state == S_Idle && start) begin
m[idx(0, c)] <= '0;
end
else if(in_handsk) begin
m[idx(0, c)] <= m_in[idx(0, c)];
end
end
end
endgenerate
generate
for(r = 1; r < ROW; r++) begin : m_row
for(c = 0; c < COL; c++) begin : m_col
always_ff @(posedge clk) begin : proc_m
if(rst) begin
m[idx(r, c)] <= '0;
end
else if(state == S_Idle && start) begin
m[idx(r, c)] <= '0;
end
else if(in_handsk) begin
m[idx(r, c)] <= m_in[idx(r, c)];
end
// else if(state == S_Output && nxt_state == S_Wait) begin
else if(state == S_Clear) begin
m[idx(r, c)] <= '0;
end
end
end
end
endgenerate
logic [COL - 1 : 0] ij_diff;
generate
for(c = 0; c < COL; c++) begin
always_comb begin
ij_diff[c] = m[idx(0, c)].i != m[idx(1, c)].i && m[idx(0, c)].j != m[idx(1, c)].j;
end
end
endgenerate
logic [ROW * COL - 1 : COL] s_diff;
generate
for(r = 1; r < ROW; r++) begin
for(c = 0; c < COL; c++) begin
always_comb begin
s_diff[idx(r, c)] = m[idx(r, c)].s != m[idx(r - 1, c)].s;
end
end
end
endgenerate
logic [ROW * COL - 1 : COL] keep; // only used in output, not flush
generate
for(c = 0; c < COL; c++) begin
always_comb begin
keep[idx(1, c)] = ij_diff[c];
end
end
endgenerate
generate
for(r = 2; r < ROW; r++) begin
for(c = 0; c < COL; c++) begin
always_comb begin
keep[idx(r, c)] = ij_diff[c] & s_diff[idx(r, c)];
end
end
end
endgenerate
// logic [(ROW - 1) * COL - 1 : 0] keep;
// generate
// for(c = 0; c < COL; c++) begin
// always_comb begin
// keep[idx(0, c)] = ij_diff[c];
// end
// end
// endgenerate
// generate
// for(r = 1; r < ROW - 1; r++) begin
// for(c = 0; c < COL; c++) begin
// always_comb begin
// keep[idx(r, c)] = keep[idx(r - 1, c)] && (m[idx(r + 1, c)].s != m[idx(r, c)].s);
// end
// end
// end
// endgenerate
logic stop_r;
always_ff @(posedge clk) begin : proc_stop_r
if(rst) begin
stop_r <= '0;
end
else if(stop) begin
stop_r <= 1'b1;
end
else if(state == S_Flush) begin
stop_r <= 1'b0;
end
end
localparam CW = $clog2(ROW * COL);
logic [CW - 1:0] cnt;
always_ff @(posedge clk) begin : proc_cnt
if(rst) begin
cnt <= '0;
end
// else if(state != S_Wait && nxt_state == S_Wait) begin
// cnt <= CW'(COL - 1); //4'd2;
// end
// else if(state != S_Output && nxt_state == S_Output) begin
// cnt <= CW'(ROW * COL - 1); //4'd11;
// end
// else if(state != S_Flush && nxt_state == S_Flush) begin
// cnt <= CW'((ROW - 1) * COL - 1); //4'd8;
// end
else if(state == S_Idle || state == S_Clear) begin
cnt <= CW'(COL - 1);
end
else if(state == S_Judge) begin
if(|ij_diff) begin
cnt <= CW'(ROW * COL - 1);
end
else begin
cnt <= CW'(COL - 1);
end
end
else if(state == S_Wait && stop_r) begin
cnt <= CW'((ROW - 1) * COL - 1);
end
else if(state == S_Wait) begin
if(in_handsk) begin
if(cnt > 4'd0) begin
cnt <= cnt - 1'b1;
end
end
end
else if(state == S_Output || state == S_Flush) begin
if(out_cont) begin
if(cnt > 4'd0) begin
cnt <= cnt - 1'b1;
end
end
end
end
always_ff @(posedge clk) begin : proc_state
if(rst) begin
state <= S_Idle;
end else begin
state <= nxt_state;
end
end
always_comb begin
nxt_state = state;
case (state)
S_Idle: begin
if(start) begin
nxt_state = S_Wait;
end
end // S_Idle:
S_Wait: begin
if(cnt == 4'b0 & in_handsk) begin
nxt_state = S_Judge;
end
else if(stop_r) begin
nxt_state = S_Flush;
end
end // S_Wait:
S_Judge: begin
if(|ij_diff) begin
nxt_state = S_Output;
end // if(ij_diff)
else begin
nxt_state = S_Wait;
end
end // S_Judge:
S_Output: begin
if(cnt == CW'(COL) & out_cont) begin
nxt_state = S_Clear;
end
end
S_Clear: begin
nxt_state = S_Wait;
end
S_Flush: begin
if(cnt == 4'd0 & out_cont) begin
nxt_state = S_Idle;
end
end
default: begin
nxt_state = state;
end
endcase
end
always_ff @(posedge clk) begin : proc_finish
if(rst) begin
finish <= 1'b0;
end
else if(state == S_Flush && (cnt == 4'd0 & out_cont)) begin
finish <= 1'b1;
end
else begin
finish <= 1'b0;
end
end
assign busy = state != S_Idle;
always_comb begin
s_axis_emin.tready = state == S_Wait;
end
wire WorkingMem emout = m[cnt];
always_comb begin
m_axis_emout.tdata = emout;
end
always_comb begin
if(state == S_Output) begin
m_axis_emout.tvalid = m[cnt].s != 32'd0 & keep[cnt];
end
else if(state == S_Flush) begin
if(cnt == 4'd0) begin
m_axis_emout.tvalid = glast || m[cnt].s != 32'd0; //glast ? 1'b1 : m[cnt].s != 32'd0;
end
else if(cnt < CW'(COL)/*4'd3*/) begin
m_axis_emout.tvalid = m[cnt].s != 32'd0;
end
else begin
m_axis_emout.tvalid = m[cnt].s != 32'd0 && s_diff[cnt];
end
end
else begin
m_axis_emout.tvalid = 1'b0;
end
end
always_comb begin
m_axis_emout.tlast = glast && (state == S_Flush && cnt == 4'd0);
end
always_comb m_axis_emout.tstrb = '1;
always_comb m_axis_emout.tkeep = '1;
endmodule // MemFilter2