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The existing code was quite confusing, with several unnecessary expression terms and apparently contradictory comments.
This reworks it to be much simpler. Instead of an ia variable which is set between the interrupt and completion, there is a claimed register which is set between claim and complete.
One difference is that claims are no longer ignored for interrupts that are not pending. However rv_plic never tries to claim a non-pending interrupt so we save a tiny bit of logic (and simplify the code) by not caring about it. I added an assertion to enforce this which is proven in FPV.
I also added a load more comments and a property to verify you can't claim and complete in the same cycle.
Both new properties are proven, and none of the other properties are disproven after 25 mins: