[cosim] Sort out error/pmp failure behaviour on unaligned accesses

[GregAC]

When spike encounters an unaligned access it splits it into single byte accesses. If one of these sees a bus error or a PMP failure it immediately causes an exception. In Ibex unaligned accesses are split in two and both accesses are tried regardless of bus errors and PMP failures of the other access.

This leads to co-sim mismatches in cases where unaligned accesses cross PMP boundaries (the co-sim framework can currently handle the difference in behaviour for bus errors). What Ibex does is architectural permissible so we should modify spike to match. I have a PR for this: lowRISC/riscv-isa-sim#23 though it also needs some changes on the co-sim side, as it currently removes outstanding unaligned accesses from the pending memory access queue on an error to help deal with the mismatch.

We can remove the co-sim behaviour that removes accesses for the pending memory access queue, that you can see at

ibex/dv/cosim/spike_cosim.cc

Lines 882 to 892 in 726eb97

	// TODO: How to check BE? May need length of transaction?
	// Remove the top pending access now so both the first and second DUT
	// accesses for this misaligned access are removed.
	pending_dside_accesses.erase(pending_dside_accesses.begin());
	}
	// For any misaligned access that sees an error immediately indicate to
	// spike the error has occured, so ensure the top pending access gets
	// removed.
	pending_access_done = true;

However this causes other errors.

This needs to be resolve, though can be done post V2. I've observed PMP tests correctly dealing with cross PMP region accesses so we have confidence this issue is not hiding a real RTL bug behind it.

estimate 4

[GregAC]

estimate range: 2 - 4