FPGA support for Digilent and RealDigital boards

Add support for the Digilent Arty S7-25, Digilent Arty S7-50, Digilent Nexys A7-100T, RealDigital Blackboard and RealDigital Boolean development boards as alternative targets.

Author: heliosfa

README.md

@@ -2,7 +2,7 @@
 
 ![Ibex demo system block diagram](doc/IbexDemoSystemBlockDiagram.png "Ibex demo system block diagram with in the center an Ibex processor connected by a memory bus to the RAM, GPIO, SPI, UART and debug module. Switches, buttons and LEDs are connected to the GPIO. The LCD is driven by SPI. The UART is used for a serial console. Finally, the debug module is used to drive the JTAG.")
 
-This an example RISC-V SoC targeting the Arty-A7 FPGA board. It comprises the
+This an example RISC-V SoC originally targeting the Arty-A7 FPGA board. It comprises the
 [lowRISC Ibex core](https://www.github.com/lowrisc/ibex) along with the
 following features:
 
@@ -14,7 +14,14 @@ following features:
 * SPI
 * A basic peripheral to write ASCII output to a file and halt simulation from software
 
-Debug can be used via a USB connection to the Arty-A7 board. No external JTAG
+Support has been added for several additional FPGA development boards:
+* Arty S7-25 and S7-50
+* Nexys A7-100T
+* Sonata
+* RealDigital Blackboard
+* RealDigital Boolean
+
+Debug can be used via a USB connection to the board. No external JTAG
 probe is required.
 
 ![Arty A7 FPGA showing the Mandelbrot set](doc/ArtyA7WithMandelbrot.png "Arty A7 FPGA with a Mandelbrot fractal on the LCD screen.")
@@ -126,6 +133,19 @@ EOF
 exit
 ```
 
+RealDigital Boolean and Blackboard
+```bash
+
+sudo su
+cat <<EOF > /etc/udev/rules.d/90-realdigital.rules
+# Future Technology Devices International, Ltd FT2232C/D/H Dual UART/FIFO IC
+# used on RealDigital boards
+ACTION=="add|change", SUBSYSTEM=="usb|tty", ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", ATTRS{manufacturer}=="Xilinx", MODE="0666"
+EOF
+
+exit
+```
+
 openFPGAloader
 ```bash
 sudo su
@@ -480,8 +500,17 @@ repository root:
 fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:demo_system
 ```
 
-The default board is the Arty A7, but you can also use different synthesis targets.
-For example, to use the Sonata board change the target to `synth_sonata`.
+The default board is the Arty A7, but you can also use different synthesis targets for supported boards.
+Currently supported targets:
+
+| Board | Target |
+| -------- | ------- |
+| Arty S7-25 | `synth_artys7-25` |
+| Arty S7-50 | `synth_artys7-50` |
+| Nexys A7-100T | `synth_nexysa7` |
+| Sonata | `synth_sonata` |
+| Blackboard | `synth_blackboard` |
+| Boolean | `synth_boolean` |
 
 ## Programming FPGA
 
@@ -490,17 +519,25 @@ To program the FPGA, either use FuseSoC again
 ```
 fusesoc --cores-root=. run --target=synth --run lowrisc:ibex:demo_system
 
-# If the above does not work, try executing the programming operation manually with..
+# If the above does not work, try executing the programming operation manually with:
 make -C ./build/lowrisc_ibex_demo_system_0/synth-vivado/ pgm
 ```
 
+Replace `synth` in the fuseoc or make invocation with the appropriate target if you are use an alternative board.
+
 You can also use [OpenFPGALoader](https://github.com/trabucayre/openFPGALoader), here are some example commands:
 ```
 # Programming the Arty A7
 ./openFPGALoader -b arty_a7_35t build/lowrisc_ibex_demo_system_0/synth-vivado/lowrisc_ibex_demo_system_0.bit
 
 # Programming the Sonata board
 ./openFPGALoader -c ft4232 build/lowrisc_ibex_demo_system_0/synth_sonata-vivado/lowrisc_ibex_demo_system_0.bit
+
+# Programming the Blackboard board
+./openFPGALoader -c ft4232 build/lowrisc_ibex_demo_system_0/synth_blackboard-vivado/lowrisc_ibex_demo_system_0.bit
+
+# Programming the Boolean board
+./openFPGALoader -c ft4232 build/lowrisc_ibex_demo_system_0/synth_boolean-vivado/lowrisc_ibex_demo_system_0.bit
 ```
 
 ## Loading an application to the programmed FPGA
@@ -518,6 +555,12 @@ You can choose to immediately run it or begin halted, allowing you to attach a d
 
 # Run demo on the Sonata board
 ./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/sonata-openocd-cfg.tcl
+
+# Run demo on the Blackboard board
+./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/boolean-openocd-cfg.tcl
+
+# Run demo on the Boolean board
+./util/load_demo_system.sh run ./sw/c/build/demo/hello_world/demo ./util/boolean-openocd-cfg.tcl
 ```
 
 To view terminal output use screen:
@@ -548,3 +591,12 @@ riscv32-unknown-elf-gdb ./sw/c/build/demo/hello_world/demo
 
 (gdb) target extended-remote localhost:3333
 ```
+
+## Board-specific notes
+
+### Realdigital Blackboard
+
+The Blackboard uses a Zynq 7000 series SoC and the serial is routed to the PS rather than the PL.
+While it could be possible to access the serial through the PS using AXI, the current implementation maps serial to the PMODC header.
+
+The mapping follows the [Pmod Interface Type 3 (UART) pinout](https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_3_1.pdf) for the Digilent Pmod USBUART interface ([Digilent 410-212](https://digilent.com/shop/pmod-usbuart-usb-to-uart-interface/)), but any 3.3V USB-UART interface can be used.

data/pins_artys7.xdc

@@ -0,0 +1,42 @@
+## Common constraints file for Arty S7-35 and S7-50.
+## Based on https://github.com/Digilent/digilent-xdc/blob/master/Arty-S7-50-Master.xdc
+## and modified for Ibex
+
+## Clock signal
+set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; #IO_L12P_T1_MRCC_34 Sch=ddr3_clk[200]
+create_clock -add -name sys_clk_pin -period 10.000 -waveform {0 5.000}  [get_ports { IO_CLK }];
+
+## CPU Reset Button. Steal BTN[3] to make things work "out of the box"
+#set_property -dict { PACKAGE_PIN C18    IOSTANDARD LVCMOS33 } [get_ports { IO_RST }]; #IO_L16P_T2_35 Sch=ck_rst
+set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS33 } [get_ports { IO_RST }]; #IO_L20P_T3_A20_15 Sch=btn[3]
+
+## Switches
+set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L20N_T3_A19_15 Sch=sw[0]
+set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L21P_T3_DQS_15 Sch=sw[1]
+set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L21N_T3_DQS_A18_15 Sch=sw[2]
+set_property -dict { PACKAGE_PIN M5    IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L6N_T0_VREF_34 Sch=sw[3]
+
+## LEDs
+set_property -dict { PACKAGE_PIN E18   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L16N_T2_A27_15 Sch=led[2]
+set_property -dict { PACKAGE_PIN F13   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L17P_T2_A26_15 Sch=led[3]
+set_property -dict { PACKAGE_PIN E13   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[4]
+set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L18P_T2_A24_15 Sch=led[5]
+
+## Buttons
+set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { BTN[0] }]; #IO_L18N_T2_A23_15 Sch=btn[0]
+set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { BTN[1] }]; #IO_L19P_T3_A22_15 Sch=btn[1]
+set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { BTN[2] }]; #IO_L19N_T3_A21_VREF_15 Sch=btn[2]
+set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS33 } [get_ports { BTN[3] }]; #IO_L20P_T3_A20_15 Sch=btn[3]
+
+## RGB LEDs
+set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #IO_L23N_T3_FWE_B_15 Sch=led0_r
+set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #IO_L14N_T2_SRCC_15 Sch=led0_g
+set_property -dict { PACKAGE_PIN F15   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #IO_L13N_T2_MRCC_15 Sch=led0_b
+set_property -dict { PACKAGE_PIN E15   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led1_r
+set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #IO_L16P_T2_A28_15 Sch=led1_g
+set_property -dict { PACKAGE_PIN E14   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #IO_L15P_T2_DQS_15 Sch=led1_b
+
+## USB-UART Interface
+set_property -dict { PACKAGE_PIN R12   IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_25_14 Sch=uart_rxd_out
+set_property -dict { PACKAGE_PIN V12   IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L24N_T3_A00_D16_14 Sch=uart_txd_in
+

data/pins_blackboard.xdc

@@ -0,0 +1,61 @@
+## Based on https://www.realdigital.org/downloads/615e6849c320c5615deeebaf0ea38e94.txt
+## and modified for Ibex
+
+##Clock
+set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];
+
+#Individual LEDS
+set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L14P_T2_SRCC_34 Schematic=LD0
+set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L14N_T2_SRCC_34 Schematic=LD1
+set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_0_34 Schematic=LD2
+set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L15P_T2_DQS_34 Schematic=LD3
+set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L3P_T0_DWS_PUDC_B_34 Schematic=LD4
+set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_25_34 Schematic=LD5
+set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L16N_T2_34 Schematic=LD6
+set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L17N_T2_34  Schematic=LD7
+set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16P_T2_34 Schematic=LD8
+set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L22N_T3_34 Schematic=LD9
+
+#RGB_LEDS
+set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #IO_L22P_T3_34  Schematic=LD10_R
+set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #IO_L18N_T2_34 Schematic=LD10_G
+set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #IO_L17P_T2_34 Schematic=LD10_B
+
+set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #IO_L8N_T1_34 Schematic=LD11_R
+set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #IO_L7P_T1_34 Schematic=LD11_G
+set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #IO_L7N_T1_34 Schematic=LD11_B
+
+#Switches
+set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L19N_T3_VREF_34 Schematic=SW0
+set_property -dict { PACKAGE_PIN U20   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L15N_T2_DQS_34 Schematic=SW1
+set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L19P_T3_34 Schematic=SW2
+set_property -dict { PACKAGE_PIN N16   IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L21N_T3_DQS_AD14N_35 Schematic=SW3
+set_property -dict { PACKAGE_PIN R14   IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L6N_T0_VREF_34 Schematic=SW4
+set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L6P_T0_34 Schematic=SW5
+set_property -dict { PACKAGE_PIN L15   IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L22N_T3_AD7N_35 Schematic=SW6
+set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L23N_T3_35 Schematic=SW7
+set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { SW[8] }]; #IO_L10P_T1_34 Sch=VGA_R4_CON
+set_property -dict { PACKAGE_PIN T12   IOSTANDARD LVCMOS33 } [get_ports { SW[9] }]; #IO_L10N_T1_34 Sch=VGA_R5_CON
+set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L18P_T2_34 Sch=VGA_R6_CON
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L18N_T2_AD13N_35 Sch=VGA_R7_CON
+
+#Push Buttons
+set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { BTN[0] }]; #IO_L8P_T1_34 Schematic=BTN0
+set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { BTN[1] }]; #IO_L4N_T0_34 Schematic=BTN1
+set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { BTN[2] }]; #IO_L24P_T3_34 Schematic=BTN2
+
+# Steal BTN[3] to be IO_RST
+set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { IO_RST }]; #IO_L23P_T3_35 Schematic=BTN3
+
+##PmodC - This is where we route the UART: Uses Digilent PMOD specification 1.3 for PMOD Interface Type 3
+# https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_3_1.pdf
+# JC3 = RX, JC2 = TX
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { UART_CTS }]; #IO_L10P_T1_34 Sch=JC1  
+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #IO_L10N_T1_34 Sch=JC2
+set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #IO_L18P_T2_34 Sch=JC3
+#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { UART_RTS }]; #IO_LP9_T1_DQS_34 Sch=JC4
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { JC7 }]; #IO_L7P_T1_AD2P_35 Sch=JC7
+#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { JC8 }]; #IO_0_35 Sch=JC8
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { JC9 }]; #IO_L16P_T2_35 Sch=JC9
+#set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { JC10 }]; #IO_L19N_T3_VREF_35 Sch=JC10

data/pins_boolean.xdc

@@ -0,0 +1,64 @@
+## Based on https://www.realdigital.org/downloads/8d5c167add28c014173edcf51db78bb9.txt
+## and modified for Ibex
+
+# clk input is from the 100 MHz oscillator on Boolean board
+create_clock -add -name gclk -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];
+set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports {IO_CLK}]
+
+# Set Bank 0 voltage
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+# On-board Slide Switches
+set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports {SW[0]}]
+set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {SW[1]}]
+set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports {SW[2]}]
+set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports {SW[3]}]
+set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports {SW[4]}]
+set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {SW[5]}]
+set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {SW[6]}]
+set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {SW[7]}]
+set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {SW[8]}]
+set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports {SW[9]}]
+set_property -dict {PACKAGE_PIN N1 IOSTANDARD LVCMOS33} [get_ports {SW[10]}]
+set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {SW[11]}]
+set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {SW[12]}]
+set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {SW[13]}]
+set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {SW[14]}]
+set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {SW[15]}]
+
+# On-board LEDs
+set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {LED[0]}]
+set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {LED[1]}]
+set_property -dict {PACKAGE_PIN F1 IOSTANDARD LVCMOS33} [get_ports {LED[2]}]
+set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS33} [get_ports {LED[3]}]
+set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {LED[4]}]
+set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {LED[5]}]
+set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {LED[6]}]
+set_property -dict {PACKAGE_PIN E5 IOSTANDARD LVCMOS33} [get_ports {LED[7]}]
+set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS33} [get_ports {LED[8]}]
+set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS33} [get_ports {LED[9]}]
+set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {LED[10]}]
+set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS33} [get_ports {LED[11]}]
+set_property -dict {PACKAGE_PIN B3 IOSTANDARD LVCMOS33} [get_ports {LED[12]}]
+set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {LED[13]}]
+set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS33} [get_ports {LED[14]}]
+set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS33} [get_ports {LED[15]}]
+
+# On-board Buttons
+set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {IO_RST}];   # Steak to be Reset. Was BTN[0]
+set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {BTN[1]}]
+set_property -dict {PACKAGE_PIN H2 IOSTANDARD LVCMOS33} [get_ports {BTN[2]}]
+set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {BTN[3]}]
+
+# On-board color LEDs
+set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS33} [get_ports {RGB_LED[0]}];   # RBG0_R
+set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS33} [get_ports {RGB_LED[1]}];   # RBG0_G
+set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {RGB_LED[2]}];   # RBG0_B
+set_property -dict {PACKAGE_PIN U3 IOSTANDARD LVCMOS33} [get_ports {RGB_LED[3]}];   # RBG1_R
+set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS33} [get_ports {RGB_LED[4]}];   # RBG1_G
+set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS33} [get_ports {RGB_LED[5]}];   # RBG1_B
+
+# UART
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports {UART_RX}]
+set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {UART_TX}]