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jpcryptGregAC
jpcrypt
authored and
GregAC
committed
Tweak CW305/312 targets for use with ChipWhisperer
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-70
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5 files changed

+81
-70
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‎data/pins_cw305.xdc

Lines changed: 16 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,15 @@
1-
## Clock signal
2-
set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { IO_CLK }]; # USB clock (96 MHz)
3-
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { IO_CLK }];
1+
## Clocks
2+
set_property -dict { PACKAGE_PIN N13 IOSTANDARD LVCMOS33 } [get_ports { I_pll_clk1 }];
3+
set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { I_cw_clkin }];
4+
5+
create_clock -period 10.000 -name pll_clk1 -waveform {0.000 5.000} [get_nets I_pll_clk1]
6+
create_clock -period 10.000 -name cw_clkin -waveform {0.000 5.000} [get_nets I_cw_clkin]
47

58
## Switches
6-
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
7-
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
8-
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
9-
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
10-
11-
## RGB LEDs
12-
set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #IO_L18N_T2_35 Sch=led0_b
13-
set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #IO_L19N_T3_VREF_35 Sch=led0_g
14-
set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #IO_L19P_T3_35 Sch=led0_r
15-
set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #IO_L20P_T3_35 Sch=led1_b
16-
set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #IO_L21P_T3_DQS_35 Sch=led1_g
17-
set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #IO_L20N_T3_35 Sch=led1_r
18-
set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[6] }]; #IO_L21N_T3_DQS_35 Sch=led2_b
19-
set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[7] }]; #IO_L22N_T3_35 Sch=led2_g
20-
set_property -dict { PACKAGE_PIN D16 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[8] }]; #IO_L22P_T3_35 Sch=led2_r
21-
set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[9] }]; #IO_L23P_T3_35 Sch=led3_b
22-
set_property -dict { PACKAGE_PIN F12 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[10] }]; #IO_L24P_T3_35 Sch=led3_g
23-
set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[11] }]; #IO_L23N_T3_35 Sch=led3_r
9+
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { J16 }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
10+
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { K16 }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
11+
set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { L14 }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
12+
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { K15 }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
2413

2514
## LEDs
2615
set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L24N_T3_35 Sch=led[4]
@@ -33,5 +22,11 @@ set_property DRIVE 8 [get_ports LED*]
3322
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { UART_TX }]; #CW IO1
3423
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { UART_RX }]; #CW IO2
3524

25+
# IO3-4:
26+
set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { IO3 }]; #IO3
27+
set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { IO4 }]; #IO4
28+
29+
3630
set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }]; #IO_L16P_T2_35 Sch=ck_rst
3731

32+
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

‎data/pins_cw312a35.xdc

Lines changed: 4 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -4,24 +4,8 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { I
44

55
## Switches
66
# IO3-4:
7-
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO3
8-
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO4
9-
10-
## RGB LEDs
11-
# HDR1-10:
12-
set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[0] }]; #HDR1
13-
set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[1] }]; #HDR2
14-
set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[2] }]; #HDR3
15-
set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[3] }]; #HDR4
16-
set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[4] }]; #HDR5
17-
set_property -dict { PACKAGE_PIN V1 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[5] }]; #HDR6
18-
set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[6] }]; #HDR7
19-
set_property -dict { PACKAGE_PIN V6 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[7] }]; #HDR8
20-
set_property -dict { PACKAGE_PIN V7 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[8] }]; #HDR9
21-
set_property -dict { PACKAGE_PIN V9 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[9] }]; #HDR10
22-
# TRACEDATA0-1:
23-
set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[10] }]; #TRACEDATA0
24-
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { RGB_LED[11] }]; #TRACEDATA1
7+
set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { IO3 }]; #IO3
8+
set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { IO4 }]; #IO4
259

2610
## LEDs
2711
set_property -dict { PACKAGE_PIN R1 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }];
@@ -36,3 +20,5 @@ set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { UART_R
3620

3721
set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { IO_RST_N }];
3822

23+
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
24+

‎ibex_demo_system.core

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -72,8 +72,9 @@ parameters:
7272
SRAMInitFile:
7373
datatype: str
7474
description: SRAM initialization file in vmem hex format
75-
#default: "../../../../../sw/build/blank/blank.vmem"
76-
default: "../../../../../sw/build/demo/hello_world/demo.vmem"
75+
default: "../../../../../sw/build/blank/blank.vmem"
76+
#default: "../../../../../sw/build/demo/hello_world/demo.vmem"
77+
#default: "../../../../../sw/build/demo/simpleserial-aes/simpleserial-aes.vmem"
7778
paramtype: vlogparam
7879

7980
# For value definition, please see ip/prim/rtl/prim_pkg.sv
@@ -108,8 +109,8 @@ targets:
108109
toplevel: top_cw305
109110
tools:
110111
vivado:
111-
part: "xc7a100tftg256-2"
112-
#part: "xc7a35tftg256-2"
112+
part: "xc7a100tftg256-2" # default to a100 part
113+
#part: "xc7a35tftg256-2" # a35 option
113114
parameters:
114115
- SRAMInitFile
115116
- PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx

‎rtl/fpga/top_cw305.sv

Lines changed: 36 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5,44 +5,66 @@
55
// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System.
66
module top_cw305 (
77
// These inputs are defined in data/pins_cw305.xdc
8-
input IO_CLK,
9-
input IO_RST_N,
10-
input [ 3:0] SW,
11-
output [ 2:0] LED,
12-
output [11:0] RGB_LED,
13-
input UART_RX,
14-
output UART_TX
8+
input logic I_pll_clk1,
9+
input logic I_cw_clkin,
10+
input logic IO_RST_N,
11+
input logic IO3,
12+
input logic J16,
13+
input logic K16,
14+
input logic L14,
15+
input logic K15,
16+
output logic IO4,
17+
output logic [ 2:0] LED,
18+
input logic UART_RX,
19+
output logic UART_TX
1520
);
1621
parameter SRAMInitFile = "";
1722

1823
logic clk_sys, rst_sys_n;
24+
reg [24:0] clock_heartbeat;
25+
26+
assign LED[0] = clock_heartbeat[24];
27+
assign LED[1] = ~UART_RX || ~UART_TX;
28+
assign LED[2] = IO4;
29+
30+
always @(posedge clk_sys) clock_heartbeat <= clock_heartbeat + 25'd1;
1931

2032
// Instantiating the Ibex Demo System.
2133
ibex_demo_system #(
22-
.GpiWidth(3),
23-
.GpoWidth(3),
24-
.PwmWidth(12),
34+
.GpiWidth(5),
35+
.GpoWidth(1),
36+
.PwmWidth(1),
2537
.SRAMInitFile(SRAMInitFile)
2638
) u_ibex_demo_system (
2739
//input
2840
.clk_sys_i(clk_sys),
2941
.rst_sys_ni(rst_sys_n),
30-
.gp_i(SW),
42+
.gp_i({IO3, K15, L14, K16, J16}),
3143
.uart_rx_i(UART_RX),
3244

3345
//output
34-
.gp_o(LED),
35-
.pwm_o(RGB_LED),
46+
.gp_o(IO4),
47+
.pwm_o(),
3648
.uart_tx_o(UART_TX),
3749

3850
.spi_rx_i(1'b0),
3951
.spi_tx_o(),
4052
.spi_sck_o()
4153
);
4254

55+
// clock source select:
56+
logic chosen_clock;
57+
BUFGMUX_CTRL U_clock_source_select (
58+
.O (chosen_clock),
59+
.I0 (I_pll_clk1),
60+
.I1 (I_cw_clkin),
61+
.S (J16) // J16 selects the clock; 0=on-board PLL, 1=from CW HS2 pin
62+
);
63+
64+
4365
// Generating the system clock and reset for the FPGA.
4466
clkgen_xil7series clkgen(
45-
.IO_CLK,
67+
.IO_CLK (chosen_clock),
4668
.IO_RST_N,
4769
.clk_sys,
4870
.rst_sys_n

‎rtl/fpga/top_cw312a35.sv

Lines changed: 20 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -5,34 +5,41 @@
55
// This is the top level SystemVerilog file that connects the IO on the board to the Ibex Demo System.
66
module top_cw312a35 (
77
// These inputs are defined in data/pins_cw305.xdc
8-
input IO_CLK,
9-
input IO_RST_N,
10-
input [ 1:0] SW,
11-
output [ 2:0] LED,
12-
output [11:0] RGB_LED,
13-
input UART_RX,
14-
output UART_TX
8+
input logic IO_CLK,
9+
input logic IO_RST_N,
10+
input logic IO3,
11+
output logic IO4,
12+
output logic [ 2:0] LED,
13+
input logic UART_RX,
14+
output logic UART_TX
1515
);
1616
parameter SRAMInitFile = "";
1717

1818
logic clk_sys, rst_sys_n;
19+
reg [24:0] clock_heartbeat;
20+
21+
assign LED[0] = clock_heartbeat[24];
22+
assign LED[1] = ~UART_RX || ~UART_TX;
23+
assign LED[2] = IO4;
24+
25+
always @(posedge clk_sys) clock_heartbeat <= clock_heartbeat + 25'd1;
1926

2027
// Instantiating the Ibex Demo System.
2128
ibex_demo_system #(
22-
.GpiWidth(3),
23-
.GpoWidth(3),
24-
.PwmWidth(12),
29+
.GpiWidth(1),
30+
.GpoWidth(1),
31+
.PwmWidth(1),
2532
.SRAMInitFile(SRAMInitFile)
2633
) u_ibex_demo_system (
2734
//input
2835
.clk_sys_i(clk_sys),
2936
.rst_sys_ni(rst_sys_n),
30-
.gp_i({2'b00, SW}),
37+
.gp_i(IO3),
3138
.uart_rx_i(UART_RX),
3239

3340
//output
34-
.gp_o(LED),
35-
.pwm_o(RGB_LED),
41+
.gp_o(IO4),
42+
.pwm_o(),
3643
.uart_tx_o(UART_TX),
3744

3845
.spi_rx_i(1'b0),

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