Search results

[DAG] Handle truncated splat in isBoolConstant

backend:AArch64

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145473

#145473 In llvm/llvm-project;

· davemgreen opened on Jun 24, 2025

[TargetLowering] Fold (a | b) == b -> (a & ~b) == 0 or similar when and-not exists

backend:AArch64

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145368

#145368 In llvm/llvm-project;

· AZero13 opened on Jun 23, 2025

[AMDGPU][SDAG] Handle ISD::PTRADD in various special cases

backend:AMDGPU

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145330

#145330 In llvm/llvm-project;

· ritter-x2a opened on Jun 23, 2025

[NFC][TableGen] Use ArrayRef instead of const vector reference

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

tablegen

Status: Open (in progress).

llvm/llvm-projectnumber 145323

#145323 In llvm/llvm-project;

· jurahul opened on Jun 23, 2025

[SelectionDAG] Optimize MPI for align(1) GEPs using base pointer

backend:AMDGPU

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145309

#145309 In llvm/llvm-project;

· Acthinks opened on Jun 23, 2025

[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine

backend:AArch64

backend:ARM

backend:loongarch

backend:PowerPC

backend:SystemZ

backend:X86

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145298

#145298 In llvm/llvm-project;

· woruyu opened on Jun 23, 2025

DAG: Emit an error if trying to legalize read/write register with illegal types

backend:AArch64

backend:AMDGPU

backend:ARM

backend:Hexagon

backend:Lanai

backend:loongarch

backend:MIPS

backend:PowerPC

backend:RISC-V

backend:Sparc

backend:SystemZ

backend:X86

llvm:codegen

llvm:globalisel

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 145197

#145197 In llvm/llvm-project;

· arsenm opened on Jun 22, 2025

[LangRef] Require that vscale be a power of two

backend:AArch64

backend:RISC-V

llvm:analysisIncludes value tracking, cost tables and constant foldingIncludes value tracking, cost tables and constant folding

llvm:instcombineCovers the InstCombine, InstSimplify and AggressiveInstCombine passesCovers the InstCombine, InstSimplify and AggressiveInstCombine passes

llvm:ir

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

llvm:transforms

vectorizers

Status: Open (in progress).

llvm/llvm-projectnumber 145098

#145098 In llvm/llvm-project;

· preames opened on Jun 20, 2025

[AMDGPU] SelectionDAG divergence tracking should take into account Target divergency.

backend:AMDGPU

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open (in progress).

llvm/llvm-projectnumber 144947

#144947 In llvm/llvm-project;

· alex-t opened on Jun 19, 2025

[llvm] LLVM backend crashes when using <code>__builtin_ia32_prefetchi</code>

backend:X86

crash-on-invalid

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open.

Bug

#144857 In llvm/llvm-project;

· MacroModel opened on Jun 19, 2025

[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open.

Feature

#144513 In llvm/llvm-project;

· RKSimon opened on Jun 17, 2025

[DAG] Add SDPatternMatch m_SpecificScalarVT / m_SpecificVectorElementVT matchers

good first issuehttps://github.com/llvm/llvm-project/contributehttps://github.com/llvm/llvm-project/contribute

llvm:SelectionDAGSelectionDAGISel as wellSelectionDAGISel as well

Status: Open.

Task

#144477 In llvm/llvm-project;

· RKSimon opened on Jun 17, 2025