[Headers][X86] VectorExprEvaluator::VisitCallExpr - allow AVX2/AVX512 per-element shift intrinsics to be used in constexpr

[RKSimon]

Handle the elementwise vector shift intrinsics inside VectorExprEvaluator::VisitCallExpr and add constexpr test coverage, similar to #152524

_mm*_sllv_epi16 _mm*_srlv_epi16 _mm*_srav_epi16
_mm*_sllv_epi32 _mm*_srlv_epi32 _mm*_srav_epi32
_mm*_sllv_epi64 _mm*_srlv_epi64 _mm*_srav_epi64

_mm*_mask_sllv_epi16 _mm*_mask_srlv_epi16 _mm*_mask_srav_epi16
_mm*_mask_sllv_epi32 _mm*_mask_srlv_epi32 _mm*_mask_srav_epi32
_mm*_mask_sllv_epi64 _mm*_mask_srlv_epi64 _mm*_mask_srav_epi64

_mm*_maskz_sllv_epi16 _mm*_maskz_srlv_epi16 _mm*_maskz_srav_epi16
_mm*_maskz_sllv_epi32 _mm*_maskz_srlv_epi32 _mm*_maskz_srav_epi32
_mm*_maskz_sllv_epi64 _mm*_maskz_srlv_epi64 _mm*_maskz_srav_epi64

for 128/256/512 variants

The shift intrinsics have special case handling for out of bounds (elementwise) shift amounts, for logical shifts if the unsigned amount is greater than or equal to the element bitwidth then the result is 0. For arithmetic shifts, the shift amount is clamped to (bitwidth-1) to splat the sign bit.

[llvmbot]

Hi!

This issue may be a good introductory issue for people new to working on LLVM. If you would like to work on this issue, your first steps are:

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3. Fix the issue locally.
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If you have any further questions about this issue, don't hesitate to ask via a comment in the thread below.

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Simon Pilgrim (RKSimon)

Handle the elementwise vector shift intrinsics inside VectorExprEvaluator::VisitCallExpr and add constexpr test coverage, similar to https://github.com//issues/152524 ``` _mm*_sllv_epi8 _mm*_srlv_epi8 _mm*_srav_epi8 _mm*_sllv_epi16 _mm*_srlv_epi16 _mm*_srav_epi16 _mm*_sllv_epi32 _mm*_srlv_epi32 _mm*_srav_epi32 _mm*_sllv_epi64 _mm*_srlv_epi64 _mm*_srav_epi64

_mm*_mask_sllv_epi8 _mm*_mask_srlv_epi8 _mm*_mask_srav_epi8
_mm*_mask_sllv_epi16 _mm*_mask_srlv_epi16 _mm*_mask_srav_epi16
_mm*_mask_sllv_epi32 _mm*_mask_srlv_epi32 _mm*_mask_srav_epi32
_mm*_mask_sllv_epi64 _mm*_mask_srlv_epi64 _mm*_mask_srav_epi64

_mm*_maskz_sllv_epi8 _mm*_maskz_srlv_epi8 _mm*_maskz_srav_epi8
_mm*_maskz_sllv_epi16 _mm*_maskz_srlv_epi16 _mm*_maskz_srav_epi16
_mm*_maskz_sllv_epi32 _mm*_maskz_srlv_epi32 _mm*_maskz_srav_epi32
_mm*_maskz_sllv_epi64 _mm*_maskz_srlv_epi64 _mm*_maskz_srav_epi64

for 128/256-512 variants

The shift intrinsics have special case handling for out of bounds (elementwise) shift amounts, for logical shifts if the unsigned amount is greater than or equal to the element bitwidth then the result is 0. For arithmetic shifts, the shift amount is clamped to (bitwidth-1) to splat the sign bit.
</details>

[llvmbot]

@llvm/issue-subscribers-good-first-issue

Author: Simon Pilgrim (RKSimon)

Handle the elementwise vector shift intrinsics inside VectorExprEvaluator::VisitCallExpr and add constexpr test coverage, similar to https://github.com//issues/152524 ``` _mm*_sllv_epi8 _mm*_srlv_epi8 _mm*_srav_epi8 _mm*_sllv_epi16 _mm*_srlv_epi16 _mm*_srav_epi16 _mm*_sllv_epi32 _mm*_srlv_epi32 _mm*_srav_epi32 _mm*_sllv_epi64 _mm*_srlv_epi64 _mm*_srav_epi64

_mm*_mask_sllv_epi8 _mm*_mask_srlv_epi8 _mm*_mask_srav_epi8
_mm*_mask_sllv_epi16 _mm*_mask_srlv_epi16 _mm*_mask_srav_epi16
_mm*_mask_sllv_epi32 _mm*_mask_srlv_epi32 _mm*_mask_srav_epi32
_mm*_mask_sllv_epi64 _mm*_mask_srlv_epi64 _mm*_mask_srav_epi64

_mm*_maskz_sllv_epi8 _mm*_maskz_srlv_epi8 _mm*_maskz_srav_epi8
_mm*_maskz_sllv_epi16 _mm*_maskz_srlv_epi16 _mm*_maskz_srav_epi16
_mm*_maskz_sllv_epi32 _mm*_maskz_srlv_epi32 _mm*_maskz_srav_epi32
_mm*_maskz_sllv_epi64 _mm*_maskz_srlv_epi64 _mm*_maskz_srav_epi64

for 128/256-512 variants

The shift intrinsics have special case handling for out of bounds (elementwise) shift amounts, for logical shifts if the unsigned amount is greater than or equal to the element bitwidth then the result is 0. For arithmetic shifts, the shift amount is clamped to (bitwidth-1) to splat the sign bit.
</details>