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[SelectionDAG] Use Register around RegisterSDNode related functions. NFC
RegisterSDNode itself already stored a Register.
1 parent 30eb193 commit fe012bd

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4 files changed

+18
-18
lines changed

4 files changed

+18
-18
lines changed

llvm/include/llvm/CodeGen/SelectionDAG.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -772,7 +772,7 @@ class SelectionDAG {
772772
SDValue getMCSymbol(MCSymbol *Sym, EVT VT);
773773

774774
SDValue getValueType(EVT);
775-
SDValue getRegister(unsigned Reg, EVT VT);
775+
SDValue getRegister(Register Reg, EVT VT);
776776
SDValue getRegisterMask(const uint32_t *RegMask);
777777
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label);
778778
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root,
@@ -784,7 +784,7 @@ class SelectionDAG {
784784
return getBlockAddress(BA, VT, Offset, true, TargetFlags);
785785
}
786786

787-
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg,
787+
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg,
788788
SDValue N) {
789789
return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
790790
getRegister(Reg, N.getValueType()), N);
@@ -793,7 +793,7 @@ class SelectionDAG {
793793
// This version of the getCopyToReg method takes an extra operand, which
794794
// indicates that there is potentially an incoming glue value (if Glue is not
795795
// null) and that there should be a glue result.
796-
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N,
796+
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N,
797797
SDValue Glue) {
798798
SDVTList VTs = getVTList(MVT::Other, MVT::Glue);
799799
SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue };
@@ -810,7 +810,7 @@ class SelectionDAG {
810810
ArrayRef(Ops, Glue.getNode() ? 4 : 3));
811811
}
812812

813-
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT) {
813+
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT) {
814814
SDVTList VTs = getVTList(VT, MVT::Other);
815815
SDValue Ops[] = { Chain, getRegister(Reg, VT) };
816816
return getNode(ISD::CopyFromReg, dl, VTs, Ops);
@@ -819,7 +819,7 @@ class SelectionDAG {
819819
// This version of the getCopyFromReg method takes an extra operand, which
820820
// indicates that there is potentially an incoming glue value (if Glue is not
821821
// null) and that there should be a glue result.
822-
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT,
822+
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT,
823823
SDValue Glue) {
824824
SDVTList VTs = getVTList(VT, MVT::Other, MVT::Glue);
825825
SDValue Ops[] = { Chain, getRegister(Reg, VT), Glue };

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -760,7 +760,7 @@ static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N) {
760760
ID.AddPointer(cast<BasicBlockSDNode>(N)->getBasicBlock());
761761
break;
762762
case ISD::Register:
763-
ID.AddInteger(cast<RegisterSDNode>(N)->getReg());
763+
ID.AddInteger(cast<RegisterSDNode>(N)->getReg().id());
764764
break;
765765
case ISD::RegisterMask:
766766
ID.AddPointer(cast<RegisterMaskSDNode>(N)->getRegMask());
@@ -2292,16 +2292,16 @@ SDValue SelectionDAG::getCommutedVectorShuffle(const ShuffleVectorSDNode &SV) {
22922292
return getVectorShuffle(VT, SDLoc(&SV), Op1, Op0, MaskVec);
22932293
}
22942294

2295-
SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) {
2295+
SDValue SelectionDAG::getRegister(Register Reg, EVT VT) {
22962296
SDVTList VTs = getVTList(VT);
22972297
FoldingSetNodeID ID;
22982298
AddNodeIDNode(ID, ISD::Register, VTs, std::nullopt);
2299-
ID.AddInteger(RegNo);
2299+
ID.AddInteger(Reg.id());
23002300
void *IP = nullptr;
23012301
if (SDNode *E = FindNodeOrInsertPos(ID, IP))
23022302
return SDValue(E, 0);
23032303

2304-
auto *N = newSDNode<RegisterSDNode>(RegNo, VTs);
2304+
auto *N = newSDNode<RegisterSDNode>(Reg, VTs);
23052305
N->SDNodeBits.IsDivergent = TLI->isSDNodeSourceOfDivergence(N, FLI, UA);
23062306
CSEMap.InsertNode(N, IP);
23072307
InsertNode(N);

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+7-7
Original file line numberDiff line numberDiff line change
@@ -2183,7 +2183,7 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
21832183
}
21842184

21852185
if (!FuncInfo.CanLowerReturn) {
2186-
unsigned DemoteReg = FuncInfo.DemoteRegister;
2186+
Register DemoteReg = FuncInfo.DemoteRegister;
21872187
const Function *F = I.getParent()->getParent();
21882188

21892189
// Emit a store of the return value through the virtual register.
@@ -3013,7 +3013,7 @@ void SelectionDAGBuilder::visitJumpTableHeader(SwitchCG::JumpTable &JT,
30133013
SwitchOp =
30143014
DAG.getZExtOrTrunc(Sub, dl, TLI.getJumpTableRegTy(DAG.getDataLayout()));
30153015

3016-
unsigned JumpTableReg =
3016+
Register JumpTableReg =
30173017
FuncInfo.CreateReg(TLI.getJumpTableRegTy(DAG.getDataLayout()));
30183018
SDValue CopyTo =
30193019
DAG.getCopyToReg(getControlRoot(), dl, JumpTableReg, SwitchOp);
@@ -7748,7 +7748,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
77487748
const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
77497749
MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
77507750
const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
7751-
unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
7751+
Register VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
77527752
SDValue N = DAG.getCopyFromReg(DAG.getEntryNode(), sdl, VReg, PtrVT);
77537753
if (Intrinsic == Intrinsic::eh_exceptioncode)
77547754
N = DAG.getZExtOrTrunc(N, sdl, MVT::i32);
@@ -11817,8 +11817,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
1181711817

1181811818
// Update the SwiftErrorVRegDefMap.
1181911819
if (Res.getOpcode() == ISD::CopyFromReg && isSwiftErrorArg) {
11820-
unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
11821-
if (Register::isVirtualRegister(Reg))
11820+
Register Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
11821+
if (Reg.isVirtual())
1182211822
SwiftError->setCurrentVReg(FuncInfo->MBB, SwiftError->getFunctionArg(),
1182311823
Reg);
1182411824
}
@@ -11829,8 +11829,8 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
1182911829
// If we can, though, try to skip creating an unnecessary vreg.
1183011830
// FIXME: This isn't very clean... it would be nice to make this more
1183111831
// general.
11832-
unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
11833-
if (Register::isVirtualRegister(Reg)) {
11832+
Register Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
11833+
if (Reg.isVirtual()) {
1183411834
FuncInfo->ValueMap[&Arg] = Reg;
1183511835
continue;
1183611836
}

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -895,8 +895,8 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() {
895895
if (N->getOpcode() != ISD::CopyToReg)
896896
continue;
897897

898-
unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
899-
if (!Register::isVirtualRegister(DestReg))
898+
Register DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
899+
if (!DestReg.isVirtual())
900900
continue;
901901

902902
// Ignore non-integer values.

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