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[RISCV] Allow crypto features to imply dependents
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2 files changed

+33
-62
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2 files changed

+33
-62
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‎llvm/lib/Target/RISCV/RISCVFeatures.td

+18-9
Original file line numberDiff line numberDiff line change
@@ -733,7 +733,8 @@ def HasStdExtZfhOrZvfh
733733

734734
def FeatureStdExtZvkb
735735
: RISCVExtension<"zvkb", 1, 0,
736-
"'Zvkb' (Vector Bit-manipulation used in Cryptography)">,
736+
"'Zvkb' (Vector Bit-manipulation used in Cryptography)",
737+
[FeatureStdExtZve32x]>,
737738
RISCVExtensionBitmask<0, 52>;
738739
def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">,
739740
AssemblerPredicate<(all_of FeatureStdExtZvkb),
@@ -750,23 +751,26 @@ def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
750751

751752
def FeatureStdExtZvbc
752753
: RISCVExtension<"zvbc", 1, 0,
753-
"'Zvbc' (Vector Carryless Multiplication)">,
754+
"'Zvbc' (Vector Carryless Multiplication)",
755+
[FeatureStdExtZve64x]>,
754756
RISCVExtensionBitmask<0, 49>;
755757
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
756758
AssemblerPredicate<(all_of FeatureStdExtZvbc),
757759
"'Zvbc' (Vector Carryless Multiplication)">;
758760

759761
def FeatureStdExtZvbc32e
760762
: RISCVExperimentalExtension<"zvbc32e", 0, 7,
761-
"'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)">;
763+
"'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)",
764+
[FeatureStdExtZve32x]>;
762765

763766
def HasStdExtZvbcOrZvbc32e : Predicate<"Subtarget->hasStdExtZvbc() || Subtarget->hasStdExtZvbc32e()">,
764767
AssemblerPredicate<(any_of FeatureStdExtZvbc, FeatureStdExtZvbc32e),
765768
"'Zvbc' or 'Zvbc32e' (Vector Carryless Multiplication)">;
766769

767770
def FeatureStdExtZvkg
768771
: RISCVExtension<"zvkg", 1, 0,
769-
"'Zvkg' (Vector GCM instructions for Cryptography)">,
772+
"'Zvkg' (Vector GCM instructions for Cryptography)",
773+
[FeatureStdExtZve32x]>,
770774
RISCVExtensionBitmask<0, 53>;
771775
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
772776
AssemblerPredicate<(all_of FeatureStdExtZvkg),
@@ -782,23 +786,26 @@ def HasStdExtZvkgs : Predicate<"Subtarget->hasStdExtZvkgs()">,
782786

783787
def FeatureStdExtZvkned
784788
: RISCVExtension<"zvkned", 1, 0,
785-
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">,
789+
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
790+
[FeatureStdExtZve32x]>,
786791
RISCVExtensionBitmask<0, 54>;
787792
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
788793
AssemblerPredicate<(all_of FeatureStdExtZvkned),
789794
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
790795

791796
def FeatureStdExtZvknha
792797
: RISCVExtension<"zvknha", 1, 0,
793-
"'Zvknha' (Vector SHA-2 (SHA-256 only))">,
798+
"'Zvknha' (Vector SHA-2 (SHA-256 only))",
799+
[FeatureStdExtZve32x]>,
794800
RISCVExtensionBitmask<0, 55>;
795801
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
796802
AssemblerPredicate<(all_of FeatureStdExtZvknha),
797803
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
798804

799805
def FeatureStdExtZvknhb
800806
: RISCVExtension<"zvknhb", 1, 0,
801-
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">,
807+
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
808+
[FeatureStdExtZve64x]>,
802809
RISCVExtensionBitmask<0, 56>;
803810
def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">,
804811
AssemblerPredicate<(all_of FeatureStdExtZvknhb),
@@ -810,15 +817,17 @@ def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarg
810817

811818
def FeatureStdExtZvksed
812819
: RISCVExtension<"zvksed", 1, 0,
813-
"'Zvksed' (SM4 Block Cipher Instructions)">,
820+
"'Zvksed' (SM4 Block Cipher Instructions)",
821+
[FeatureStdExtZve32x]>,
814822
RISCVExtensionBitmask<0, 57>;
815823
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
816824
AssemblerPredicate<(all_of FeatureStdExtZvksed),
817825
"'Zvksed' (SM4 Block Cipher Instructions)">;
818826

819827
def FeatureStdExtZvksh
820828
: RISCVExtension<"zvksh", 1, 0,
821-
"'Zvksh' (SM3 Hash Function Instructions)">,
829+
"'Zvksh' (SM3 Hash Function Instructions)",
830+
[FeatureStdExtZve32x]>,
822831
RISCVExtensionBitmask<0, 58>;
823832
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
824833
AssemblerPredicate<(all_of FeatureStdExtZvksh),

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

+15-53
Original file line numberDiff line numberDiff line change
@@ -643,60 +643,22 @@ TEST(ParseArchString, MissingDepency) {
643643
"'zvl*b' requires 'v' or 'zve*' extension to also be specified");
644644
}
645645

646-
for (StringRef Input : {"rv32i_zvbb"}) {
646+
// These all have an implication relationship, thus should pass
647+
for (StringRef Input : {
648+
"rv32i_zvbb",
649+
"rv32i_zvbc32e0p7",
650+
"rv32i_zvbc",
651+
"rv32i_zvkb",
652+
"rv32i_zvkg",
653+
"rv32i_zvkgs0p7",
654+
"rv32i_zvkned",
655+
"rv32i_zvknha",
656+
"rv32i_zvksed",
657+
"rv32i_zvksh",
658+
"rv32i_zvknhb",
659+
}) {
647660
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
648-
"'zvbb' requires 'v' or 'zve*' extension to also be specified");
649-
}
650-
651-
for (StringRef Input : {"rv32i_zvbc32e0p7"}) {
652-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
653-
"'zvbc32e' requires 'v' or 'zve*' extension to also be specified");
654-
}
655-
656-
for (StringRef Input : {"rv32i_zvbc"}) {
657-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
658-
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
659-
}
660-
661-
for (StringRef Input : {"rv32i_zvkb"}) {
662-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
663-
"'zvkb' requires 'v' or 'zve*' extension to also be specified");
664-
}
665-
666-
for (StringRef Input : {"rv32i_zvkg"}) {
667-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
668-
"'zvkg' requires 'v' or 'zve*' extension to also be specified");
669-
}
670-
671-
for (StringRef Input : {"rv32i_zvkgs0p7"}) {
672-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
673-
"'zvkg' requires 'v' or 'zve*' extension to also be specified");
674-
}
675-
676-
for (StringRef Input : {"rv32i_zvkned"}) {
677-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
678-
"'zvkned' requires 'v' or 'zve*' extension to also be specified");
679-
}
680-
681-
for (StringRef Input : {"rv32i_zvknha"}) {
682-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
683-
"'zvknha' requires 'v' or 'zve*' extension to also be specified");
684-
}
685-
686-
for (StringRef Input : {"rv32i_zvksed"}) {
687-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
688-
"'zvksed' requires 'v' or 'zve*' extension to also be specified");
689-
}
690-
691-
for (StringRef Input : {"rv32i_zvksh"}) {
692-
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
693-
"'zvksh' requires 'v' or 'zve*' extension to also be specified");
694-
}
695-
696-
for (StringRef Input : {"rv32i_zvknhb"}) {
697-
EXPECT_EQ(
698-
toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
699-
"'zvknhb' requires 'v' or 'zve64*' extension to also be specified");
661+
"");
700662
}
701663

702664
for (StringRef Input : {"rv32i_zacas1p0"}) {

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