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[SCEV] Fix cache poisoning from depth-limited truncate expressions
Don't insert depth-limited unsimplified SCEVTruncateExpr into the UniqueSCEVs cache. Caching these prevents later queries at lower depth from properly simplifying (e.g., trunc(AddRec) -> AddRec). This fixes an assertion failure in IndVarSimplify where getTruncateExpr on an AddRecExpr returned a cached SCEVTruncateExpr instead of the expected SCEVAddRecExpr.
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lines changed

3 files changed

+232
-3
lines changed

‎llvm/lib/Analysis/ScalarEvolution.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1172,9 +1172,12 @@ const SCEV *ScalarEvolution::getTruncateExpr(const SCEV *Op, Type *Ty,
11721172
return getTruncateOrZeroExtend(SZ->getOperand(), Ty, Depth + 1);
11731173

11741174
if (Depth > MaxCastDepth) {
1175+
// Avoid caching depth-limited unsimplified results. Later queries at lower
1176+
// depth should be able to simplify (e.g., truncate of AddRec -> AddRec).
1177+
// Caching here would return this unsimplified SCEVTruncateExpr for future
1178+
// queries, preventing proper simplification.
11751179
SCEV *S =
11761180
new (SCEVAllocator) SCEVTruncateExpr(ID.Intern(SCEVAllocator), Op, Ty);
1177-
UniqueSCEVs.InsertNode(S, IP);
11781181
registerUser(S, Op);
11791182
return S;
11801183
}

‎llvm/lib/Transforms/Scalar/IndVarSimplify.cpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1033,8 +1033,11 @@ static Value *genLoopLimit(PHINode *IndVar, BasicBlock *ExitingBB,
10331033
SE->getTypeSizeInBits(AR->getType()) >
10341034
SE->getTypeSizeInBits(ExitCount->getType())) {
10351035
const SCEV *IVInit = AR->getStart();
1036-
if (!isa<SCEVConstant>(IVInit) || !isa<SCEVConstant>(ExitCount))
1037-
AR = cast<SCEVAddRecExpr>(SE->getTruncateExpr(AR, ExitCount->getType()));
1036+
if (!isa<SCEVConstant>(IVInit) || !isa<SCEVConstant>(ExitCount)) {
1037+
const SCEV *TruncExpr = SE->getTruncateExpr(AR, ExitCount->getType());
1038+
assert(isa<SCEVAddRecExpr>(TruncExpr) && "TruncateExpr should be an SCEVAddRecExpr");
1039+
AR = cast<SCEVAddRecExpr>(TruncExpr);
1040+
}
10381041
}
10391042

10401043
const SCEVAddRecExpr *ARBase = UsePostInc ? AR->getPostIncExpr(*SE) : AR;

‎llvm/test/Transforms/IndVarSimplify/scev-update-loop-opt.ll‎

Lines changed: 223 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,223 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
2+
; RUN: opt %s -passes="loop(loop-idiom,indvars,loop-deletion,loop-unroll-full)" -S | FileCheck %s
3+
; REQUIRES: asserts
4+
5+
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
6+
target triple = "x86_64-unknown-linux-gnu"
7+
8+
define void @_ZNK4Test29TestViewOperator_LeftAndRightIiN6Kokkos6SerialELj7EEclEmRi(i32 %conv5, i1 %cmp13, i1 %cmp20, i1 %cmp27, i1 %cmp34, i1 %cmp41) local_unnamed_addr {
9+
; CHECK-LABEL: define void @_ZNK4Test29TestViewOperator_LeftAndRightIiN6Kokkos6SerialELj7EEclEmRi(
10+
; CHECK-SAME: i32 [[CONV5:%.*]], i1 [[CMP13:%.*]], i1 [[CMP20:%.*]], i1 [[CMP27:%.*]], i1 [[CMP34:%.*]], i1 [[CMP41:%.*]]) local_unnamed_addr {
11+
; CHECK-NEXT: [[ENTRY:.*:]]
12+
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[CONV5]], 1
13+
; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
14+
; CHECK-NEXT: br label %[[FOR_COND:.*]]
15+
; CHECK: [[FOR_COND_LOOPEXIT:.*]]:
16+
; CHECK-NEXT: br label %[[FOR_COND]]
17+
; CHECK: [[FOR_COND]]:
18+
; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[CONV5]] to i64
19+
; CHECK-NEXT: br label %[[FOR_COND2:.*]]
20+
; CHECK: [[FOR_COND2]]:
21+
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_COND_CLEANUP14:.*]] ], [ 0, %[[FOR_COND]] ]
22+
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV]], [[TMP2]]
23+
; CHECK-NEXT: br i1 [[EXITCOND]], label %[[FOR_COND9_PREHEADER:.*]], label %[[FOR_COND_LOOPEXIT]]
24+
; CHECK: [[FOR_COND9_PREHEADER]]:
25+
; CHECK-NEXT: br label %[[FOR_COND9:.*]]
26+
; CHECK: [[FOR_COND9_LOOPEXIT:.*]]:
27+
; CHECK-NEXT: br label %[[FOR_COND9]]
28+
; CHECK: [[FOR_COND9]]:
29+
; CHECK-NEXT: br i1 [[CMP13]], label %[[FOR_COND16_PREHEADER:.*]], label %[[FOR_COND_CLEANUP14]]
30+
; CHECK: [[FOR_COND16_PREHEADER]]:
31+
; CHECK-NEXT: br label %[[FOR_COND16:.*]]
32+
; CHECK: [[FOR_COND_CLEANUP14]]:
33+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
34+
; CHECK-NEXT: br label %[[FOR_COND2]]
35+
; CHECK: [[FOR_COND16_LOOPEXIT:.*]]:
36+
; CHECK-NEXT: br label %[[FOR_COND16]]
37+
; CHECK: [[FOR_COND16]]:
38+
; CHECK-NEXT: br i1 [[CMP20]], label %[[FOR_COND23_PREHEADER:.*]], label %[[FOR_COND9_LOOPEXIT]]
39+
; CHECK: [[FOR_COND23_PREHEADER]]:
40+
; CHECK-NEXT: br label %[[FOR_COND23:.*]]
41+
; CHECK: [[FOR_COND23_LOOPEXIT:.*]]:
42+
; CHECK-NEXT: br label %[[FOR_COND23]]
43+
; CHECK: [[FOR_COND23]]:
44+
; CHECK-NEXT: br i1 [[CMP27]], label %[[FOR_COND30_PREHEADER:.*]], label %[[FOR_COND16_LOOPEXIT]]
45+
; CHECK: [[FOR_COND30_PREHEADER]]:
46+
; CHECK-NEXT: br label %[[FOR_COND30:.*]]
47+
; CHECK: [[FOR_COND30_LOOPEXIT_LOOPEXIT:.*]]:
48+
; CHECK-NEXT: br label %[[FOR_COND30_LOOPEXIT:.*]]
49+
; CHECK: [[FOR_COND30_LOOPEXIT]]:
50+
; CHECK-NEXT: br label %[[FOR_COND30]]
51+
; CHECK: [[FOR_COND30]]:
52+
; CHECK-NEXT: br i1 [[CMP34]], label %[[FOR_COND37_PREHEADER:.*]], label %[[FOR_COND23_LOOPEXIT]]
53+
; CHECK: [[FOR_COND37_PREHEADER]]:
54+
; CHECK-NEXT: br label %[[FOR_COND37_PEEL_BEGIN:.*]]
55+
; CHECK: [[FOR_COND37_PEEL_BEGIN]]:
56+
; CHECK-NEXT: br label %[[FOR_COND37_PEEL:.*]]
57+
; CHECK: [[FOR_COND37_PEEL]]:
58+
; CHECK-NEXT: br i1 [[CMP41]], label %[[FOR_BODY43_PEEL:.*]], label %[[FOR_COND30_LOOPEXIT]]
59+
; CHECK: [[FOR_BODY43_PEEL]]:
60+
; CHECK-NEXT: [[CONV45_PEEL:%.*]] = zext i32 0 to i64
61+
; CHECK-NEXT: [[CALL31_I_I_PEEL:%.*]] = load volatile i64, ptr null, align 8
62+
; CHECK-NEXT: [[MUL79_I_I_PEEL:%.*]] = mul i64 [[CALL31_I_I_PEEL]], [[INDVARS_IV]]
63+
; CHECK-NEXT: [[DOTIDX1_PEEL:%.*]] = add i64 [[CONV45_PEEL]], [[MUL79_I_I_PEEL]]
64+
; CHECK-NEXT: [[SUB_PTR_LHS_CAST_PEEL:%.*]] = shl i64 [[DOTIDX1_PEEL]], 2
65+
; CHECK-NEXT: [[SUB_PTR_DIV_PEEL:%.*]] = ashr exact i64 [[SUB_PTR_LHS_CAST_PEEL]], 1
66+
; CHECK-NEXT: [[CMP55_PEEL:%.*]] = icmp sgt i64 0, 0
67+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP55_PEEL]])
68+
; CHECK-NEXT: br label %[[FOR_COND37_PEEL_NEXT:.*]]
69+
; CHECK: [[FOR_COND37_PEEL_NEXT]]:
70+
; CHECK-NEXT: br label %[[FOR_COND37_PEEL_NEXT1:.*]]
71+
; CHECK: [[FOR_COND37_PEEL_NEXT1]]:
72+
; CHECK-NEXT: br label %[[FOR_COND37_PREHEADER_PEEL_NEWPH:.*]]
73+
; CHECK: [[FOR_COND37_PREHEADER_PEEL_NEWPH]]:
74+
; CHECK-NEXT: br label %[[FOR_COND37:.*]]
75+
; CHECK: [[FOR_COND37]]:
76+
; CHECK-NEXT: [[OFFSET_619:%.*]] = phi i64 [ [[SUB_PTR_DIV:%.*]], %[[FOR_BODY43:.*]] ], [ [[SUB_PTR_DIV_PEEL]], %[[FOR_COND37_PREHEADER_PEEL_NEWPH]] ]
77+
; CHECK-NEXT: br i1 [[CMP41]], label %[[FOR_BODY43]], label %[[FOR_COND30_LOOPEXIT_LOOPEXIT]]
78+
; CHECK: [[FOR_BODY43]]:
79+
; CHECK-NEXT: [[CALL31_I_I:%.*]] = load volatile i64, ptr null, align 8
80+
; CHECK-NEXT: [[ADD33_I_I:%.*]] = add i64 [[INDVARS_IV]], [[CALL31_I_I]]
81+
; CHECK-NEXT: [[MUL42_I_I:%.*]] = mul i64 [[TMP1]], [[ADD33_I_I]]
82+
; CHECK-NEXT: [[ADD43_I_I:%.*]] = add i64 [[MUL42_I_I]], 1
83+
; CHECK-NEXT: [[MUL52_I_I:%.*]] = mul i64 [[TMP1]], [[ADD43_I_I]]
84+
; CHECK-NEXT: [[ADD53_I_I:%.*]] = add i64 [[MUL52_I_I]], 1
85+
; CHECK-NEXT: [[MUL62_I_I:%.*]] = mul i64 [[TMP1]], [[ADD53_I_I]]
86+
; CHECK-NEXT: [[ADD63_I_I:%.*]] = add i64 [[MUL62_I_I]], 1
87+
; CHECK-NEXT: [[MUL72_I_I:%.*]] = mul i64 [[INDVARS_IV]], [[ADD63_I_I]]
88+
; CHECK-NEXT: [[MUL79_I_I:%.*]] = mul i64 [[CALL31_I_I]], [[MUL72_I_I]]
89+
; CHECK-NEXT: [[DOTIDX1:%.*]] = add i64 [[TMP1]], [[MUL79_I_I]]
90+
; CHECK-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = shl i64 [[DOTIDX1]], 2
91+
; CHECK-NEXT: [[SUB_PTR_DIV]] = ashr exact i64 [[SUB_PTR_LHS_CAST]], 1
92+
; CHECK-NEXT: [[CMP55:%.*]] = icmp sgt i64 [[OFFSET_619]], 0
93+
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP55]])
94+
; CHECK-NEXT: br label %[[FOR_COND37]], !llvm.loop [[LOOP0:![0-9]+]]
95+
;
96+
entry:
97+
br label %for.cond
98+
99+
for.cond: ; preds = %for.cond2, %entry
100+
br label %for.cond2
101+
102+
for.cond2: ; preds = %for.cond.cleanup14, %for.cond
103+
%i5.0 = phi i32 [ 0, %for.cond ], [ %inc70, %for.cond.cleanup14 ]
104+
%cmp6 = icmp ult i32 %i5.0, %conv5
105+
br i1 %cmp6, label %for.cond9, label %for.cond
106+
107+
for.cond9: ; preds = %for.cond16, %for.cond2
108+
br i1 %cmp13, label %for.cond16, label %for.cond.cleanup14
109+
110+
for.cond.cleanup14: ; preds = %for.cond9
111+
%inc70 = add i32 %i5.0, 1
112+
br label %for.cond2
113+
114+
for.cond16: ; preds = %for.cond23, %for.cond9
115+
br i1 %cmp20, label %for.cond23, label %for.cond9
116+
117+
for.cond23: ; preds = %for.cond30, %for.cond16
118+
br i1 %cmp27, label %for.cond30, label %for.cond16
119+
120+
for.cond30: ; preds = %for.cond37, %for.cond23
121+
br i1 %cmp34, label %for.cond37, label %for.cond23
122+
123+
for.cond37: ; preds = %for.body43, %for.cond30
124+
%i0.018 = phi i32 [ %inc, %for.body43 ], [ 0, %for.cond30 ]
125+
%offset.619 = phi i64 [ %sub.ptr.div, %for.body43 ], [ 0, %for.cond30 ]
126+
br i1 %cmp41, label %for.body43, label %for.cond30
127+
128+
for.body43: ; preds = %for.cond37
129+
%conv45 = zext i32 %i0.018 to i64
130+
%conv50 = zext i32 %i5.0 to i64
131+
%call31.i.i = load volatile i64, ptr null, align 8
132+
%add33.i.i = add i64 %conv50, %call31.i.i
133+
%mul42.i.i = mul i64 %conv45, %add33.i.i
134+
%add43.i.i = add i64 %mul42.i.i, 1
135+
%mul52.i.i = mul i64 %conv45, %add43.i.i
136+
%add53.i.i = add i64 %mul52.i.i, 1
137+
%mul62.i.i = mul i64 %conv45, %add53.i.i
138+
%add63.i.i = add i64 %mul62.i.i, 1
139+
%mul72.i.i = mul i64 %conv50, %add63.i.i
140+
%mul79.i.i = mul i64 %call31.i.i, %mul72.i.i
141+
%.idx1 = add i64 %conv45, %mul79.i.i
142+
%sub.ptr.lhs.cast = shl i64 %.idx1, 2
143+
%sub.ptr.div = ashr exact i64 %sub.ptr.lhs.cast, 1
144+
%cmp55 = icmp sgt i64 %offset.619, 0
145+
call void @llvm.assume(i1 %cmp55)
146+
%inc = add i32 %conv5, 1
147+
br label %for.cond37
148+
}
149+
150+
define ptr @_ZNK6Kokkos11DynRankViewIiJNS_10LayoutLeftENS_6SerialEEEclEmmmmmmm(i64 %i0, i64 %i5) local_unnamed_addr {
151+
; CHECK-LABEL: define ptr @_ZNK6Kokkos11DynRankViewIiJNS_10LayoutLeftENS_6SerialEEEclEmmmmmmm(
152+
; CHECK-SAME: i64 [[I0:%.*]], i64 [[I5:%.*]]) local_unnamed_addr {
153+
; CHECK-NEXT: [[ENTRY:.*:]]
154+
; CHECK-NEXT: [[CALL31_I:%.*]] = load volatile i64, ptr null, align 8
155+
; CHECK-NEXT: [[ADD33_I:%.*]] = add i64 [[I5]], [[CALL31_I]]
156+
; CHECK-NEXT: [[MUL42_I:%.*]] = mul i64 [[I0]], [[ADD33_I]]
157+
; CHECK-NEXT: [[ADD43_I:%.*]] = add i64 [[MUL42_I]], 1
158+
; CHECK-NEXT: [[MUL52_I:%.*]] = mul i64 [[I0]], [[ADD43_I]]
159+
; CHECK-NEXT: [[ADD53_I:%.*]] = add i64 [[MUL52_I]], 1
160+
; CHECK-NEXT: [[MUL62_I:%.*]] = mul i64 [[I0]], [[ADD53_I]]
161+
; CHECK-NEXT: [[ADD63_I:%.*]] = add i64 [[MUL62_I]], 1
162+
; CHECK-NEXT: [[MUL72_I:%.*]] = mul i64 [[I5]], [[ADD63_I]]
163+
; CHECK-NEXT: [[MUL79_I:%.*]] = mul i64 [[CALL31_I]], [[MUL72_I]]
164+
; CHECK-NEXT: [[ADD80_I:%.*]] = add i64 [[I0]], [[MUL79_I]]
165+
; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr i32, ptr null, i64 [[ADD80_I]]
166+
; CHECK-NEXT: ret ptr [[ARRAYIDX_I]]
167+
;
168+
entry:
169+
%call31.i = load volatile i64, ptr null, align 8
170+
%add33.i = add i64 %i5, %call31.i
171+
%mul42.i = mul i64 %i0, %add33.i
172+
%add43.i = add i64 %mul42.i, 1
173+
%mul52.i = mul i64 %i0, %add43.i
174+
%add53.i = add i64 %mul52.i, 1
175+
%mul62.i = mul i64 %i0, %add53.i
176+
%add63.i = add i64 %mul62.i, 1
177+
%mul72.i = mul i64 %i5, %add63.i
178+
%mul79.i = mul i64 %call31.i, %mul72.i
179+
%add80.i = add i64 %i0, %mul79.i
180+
%arrayidx.i = getelementptr i32, ptr null, i64 %add80.i
181+
ret ptr %arrayidx.i
182+
}
183+
184+
define i64 @_ZNK6Kokkos4ViewIPPPPPPPiJNS_10LayoutLeftENS_6SerialEEE14compute_offsetIJLm0ELm1ELm2ELm3ELm4ELm5ELm6EEJmmmmmmmEEEDaSt16integer_sequenceImJXspT_EEEDpT0_(i64 %index_offsets, i64 %index_offsets9) local_unnamed_addr {
185+
; CHECK-LABEL: define i64 @_ZNK6Kokkos4ViewIPPPPPPPiJNS_10LayoutLeftENS_6SerialEEE14compute_offsetIJLm0ELm1ELm2ELm3ELm4ELm5ELm6EEJmmmmmmmEEEDaSt16integer_sequenceImJXspT_EEEDpT0_(
186+
; CHECK-SAME: i64 [[INDEX_OFFSETS:%.*]], i64 [[INDEX_OFFSETS9:%.*]]) local_unnamed_addr {
187+
; CHECK-NEXT: [[ENTRY:.*:]]
188+
; CHECK-NEXT: [[CALL31:%.*]] = load volatile i64, ptr null, align 8
189+
; CHECK-NEXT: [[ADD33:%.*]] = add i64 [[INDEX_OFFSETS9]], [[CALL31]]
190+
; CHECK-NEXT: [[MUL42:%.*]] = mul i64 [[INDEX_OFFSETS]], [[ADD33]]
191+
; CHECK-NEXT: [[ADD43:%.*]] = add i64 [[MUL42]], 1
192+
; CHECK-NEXT: [[MUL52:%.*]] = mul i64 [[INDEX_OFFSETS]], [[ADD43]]
193+
; CHECK-NEXT: [[ADD53:%.*]] = add i64 [[MUL52]], 1
194+
; CHECK-NEXT: [[MUL62:%.*]] = mul i64 [[INDEX_OFFSETS]], [[ADD53]]
195+
; CHECK-NEXT: [[ADD63:%.*]] = add i64 [[MUL62]], 1
196+
; CHECK-NEXT: [[MUL72:%.*]] = mul i64 [[INDEX_OFFSETS9]], [[ADD63]]
197+
; CHECK-NEXT: [[MUL79:%.*]] = mul i64 [[CALL31]], [[MUL72]]
198+
; CHECK-NEXT: [[ADD80:%.*]] = add i64 [[INDEX_OFFSETS]], [[MUL79]]
199+
; CHECK-NEXT: ret i64 [[ADD80]]
200+
;
201+
entry:
202+
%call31 = load volatile i64, ptr null, align 8
203+
%add33 = add i64 %index_offsets9, %call31
204+
%mul42 = mul i64 %index_offsets, %add33
205+
%add43 = add i64 %mul42, 1
206+
%mul52 = mul i64 %index_offsets, %add43
207+
%add53 = add i64 %mul52, 1
208+
%mul62 = mul i64 %index_offsets, %add53
209+
%add63 = add i64 %mul62, 1
210+
%mul72 = mul i64 %index_offsets9, %add63
211+
%mul79 = mul i64 %call31, %mul72
212+
%add80 = add i64 %index_offsets, %mul79
213+
ret i64 %add80
214+
}
215+
216+
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write)
217+
declare void @llvm.assume(i1 noundef) #0
218+
219+
attributes #0 = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
220+
;.
221+
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
222+
; CHECK: [[META1]] = !{!"llvm.loop.peeled.count", i32 1}
223+
;.

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