!fixup relax cost only, restore test

Author: antoniofrighetto

llvm/lib/Transforms/Utils/SimplifyCFG.cpp

@@ -7225,6 +7225,12 @@ static bool simplifySwitchOfPowersOfTwo(SwitchInst *SI, IRBuilder<> &Builder,
   if (SI->getNumCases() < 4)
     return false;
 
+  // We perform this optimization only for switches with
+  // unreachable default case.
+  // This assumtion will save us from checking if `Condition` is a power of two.
+  if (!SI->defaultDestUnreachable())
+    return false;
+
   // Check that switch cases are powers of two.
   SmallVector<uint64_t, 4> Values;
   for (const auto &Case : SI->cases()) {

llvm/test/Transforms/SimplifyCFG/RISCV/switch-of-powers-of-two.ll

@@ -60,44 +60,30 @@ return:
   ret i32 %p
 }
 
-; Check that switch's of powers of two range is not reduced if default case is reachable,
-; unless Zbb extension is on.
+; Check that switch's of powers of two range is not reduced if default case is reachable
 define i32 @switch_of_powers_reachable_default(i32 %x) {
-; RV64I-LABEL: @switch_of_powers_reachable_default(
-; RV64I-NEXT:  entry:
-; RV64I-NEXT:    switch i32 [[X:%.*]], label [[RETURN:%.*]] [
-; RV64I-NEXT:      i32 1, label [[BB1:%.*]]
-; RV64I-NEXT:      i32 8, label [[BB2:%.*]]
-; RV64I-NEXT:      i32 16, label [[BB3:%.*]]
-; RV64I-NEXT:      i32 32, label [[BB4:%.*]]
-; RV64I-NEXT:      i32 64, label [[BB5:%.*]]
-; RV64I-NEXT:    ]
-; RV64I:       bb1:
-; RV64I-NEXT:    br label [[RETURN]]
-; RV64I:       bb2:
-; RV64I-NEXT:    br label [[RETURN]]
-; RV64I:       bb3:
-; RV64I-NEXT:    br label [[RETURN]]
-; RV64I:       bb4:
-; RV64I-NEXT:    br label [[RETURN]]
-; RV64I:       bb5:
-; RV64I-NEXT:    br label [[RETURN]]
-; RV64I:       return:
-; RV64I-NEXT:    [[P:%.*]] = phi i32 [ 3, [[BB1]] ], [ 2, [[BB2]] ], [ 1, [[BB3]] ], [ 0, [[BB4]] ], [ 42, [[BB5]] ], [ -1, [[ENTRY:%.*]] ]
-; RV64I-NEXT:    ret i32 [[P]]
-;
-; RV64ZBB-LABEL: @switch_of_powers_reachable_default(
-; RV64ZBB-NEXT:  entry:
-; RV64ZBB-NEXT:    [[TMP0:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true)
-; RV64ZBB-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[TMP0]], 7
-; RV64ZBB-NEXT:    br i1 [[TMP1]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
-; RV64ZBB:       switch.lookup:
-; RV64ZBB-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], ptr @switch.table.switch_of_powers_reachable_default, i32 0, i32 [[TMP0]]
-; RV64ZBB-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
-; RV64ZBB-NEXT:    br label [[RETURN]]
-; RV64ZBB:       return:
-; RV64ZBB-NEXT:    [[P:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ -1, [[ENTRY:%.*]] ]
-; RV64ZBB-NEXT:    ret i32 [[P]]
+; CHECK-LABEL: @switch_of_powers_reachable_default(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[X:%.*]], label [[RETURN:%.*]] [
+; CHECK-NEXT:      i32 1, label [[BB1:%.*]]
+; CHECK-NEXT:      i32 8, label [[BB2:%.*]]
+; CHECK-NEXT:      i32 16, label [[BB3:%.*]]
+; CHECK-NEXT:      i32 32, label [[BB4:%.*]]
+; CHECK-NEXT:      i32 64, label [[BB5:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       bb1:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       bb2:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       bb3:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       bb4:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       bb5:
+; CHECK-NEXT:    br label [[RETURN]]
+; CHECK:       return:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 3, [[BB1]] ], [ 2, [[BB2]] ], [ 1, [[BB3]] ], [ 0, [[BB4]] ], [ 42, [[BB5]] ], [ -1, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[P]]
 ;
 entry:
   switch i32 %x, label %default_case [