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[NFC] Update attributes for FP8 instructions using new target memory locations
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2 files changed

+67
-37
lines changed

2 files changed

+67
-37
lines changed

‎clang/test/CodeGen/AArch64/attr-fp8-function.c

Lines changed: 17 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -18,20 +18,29 @@ svfloat16_t test_svcvtlt2_f16_mf8(svmfloat8_t zn, fpm_t fpm) __arm_streaming {
1818
return svcvtlt2_f16_mf8_fpm(zn, fpm);
1919
}
2020

21-
// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR3:#.*]]
22-
// CHECK: declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) [[ATTR4:#.*]]
21+
// CHECK: declare void @llvm.aarch64.set.fpmr(i64) [[ATTR2:#.*]]
22+
// CHECK: declare <vscale x 8 x half> @llvm.aarch64.sve.fp8.cvtlt2.nxv8f16(<vscale x 16 x i8>) [[ATTR3:#.*]]
2323

2424

2525
// SME
26+
// With only fprm as inaccessible memory
2627
svfloat32_t test_svmlalltt_lane_f32_mf8(svfloat32_t zda, svmfloat8_t zn, svmfloat8_t zm, fpm_t fpm) __arm_streaming {
2728
return svmlalltt_lane_f32_mf8_fpm(zda, zn, zm, 7, fpm);
2829
}
2930

30-
// CHECK: declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) [[ATTR4]]
31+
// CHECK: declare <vscale x 4 x float> @llvm.aarch64.sve.fp8.fmlalltt.lane.nxv4f32(<vscale x 4 x float>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) [[ATTR3:#.*]]
3132

32-
// CHECK: declare <16 x i8> @llvm.aarch64.neon.fp8.fcvtn.v16i8.v8f16(<8 x half>, <8 x half>) [[ATTR4]]
33+
// With fpmr and za as incaccessible memory
34+
void test_svdot_lane_za32_f8_vg1x2(uint32_t slice, svmfloat8x2_t zn, svmfloat8_t zm, fpm_t fpmr) __arm_streaming __arm_inout("za") {
35+
svdot_lane_za32_mf8_vg1x2_fpm(slice, zn, zm, 3, fpmr);
36+
}
37+
38+
// CHECK: declare void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, i32 immarg) [[ATTR5:#.*]]
39+
// CHECK: declare <16 x i8> @llvm.aarch64.neon.fp8.fcvtn.v16i8.v8f16(<8 x half>, <8 x half>) [[ATTR3]]
3340

34-
// CHECK: attributes [[ATTR1:#.*]] = {{{.*}}}
35-
// CHECK: attributes [[ATTR2:#.*]] = {{{.*}}}
36-
// CHECK: attributes [[ATTR3]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: write) }
37-
// CHECK: attributes [[ATTR4]] = { nocallback nofree nosync nounwind willreturn memory(inaccessiblemem: read) }
41+
// CHECK: attributes [[ATTR0:#.*]] = {{{.*}}}
42+
// CHECK: attributes [[ATTR1:#.*]] = {{{.*}}}
43+
// CHECK: attributes [[ATTR2]] = { nocallback nofree nosync nounwind willreturn memory(aarch64_fpmr: write) }
44+
// CHECK: attributes [[ATTR3]] = { nocallback nofree nosync nounwind willreturn memory(aarch64_fpmr: read) }
45+
// CHECK: attributes [[ATTR4:#.*]] = {{{.*}}}
46+
// CHECK: attributes [[ATTR5:#.*]] = { nocallback nofree nosync nounwind willreturn memory(aarch64_fpmr: read, aarch64_za: readwrite) }

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 50 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -761,7 +761,7 @@ let TargetPrefix = "aarch64" in {
761761
class RNDR_Intrinsic
762762
: DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem, IntrHasSideEffects]>;
763763
class FPMR_Set_Intrinsic
764-
: DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrWriteMem, IntrInaccessibleMemOnly]>;
764+
: DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrInaccessibleWriteMemOnly<AArch64_FPMR>]>;
765765
}
766766

767767
// FP environment registers.
@@ -999,7 +999,7 @@ def int_aarch64_st64bv0: Intrinsic<[llvm_i64_ty], !listconcat([llvm_ptr_ty], dat
999999

10001000
// Conversions
10011001
class AdvSIMD_FP8_1VectorArg_Long_Intrinsic
1002-
: DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrReadMem, IntrInaccessibleMemOnly]>;
1002+
: DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
10031003

10041004
def int_aarch64_neon_fp8_cvtl1 : AdvSIMD_FP8_1VectorArg_Long_Intrinsic;
10051005
def int_aarch64_neon_fp8_cvtl2 : AdvSIMD_FP8_1VectorArg_Long_Intrinsic;
@@ -1008,28 +1008,28 @@ def int_aarch64_st64bv0: Intrinsic<[llvm_i64_ty], !listconcat([llvm_ptr_ty], dat
10081008
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
10091009
[llvm_anyvector_ty,
10101010
LLVMMatchType<1>],
1011-
[IntrReadMem, IntrInaccessibleMemOnly]>;
1011+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
10121012
def int_aarch64_neon_fp8_fcvtn2
10131013
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
10141014
[LLVMMatchType<0>,
10151015
llvm_anyvector_ty,
10161016
LLVMMatchType<1>],
1017-
[IntrReadMem, IntrInaccessibleMemOnly]>;
1017+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
10181018

10191019
// Dot-product
10201020
class AdvSIMD_FP8_DOT_Intrinsic
10211021
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
10221022
[LLVMMatchType<0>,
10231023
llvm_anyvector_ty,
10241024
LLVMMatchType<1>],
1025-
[IntrReadMem, IntrInaccessibleMemOnly]>;
1025+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
10261026
class AdvSIMD_FP8_DOT_LANE_Intrinsic
10271027
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
10281028
[LLVMMatchType<0>,
10291029
llvm_anyvector_ty,
10301030
llvm_v16i8_ty,
10311031
llvm_i32_ty],
1032-
[IntrReadMem, IntrInaccessibleMemOnly, ImmArg<ArgIndex<3>>]>;
1032+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, ImmArg<ArgIndex<3>>]>;
10331033

10341034
def int_aarch64_neon_fp8_fdot2 : AdvSIMD_FP8_DOT_Intrinsic;
10351035
def int_aarch64_neon_fp8_fdot2_lane : AdvSIMD_FP8_DOT_LANE_Intrinsic;
@@ -1044,15 +1044,15 @@ def int_aarch64_st64bv0: Intrinsic<[llvm_i64_ty], !listconcat([llvm_ptr_ty], dat
10441044
[LLVMMatchType<0>,
10451045
llvm_v16i8_ty,
10461046
llvm_v16i8_ty],
1047-
[IntrReadMem, IntrInaccessibleMemOnly]>;
1047+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
10481048

10491049
class AdvSIMD_FP8_FMLA_LANE_Intrinsic
10501050
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
10511051
[LLVMMatchType<0>,
10521052
llvm_v16i8_ty,
10531053
llvm_v16i8_ty,
10541054
llvm_i32_ty],
1055-
[IntrReadMem, IntrInaccessibleMemOnly, ImmArg<ArgIndex<3>>]>;
1055+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, ImmArg<ArgIndex<3>>]>;
10561056

10571057
def int_aarch64_neon_fp8_fmlalb : AdvSIMD_FP8_FMLA_Intrinsic;
10581058
def int_aarch64_neon_fp8_fmlalt : AdvSIMD_FP8_FMLA_Intrinsic;
@@ -3070,13 +3070,26 @@ let TargetPrefix = "aarch64" in {
30703070
llvm_anyvector_ty,
30713071
LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
30723072

3073+
class SME_FP8_OuterProduct_QuarterTile_Single_Single
3074+
: DefaultAttrsIntrinsic<[],
3075+
[llvm_i32_ty,
3076+
llvm_anyvector_ty,
3077+
LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>, IntrHasSideEffects]>;
3078+
30733079
class SME_OuterProduct_QuarterTile_Single_Multi
30743080
: DefaultAttrsIntrinsic<[],
30753081
[llvm_i32_ty,
30763082
llvm_anyvector_ty,
30773083
LLVMMatchType<0>,
30783084
LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
30793085

3086+
class SME_FP8_OuterProduct_QuarterTile_Single_Multi
3087+
: DefaultAttrsIntrinsic<[],
3088+
[llvm_i32_ty,
3089+
llvm_anyvector_ty,
3090+
LLVMMatchType<0>,
3091+
LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>, IntrHasSideEffects]>;
3092+
30803093
class SME_OuterProduct_QuarterTile_Multi_Multi
30813094
: DefaultAttrsIntrinsic<[],
30823095
[llvm_i32_ty,
@@ -3085,6 +3098,14 @@ let TargetPrefix = "aarch64" in {
30853098
LLVMMatchType<0>,
30863099
LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly, IntrHasSideEffects]>;
30873100

3101+
class SME_FP8_OuterProduct_QuarterTile_Multi_Multi
3102+
: DefaultAttrsIntrinsic<[],
3103+
[llvm_i32_ty,
3104+
llvm_anyvector_ty,
3105+
LLVMMatchType<0>,
3106+
LLVMMatchType<0>,
3107+
LLVMMatchType<0>], [ImmArg<ArgIndex<0>>, IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>, IntrHasSideEffects]>;
3108+
30883109
// 2-way and 4-way multi-vector signed/unsigned Quarter Tile Quarter Product A/S
30893110
foreach mode = ["s", "a"] in {
30903111
foreach za = ["", "_za64"] in {
@@ -3127,10 +3148,10 @@ let TargetPrefix = "aarch64" in {
31273148

31283149
// 16 and 32 bit multi-vector floating point 8 Quarter Tile Quarter Product
31293150
foreach za = ["za16", "za32"] in {
3130-
def int_aarch64_sme_fp8_fmop4a_ # za # "_1x1" : SME_OuterProduct_QuarterTile_Single_Single;
3131-
def int_aarch64_sme_fp8_fmop4a_ # za # "_1x2" : SME_OuterProduct_QuarterTile_Single_Multi;
3132-
def int_aarch64_sme_fp8_fmop4a_ # za # "_2x1" : SME_OuterProduct_QuarterTile_Single_Multi;
3133-
def int_aarch64_sme_fp8_fmop4a_ # za # "_2x2" : SME_OuterProduct_QuarterTile_Multi_Multi;
3151+
def int_aarch64_sme_fp8_fmop4a_ # za # "_1x1" : SME_FP8_OuterProduct_QuarterTile_Single_Single;
3152+
def int_aarch64_sme_fp8_fmop4a_ # za # "_1x2" : SME_FP8_OuterProduct_QuarterTile_Single_Multi;
3153+
def int_aarch64_sme_fp8_fmop4a_ # za # "_2x1" : SME_FP8_OuterProduct_QuarterTile_Single_Multi;
3154+
def int_aarch64_sme_fp8_fmop4a_ # za # "_2x2" : SME_FP8_OuterProduct_QuarterTile_Multi_Multi;
31343155
}
31353156

31363157
class SME_AddVectorToTile_Intrinsic
@@ -4027,7 +4048,7 @@ let TargetPrefix = "aarch64" in {
40274048
class SVE2_FP8_Cvt
40284049
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
40294050
[llvm_nxv16i8_ty],
4030-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4051+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
40314052

40324053
def int_aarch64_sve_fp8_cvt1 : SVE2_FP8_Cvt;
40334054
def int_aarch64_sve_fp8_cvt2 : SVE2_FP8_Cvt;
@@ -4038,28 +4059,28 @@ let TargetPrefix = "aarch64" in {
40384059
class SVE2_FP8_Narrow_Cvt
40394060
: DefaultAttrsIntrinsic<[llvm_nxv16i8_ty],
40404061
[llvm_anyvector_ty, LLVMMatchType<0>],
4041-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4062+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
40424063

40434064
def int_aarch64_sve_fp8_cvtn : SVE2_FP8_Narrow_Cvt;
40444065
def int_aarch64_sve_fp8_cvtnb : SVE2_FP8_Narrow_Cvt;
40454066

40464067
def int_aarch64_sve_fp8_cvtnt
40474068
: DefaultAttrsIntrinsic<[llvm_nxv16i8_ty],
40484069
[llvm_nxv16i8_ty, llvm_anyvector_ty, LLVMMatchType<0>],
4049-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4070+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
40504071

40514072
// Dot product
40524073
class SVE2_FP8_FMLA_FDOT
40534074
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
40544075
[LLVMMatchType<0>,
40554076
llvm_nxv16i8_ty, llvm_nxv16i8_ty],
4056-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4077+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
40574078

40584079
class SVE2_FP8_FMLA_FDOT_Lane
40594080
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
40604081
[LLVMMatchType<0>,
40614082
llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_i32_ty],
4062-
[IntrReadMem, IntrInaccessibleMemOnly, ImmArg<ArgIndex<3>>]>;
4083+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, ImmArg<ArgIndex<3>>]>;
40634084

40644085
def int_aarch64_sve_fp8_fdot : SVE2_FP8_FMLA_FDOT;
40654086
def int_aarch64_sve_fp8_fdot_lane : SVE2_FP8_FMLA_FDOT_Lane;
@@ -4086,69 +4107,69 @@ let TargetPrefix = "aarch64" in {
40864107
class SVE2_FP8_CVT_X2_Single_Intrinsic
40874108
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
40884109
[llvm_nxv16i8_ty],
4089-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4110+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
40904111

40914112
class SVE2_FP8_CVT_Single_X4_Intrinsic
40924113
: DefaultAttrsIntrinsic<[llvm_nxv16i8_ty],
40934114
[llvm_nxv4f32_ty, llvm_nxv4f32_ty, llvm_nxv4f32_ty, llvm_nxv4f32_ty],
4094-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4115+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
40954116

40964117
class SME_FP8_OuterProduct_Intrinsic
40974118
: DefaultAttrsIntrinsic<[],
40984119
[llvm_i32_ty,
40994120
llvm_nxv16i1_ty, llvm_nxv16i1_ty,
41004121
llvm_nxv16i8_ty, llvm_nxv16i8_ty],
4101-
[ImmArg<ArgIndex<0>>, IntrInaccessibleMemOnly]>;
4122+
[ImmArg<ArgIndex<0>>, IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>]>;
41024123

41034124
class SME_FP8_ZA_LANE_VGx1_Intrinsic
41044125
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41054126
llvm_nxv16i8_ty,
41064127
llvm_nxv16i8_ty,
41074128
llvm_i32_ty],
4108-
[IntrInaccessibleMemOnly, ImmArg<ArgIndex<3>>]>;
4129+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>, ImmArg<ArgIndex<3>>]>;
41094130

41104131
class SME_FP8_ZA_LANE_VGx2_Intrinsic
41114132
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41124133
llvm_nxv16i8_ty, llvm_nxv16i8_ty,
41134134
llvm_nxv16i8_ty,
41144135
llvm_i32_ty],
4115-
[IntrInaccessibleMemOnly, ImmArg<ArgIndex<4>>]>;
4136+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>, ImmArg<ArgIndex<4>>]>;
41164137

41174138
class SME_FP8_ZA_LANE_VGx4_Intrinsic
41184139
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41194140
llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty,
41204141
llvm_nxv16i8_ty,
41214142
llvm_i32_ty],
4122-
[IntrInaccessibleMemOnly, ImmArg<ArgIndex<6>>]>;
4143+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>, ImmArg<ArgIndex<6>>]>;
41234144
class SME_FP8_ZA_SINGLE_VGx1_Intrinsic
41244145
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41254146
llvm_nxv16i8_ty,
41264147
llvm_nxv16i8_ty],
4127-
[IntrInaccessibleMemOnly]>;
4148+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>]>;
41284149

41294150
class SME_FP8_ZA_SINGLE_VGx2_Intrinsic
41304151
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41314152
llvm_nxv16i8_ty, llvm_nxv16i8_ty,
41324153
llvm_nxv16i8_ty],
4133-
[IntrInaccessibleMemOnly]>;
4154+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>]>;
41344155

41354156
class SME_FP8_ZA_SINGLE_VGx4_Intrinsic
41364157
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41374158
llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty,
41384159
llvm_nxv16i8_ty],
4139-
[IntrInaccessibleMemOnly]>;
4160+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>]>;
41404161

41414162
class SME_FP8_ZA_MULTI_VGx2_Intrinsic
41424163
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41434164
llvm_nxv16i8_ty, llvm_nxv16i8_ty,
41444165
llvm_nxv16i8_ty, llvm_nxv16i8_ty],
4145-
[IntrInaccessibleMemOnly]>;
4166+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>]>;
41464167

41474168
class SME_FP8_ZA_MULTI_VGx4_Intrinsic
41484169
: DefaultAttrsIntrinsic<[], [llvm_i32_ty,
41494170
llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty,
41504171
llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty, llvm_nxv16i8_ty],
4151-
[IntrInaccessibleMemOnly]>;
4172+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>, IntrInaccessibleReadWriteMem<AArch64_ZA>]>;
41524173
//
41534174
// CVT from FP8 to half-precision/BFloat16 multi-vector
41544175
//
@@ -4167,7 +4188,7 @@ let TargetPrefix = "aarch64" in {
41674188
def int_aarch64_sve_fp8_cvt_x2
41684189
: DefaultAttrsIntrinsic<[llvm_nxv16i8_ty],
41694190
[llvm_anyvector_ty, LLVMMatchType<0>],
4170-
[IntrReadMem, IntrInaccessibleMemOnly]>;
4191+
[IntrInaccessibleReadMemOnly<AArch64_FPMR>]>;
41714192

41724193
def int_aarch64_sve_fp8_cvt_x4 : SVE2_FP8_CVT_Single_X4_Intrinsic;
41734194
def int_aarch64_sve_fp8_cvtn_x4 : SVE2_FP8_CVT_Single_X4_Intrinsic;

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