Apply some reviwer comment tidyups

Author: chrisjbris

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5942,7 +5942,6 @@ SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
 SDValue SITargetLowering::lowerROTR(SDValue Op, SelectionDAG &DAG) const {
   unsigned Opc = Op.getOpcode();
   EVT VT = Op.getValueType();
-  assert(Opc == ISD::ROTR && "Expected ROTR Opcode for lowerROTR.");
 
   assert((VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v8i32 ||
           VT == MVT::v16i32) &&

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -2379,7 +2379,6 @@ def : AMDGPUPat <
 let True16Predicate = NotHasTrue16BitInsts in {
 def : ROTRPattern <V_ALIGNBIT_B32_e64>;
 
-
 def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
           (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
                           (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;