Fix rotr regression by adding lowerRotr() on the legalizer codepath

Author: chrisjbris

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -5944,6 +5944,35 @@ SDValue SITargetLowering::splitUnaryVectorOp(SDValue Op,
   return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(Op), VT, OpLo, OpHi);
 }
 
+// Enable lowering of ROTR for vxi32 types.
+SDValue SITargetLowering::lowerROTR(SDValue Op,
+  SelectionDAG &DAG) const {
+    unsigned Opc = Op.getOpcode();
+    EVT VT = Op.getValueType();
+    assert(Opc == ISD::ROTR && "Expected ROTR Opcode for lowerROTR.");
+
+    assert((VT == MVT::v2i32 || VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32) &&
+           "Unexpected ValueType.");
+
+    unsigned VectorSize = VT.getVectorNumElements();
+    EVT ElementType = VT.getVectorElementType();
+    SDLoc SL(Op);
+    auto LHS = Op->getOperand(0);
+    auto RHS = Op->getOperand(1);
+
+    SmallVector<SDValue, 4> RotateTargets;
+    SmallVector<SDValue, 4> RotateSizes;
+    SmallVector<SDValue, 4> Ops;
+
+    DAG.ExtractVectorElements(LHS, RotateTargets, 0,VectorSize, ElementType);
+    DAG.ExtractVectorElements(RHS, RotateSizes, 0,VectorSize, ElementType);
+
+    for(unsigned i=0; i < VectorSize; i++)
+      Ops.push_back(DAG.getNode(ISD::ROTR, SL, ElementType, RotateTargets[i], RotateSizes[i], Op->getFlags()));
+
+    return DAG.getBuildVector(VT, SL, Ops);
+  }
+
 // Work around LegalizeDAG doing the wrong thing and fully scalarizing if the
 // wider vector type is legal.
 SDValue SITargetLowering::splitBinaryVectorOp(SDValue Op,
@@ -6130,6 +6159,8 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
     return lowerGET_FPENV(Op, DAG);
   case ISD::SET_FPENV:
     return lowerSET_FPENV(Op, DAG);
+  case ISD::ROTR:
+    return lowerROTR(Op, DAG);
   }
   return SDValue();
 }

llvm/lib/Target/AMDGPU/SIISelLowering.h

@@ -440,6 +440,7 @@ class SITargetLowering final : public AMDGPUTargetLowering {
   SDValue lowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerGET_FPENV(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSET_FPENV(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerROTR(SDValue Op, SelectionDAG &DAG) const;
 
   Register getRegisterByName(const char* RegName, LLT VT,
                              const MachineFunction &MF) const override;

llvm/test/CodeGen/AMDGPU/rotr.ll

@@ -121,29 +121,17 @@ define amdgpu_kernel void @rotr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[6:7]
 ; GFX10-NEXT:    s_endpgm
 ;
-; GFX11-TRUE16-LABEL: rotr_v2i32:
-; GFX11-TRUE16:       ; %bb.0: ; %entry
-; GFX11-TRUE16-NEXT:    s_clause 0x1
-; GFX11-TRUE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT:    v_alignbit_b32 v1, s1, s1, s2
-; GFX11-TRUE16-NEXT:    v_alignbit_b32 v0, s0, s0, s2
-; GFX11-TRUE16-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-TRUE16-NEXT:    s_endpgm
-;
-; GFX11-FAKE16-LABEL: rotr_v2i32:
-; GFX11-FAKE16:       ; %bb.0: ; %entry
-; GFX11-FAKE16-NEXT:    s_clause 0x1
-; GFX11-FAKE16-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c
-; GFX11-FAKE16-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v2, 0
-; GFX11-FAKE16-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, s1, s1, s3
-; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, s0, s0, s2
-; GFX11-FAKE16-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
-; GFX11-FAKE16-NEXT:    s_endpgm
+; GFX11-LABEL: rotr_v2i32:
+; GFX11:       ; %bb.0: ; %entry
+; GFX11-NEXT:    s_clause 0x1
+; GFX11-NEXT:    s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-NEXT:    s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT:    v_mov_b32_e32 v2, 0
+; GFX11-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX11-NEXT:    v_alignbit_b32 v1, s1, s1, s3
+; GFX11-NEXT:    v_alignbit_b32 v0, s0, s0, s2
+; GFX11-NEXT:    global_store_b64 v2, v[0:1], s[4:5]
+; GFX11-NEXT:    s_endpgm
 entry:
   %tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
   %tmp1 = shl <2 x i32> %x, %tmp0