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[DAG] isKnownNeverNaN - add DemandedElts element mask to isKnownNeverNaN calls (#135952)
Matches what we've done for computeKnownBits etc. to improve vector handling
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9 files changed

+101
-52
lines changed

9 files changed

+101
-52
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2142,11 +2142,25 @@ class SelectionDAG {
21422142
/// X|Cst == X+Cst iff X&Cst = 0.
21432143
bool isBaseWithConstantOffset(SDValue Op) const;
21442144

2145+
/// Test whether the given SDValue (or all elements of it, if it is a
2146+
/// vector) is known to never be NaN in \p DemandedElts. If \p SNaN is true,
2147+
/// returns if \p Op is known to never be a signaling NaN (it may still be a
2148+
/// qNaN).
2149+
bool isKnownNeverNaN(SDValue Op, const APInt &DemandedElts, bool SNaN = false,
2150+
unsigned Depth = 0) const;
2151+
21452152
/// Test whether the given SDValue (or all elements of it, if it is a
21462153
/// vector) is known to never be NaN. If \p SNaN is true, returns if \p Op is
21472154
/// known to never be a signaling NaN (it may still be a qNaN).
21482155
bool isKnownNeverNaN(SDValue Op, bool SNaN = false, unsigned Depth = 0) const;
21492156

2157+
/// \returns true if \p Op is known to never be a signaling NaN in \p
2158+
/// DemandedElts.
2159+
bool isKnownNeverSNaN(SDValue Op, const APInt &DemandedElts,
2160+
unsigned Depth = 0) const {
2161+
return isKnownNeverNaN(Op, DemandedElts, true, Depth);
2162+
}
2163+
21502164
/// \returns true if \p Op is known to never be a signaling NaN.
21512165
bool isKnownNeverSNaN(SDValue Op, unsigned Depth = 0) const {
21522166
return isKnownNeverNaN(Op, true, Depth);

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4283,6 +4283,7 @@ class TargetLowering : public TargetLoweringBase {
42834283
/// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
42844284
/// NaN.
42854285
virtual bool isKnownNeverNaNForTargetNode(SDValue Op,
4286+
const APInt &DemandedElts,
42864287
const SelectionDAG &DAG,
42874288
bool SNaN = false,
42884289
unsigned Depth = 0) const;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 59 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -5601,7 +5601,24 @@ bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
56015601
(Op.getOpcode() == ISD::ADD || isADDLike(Op));
56025602
}
56035603

5604-
bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const {
5604+
bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN,
5605+
unsigned Depth) const {
5606+
EVT VT = Op.getValueType();
5607+
5608+
// Since the number of lanes in a scalable vector is unknown at compile time,
5609+
// we track one bit which is implicitly broadcast to all lanes. This means
5610+
// that all lanes in a scalable vector are considered demanded.
5611+
APInt DemandedElts = VT.isFixedLengthVector()
5612+
? APInt::getAllOnes(VT.getVectorNumElements())
5613+
: APInt(1, 1);
5614+
5615+
return isKnownNeverNaN(Op, DemandedElts, SNaN, Depth);
5616+
}
5617+
5618+
bool SelectionDAG::isKnownNeverNaN(SDValue Op, const APInt &DemandedElts,
5619+
bool SNaN, unsigned Depth) const {
5620+
assert(!DemandedElts.isZero() && "No demanded elements");
5621+
56055622
// If we're told that NaNs won't happen, assume they won't.
56065623
if (getTarget().Options.NoNaNsFPMath || Op->getFlags().hasNoNaNs())
56075624
return true;
@@ -5657,21 +5674,21 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
56575674
case ISD::FLDEXP: {
56585675
if (SNaN)
56595676
return true;
5660-
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
5677+
return isKnownNeverNaN(Op.getOperand(0), DemandedElts, SNaN, Depth + 1);
56615678
}
56625679
case ISD::FABS:
56635680
case ISD::FNEG:
56645681
case ISD::FCOPYSIGN: {
5665-
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
5682+
return isKnownNeverNaN(Op.getOperand(0), DemandedElts, SNaN, Depth + 1);
56665683
}
56675684
case ISD::SELECT:
5668-
return isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1) &&
5669-
isKnownNeverNaN(Op.getOperand(2), SNaN, Depth + 1);
5685+
return isKnownNeverNaN(Op.getOperand(1), DemandedElts, SNaN, Depth + 1) &&
5686+
isKnownNeverNaN(Op.getOperand(2), DemandedElts, SNaN, Depth + 1);
56705687
case ISD::FP_EXTEND:
56715688
case ISD::FP_ROUND: {
56725689
if (SNaN)
56735690
return true;
5674-
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
5691+
return isKnownNeverNaN(Op.getOperand(0), DemandedElts, SNaN, Depth + 1);
56755692
}
56765693
case ISD::SINT_TO_FP:
56775694
case ISD::UINT_TO_FP:
@@ -5693,42 +5710,61 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, bool SNaN, unsigned Depth) const
56935710
case ISD::FMAXIMUMNUM: {
56945711
// Only one needs to be known not-nan, since it will be returned if the
56955712
// other ends up being one.
5696-
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) ||
5697-
isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
5713+
return isKnownNeverNaN(Op.getOperand(0), DemandedElts, SNaN, Depth + 1) ||
5714+
isKnownNeverNaN(Op.getOperand(1), DemandedElts, SNaN, Depth + 1);
56985715
}
56995716
case ISD::FMINNUM_IEEE:
57005717
case ISD::FMAXNUM_IEEE: {
57015718
if (SNaN)
57025719
return true;
57035720
// This can return a NaN if either operand is an sNaN, or if both operands
57045721
// are NaN.
5705-
return (isKnownNeverNaN(Op.getOperand(0), false, Depth + 1) &&
5706-
isKnownNeverSNaN(Op.getOperand(1), Depth + 1)) ||
5707-
(isKnownNeverNaN(Op.getOperand(1), false, Depth + 1) &&
5708-
isKnownNeverSNaN(Op.getOperand(0), Depth + 1));
5722+
return (isKnownNeverNaN(Op.getOperand(0), DemandedElts, false, Depth + 1) &&
5723+
isKnownNeverSNaN(Op.getOperand(1), DemandedElts, Depth + 1)) ||
5724+
(isKnownNeverNaN(Op.getOperand(1), DemandedElts, false, Depth + 1) &&
5725+
isKnownNeverSNaN(Op.getOperand(0), DemandedElts, Depth + 1));
57095726
}
57105727
case ISD::FMINIMUM:
57115728
case ISD::FMAXIMUM: {
57125729
// TODO: Does this quiet or return the origina NaN as-is?
5713-
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1) &&
5714-
isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
5730+
return isKnownNeverNaN(Op.getOperand(0), DemandedElts, SNaN, Depth + 1) &&
5731+
isKnownNeverNaN(Op.getOperand(1), DemandedElts, SNaN, Depth + 1);
5732+
}
5733+
case ISD::EXTRACT_VECTOR_ELT: {
5734+
SDValue Src = Op.getOperand(0);
5735+
auto *Idx = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5736+
EVT SrcVT = Src.getValueType();
5737+
if (SrcVT.isFixedLengthVector() && Idx &&
5738+
Idx->getAPIntValue().ult(SrcVT.getVectorNumElements())) {
5739+
APInt DemandedSrcElts = APInt::getOneBitSet(SrcVT.getVectorNumElements(),
5740+
Idx->getZExtValue());
5741+
return isKnownNeverNaN(Src, DemandedSrcElts, SNaN, Depth + 1);
5742+
}
5743+
return isKnownNeverNaN(Src, SNaN, Depth + 1);
57155744
}
5716-
case ISD::EXTRACT_VECTOR_ELT:
57175745
case ISD::EXTRACT_SUBVECTOR: {
5718-
return isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
5746+
SDValue Src = Op.getOperand(0);
5747+
if (Src.getValueType().isFixedLengthVector()) {
5748+
unsigned Idx = Op.getConstantOperandVal(1);
5749+
unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
5750+
APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
5751+
return isKnownNeverNaN(Src, DemandedSrcElts, SNaN, Depth + 1);
5752+
}
5753+
return isKnownNeverNaN(Src, SNaN, Depth + 1);
57195754
}
57205755
case ISD::BUILD_VECTOR: {
5721-
for (const SDValue &Opnd : Op->ops())
5722-
if (!isKnownNeverNaN(Opnd, SNaN, Depth + 1))
5756+
unsigned NumElts = Op.getNumOperands();
5757+
for (unsigned I = 0; I != NumElts; ++I)
5758+
if (DemandedElts[I] &&
5759+
!isKnownNeverNaN(Op.getOperand(I), SNaN, Depth + 1))
57235760
return false;
57245761
return true;
57255762
}
57265763
default:
5727-
if (Opcode >= ISD::BUILTIN_OP_END ||
5728-
Opcode == ISD::INTRINSIC_WO_CHAIN ||
5729-
Opcode == ISD::INTRINSIC_W_CHAIN ||
5730-
Opcode == ISD::INTRINSIC_VOID) {
5731-
return TLI->isKnownNeverNaNForTargetNode(Op, *this, SNaN, Depth);
5764+
if (Opcode >= ISD::BUILTIN_OP_END || Opcode == ISD::INTRINSIC_WO_CHAIN ||
5765+
Opcode == ISD::INTRINSIC_W_CHAIN || Opcode == ISD::INTRINSIC_VOID) {
5766+
return TLI->isKnownNeverNaNForTargetNode(Op, DemandedElts, *this, SNaN,
5767+
Depth);
57325768
}
57335769

57345770
return false;

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3928,6 +3928,7 @@ bool TargetLowering::canCreateUndefOrPoisonForTargetNode(
39283928
}
39293929

39303930
bool TargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
3931+
const APInt &DemandedElts,
39313932
const SelectionDAG &DAG,
39323933
bool SNaN,
39333934
unsigned Depth) const {

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5971,10 +5971,9 @@ unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
59715971
}
59725972
}
59735973

5974-
bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
5975-
const SelectionDAG &DAG,
5976-
bool SNaN,
5977-
unsigned Depth) const {
5974+
bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(
5975+
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool SNaN,
5976+
unsigned Depth) const {
59785977
unsigned Opcode = Op.getOpcode();
59795978
switch (Opcode) {
59805979
case AMDGPUISD::FMIN_LEGACY:

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -321,9 +321,8 @@ class AMDGPUTargetLowering : public TargetLowering {
321321
const MachineRegisterInfo &MRI,
322322
unsigned Depth = 0) const override;
323323

324-
bool isKnownNeverNaNForTargetNode(SDValue Op,
325-
const SelectionDAG &DAG,
326-
bool SNaN = false,
324+
bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
325+
const SelectionDAG &DAG, bool SNaN = false,
327326
unsigned Depth = 0) const override;
328327

329328
bool isReassocProfitable(MachineRegisterInfo &MRI, Register N0,

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16684,6 +16684,7 @@ bool SITargetLowering::denormalsEnabledForType(
1668416684
}
1668516685

1668616686
bool SITargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
16687+
const APInt &DemandedElts,
1668716688
const SelectionDAG &DAG,
1668816689
bool SNaN,
1668916690
unsigned Depth) const {
@@ -16696,8 +16697,8 @@ bool SITargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
1669616697
return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
1669716698
}
1669816699

16699-
return AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(Op, DAG, SNaN,
16700-
Depth);
16700+
return AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(Op, DemandedElts,
16701+
DAG, SNaN, Depth);
1670116702
}
1670216703

1670316704
// On older subtargets, global FP atomic instructions have a hardcoded FP mode

‎llvm/lib/Target/AMDGPU/SIISelLowering.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -546,9 +546,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
546546

547547
bool isProfitableToHoist(Instruction *I) const override;
548548

549-
bool isKnownNeverNaNForTargetNode(SDValue Op,
550-
const SelectionDAG &DAG,
551-
bool SNaN = false,
549+
bool isKnownNeverNaNForTargetNode(SDValue Op, const APInt &DemandedElts,
550+
const SelectionDAG &DAG, bool SNaN = false,
552551
unsigned Depth = 0) const override;
553552
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
554553
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override;

‎llvm/test/CodeGen/AMDGPU/mad-mix-lo.ll

Lines changed: 16 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1057,54 +1057,53 @@ define <3 x half> @v_mad_mix_v3f32_clamp_postcvt(<3 x half> %src0, <3 x half> %s
10571057
; SDAG-GFX1100-TRUE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
10581058
; SDAG-GFX1100-TRUE16: ; %bb.0:
10591059
; SDAG-GFX1100-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1060-
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
10611060
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
10621061
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
10631062
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
1064-
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
1065-
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
1066-
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
1067-
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1068-
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v2, v3, v5, v4 op_sel_hi:[1,1,1]
1069-
; SDAG-GFX1100-TRUE16-NEXT: v_pack_b32_f16 v1, v0.l, 0
1063+
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
1064+
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
1065+
; SDAG-GFX1100-TRUE16-NEXT: v_pack_b32_f16 v1, v1.l, 0
1066+
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixlo_f16 v3, v3, v5, v6 op_sel_hi:[1,1,1] clamp
10701067
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1071-
; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v0, v2, v2 clamp
10721068
; SDAG-GFX1100-TRUE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1069+
; SDAG-GFX1100-TRUE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
1070+
; SDAG-GFX1100-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
1071+
; SDAG-GFX1100-TRUE16-NEXT: v_mov_b32_e32 v0, v3
10731072
; SDAG-GFX1100-TRUE16-NEXT: s_setpc_b64 s[30:31]
10741073
;
10751074
; SDAG-GFX1100-FAKE16-LABEL: v_mad_mix_v3f32_clamp_postcvt:
10761075
; SDAG-GFX1100-FAKE16: ; %bb.0:
10771076
; SDAG-GFX1100-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1078-
; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
10791077
; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
1078+
; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
10801079
; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1081-
; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
10821080
; SDAG-GFX1100-FAKE16-NEXT: v_pack_b32_f16 v1, v1, 0
1081+
; SDAG-GFX1100-FAKE16-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
10831082
; SDAG-GFX1100-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
1084-
; SDAG-GFX1100-FAKE16-NEXT: v_pk_max_f16 v0, v6, v6 clamp
10851083
; SDAG-GFX1100-FAKE16-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1084+
; SDAG-GFX1100-FAKE16-NEXT: v_mov_b32_e32 v0, v3
10861085
; SDAG-GFX1100-FAKE16-NEXT: s_setpc_b64 s[30:31]
10871086
;
10881087
; SDAG-GFX900-LABEL: v_mad_mix_v3f32_clamp_postcvt:
10891088
; SDAG-GFX900: ; %bb.0:
10901089
; SDAG-GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1091-
; SDAG-GFX900-NEXT: v_mad_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
10921090
; SDAG-GFX900-NEXT: v_mad_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
1091+
; SDAG-GFX900-NEXT: v_mad_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
10931092
; SDAG-GFX900-NEXT: v_pack_b32_f16 v1, v1, 0
1094-
; SDAG-GFX900-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
1095-
; SDAG-GFX900-NEXT: v_pk_max_f16 v0, v6, v6 clamp
1093+
; SDAG-GFX900-NEXT: v_mad_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
10961094
; SDAG-GFX900-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1095+
; SDAG-GFX900-NEXT: v_mov_b32_e32 v0, v3
10971096
; SDAG-GFX900-NEXT: s_setpc_b64 s[30:31]
10981097
;
10991098
; SDAG-GFX906-LABEL: v_mad_mix_v3f32_clamp_postcvt:
11001099
; SDAG-GFX906: ; %bb.0:
11011100
; SDAG-GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1102-
; SDAG-GFX906-NEXT: v_fma_mixlo_f16 v6, v0, v2, v4 op_sel_hi:[1,1,1]
11031101
; SDAG-GFX906-NEXT: v_fma_mixlo_f16 v1, v1, v3, v5 op_sel_hi:[1,1,1]
1102+
; SDAG-GFX906-NEXT: v_fma_mixlo_f16 v3, v0, v2, v4 op_sel_hi:[1,1,1] clamp
11041103
; SDAG-GFX906-NEXT: v_pack_b32_f16 v1, v1, 0
1105-
; SDAG-GFX906-NEXT: v_fma_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]
1106-
; SDAG-GFX906-NEXT: v_pk_max_f16 v0, v6, v6 clamp
1104+
; SDAG-GFX906-NEXT: v_fma_mixhi_f16 v3, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp
11071105
; SDAG-GFX906-NEXT: v_pk_max_f16 v1, v1, v1 clamp
1106+
; SDAG-GFX906-NEXT: v_mov_b32_e32 v0, v3
11081107
; SDAG-GFX906-NEXT: s_setpc_b64 s[30:31]
11091108
;
11101109
; SDAG-VI-LABEL: v_mad_mix_v3f32_clamp_postcvt:

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