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davemgreendavemgreen
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[ARM] Add neon vector support for ceil
As per #142559, this marks fceil as legal for Neon and upgrades the existing arm.neon.vrintp intrinsics.
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8 files changed

+17
-61
lines changed

8 files changed

+17
-61
lines changed

‎clang/lib/CodeGen/TargetBuiltins/ARM.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -847,8 +847,8 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
847847
NEONMAP1(vrndmq_v, floor, Add1ArgType),
848848
NEONMAP1(vrndn_v, arm_neon_vrintn, Add1ArgType),
849849
NEONMAP1(vrndnq_v, arm_neon_vrintn, Add1ArgType),
850-
NEONMAP1(vrndp_v, arm_neon_vrintp, Add1ArgType),
851-
NEONMAP1(vrndpq_v, arm_neon_vrintp, Add1ArgType),
850+
NEONMAP1(vrndp_v, ceil, Add1ArgType),
851+
NEONMAP1(vrndpq_v, ceil, Add1ArgType),
852852
NEONMAP1(vrndq_v, arm_neon_vrintz, Add1ArgType),
853853
NEONMAP1(vrndx_v, arm_neon_vrintx, Add1ArgType),
854854
NEONMAP1(vrndxq_v, arm_neon_vrintx, Add1ArgType),

‎clang/test/CodeGen/arm-neon-directed-rounding.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -166,7 +166,7 @@ float32x4_t test_vrndnq_f32(float32x4_t a) {
166166
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
167167
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
168168
// CHECK-A32-NEXT: [[VRNDP_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
169-
// CHECK-A32-NEXT: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintp.v2f32(<2 x float> [[VRNDP_V_I]])
169+
// CHECK-A32-NEXT: [[VRNDP_V1_I:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[VRNDP_V_I]])
170170
// CHECK-A32-NEXT: [[VRNDP_V2_I:%.*]] = bitcast <2 x float> [[VRNDP_V1_I]] to <8 x i8>
171171
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDP_V2_I]] to <2 x i32>
172172
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
@@ -191,7 +191,7 @@ float32x2_t test_vrndp_f32(float32x2_t a) {
191191
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
192192
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
193193
// CHECK-A32-NEXT: [[VRNDPQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
194-
// CHECK-A32-NEXT: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintp.v4f32(<4 x float> [[VRNDPQ_V_I]])
194+
// CHECK-A32-NEXT: [[VRNDPQ_V1_I:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> [[VRNDPQ_V_I]])
195195
// CHECK-A32-NEXT: [[VRNDPQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDPQ_V1_I]] to <16 x i8>
196196
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDPQ_V2_I]] to <4 x i32>
197197
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>

‎clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -650,7 +650,7 @@ float16x8_t test_vrndnq_f16(float16x8_t a) {
650650
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
651651
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
652652
// CHECK-NEXT: [[VRNDP_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
653-
// CHECK-NEXT: [[VRNDP_V1_I:%.*]] = call <4 x half> @llvm.arm.neon.vrintp.v4f16(<4 x half> [[VRNDP_V_I]])
653+
// CHECK-NEXT: [[VRNDP_V1_I:%.*]] = call <4 x half> @llvm.ceil.v4f16(<4 x half> [[VRNDP_V_I]])
654654
// CHECK-NEXT: [[VRNDP_V2_I:%.*]] = bitcast <4 x half> [[VRNDP_V1_I]] to <8 x i8>
655655
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDP_V2_I]] to <4 x i16>
656656
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
@@ -666,7 +666,7 @@ float16x4_t test_vrndp_f16(float16x4_t a) {
666666
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
667667
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
668668
// CHECK-NEXT: [[VRNDPQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
669-
// CHECK-NEXT: [[VRNDPQ_V1_I:%.*]] = call <8 x half> @llvm.arm.neon.vrintp.v8f16(<8 x half> [[VRNDPQ_V_I]])
669+
// CHECK-NEXT: [[VRNDPQ_V1_I:%.*]] = call <8 x half> @llvm.ceil.v8f16(<8 x half> [[VRNDPQ_V_I]])
670670
// CHECK-NEXT: [[VRNDPQ_V2_I:%.*]] = bitcast <8 x half> [[VRNDPQ_V1_I]] to <16 x i8>
671671
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDPQ_V2_I]] to <8 x i16>
672672
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>

‎llvm/include/llvm/IR/IntrinsicsARM.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -681,7 +681,6 @@ def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
681681
def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
682682
def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
683683
def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
684-
def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
685684

686685
// De-interleaving vector loads from N-element structures.
687686
// Source operands are the address and alignment.

‎llvm/lib/IR/AutoUpgrade.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -719,8 +719,9 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
719719
.StartsWith("vqaddu.", Intrinsic::uadd_sat)
720720
.StartsWith("vqsubs.", Intrinsic::ssub_sat)
721721
.StartsWith("vqsubu.", Intrinsic::usub_sat)
722-
.StartsWith("vrintm.", Intrinsic::floor)
723722
.StartsWith("vrinta.", Intrinsic::round)
723+
.StartsWith("vrintm.", Intrinsic::floor)
724+
.StartsWith("vrintp.", Intrinsic::ceil)
724725
.Default(Intrinsic::not_intrinsic);
725726
if (ID != Intrinsic::not_intrinsic) {
726727
NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1548,6 +1548,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15481548
setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
15491549
setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
15501550
setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
1551+
setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
1552+
setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
15511553
}
15521554

15531555
if (Subtarget->hasFullFP16()) {
@@ -1565,6 +1567,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15651567
setOperationAction(ISD::FFLOOR, MVT::v8f16, Legal);
15661568
setOperationAction(ISD::FROUND, MVT::v4f16, Legal);
15671569
setOperationAction(ISD::FROUND, MVT::v8f16, Legal);
1570+
setOperationAction(ISD::FCEIL, MVT::v4f16, Legal);
1571+
setOperationAction(ISD::FCEIL, MVT::v8f16, Legal);
15681572
}
15691573
}
15701574

‎llvm/lib/Target/ARM/ARMInstrNEON.td

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7317,7 +7317,7 @@ defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
73177317
defm VRINTAN : VRINT_FPI<"a", 0b010, fround>;
73187318
defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
73197319
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
7320-
defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
7320+
defm VRINTPN : VRINT_FPI<"p", 0b111, fceil>;
73217321

73227322
// Cryptography instructions
73237323
let PostEncoderMethod = "NEONThumb2DataIPostEncoder",

‎llvm/test/CodeGen/ARM/vrint.ll

Lines changed: 4 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1451,21 +1451,7 @@ define <4 x half> @frintp_4h(<4 x half> %A) nounwind {
14511451
;
14521452
; CHECK-FP16-LABEL: frintp_4h:
14531453
; CHECK-FP16: @ %bb.0:
1454-
; CHECK-FP16-NEXT: vmovx.f16 s2, s0
1455-
; CHECK-FP16-NEXT: vrintp.f16 s2, s2
1456-
; CHECK-FP16-NEXT: vmov r0, s2
1457-
; CHECK-FP16-NEXT: vrintp.f16 s2, s0
1458-
; CHECK-FP16-NEXT: vmov r1, s2
1459-
; CHECK-FP16-NEXT: vrintp.f16 s2, s1
1460-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
1461-
; CHECK-FP16-NEXT: vrintp.f16 s0, s0
1462-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
1463-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
1464-
; CHECK-FP16-NEXT: vmov r0, s2
1465-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
1466-
; CHECK-FP16-NEXT: vmov r0, s0
1467-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
1468-
; CHECK-FP16-NEXT: vorr d0, d16, d16
1454+
; CHECK-FP16-NEXT: vrintp.f16 d0, d0
14691455
; CHECK-FP16-NEXT: bx lr
14701456
%tmp3 = call <4 x half> @llvm.ceil.v4f16(<4 x half> %A)
14711457
ret <4 x half> %tmp3
@@ -1615,35 +1601,7 @@ define <8 x half> @frintp_8h(<8 x half> %A) nounwind {
16151601
;
16161602
; CHECK-FP16-LABEL: frintp_8h:
16171603
; CHECK-FP16: @ %bb.0:
1618-
; CHECK-FP16-NEXT: vmovx.f16 s4, s2
1619-
; CHECK-FP16-NEXT: vrintp.f16 s4, s4
1620-
; CHECK-FP16-NEXT: vmov r0, s4
1621-
; CHECK-FP16-NEXT: vrintp.f16 s4, s2
1622-
; CHECK-FP16-NEXT: vmov r1, s4
1623-
; CHECK-FP16-NEXT: vrintp.f16 s4, s3
1624-
; CHECK-FP16-NEXT: vmov.16 d17[0], r1
1625-
; CHECK-FP16-NEXT: vmov.16 d17[1], r0
1626-
; CHECK-FP16-NEXT: vmov r0, s4
1627-
; CHECK-FP16-NEXT: vmovx.f16 s4, s3
1628-
; CHECK-FP16-NEXT: vrintp.f16 s4, s4
1629-
; CHECK-FP16-NEXT: vmov.16 d17[2], r0
1630-
; CHECK-FP16-NEXT: vmov r0, s4
1631-
; CHECK-FP16-NEXT: vmovx.f16 s4, s0
1632-
; CHECK-FP16-NEXT: vrintp.f16 s4, s4
1633-
; CHECK-FP16-NEXT: vmov.16 d17[3], r0
1634-
; CHECK-FP16-NEXT: vmov r0, s4
1635-
; CHECK-FP16-NEXT: vrintp.f16 s4, s0
1636-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
1637-
; CHECK-FP16-NEXT: vmov r1, s4
1638-
; CHECK-FP16-NEXT: vrintp.f16 s4, s1
1639-
; CHECK-FP16-NEXT: vrintp.f16 s0, s0
1640-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
1641-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
1642-
; CHECK-FP16-NEXT: vmov r0, s4
1643-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
1644-
; CHECK-FP16-NEXT: vmov r0, s0
1645-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
1646-
; CHECK-FP16-NEXT: vorr q0, q8, q8
1604+
; CHECK-FP16-NEXT: vrintp.f16 q0, q0
16471605
; CHECK-FP16-NEXT: bx lr
16481606
%tmp3 = call <8 x half> @llvm.ceil.v8f16(<8 x half> %A)
16491607
ret <8 x half> %tmp3
@@ -1669,9 +1627,7 @@ define <2 x float> @frintp_2s(<2 x float> %A) nounwind {
16691627
;
16701628
; CHECK-LABEL: frintp_2s:
16711629
; CHECK: @ %bb.0:
1672-
; CHECK-NEXT: vrintp.f32 s3, s1
1673-
; CHECK-NEXT: vrintp.f32 s2, s0
1674-
; CHECK-NEXT: vmov.f64 d0, d1
1630+
; CHECK-NEXT: vrintp.f32 d0, d0
16751631
; CHECK-NEXT: bx lr
16761632
%tmp3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A)
16771633
ret <2 x float> %tmp3
@@ -1703,11 +1659,7 @@ define <4 x float> @frintp_4s(<4 x float> %A) nounwind {
17031659
;
17041660
; CHECK-LABEL: frintp_4s:
17051661
; CHECK: @ %bb.0:
1706-
; CHECK-NEXT: vrintp.f32 s7, s3
1707-
; CHECK-NEXT: vrintp.f32 s6, s2
1708-
; CHECK-NEXT: vrintp.f32 s5, s1
1709-
; CHECK-NEXT: vrintp.f32 s4, s0
1710-
; CHECK-NEXT: vorr q0, q1, q1
1662+
; CHECK-NEXT: vrintp.f32 q0, q0
17111663
; CHECK-NEXT: bx lr
17121664
%tmp3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A)
17131665
ret <4 x float> %tmp3

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