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[AMDGPU][NPM] Add isRequired to passes missing it
1 parent fb8546e commit 4a28f68

16 files changed

+17
-1
lines changed

llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h

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@@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin<StructurizeCFGPass> {
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function_ref<StringRef(StringRef)> MapClassName2PassName);
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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static bool isRequired() { return true; }
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};
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} // namespace llvm
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llvm/include/llvm/Transforms/Utils/LoopSimplify.h

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@@ -54,6 +54,7 @@ class ScalarEvolution;
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class LoopSimplifyPass : public PassInfoMixin<LoopSimplifyPass> {
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public:
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LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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static bool isRequired() { return true; }
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};
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/// Simplify each loop in a loop nest recursively.

llvm/lib/Target/AMDGPU/AMDGPU.h

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@@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public PassInfoMixin<SILowerI1CopiesPass> {
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SILowerI1CopiesPass() = default;
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
@@ -365,6 +366,7 @@ class SIModeRegisterPass : public PassInfoMixin<SIModeRegisterPass> {
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public:
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SIModeRegisterPass() {}
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PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager &AM);
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static bool isRequired() { return true; }
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};
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class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
@@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass
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public:
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SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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static bool isRequired() { return true; }
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};
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void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);

llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h

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@@ -290,6 +290,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {

llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h

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@@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass
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: public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
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public:
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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static bool isRequired() { return true; }
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};
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} // end namespace llvm

llvm/lib/Target/AMDGPU/GCNNSAReassign.h

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@@ -16,6 +16,7 @@ class GCNNSAReassignPass : public PassInfoMixin<GCNNSAReassignPass> {
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public:
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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} // namespace llvm
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llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h

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@@ -17,6 +17,7 @@ class GCNPreRALongBranchRegPass
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public:
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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} // namespace llvm
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llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h

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@@ -17,6 +17,7 @@ class GCNRewritePartialRegUsesPass
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public:
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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} // namespace llvm
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llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h

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@@ -18,6 +18,7 @@ class SIFixSGPRCopiesPass : public PassInfoMixin<SIFixSGPRCopiesPass> {
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SIFixSGPRCopiesPass() = default;
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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} // namespace llvm

llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h

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@@ -16,6 +16,7 @@ class SIFixVGPRCopiesPass : public PassInfoMixin<SIFixVGPRCopiesPass> {
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public:
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PreservedAnalyses run(MachineFunction &MF,
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MachineFunctionAnalysisManager &MFAM);
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static bool isRequired() { return true; }
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};
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} // namespace llvm
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