Use custom for v2i32 rotr instead of additional patterns. Tidy up PerformOrCombine()

Author: chrisjbris

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -431,12 +431,12 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
   }
 
   setOperationAction({ISD::AND, ISD::OR, ISD::XOR}, MVT::v2i32, Legal);
-  // Prevent SELECT from being implemented with the above bitwise ops and
-  // instead use cndmask.
+  // Prevent SELECT v2i32 from being implemented with the above bitwise ops and
+  // instead lower to cndmask in SITargetLowering::LowerSELECT().
   setOperationAction(ISD::SELECT, MVT::v2i32, Custom);
   // Enable MatchRotate to produce ISD::ROTR, which is later transformed to
   // alignbit.
-  setOperationAction(ISD::ROTR, MVT::v2i32, Legal);
+  setOperationAction(ISD::ROTR, MVT::v2i32, Custom);
 
   setOperationAction(ISD::BUILD_VECTOR, {MVT::v4f16, MVT::v4i16, MVT::v4bf16},
                      Custom);
@@ -12893,11 +12893,6 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
   if (VT == MVT::v2i32) {
     if (LHS->getOpcode() == ISD::BUILD_VECTOR &&
         RHS->getOpcode() == ISD::BUILD_VECTOR) {
-      // DAG.canonicalizeCommutativeBinop(ISD::OR, RHS, LHS);
-      SDValue BVLHS = LHS->getOperand(0);
-      SDValue CLHS = LHS->getOperand(1);
-      SDValue CRHS = RHS->getOperand(0);
-      SDValue BVRHS = RHS->getOperand(1);
       LLVM_DEBUG(dbgs() << "### Performing v2i32 SIISelLowering "
                            "DAGCombine::CombineOR\n";);
 

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -2379,19 +2379,6 @@ def : AMDGPUPat <
 let True16Predicate = NotHasTrue16BitInsts in {
 def : ROTRPattern <V_ALIGNBIT_B32_e64>;
 
-def : AMDGPUPat <
-  (rotr v2i32:$src0, v2i32:$src1),
-  (REG_SEQUENCE VReg_64,
-    (V_ALIGNBIT_B32_e64
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      (i32 (EXTRACT_SUBREG VReg_64:$src1, sub0))), sub0,
-    (V_ALIGNBIT_B32_e64
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)),
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)), 
-      (i32 (EXTRACT_SUBREG VReg_64:$src1, sub1))), sub1)
->;
-
 // Prevents regression in fneg-modifier-casting.ll along with modifications to XorCombine() when v2i32 or is legal.
 def : AMDGPUPat <
   (fneg (select i1:$src0, (f32 (bitconvert i32:$src1)), (f32 (bitconvert i32:$src2)))),
@@ -2404,20 +2391,6 @@ def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
 def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
           (V_ALIGNBIT_B32_e64 (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
                           (i32 (EXTRACT_SUBREG (i64 $src0), sub0)), $src1)>;
-
-def : GCNPat <
-  (rotr v2i32:$src0, v2i32:$src1),
-  (REG_SEQUENCE VReg_64,
-    (V_ALIGNBIT_B32_e64
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      (i32 (EXTRACT_SUBREG VReg_64:$src1, sub0))), sub0,
-    (V_ALIGNBIT_B32_e64
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)),
-      (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)), 
-      (i32 (EXTRACT_SUBREG VReg_64:$src1, sub1))), sub1)
->;
-
 } // end True16Predicate = NotHasTrue16BitInsts
 
 let True16Predicate = UseRealTrue16Insts in {
@@ -2436,20 +2409,6 @@ def : GCNPat <
                           /* clamp */ 0, /* op_sel */ 0)
 >;
 
-def : GCNPat <
-  (rotr v2i32:$src0, v2i32:$src1),
-  (REG_SEQUENCE VReg_64,
-    (V_ALIGNBIT_B32_t16_e64
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      0, (EXTRACT_SUBREG (i32 (EXTRACT_SUBREG VReg_64:$src1, sub0)) ,lo16),0,0), sub0,
-    (V_ALIGNBIT_B32_t16_e64
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)),
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)), 
-      0, (EXTRACT_SUBREG (i32 (EXTRACT_SUBREG VReg_64:$src1, sub0)) ,lo16),0,0), sub1)
->;
-
-
 def : GCNPat<(i32 (trunc (srl i64:$src0, (i32 ShiftAmt32Imm:$src1)))),
           (V_ALIGNBIT_B32_t16_e64 0, /* src0_modifiers */
                           (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),
@@ -2476,20 +2435,6 @@ def : GCNPat <
                              $src1, /* clamp */ 0, /* op_sel */ 0)
 >;
 
-def : GCNPat <
-  (rotr v2i32:$src0, v2i32:$src1),
-  (REG_SEQUENCE VReg_64,
-    (V_ALIGNBIT_B32_fake16_e64
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub0)), 
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src1, sub0)),0,0), sub0,
-    (V_ALIGNBIT_B32_fake16_e64
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)),
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src0, sub1)), 
-      0, (i32 (EXTRACT_SUBREG VReg_64:$src1, sub1)),0,0), sub1)
->;
-
-
 def : GCNPat<(i32 (trunc (srl i64:$src0, (and i32:$src1, (i32 31))))),
      (V_ALIGNBIT_B32_fake16_e64 0, /* src0_modifiers */
                                (i32 (EXTRACT_SUBREG (i64 $src0), sub1)),