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Commit 25f6d5b

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fix wrong SNaN handling
1 parent 5d0919a commit 25f6d5b

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1 file changed

+120
-27
lines changed

1 file changed

+120
-27
lines changed

llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp

Lines changed: 120 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -886,8 +886,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
886886
case TargetOpcode::G_FMA:
887887
case TargetOpcode::G_STRICT_FMA:
888888
case TargetOpcode::G_FMAD: {
889-
Known.knownNot(fcSNan);
890-
891889
if ((InterestedClasses & fcNegative) == fcNone)
892890
break;
893891

@@ -923,8 +921,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
923921

924922
if (KnownSrc.isKnownNeverPosInfinity())
925923
Known.knownNot(fcPosInf);
926-
if (KnownSrc.isKnownNever(fcSNan))
927-
Known.knownNot(fcSNan);
928924

929925
// Any negative value besides -0 returns a nan.
930926
if (KnownSrc.isKnownNeverNaN() && KnownSrc.cannotBeOrderedLessThanZero())
@@ -947,6 +943,7 @@ void GISelValueTracking::computeKnownFPClass(Register R,
947943
}
948944
case TargetOpcode::G_FSIN:
949945
case TargetOpcode::G_FCOS:
946+
case TargetOpcode::G_FTAN:
950947
case TargetOpcode::G_FSINCOS: {
951948
// Return NaN on infinite inputs.
952949
Register Val = MI.getOperand(1).getReg();
@@ -955,7 +952,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
955952
computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,
956953
Depth + 1);
957954

958-
Known.knownNot(fcSNan);
959955
Known.knownNot(fcInf);
960956

961957
if (KnownSrc.isKnownNeverNaN() && KnownSrc.isKnownNeverInfinity())
@@ -980,8 +976,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
980976
Depth + 1);
981977

982978
bool NeverNaN = KnownLHS.isKnownNeverNaN() || KnownRHS.isKnownNeverNaN();
983-
bool NeverSNaN =
984-
KnownLHS.isKnownNever(fcSNan) || KnownRHS.isKnownNever(fcSNan);
985979
Known = KnownLHS | KnownRHS;
986980

987981
if (Opcode == TargetOpcode::G_FMAXNUM_IEEE ||
@@ -995,12 +989,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
995989
Opcode == TargetOpcode::G_FMAXIMUMNUM))
996990
Known.knownNot(fcNan);
997991

998-
if (NeverSNaN && (Opcode == TargetOpcode::G_FMINNUM ||
999-
Opcode == TargetOpcode::G_FMAXNUM ||
1000-
Opcode == TargetOpcode::G_FMINIMUMNUM ||
1001-
Opcode == TargetOpcode::G_FMAXIMUMNUM))
1002-
Known.knownNot(fcSNan);
1003-
1004992
if ((Opcode == TargetOpcode::G_FMAXNUM_IEEE ||
1005993
Opcode == TargetOpcode::G_FMINNUM_IEEE) &&
1006994
((KnownLHS.isKnownNeverNaN() && KnownRHS.isKnownNever(fcSNan)) ||
@@ -1197,6 +1185,8 @@ void GISelValueTracking::computeKnownFPClass(Register R,
11971185
if (KnownSrc.isKnownNeverNaN()) {
11981186
Known.knownNot(fcNan);
11991187
Known.signBitMustBeZero();
1188+
} else {
1189+
Known.knownNot(fcSNan);
12001190
}
12011191

12021192
break;
@@ -1308,8 +1298,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
13081298
Register RHS = MI.getOperand(2).getReg();
13091299
KnownFPClass KnownLHS, KnownRHS;
13101300

1311-
Known.knownNot(fcSNan);
1312-
13131301
bool WantNegative =
13141302
(Opcode == TargetOpcode::G_FADD ||
13151303
Opcode == TargetOpcode::G_STRICT_FADD) &&
@@ -1375,8 +1363,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
13751363
Register LHS = MI.getOperand(1).getReg();
13761364
Register RHS = MI.getOperand(2).getReg();
13771365

1378-
Known.knownNot(fcSNan);
1379-
13801366
// X * X is always non-negative or a NaN.
13811367
if (LHS == RHS)
13821368
Known.knownNot(fcNegative);
@@ -1423,7 +1409,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
14231409
case TargetOpcode::G_FREM: {
14241410
Register LHS = MI.getOperand(1).getReg();
14251411
Register RHS = MI.getOperand(2).getReg();
1426-
Known.knownNot(fcSNan);
14271412

14281413
if (LHS == RHS) {
14291414
// TODO: Could filter out snan if we inspect the operand
@@ -1710,16 +1695,124 @@ void GISelValueTracking::computeKnownFPClass(Register R,
17101695
computeKnownFPClass(Src, DemandedElts, InterestedClasses, Known, Depth + 1);
17111696
break;
17121697
}
1713-
case TargetOpcode::G_FTAN:
1714-
case TargetOpcode::G_FACOS:
1715-
case TargetOpcode::G_FASIN:
1716-
case TargetOpcode::G_FATAN:
1717-
case TargetOpcode::G_FATAN2:
1718-
case TargetOpcode::G_FCOSH:
1719-
case TargetOpcode::G_FSINH:
1698+
case TargetOpcode::G_FATAN: {
1699+
Register Val = MI.getOperand(1).getReg();
1700+
KnownFPClass KnownSrc;
1701+
1702+
computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,
1703+
Depth + 1);
1704+
1705+
if (KnownSrc.isKnownAlways(fcInf))
1706+
Known.KnownFPClasses = fcNan;
1707+
1708+
break;
1709+
}
1710+
case TargetOpcode::G_FATAN2: {
1711+
Register LHS = MI.getOperand(1).getReg();
1712+
Register RHS = MI.getOperand(2).getReg();
1713+
KnownFPClass KnownLHS;
1714+
KnownFPClass KnownRHS;
1715+
1716+
computeKnownFPClass(LHS, DemandedElts, InterestedClasses, KnownLHS,
1717+
Depth + 1);
1718+
1719+
computeKnownFPClass(RHS, DemandedElts, InterestedClasses, KnownRHS,
1720+
Depth + 1);
1721+
1722+
if (!KnownRHS.isKnownNeverNaN() || !KnownRHS.isKnownNeverNaN())
1723+
break;
1724+
1725+
if (KnownLHS.isKnownAlways(fcZero)) {
1726+
// atan2(+-0, −0) -> +-pi
1727+
// atan2(+-0, x) -> +-pi for x < 0
1728+
if (KnownRHS.isKnownAlways(fcNegFinite)) {
1729+
Known.KnownFPClasses = fcFinite;
1730+
break;
1731+
}
1732+
1733+
// atan2(+-0, +0) -> +-0
1734+
// atan2(+-0, x) -> +-0 for x > 0
1735+
if (KnownRHS.isKnownAlways(fcPosFinite)) {
1736+
Known.KnownFPClasses = fcZero;
1737+
break;
1738+
}
1739+
}
1740+
1741+
if (KnownRHS.isKnownAlways(fcZero)) {
1742+
// atan2(y, +-0) -> -pi/2 for y < 0
1743+
if (KnownLHS.isKnownNeverZero() && KnownLHS.isKnownAlways(fcNegFinite)) {
1744+
Known.KnownFPClasses = fcNegFinite;
1745+
break;
1746+
}
1747+
1748+
// atan2(y, +-0) -> +pi/2 for y > 0
1749+
if (KnownLHS.isKnownNeverZero() && KnownLHS.isKnownAlways(fcPosFinite)) {
1750+
Known.KnownFPClasses = fcPosFinite;
1751+
break;
1752+
}
1753+
}
1754+
1755+
if (KnownLHS.isKnownAlways(fcPosFinite) && KnownLHS.isKnownNeverZero()) {
1756+
// atan2(+-y, -inf) -> +-pi for finite y > 0
1757+
if (KnownRHS.isKnownAlways(fcNegInf)) {
1758+
Known.KnownFPClasses = fcFinite;
1759+
break;
1760+
}
1761+
1762+
// atan2(+-y, +inf) -> +-0 for finite y > 0
1763+
if (KnownRHS.isKnownAlways(fcPosInf)) {
1764+
Known.KnownFPClasses = fcZero;
1765+
break;
1766+
}
1767+
}
1768+
1769+
if (KnownLHS.isKnownAlways(fcInf)) {
1770+
// atan2(+-inf, x) -> +-pi/2 for finite x
1771+
// atan2(+-inf, -inf) -> +-3pi/4
1772+
// atan2(+-inf, +inf) -> +-pi/4
1773+
Known.KnownFPClasses = fcFinite;
1774+
break;
1775+
}
1776+
1777+
break;
1778+
}
1779+
case TargetOpcode::G_FCOSH: {
1780+
Register Val = MI.getOperand(1).getReg();
1781+
KnownFPClass KnownSrc;
1782+
1783+
computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,
1784+
Depth + 1);
1785+
1786+
// cosh(+-inf) -> +inf
1787+
if (KnownSrc.isKnownAlways(fcInf))
1788+
Known.KnownFPClasses = fcPosInf;
1789+
1790+
break;
1791+
}
1792+
case TargetOpcode::G_FSINH: {
1793+
Register Val = MI.getOperand(1).getReg();
1794+
KnownFPClass KnownSrc;
1795+
1796+
computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,
1797+
Depth + 1);
1798+
1799+
// sinh(±∞) is ±∞
1800+
if (KnownSrc.isKnownAlways(fcInf))
1801+
Known.KnownFPClasses = fcInf;
1802+
1803+
break;
1804+
}
17201805
case TargetOpcode::G_FTANH: {
1721-
Known.knownNot(fcSNan);
1722-
// TODO: ...
1806+
Register Val = MI.getOperand(1).getReg();
1807+
KnownFPClass KnownSrc;
1808+
1809+
computeKnownFPClass(Val, DemandedElts, InterestedClasses, KnownSrc,
1810+
Depth + 1);
1811+
1812+
// tanh(+-inf) is +-1
1813+
if (KnownSrc.isKnownAlways(fcInf))
1814+
Known.KnownFPClasses = fcFinite;
1815+
17231816
break;
17241817
}
17251818
}

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