@@ -886,8 +886,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
886
886
case TargetOpcode::G_FMA:
887
887
case TargetOpcode::G_STRICT_FMA:
888
888
case TargetOpcode::G_FMAD: {
889
- Known.knownNot (fcSNan);
890
-
891
889
if ((InterestedClasses & fcNegative) == fcNone)
892
890
break ;
893
891
@@ -923,8 +921,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
923
921
924
922
if (KnownSrc.isKnownNeverPosInfinity ())
925
923
Known.knownNot (fcPosInf);
926
- if (KnownSrc.isKnownNever (fcSNan))
927
- Known.knownNot (fcSNan);
928
924
929
925
// Any negative value besides -0 returns a nan.
930
926
if (KnownSrc.isKnownNeverNaN () && KnownSrc.cannotBeOrderedLessThanZero ())
@@ -947,6 +943,7 @@ void GISelValueTracking::computeKnownFPClass(Register R,
947
943
}
948
944
case TargetOpcode::G_FSIN:
949
945
case TargetOpcode::G_FCOS:
946
+ case TargetOpcode::G_FTAN:
950
947
case TargetOpcode::G_FSINCOS: {
951
948
// Return NaN on infinite inputs.
952
949
Register Val = MI.getOperand (1 ).getReg ();
@@ -955,7 +952,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
955
952
computeKnownFPClass (Val, DemandedElts, InterestedClasses, KnownSrc,
956
953
Depth + 1 );
957
954
958
- Known.knownNot (fcSNan);
959
955
Known.knownNot (fcInf);
960
956
961
957
if (KnownSrc.isKnownNeverNaN () && KnownSrc.isKnownNeverInfinity ())
@@ -980,8 +976,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
980
976
Depth + 1 );
981
977
982
978
bool NeverNaN = KnownLHS.isKnownNeverNaN () || KnownRHS.isKnownNeverNaN ();
983
- bool NeverSNaN =
984
- KnownLHS.isKnownNever (fcSNan) || KnownRHS.isKnownNever (fcSNan);
985
979
Known = KnownLHS | KnownRHS;
986
980
987
981
if (Opcode == TargetOpcode::G_FMAXNUM_IEEE ||
@@ -995,12 +989,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
995
989
Opcode == TargetOpcode::G_FMAXIMUMNUM))
996
990
Known.knownNot (fcNan);
997
991
998
- if (NeverSNaN && (Opcode == TargetOpcode::G_FMINNUM ||
999
- Opcode == TargetOpcode::G_FMAXNUM ||
1000
- Opcode == TargetOpcode::G_FMINIMUMNUM ||
1001
- Opcode == TargetOpcode::G_FMAXIMUMNUM))
1002
- Known.knownNot (fcSNan);
1003
-
1004
992
if ((Opcode == TargetOpcode::G_FMAXNUM_IEEE ||
1005
993
Opcode == TargetOpcode::G_FMINNUM_IEEE) &&
1006
994
((KnownLHS.isKnownNeverNaN () && KnownRHS.isKnownNever (fcSNan)) ||
@@ -1197,6 +1185,8 @@ void GISelValueTracking::computeKnownFPClass(Register R,
1197
1185
if (KnownSrc.isKnownNeverNaN ()) {
1198
1186
Known.knownNot (fcNan);
1199
1187
Known.signBitMustBeZero ();
1188
+ } else {
1189
+ Known.knownNot (fcSNan);
1200
1190
}
1201
1191
1202
1192
break ;
@@ -1308,8 +1298,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
1308
1298
Register RHS = MI.getOperand (2 ).getReg ();
1309
1299
KnownFPClass KnownLHS, KnownRHS;
1310
1300
1311
- Known.knownNot (fcSNan);
1312
-
1313
1301
bool WantNegative =
1314
1302
(Opcode == TargetOpcode::G_FADD ||
1315
1303
Opcode == TargetOpcode::G_STRICT_FADD) &&
@@ -1375,8 +1363,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
1375
1363
Register LHS = MI.getOperand (1 ).getReg ();
1376
1364
Register RHS = MI.getOperand (2 ).getReg ();
1377
1365
1378
- Known.knownNot (fcSNan);
1379
-
1380
1366
// X * X is always non-negative or a NaN.
1381
1367
if (LHS == RHS)
1382
1368
Known.knownNot (fcNegative);
@@ -1423,7 +1409,6 @@ void GISelValueTracking::computeKnownFPClass(Register R,
1423
1409
case TargetOpcode::G_FREM: {
1424
1410
Register LHS = MI.getOperand (1 ).getReg ();
1425
1411
Register RHS = MI.getOperand (2 ).getReg ();
1426
- Known.knownNot (fcSNan);
1427
1412
1428
1413
if (LHS == RHS) {
1429
1414
// TODO: Could filter out snan if we inspect the operand
@@ -1710,16 +1695,124 @@ void GISelValueTracking::computeKnownFPClass(Register R,
1710
1695
computeKnownFPClass (Src, DemandedElts, InterestedClasses, Known, Depth + 1 );
1711
1696
break ;
1712
1697
}
1713
- case TargetOpcode::G_FTAN:
1714
- case TargetOpcode::G_FACOS:
1715
- case TargetOpcode::G_FASIN:
1716
- case TargetOpcode::G_FATAN:
1717
- case TargetOpcode::G_FATAN2:
1718
- case TargetOpcode::G_FCOSH:
1719
- case TargetOpcode::G_FSINH:
1698
+ case TargetOpcode::G_FATAN: {
1699
+ Register Val = MI.getOperand (1 ).getReg ();
1700
+ KnownFPClass KnownSrc;
1701
+
1702
+ computeKnownFPClass (Val, DemandedElts, InterestedClasses, KnownSrc,
1703
+ Depth + 1 );
1704
+
1705
+ if (KnownSrc.isKnownAlways (fcInf))
1706
+ Known.KnownFPClasses = fcNan;
1707
+
1708
+ break ;
1709
+ }
1710
+ case TargetOpcode::G_FATAN2: {
1711
+ Register LHS = MI.getOperand (1 ).getReg ();
1712
+ Register RHS = MI.getOperand (2 ).getReg ();
1713
+ KnownFPClass KnownLHS;
1714
+ KnownFPClass KnownRHS;
1715
+
1716
+ computeKnownFPClass (LHS, DemandedElts, InterestedClasses, KnownLHS,
1717
+ Depth + 1 );
1718
+
1719
+ computeKnownFPClass (RHS, DemandedElts, InterestedClasses, KnownRHS,
1720
+ Depth + 1 );
1721
+
1722
+ if (!KnownRHS.isKnownNeverNaN () || !KnownRHS.isKnownNeverNaN ())
1723
+ break ;
1724
+
1725
+ if (KnownLHS.isKnownAlways (fcZero)) {
1726
+ // atan2(+-0, −0) -> +-pi
1727
+ // atan2(+-0, x) -> +-pi for x < 0
1728
+ if (KnownRHS.isKnownAlways (fcNegFinite)) {
1729
+ Known.KnownFPClasses = fcFinite;
1730
+ break ;
1731
+ }
1732
+
1733
+ // atan2(+-0, +0) -> +-0
1734
+ // atan2(+-0, x) -> +-0 for x > 0
1735
+ if (KnownRHS.isKnownAlways (fcPosFinite)) {
1736
+ Known.KnownFPClasses = fcZero;
1737
+ break ;
1738
+ }
1739
+ }
1740
+
1741
+ if (KnownRHS.isKnownAlways (fcZero)) {
1742
+ // atan2(y, +-0) -> -pi/2 for y < 0
1743
+ if (KnownLHS.isKnownNeverZero () && KnownLHS.isKnownAlways (fcNegFinite)) {
1744
+ Known.KnownFPClasses = fcNegFinite;
1745
+ break ;
1746
+ }
1747
+
1748
+ // atan2(y, +-0) -> +pi/2 for y > 0
1749
+ if (KnownLHS.isKnownNeverZero () && KnownLHS.isKnownAlways (fcPosFinite)) {
1750
+ Known.KnownFPClasses = fcPosFinite;
1751
+ break ;
1752
+ }
1753
+ }
1754
+
1755
+ if (KnownLHS.isKnownAlways (fcPosFinite) && KnownLHS.isKnownNeverZero ()) {
1756
+ // atan2(+-y, -inf) -> +-pi for finite y > 0
1757
+ if (KnownRHS.isKnownAlways (fcNegInf)) {
1758
+ Known.KnownFPClasses = fcFinite;
1759
+ break ;
1760
+ }
1761
+
1762
+ // atan2(+-y, +inf) -> +-0 for finite y > 0
1763
+ if (KnownRHS.isKnownAlways (fcPosInf)) {
1764
+ Known.KnownFPClasses = fcZero;
1765
+ break ;
1766
+ }
1767
+ }
1768
+
1769
+ if (KnownLHS.isKnownAlways (fcInf)) {
1770
+ // atan2(+-inf, x) -> +-pi/2 for finite x
1771
+ // atan2(+-inf, -inf) -> +-3pi/4
1772
+ // atan2(+-inf, +inf) -> +-pi/4
1773
+ Known.KnownFPClasses = fcFinite;
1774
+ break ;
1775
+ }
1776
+
1777
+ break ;
1778
+ }
1779
+ case TargetOpcode::G_FCOSH: {
1780
+ Register Val = MI.getOperand (1 ).getReg ();
1781
+ KnownFPClass KnownSrc;
1782
+
1783
+ computeKnownFPClass (Val, DemandedElts, InterestedClasses, KnownSrc,
1784
+ Depth + 1 );
1785
+
1786
+ // cosh(+-inf) -> +inf
1787
+ if (KnownSrc.isKnownAlways (fcInf))
1788
+ Known.KnownFPClasses = fcPosInf;
1789
+
1790
+ break ;
1791
+ }
1792
+ case TargetOpcode::G_FSINH: {
1793
+ Register Val = MI.getOperand (1 ).getReg ();
1794
+ KnownFPClass KnownSrc;
1795
+
1796
+ computeKnownFPClass (Val, DemandedElts, InterestedClasses, KnownSrc,
1797
+ Depth + 1 );
1798
+
1799
+ // sinh(±∞) is ±∞
1800
+ if (KnownSrc.isKnownAlways (fcInf))
1801
+ Known.KnownFPClasses = fcInf;
1802
+
1803
+ break ;
1804
+ }
1720
1805
case TargetOpcode::G_FTANH: {
1721
- Known.knownNot (fcSNan);
1722
- // TODO: ...
1806
+ Register Val = MI.getOperand (1 ).getReg ();
1807
+ KnownFPClass KnownSrc;
1808
+
1809
+ computeKnownFPClass (Val, DemandedElts, InterestedClasses, KnownSrc,
1810
+ Depth + 1 );
1811
+
1812
+ // tanh(+-inf) is +-1
1813
+ if (KnownSrc.isKnownAlways (fcInf))
1814
+ Known.KnownFPClasses = fcFinite;
1815
+
1723
1816
break ;
1724
1817
}
1725
1818
}
0 commit comments