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[RISCV] Narrow indices to e16 for LMUL > 1 when lowering vector_reverse (#104427)
The vector_shuffle lowering already does this to reduce register pressure, so also do it here.
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-36
lines changed

2 files changed

+59
-36
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10321,8 +10321,6 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
1032110321

1032210322
// If this is SEW=8 and VLMAX is potentially more than 256, we need
1032310323
// to use vrgatherei16.vv.
10324-
// TODO: It's also possible to use vrgatherei16.vv for other types to
10325-
// decrease register width for the index calculation.
1032610324
if (MaxVLMAX > 256 && EltSize == 8) {
1032710325
// If this is LMUL=8, we have to split before can use vrgatherei16.vv.
1032810326
// Reverse each half, then reassemble them in reverse order.
@@ -10348,6 +10346,15 @@ SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
1034810346
GatherOpc = RISCVISD::VRGATHEREI16_VV_VL;
1034910347
}
1035010348

10349+
// At LMUL > 1, do the index computation in 16 bits to reduce register
10350+
// pressure.
10351+
if (IntVT.getScalarType().bitsGT(MVT::i16) &&
10352+
IntVT.bitsGT(getLMUL1VT(IntVT))) {
10353+
assert(isUInt<16>(MaxVLMAX - 1)); // Largest VLMAX is 65536 @ zvl65536b
10354+
GatherOpc = RISCVISD::VRGATHEREI16_VV_VL;
10355+
IntVT = IntVT.changeVectorElementType(MVT::i16);
10356+
}
10357+
1035110358
MVT XLenVT = Subtarget.getXLenVT();
1035210359
auto [Mask, VL] = getDefaultScalableVLOps(VecVT, DL, DAG, Subtarget);
1035310360

‎llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

Lines changed: 50 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1285,10 +1285,11 @@ define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) {
12851285
; CHECK-NEXT: csrr a0, vlenb
12861286
; CHECK-NEXT: srli a0, a0, 1
12871287
; CHECK-NEXT: addi a0, a0, -1
1288-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1288+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
12891289
; CHECK-NEXT: vid.v v10
12901290
; CHECK-NEXT: vrsub.vx v12, v10, a0
1291-
; CHECK-NEXT: vrgather.vv v10, v8, v12
1291+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1292+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
12921293
; CHECK-NEXT: vmv.v.v v8, v10
12931294
; CHECK-NEXT: ret
12941295
%res = call <vscale x 4 x i32> @llvm.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
@@ -1300,10 +1301,11 @@ define <vscale x 8 x i32> @reverse_nxv8i32(<vscale x 8 x i32> %a) {
13001301
; CHECK: # %bb.0:
13011302
; CHECK-NEXT: csrr a0, vlenb
13021303
; CHECK-NEXT: addi a0, a0, -1
1303-
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1304+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
13041305
; CHECK-NEXT: vid.v v12
13051306
; CHECK-NEXT: vrsub.vx v16, v12, a0
1306-
; CHECK-NEXT: vrgather.vv v12, v8, v16
1307+
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1308+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
13071309
; CHECK-NEXT: vmv.v.v v8, v12
13081310
; CHECK-NEXT: ret
13091311
%res = call <vscale x 8 x i32> @llvm.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)
@@ -1316,10 +1318,11 @@ define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) {
13161318
; CHECK-NEXT: csrr a0, vlenb
13171319
; CHECK-NEXT: slli a0, a0, 1
13181320
; CHECK-NEXT: addi a0, a0, -1
1319-
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1321+
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
13201322
; CHECK-NEXT: vid.v v16
13211323
; CHECK-NEXT: vrsub.vx v24, v16, a0
1322-
; CHECK-NEXT: vrgather.vv v16, v8, v24
1324+
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
1325+
; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
13231326
; CHECK-NEXT: vmv.v.v v8, v16
13241327
; CHECK-NEXT: ret
13251328
%res = call <vscale x 16 x i32> @llvm.vector.reverse.nxv16i32(<vscale x 16 x i32> %a)
@@ -1348,10 +1351,11 @@ define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) {
13481351
; CHECK-NEXT: csrr a0, vlenb
13491352
; CHECK-NEXT: srli a0, a0, 2
13501353
; CHECK-NEXT: addi a0, a0, -1
1351-
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1354+
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
13521355
; CHECK-NEXT: vid.v v10
13531356
; CHECK-NEXT: vrsub.vx v12, v10, a0
1354-
; CHECK-NEXT: vrgather.vv v10, v8, v12
1357+
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1358+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
13551359
; CHECK-NEXT: vmv.v.v v8, v10
13561360
; CHECK-NEXT: ret
13571361
%res = call <vscale x 2 x i64> @llvm.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)
@@ -1364,10 +1368,11 @@ define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) {
13641368
; CHECK-NEXT: csrr a0, vlenb
13651369
; CHECK-NEXT: srli a0, a0, 1
13661370
; CHECK-NEXT: addi a0, a0, -1
1367-
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1371+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
13681372
; CHECK-NEXT: vid.v v12
13691373
; CHECK-NEXT: vrsub.vx v16, v12, a0
1370-
; CHECK-NEXT: vrgather.vv v12, v8, v16
1374+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1375+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
13711376
; CHECK-NEXT: vmv.v.v v8, v12
13721377
; CHECK-NEXT: ret
13731378
%res = call <vscale x 4 x i64> @llvm.vector.reverse.nxv4i64(<vscale x 4 x i64> %a)
@@ -1379,10 +1384,11 @@ define <vscale x 8 x i64> @reverse_nxv8i64(<vscale x 8 x i64> %a) {
13791384
; CHECK: # %bb.0:
13801385
; CHECK-NEXT: csrr a0, vlenb
13811386
; CHECK-NEXT: addi a0, a0, -1
1382-
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1387+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
13831388
; CHECK-NEXT: vid.v v16
13841389
; CHECK-NEXT: vrsub.vx v24, v16, a0
1385-
; CHECK-NEXT: vrgather.vv v16, v8, v24
1390+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1391+
; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
13861392
; CHECK-NEXT: vmv.v.v v8, v16
13871393
; CHECK-NEXT: ret
13881394
%res = call <vscale x 8 x i64> @llvm.vector.reverse.nxv8i64(<vscale x 8 x i64> %a)
@@ -1526,10 +1532,11 @@ define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) {
15261532
; CHECK-NEXT: csrr a0, vlenb
15271533
; CHECK-NEXT: srli a0, a0, 1
15281534
; CHECK-NEXT: addi a0, a0, -1
1529-
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1535+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
15301536
; CHECK-NEXT: vid.v v10
15311537
; CHECK-NEXT: vrsub.vx v12, v10, a0
1532-
; CHECK-NEXT: vrgather.vv v10, v8, v12
1538+
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1539+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
15331540
; CHECK-NEXT: vmv.v.v v8, v10
15341541
; CHECK-NEXT: ret
15351542
%res = call <vscale x 4 x float> @llvm.vector.reverse.nxv4f32(<vscale x 4 x float> %a)
@@ -1541,10 +1548,11 @@ define <vscale x 8 x float> @reverse_nxv8f32(<vscale x 8 x float> %a) {
15411548
; CHECK: # %bb.0:
15421549
; CHECK-NEXT: csrr a0, vlenb
15431550
; CHECK-NEXT: addi a0, a0, -1
1544-
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1551+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
15451552
; CHECK-NEXT: vid.v v12
15461553
; CHECK-NEXT: vrsub.vx v16, v12, a0
1547-
; CHECK-NEXT: vrgather.vv v12, v8, v16
1554+
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1555+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
15481556
; CHECK-NEXT: vmv.v.v v8, v12
15491557
; CHECK-NEXT: ret
15501558
%res = call <vscale x 8 x float> @llvm.vector.reverse.nxv8f32(<vscale x 8 x float> %a)
@@ -1557,10 +1565,11 @@ define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) {
15571565
; CHECK-NEXT: csrr a0, vlenb
15581566
; CHECK-NEXT: slli a0, a0, 1
15591567
; CHECK-NEXT: addi a0, a0, -1
1560-
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1568+
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
15611569
; CHECK-NEXT: vid.v v16
15621570
; CHECK-NEXT: vrsub.vx v24, v16, a0
1563-
; CHECK-NEXT: vrgather.vv v16, v8, v24
1571+
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
1572+
; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
15641573
; CHECK-NEXT: vmv.v.v v8, v16
15651574
; CHECK-NEXT: ret
15661575
%res = call <vscale x 16 x float> @llvm.vector.reverse.nxv16f32(<vscale x 16 x float> %a)
@@ -1589,10 +1598,11 @@ define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) {
15891598
; CHECK-NEXT: csrr a0, vlenb
15901599
; CHECK-NEXT: srli a0, a0, 2
15911600
; CHECK-NEXT: addi a0, a0, -1
1592-
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1601+
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
15931602
; CHECK-NEXT: vid.v v10
15941603
; CHECK-NEXT: vrsub.vx v12, v10, a0
1595-
; CHECK-NEXT: vrgather.vv v10, v8, v12
1604+
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1605+
; CHECK-NEXT: vrgatherei16.vv v10, v8, v12
15961606
; CHECK-NEXT: vmv.v.v v8, v10
15971607
; CHECK-NEXT: ret
15981608
%res = call <vscale x 2 x double> @llvm.vector.reverse.nxv2f64(<vscale x 2 x double> %a)
@@ -1605,10 +1615,11 @@ define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) {
16051615
; CHECK-NEXT: csrr a0, vlenb
16061616
; CHECK-NEXT: srli a0, a0, 1
16071617
; CHECK-NEXT: addi a0, a0, -1
1608-
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1618+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
16091619
; CHECK-NEXT: vid.v v12
16101620
; CHECK-NEXT: vrsub.vx v16, v12, a0
1611-
; CHECK-NEXT: vrgather.vv v12, v8, v16
1621+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1622+
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
16121623
; CHECK-NEXT: vmv.v.v v8, v12
16131624
; CHECK-NEXT: ret
16141625
%res = call <vscale x 4 x double> @llvm.vector.reverse.nxv4f64(<vscale x 4 x double> %a)
@@ -1620,10 +1631,11 @@ define <vscale x 8 x double> @reverse_nxv8f64(<vscale x 8 x double> %a) {
16201631
; CHECK: # %bb.0:
16211632
; CHECK-NEXT: csrr a0, vlenb
16221633
; CHECK-NEXT: addi a0, a0, -1
1623-
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1634+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
16241635
; CHECK-NEXT: vid.v v16
16251636
; CHECK-NEXT: vrsub.vx v24, v16, a0
1626-
; CHECK-NEXT: vrgather.vv v16, v8, v24
1637+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1638+
; CHECK-NEXT: vrgatherei16.vv v16, v8, v24
16271639
; CHECK-NEXT: vmv.v.v v8, v16
16281640
; CHECK-NEXT: ret
16291641
%res = call <vscale x 8 x double> @llvm.vector.reverse.nxv8f64(<vscale x 8 x double> %a)
@@ -1638,10 +1650,11 @@ define <vscale x 3 x i64> @reverse_nxv3i64(<vscale x 3 x i64> %a) {
16381650
; CHECK-NEXT: csrr a0, vlenb
16391651
; CHECK-NEXT: srli a0, a0, 1
16401652
; CHECK-NEXT: addi a0, a0, -1
1641-
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1653+
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
16421654
; CHECK-NEXT: vid.v v12
16431655
; CHECK-NEXT: vrsub.vx v12, v12, a0
1644-
; CHECK-NEXT: vrgather.vv v16, v8, v12
1656+
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1657+
; CHECK-NEXT: vrgatherei16.vv v16, v8, v12
16451658
; CHECK-NEXT: vmv1r.v v8, v17
16461659
; CHECK-NEXT: vmv1r.v v9, v18
16471660
; CHECK-NEXT: vmv1r.v v10, v19
@@ -1655,10 +1668,11 @@ define <vscale x 6 x i64> @reverse_nxv6i64(<vscale x 6 x i64> %a) {
16551668
; CHECK: # %bb.0:
16561669
; CHECK-NEXT: csrr a0, vlenb
16571670
; CHECK-NEXT: addi a0, a0, -1
1658-
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1671+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
16591672
; CHECK-NEXT: vid.v v16
16601673
; CHECK-NEXT: vrsub.vx v16, v16, a0
1661-
; CHECK-NEXT: vrgather.vv v24, v8, v16
1674+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1675+
; CHECK-NEXT: vrgatherei16.vv v24, v8, v16
16621676
; CHECK-NEXT: vmv2r.v v8, v26
16631677
; CHECK-NEXT: vmv2r.v v10, v28
16641678
; CHECK-NEXT: vmv2r.v v12, v30
@@ -1684,12 +1698,13 @@ define <vscale x 12 x i64> @reverse_nxv12i64(<vscale x 12 x i64> %a) {
16841698
; RV32-NEXT: andi sp, sp, -64
16851699
; RV32-NEXT: csrr a0, vlenb
16861700
; RV32-NEXT: addi a1, a0, -1
1687-
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
1701+
; RV32-NEXT: vsetvli a2, zero, e16, m2, ta, ma
16881702
; RV32-NEXT: vid.v v24
16891703
; RV32-NEXT: vrsub.vx v24, v24, a1
1690-
; RV32-NEXT: vrgather.vv v0, v16, v24
1704+
; RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1705+
; RV32-NEXT: vrgatherei16.vv v0, v16, v24
16911706
; RV32-NEXT: vmv4r.v v16, v4
1692-
; RV32-NEXT: vrgather.vv v0, v8, v24
1707+
; RV32-NEXT: vrgatherei16.vv v0, v8, v24
16931708
; RV32-NEXT: vmv4r.v v20, v0
16941709
; RV32-NEXT: slli a0, a0, 3
16951710
; RV32-NEXT: addi a1, sp, 64
@@ -1720,12 +1735,13 @@ define <vscale x 12 x i64> @reverse_nxv12i64(<vscale x 12 x i64> %a) {
17201735
; RV64-NEXT: andi sp, sp, -64
17211736
; RV64-NEXT: csrr a0, vlenb
17221737
; RV64-NEXT: addi a1, a0, -1
1723-
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
1738+
; RV64-NEXT: vsetvli a2, zero, e16, m2, ta, ma
17241739
; RV64-NEXT: vid.v v24
17251740
; RV64-NEXT: vrsub.vx v24, v24, a1
1726-
; RV64-NEXT: vrgather.vv v0, v16, v24
1741+
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1742+
; RV64-NEXT: vrgatherei16.vv v0, v16, v24
17271743
; RV64-NEXT: vmv4r.v v16, v4
1728-
; RV64-NEXT: vrgather.vv v0, v8, v24
1744+
; RV64-NEXT: vrgatherei16.vv v0, v8, v24
17291745
; RV64-NEXT: vmv4r.v v20, v0
17301746
; RV64-NEXT: slli a0, a0, 3
17311747
; RV64-NEXT: addi a1, sp, 64

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