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dts: microchip: pic64gx-curiosity-kit: add video capture pipeline
Add dts changes for microchip pic64gx-curiosity-kit for simple bus1, i2c and capture pipeline Signed-off-by: Shravan Chippa <[email protected]> [conor: various compliance cleanup] Signed-off-by: Conor Dooley <[email protected]>
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arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts

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@@ -99,6 +99,14 @@
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&mmc {
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bus-width = <4>;
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disable-wp;

arch/riscv/boot/dts/microchip/pic64gx.dtsi

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/dts-v1/;
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#include "dt-bindings/clock/microchip,mpfs-clock.h"
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#include <dt-bindings/media/microchip-common.h>
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/ {
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#address-cells = <2>;
@@ -203,6 +204,18 @@
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#clock-cells = <0>;
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};
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axiclk: axi-aclk0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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videoclk: video-aclk0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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syscontroller: syscontroller {
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compatible = "microchip,pic64gx-sys-controller";
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mboxes = <&mbox 0>;
@@ -619,5 +632,200 @@
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clocks = <&refclk>;
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#clock-cells = <1>;
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};
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bus1: bus@40000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
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<0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
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<0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
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<0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
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<0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */
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dma-ranges = <0x14 0x0 0x0 0x80000000 0x0 0x40000000>;
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/* Camera YUV422 pipeline */
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mchp_vdma_cam: video-pipeline@60000000 {
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compatible = "microchip,pic64gx-video-dma",
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"microchip,video-dma-rtl-v0";
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reg = <0x0 0x60000000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <118>;
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dma-noncoherent;
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clock-names = "axi", "video";
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clocks = <&axiclk>, <&videoclk>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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/* Sink port */
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reg = <0>;
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mchp_vdma_ep_cam: endpoint {
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remote-endpoint = <&rgbtoyuv422_out>;
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};
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};
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};
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};
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rgbtoyuv422: generic-video-pipeline-connector@60007000 {
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compatible = "microchip,pic64gx-generic-video-pipeline-connector",
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"microchip,generic-video-pipeline-connector";
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reg = <0x0 0x60007000 0x0 0x1000>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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microchip,video-format = <MVCF_RGB>;
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microchip,video-width = <8>;
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rgbtoyuv422_in: endpoint {
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remote-endpoint = <&rgb_scaler_out>;
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};
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};
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port@1 {
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reg = <1>;
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microchip,video-format = <MVCF_YUV_422>;
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microchip,video-width = <8>;
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rgbtoyuv422_out: endpoint {
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remote-endpoint = <&mchp_vdma_ep_cam>;
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};
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};
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};
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};
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rgb_scaler: rgb-scaler@60005000 {
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compatible = "microchip,pic64gx-rgb-scaler",
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"microchip,rgb-scaler-rtl-v1";
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reg = <0x0 0x60005000 0x0 0x1000>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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rgb_scaler_in: endpoint {
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remote-endpoint = <&image_enhancement_out>;
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};
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};
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port@1 {
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reg = <1>;
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rgb_scaler_out: endpoint {
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remote-endpoint = <&rgbtoyuv422_in>;
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};
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};
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};
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};
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image_enhancement: image-enhancement@60004000 {
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compatible = "microchip,pic64gx-image-enhancement",
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"microchip,image-enhancement-rtl-v1";
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reg = <0x0 0x60004000 0x0 0x1000>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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image_enhancement_in: endpoint {
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remote-endpoint = <&white_balance_out>;
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};
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};
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port@1 {
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reg = <1>;
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image_enhancement_out: endpoint {
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remote-endpoint = <&rgb_scaler_in>;
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};
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};
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};
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};
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white_balance: white-balance@60006000 {
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compatible = "microchip,pic64gx-white-balance",
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"microchip,white-balance-rtl-v1.1";
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reg = <0x0 0x6000b000 0x0 0x1000>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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white_balance_in: endpoint {
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remote-endpoint = <&mono_to_rgb_out>;
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};
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};
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port@1 {
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reg = <1>;
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white_balance_out: endpoint {
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remote-endpoint = <&image_enhancement_in>;
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};
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};
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};
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};
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mono_to_rgb: demosaic@60008000 {
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compatible = "microchip,pic64gx-bayer-interpolation",
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"microchip,bayer-interpolation-rtl-v4.8";
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reg = <0x0 0x60008000 0x0 0x1000>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mono_to_rgb_in: endpoint {
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remote-endpoint = <&csi2_out>;
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};
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};
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port@1 {
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reg = <1>;
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mono_to_rgb_out: endpoint {
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remote-endpoint = <&white_balance_in>;
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};
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};
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};
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};
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mcsi2rx: csi2rx@6001000 {
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compatible = "microchip,pic64gx-mipi-csi2-rx",
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"microchip,mipi-csi2-rx-rtl-v0";
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reg = <0x00 0x60001000 0x00 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <120>;
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microchip,csi-pxl-format = <0x2b>;
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microchip,csi-fixed-out-raw8;
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clock-names = "axi", "video";
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clocks = <&axiclk>, <&videoclk>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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csi2_out: endpoint {
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remote-endpoint = <&mono_to_rgb_in>;
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};
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};
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};
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};
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};
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};
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};

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