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cpu_threaded.c
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/* gameplaySP
*
* Copyright (C) 2006 Exophase <[email protected]>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Not-so-important todo:
// - stm reglist writeback when base is in the list needs adjustment
// - block memory needs psr swapping and user mode reg swapping
#include "common.h"
#if defined(VITA)
#include <psp2/kernel/sysmem.h>
#include <stdio.h>
#elif defined(PS2)
#include <kernel.h>
#endif
u8 *last_rom_translation_ptr = NULL;
u8 *last_ram_translation_ptr = NULL;
#if defined(MMAP_JIT_CACHE)
u8* rom_translation_cache;
u8* ram_translation_cache;
u8 *rom_translation_ptr;
u8 *ram_translation_ptr;
#elif defined(VITA)
u8* rom_translation_cache;
u8* ram_translation_cache;
u8 *rom_translation_ptr;
u8 *ram_translation_ptr;
int sceBlock;
#elif defined(_3DS)
u8* rom_translation_cache_ptr;
u8* ram_translation_cache_ptr;
u8 *rom_translation_ptr = rom_translation_cache;
u8 *ram_translation_ptr = ram_translation_cache;
#else
u8 *rom_translation_ptr = rom_translation_cache;
u8 *ram_translation_ptr = ram_translation_cache;
#endif
/* Note, see stub files for more cache definitions */
u32 iwram_code_min = ~0U;
u32 iwram_code_max = 0U;
u32 ewram_code_min = ~0U;
u32 ewram_code_max = 0U;
#define INITIAL_ROM_WATERMARK 16 // To avoid NULL aliasing
u32 rom_cache_watermark = INITIAL_ROM_WATERMARK;
u8 *bios_swi_entrypoint = NULL;
// Contains an offset table to rom_translation cache area
// It features a chaining linked list for collisions
// The rom area has a small header section that contains:
// - PC value for the entry
// - Offset to the next entry (if any)
typedef struct
{
u32 pc_value;
u32 next_entry;
} hashhdr_type;
u32 rom_branch_hash[ROM_BRANCH_HASH_SIZE];
typedef struct
{
u8 *block_offset;
u16 flag_data;
u8 condition;
u8 update_cycles;
} block_data_type;
typedef struct
{
u32 branch_target;
u8 *branch_source;
} block_exit_type;
// Div (6) and DivArm (7)
#define is_div_swi(swinum) (((swinum) & 0xFE) == 0x06)
#define arm_decode_data_proc_reg(opcode) \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_data_proc_imm(opcode) \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 imm = opcode & 0xFF; \
u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \
#define arm_decode_psr_reg(opcode) \
u32 psr_pfield = ((opcode >> 16) & 1) | ((opcode >> 18) & 2); \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_psr_imm(opcode) \
u32 psr_pfield = ((opcode >> 16) & 1) | ((opcode >> 18) & 2); \
u32 rd = (opcode >> 12) & 0x0F; \
u32 imm = opcode & 0xFF; \
u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \
#define arm_decode_branchx(opcode) \
u32 rn = opcode & 0x0F \
#define arm_decode_multiply() \
u32 rd = (opcode >> 16) & 0x0F; \
u32 rn = (opcode >> 12) & 0x0F; \
u32 rs = (opcode >> 8) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_multiply_long() \
u32 rdhi = (opcode >> 16) & 0x0F; \
u32 rdlo = (opcode >> 12) & 0x0F; \
u32 rs = (opcode >> 8) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_swap() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_half_trans_r() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_half_trans_of() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F) \
#define arm_decode_data_trans_imm() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 offset = opcode & 0x0FFF \
#define arm_decode_data_trans_reg() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_block_trans() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 reg_list = opcode & 0xFFFF \
#define arm_decode_branch() \
s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \
#define thumb_decode_shift() \
u32 imm = (opcode >> 6) & 0x1F; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_add_sub() \
u32 rn = (opcode >> 6) & 0x07; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_add_sub_imm() \
u32 imm = (opcode >> 6) & 0x07; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_imm() \
u32 imm = opcode & 0xFF \
#define thumb_decode_alu_op() \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_hireg_op() \
u32 rs = (opcode >> 3) & 0x0F; \
u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07) \
#define thumb_decode_mem_reg() \
u32 ro = (opcode >> 6) & 0x07; \
u32 rb = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_mem_imm() \
u32 imm = (opcode >> 6) & 0x1F; \
u32 rb = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_add_sp() \
u32 imm = opcode & 0x7F \
#define thumb_decode_rlist() \
u32 reg_list = opcode & 0xFF \
#define thumb_decode_branch_cond() \
s32 offset = (s8)(opcode & 0xFF) \
#define thumb_decode_branch() \
u32 offset = opcode & 0x07FF \
/* Include the right emitter headers */
#if defined(MIPS_ARCH)
#include "mips/mips_emit.h"
#elif defined(ARM_ARCH)
#include "arm/arm_emit.h"
#elif defined(ARM64_ARCH)
#include "arm/arm64_emit.h"
#else
#include "x86/x86_emit.h"
#endif
/* Cache invalidation */
#if defined(PSP)
void platform_cache_sync(void *baseaddr, void *endptr) {
sceKernelDcacheWritebackRange(baseaddr, ((char*)endptr) - ((char*)baseaddr));
sceKernelIcacheInvalidateRange(baseaddr, ((char*)endptr) - ((char*)baseaddr));
}
#elif defined(PS2)
void platform_cache_sync(void *baseaddr, void *endptr) {
FlushCache(0); // Dcache flush
FlushCache(2); // Icache invalidate
}
#elif defined(VITA)
void platform_cache_sync(void *baseaddr, void *endptr) {
sceKernelSyncVMDomain(sceBlock, baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
}
#elif defined(_3DS)
#include "3ds/3ds_utils.h"
void platform_cache_sync(void *baseaddr, void *endptr) {
ctr_flush_invalidate_cache();
}
#elif defined(ARM_ARCH) || defined(ARM64_ARCH)
void platform_cache_sync(void *baseaddr, void *endptr) {
__clear_cache(baseaddr, endptr);
}
#elif defined(MIPS_ARCH)
void platform_cache_sync(void *baseaddr, void *endptr) {
__builtin___clear_cache(baseaddr, endptr);
}
#else
/* x86 CPUs have icache consistency checks */
void platform_cache_sync(void *baseaddr, void *endptr) {}
#endif
void translate_icache_sync() {
// Cache emitted code can only grow
if (last_rom_translation_ptr < rom_translation_ptr) {
platform_cache_sync(last_rom_translation_ptr, rom_translation_ptr);
last_rom_translation_ptr = rom_translation_ptr;
}
if (last_ram_translation_ptr < ram_translation_ptr) {
platform_cache_sync(last_ram_translation_ptr, ram_translation_ptr);
last_ram_translation_ptr = ram_translation_ptr;
}
}
/* End of Cache invalidation */
#define check_pc_region(pc) \
new_pc_region = (pc >> 15); \
if(new_pc_region != pc_region) \
{ \
pc_region = new_pc_region; \
pc_address_block = memory_map_read[new_pc_region]; \
\
if(!pc_address_block) \
pc_address_block = load_gamepak_page(pc_region & 0x3FF); \
} \
#define translate_arm_instruction() \
check_pc_region(pc); \
opcode = address32(pc_address_block, (pc & 0x7FFF)); \
condition = block_data[block_data_position].condition; \
\
if((condition != last_condition) || (condition >= 0x20)) \
{ \
if((last_condition & 0x0F) != 0x0E) \
{ \
generate_branch_patch_conditional(backpatch_address, translation_ptr); \
} \
\
last_condition = condition; \
\
condition &= 0x0F; \
\
if(condition != 0x0E) \
{ \
arm_conditional_block_header(); \
} \
} \
emit_trace_arm_instruction(pc); \
\
switch((opcode >> 20) & 0xFF) \
{ \
case 0x00: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], -rm */ \
arm_access_memory(store, down, post, u16, half_reg); \
} \
else \
{ \
/* MUL rd, rm, rs */ \
arm_multiply(no, no); \
cycle_count += 2; /* variable 1..4, pick 2 as an aprox. */ \
} \
} \
else \
{ \
/* AND rd, rn, reg_op */ \
arm_data_proc(and, reg, no_flags); \
} \
break; \
\
case 0x01: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* MULS rd, rm, rs */ \
arm_multiply(no, yes); \
cycle_count += 2; /* variable 1..4, pick 2 as an aprox. */ \
break; \
\
case 1: \
/* LDRH rd, [rn], -rm */ \
arm_access_memory(load, down, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -rm */ \
arm_access_memory(load, down, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -rm */ \
arm_access_memory(load, down, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ANDS rd, rn, reg_op */ \
arm_data_proc(ands, reg_flags, flags); \
} \
break; \
\
case 0x02: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], -rm */ \
arm_access_memory(store, down, post, u16, half_reg); \
} \
else \
{ \
/* MLA rd, rm, rs, rn */ \
arm_multiply(yes, no); \
cycle_count += 3; /* variable 2..5, pick 3 as an aprox. */ \
} \
} \
else \
{ \
/* EOR rd, rn, reg_op */ \
arm_data_proc(eor, reg, no_flags); \
} \
break; \
\
case 0x03: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* MLAS rd, rm, rs, rn */ \
arm_multiply(yes, yes); \
cycle_count += 3; /* variable 2..5, pick 3 as an aprox. */ \
break; \
\
case 1: \
/* LDRH rd, [rn], -rm */ \
arm_access_memory(load, down, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -rm */ \
arm_access_memory(load, down, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -rm */ \
arm_access_memory(load, down, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* EORS rd, rn, reg_op */ \
arm_data_proc(eors, reg_flags, flags); \
} \
break; \
\
case 0x04: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn], -imm */ \
arm_access_memory(store, down, post, u16, half_imm); \
} \
else \
{ \
/* SUB rd, rn, reg_op */ \
arm_data_proc(sub, reg, no_flags); \
} \
break; \
\
case 0x05: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn], -imm */ \
arm_access_memory(load, down, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -imm */ \
arm_access_memory(load, down, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -imm */ \
arm_access_memory(load, down, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* SUBS rd, rn, reg_op */ \
arm_data_proc(subs, reg, flags); \
} \
break; \
\
case 0x06: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn], -imm */ \
arm_access_memory(store, down, post, u16, half_imm); \
} \
else \
{ \
/* RSB rd, rn, reg_op */ \
arm_data_proc(rsb, reg, no_flags); \
} \
break; \
\
case 0x07: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn], -imm */ \
arm_access_memory(load, down, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -imm */ \
arm_access_memory(load, down, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -imm */ \
arm_access_memory(load, down, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* RSBS rd, rn, reg_op */ \
arm_data_proc(rsbs, reg, flags); \
} \
break; \
\
case 0x08: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +rm */ \
arm_access_memory(store, up, post, u16, half_reg); \
} \
else \
{ \
/* UMULL rd, rm, rs */ \
arm_multiply_long(u64, no, no); \
cycle_count += 3; /* this is an aproximation :P */ \
} \
} \
else \
{ \
/* ADD rd, rn, reg_op */ \
arm_data_proc(add, reg, no_flags); \
} \
break; \
\
case 0x09: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* UMULLS rdlo, rdhi, rm, rs */ \
arm_multiply_long(u64, no, yes); \
cycle_count += 3; /* this is an aproximation :P */ \
break; \
\
case 1: \
/* LDRH rd, [rn], +rm */ \
arm_access_memory(load, up, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +rm */ \
arm_access_memory(load, up, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +rm */ \
arm_access_memory(load, up, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ADDS rd, rn, reg_op */ \
arm_data_proc(adds, reg, flags); \
} \
break; \
\
case 0x0A: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +rm */ \
arm_access_memory(store, up, post, u16, half_reg); \
} \
else \
{ \
/* UMLAL rd, rm, rs */ \
arm_multiply_long(u64_add, yes, no); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
} \
} \
else \
{ \
/* ADC rd, rn, reg_op */ \
arm_data_proc(adc, reg, no_flags); \
} \
break; \
\
case 0x0B: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* UMLALS rdlo, rdhi, rm, rs */ \
arm_multiply_long(u64_add, yes, yes); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
break; \
\
case 1: \
/* LDRH rd, [rn], +rm */ \
arm_access_memory(load, up, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +rm */ \
arm_access_memory(load, up, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +rm */ \
arm_access_memory(load, up, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ADCS rd, rn, reg_op */ \
arm_data_proc(adcs, reg, flags); \
} \
break; \
\
case 0x0C: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +imm */ \
arm_access_memory(store, up, post, u16, half_imm); \
} \
else \
{ \
/* SMULL rd, rm, rs */ \
arm_multiply_long(s64, no, no); \
cycle_count += 2; /* Between 1 and 4 cycles? */ \
} \
} \
else \
{ \
/* SBC rd, rn, reg_op */ \
arm_data_proc(sbc, reg, no_flags); \
} \
break; \
\
case 0x0D: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* SMULLS rdlo, rdhi, rm, rs */ \
arm_multiply_long(s64, no, yes); \
cycle_count += 2; /* Between 1 and 4 cycles? */ \
break; \
\
case 1: \
/* LDRH rd, [rn], +imm */ \
arm_access_memory(load, up, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +imm */ \
arm_access_memory(load, up, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +imm */ \
arm_access_memory(load, up, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* SBCS rd, rn, reg_op */ \
arm_data_proc(sbcs, reg, flags); \
} \
break; \
\
case 0x0E: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +imm */ \
arm_access_memory(store, up, post, u16, half_imm); \
} \
else \
{ \
/* SMLAL rd, rm, rs */ \
arm_multiply_long(s64_add, yes, no); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
} \
} \
else \
{ \
/* RSC rd, rn, reg_op */ \
arm_data_proc(rsc, reg, no_flags); \
} \
break; \
\
case 0x0F: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* SMLALS rdlo, rdhi, rm, rs */ \
arm_multiply_long(s64_add, yes, yes); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
break; \
\
case 1: \
/* LDRH rd, [rn], +imm */ \
arm_access_memory(load, up, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +imm */ \
arm_access_memory(load, up, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +imm */ \
arm_access_memory(load, up, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* RSCS rd, rn, reg_op */ \
arm_data_proc(rscs, reg, flags); \
} \
break; \
\
case 0x10: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn - rm] */ \
arm_access_memory(store, down, pre, u16, half_reg); \
} \
else \
{ \
/* SWP rd, rm, [rn] */ \
arm_swap(u32); \
} \
} \
else \
{ \
/* MRS rd, cpsr */ \
arm_psr(reg, read, cpsr); \
} \
break; \
\
case 0x11: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - rm] */ \
arm_access_memory(load, down, pre, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn - rm] */ \
arm_access_memory(load, down, pre, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn - rm] */ \
arm_access_memory(load, down, pre, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* TST rd, rn, reg_op */ \
arm_data_proc_test(tst, reg_flags); \
} \
break; \
\
case 0x12: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn - rm]! */ \
arm_access_memory(store, down, pre_wb, u16, half_reg); \
} \
else \
{ \
if(opcode & 0x10) \
{ \
/* BX rn */ \
arm_bx(); \
} \
else \
{ \
/* MSR cpsr, rm */ \
arm_psr(reg, store, cpsr); \
} \
} \
break; \
\
case 0x13: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - rm]! */ \
arm_access_memory(load, down, pre_wb, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn - rm]! */ \
arm_access_memory(load, down, pre_wb, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn - rm]! */ \
arm_access_memory(load, down, pre_wb, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* TEQ rd, rn, reg_op */ \
arm_data_proc_test(teq, reg_flags); \
} \
break; \
\
case 0x14: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn - imm] */ \
arm_access_memory(store, down, pre, u16, half_imm); \
} \
else \
{ \
/* SWPB rd, rm, [rn] */ \
arm_swap(u8); \
} \
} \
else \
{ \
/* MRS rd, spsr */ \
arm_psr(reg, read, spsr); \
} \
break; \
\
case 0x15: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - imm] */ \
arm_access_memory(load, down, pre, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn - imm] */ \
arm_access_memory(load, down, pre, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn - imm] */ \
arm_access_memory(load, down, pre, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* CMP rn, reg_op */ \
arm_data_proc_test(cmp, reg); \
} \
break; \
\
case 0x16: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn - imm]! */ \
arm_access_memory(store, down, pre_wb, u16, half_imm); \
} \
else \
{ \
/* MSR spsr, rm */ \
arm_psr(reg, store, spsr); \
} \
break; \
\
case 0x17: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - imm]! */ \
arm_access_memory(load, down, pre_wb, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn - imm]! */ \
arm_access_memory(load, down, pre_wb, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn - imm]! */ \
arm_access_memory(load, down, pre_wb, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* CMN rd, rn, reg_op */ \
arm_data_proc_test(cmn, reg); \
} \
break; \
\
case 0x18: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn + rm] */ \
arm_access_memory(store, up, pre, u16, half_reg); \
} \
else \
{ \
/* ORR rd, rn, reg_op */ \
arm_data_proc(orr, reg, no_flags); \
} \
break; \
\
case 0x19: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn + rm] */ \
arm_access_memory(load, up, pre, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn + rm] */ \
arm_access_memory(load, up, pre, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn + rm] */ \
arm_access_memory(load, up, pre, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ORRS rd, rn, reg_op */ \
arm_data_proc(orrs, reg_flags, flags); \
} \
break; \
\
case 0x1A: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn + rm]! */ \
arm_access_memory(store, up, pre_wb, u16, half_reg); \
} \
else \
{ \
/* MOV rd, reg_op */ \
arm_data_proc_unary(mov, reg, no_flags); \
} \
break; \
\
case 0x1B: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn + rm]! */ \
arm_access_memory(load, up, pre_wb, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn + rm]! */ \
arm_access_memory(load, up, pre_wb, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn + rm]! */ \
arm_access_memory(load, up, pre_wb, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* MOVS rd, reg_op */ \
arm_data_proc_unary(movs, reg_flags, flags); \
} \
break; \
\
case 0x1C: \
if((opcode & 0x90) == 0x90) \
{ \