ARM: dts: rockchip: reconfig dwc2 device fifo size

According to the dwc2 programmer's guide v3.10a, in '2.1.3.2 Dedicated
FIFO Mode with No Thresholding', it suggested that:

Device RxFIFO =
- Scatter/Gather DMA mode:
(4 * number of control endpoints + 6) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK

on rockchip platforms:
(4 * 1 + 6) + ((1024 / 4) + 1) + (2 * 6) + 1 = 280

- Slave or Buffer DMA mode:
(5 * number of control endpoints + 8) + ((largest USB packet used / 4) +
1 for status information) + (2 * number of OUT endpoints) + 1 for Global NAK

on rockchip platforms:
(5 * 1 + 8) + ((1024 / 4) + 1) + (2 * 6) + 1 = 283

Device IN Endpoint TxFIFO =
The TxFIFO must equal at least one MaxPacketSize (MPS).

In addition to RxFIFO and TxFIFOs, refer to dwc2 databook v3.10a,
'Figure 2-13 Device Mode FIFO Address Mapping and AHB FIFO Access Mapping
(Dedicated FIFO)', it required that when the device is operating in non
Scatter Gather Internal DMA mode, the last locations of the SPRAM are used
to store the DMAADDR values for each Endpoint (1 location per endpoint).

When the device is operating in Scatter Gather mode, then the last locations
of the SPRAM store the Base Descriptor address, Current Descriptor address,
Current Buffer address, and status quadlet information for each endpoint
direction (4 locations per Endpoint). If an Endpoint is bidirectional , then
4 locations will be used for IN, and another 4 for OUT).

Considering that the total FIFO size of dwc2 otg is 0x3cc (972),
and we must reserve (4 * 13) = 52 locations for all Endpoints.
So reconfig dwc2 device fifo size as follows:

Device RxFIFO = 280
Device IN Endpoint TxFIFO
- FIFO #0 = (64 / 4) = 16 (Assuming this is used for EP0)
- FIFO #1 = (1024/4) = 256 (Assuming this is used for Isochronous)
- FIFO #2 = (512/4) = 128
- FIFO #3 = (512/4) = 128
- FIFO #4 = (256/4) = 64
- FIFO #5 = (128/4) = 32
- FIFO #6 = (64/4) = 16

After reconfig the dwc2 device fifo size, test mtp write on rockchip
platform (PC -> rockchip platform) on rk312x/rk3326/px30/rk3288 evb,
when mask the 'vfs_write' in f_mtp.c, the writing data rate can be
increased from 16MBps ~ 20MBps to 30MBps ~ 36MBps on different kinds
of rockchip evbs.

Change-Id: Icdf8a5dd95f96d174233e4ffc765c9a982b9f0b6
Signed-off-by: William Wu <[email protected]>

Author: wuliangfeng

arch/arm/boot/dts/rk3036.dtsi

@@ -373,8 +373,8 @@
 		clock-names = "otg";
 		dr_mode = "otg";
 		g-np-tx-fifo-size = <16>;
-		g-rx-fifo-size = <275>;
-		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
 		g-use-dma;
 		status = "disabled";
 	};

arch/arm/boot/dts/rk312x.dtsi

@@ -615,8 +615,8 @@
 		clock-names = "otg";
 		dr_mode = "otg";
 		g-np-tx-fifo-size = <16>;
-		g-rx-fifo-size = <275>;
-		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
 		g-use-dma;
 		phys = <&u2phy_otg>;
 		phy-names = "usb2-phy";

arch/arm/boot/dts/rk322x.dtsi

@@ -1084,8 +1084,8 @@
 		clock-names = "otg";
 		dr_mode = "otg";
 		g-np-tx-fifo-size = <16>;
-		g-rx-fifo-size = <275>;
-		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
 		g-use-dma;
 		phys = <&u2phy0_otg>;
 		phy-names = "usb2-phy";

arch/arm/boot/dts/rk3288.dtsi

@@ -697,8 +697,8 @@
 		clock-names = "otg";
 		dr_mode = "otg";
 		g-np-tx-fifo-size = <16>;
-		g-rx-fifo-size = <275>;
-		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
 		g-use-dma;
 		phys = <&usbphy0>;
 		phy-names = "usb2-phy";

arch/arm/boot/dts/rk3xxx.dtsi

@@ -180,8 +180,8 @@
 		clock-names = "otg";
 		dr_mode = "otg";
 		g-np-tx-fifo-size = <16>;
-		g-rx-fifo-size = <275>;
-		g-tx-fifo-size = <256 128 128 64 64 32>;
+		g-rx-fifo-size = <280>;
+		g-tx-fifo-size = <256 128 128 64 32 16>;
 		g-use-dma;
 		phys = <&usbphy0>;
 		phy-names = "usb2-phy";