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#define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0
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#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0)
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#define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K 1
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K 2
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K 3
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+ #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K 4
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#define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248)
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#define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264)
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#define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268)
@@ -407,6 +411,7 @@ struct wsa_macro {
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int ear_spkr_gain ;
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int spkr_gain_offset ;
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int spkr_mode ;
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+ u32 pcm_rate_vi ;
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int is_softclip_on [WSA_MACRO_SOFTCLIP_MAX ];
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int softclip_clk_users [WSA_MACRO_SOFTCLIP_MAX ];
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struct regmap * regmap ;
@@ -1280,6 +1285,7 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
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struct snd_soc_dai * dai )
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{
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struct snd_soc_component * component = dai -> component ;
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+ struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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int ret ;
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switch (substream -> stream ) {
@@ -1291,6 +1297,11 @@ static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
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__func__ , params_rate (params ));
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return ret ;
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}
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+ break ;
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+ case SNDRV_PCM_STREAM_CAPTURE :
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+ if (dai -> id == WSA_MACRO_AIF_VI )
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+ wsa -> pcm_rate_vi = params_rate (params );
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+
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break ;
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default :
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break ;
@@ -1448,35 +1459,11 @@ static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
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}
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}
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- static int wsa_macro_mclk_event (struct snd_soc_dapm_widget * w ,
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- struct snd_kcontrol * kcontrol , int event )
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+ static void wsa_macro_enable_disable_vi_sense (struct snd_soc_component * component , bool enable ,
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+ u32 tx_reg0 , u32 tx_reg1 , u32 val )
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{
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- struct snd_soc_component * component = snd_soc_dapm_to_component (w -> dapm );
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- struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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-
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- wsa_macro_mclk_enable (wsa , event == SND_SOC_DAPM_PRE_PMU );
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- return 0 ;
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- }
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-
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- static int wsa_macro_enable_vi_feedback (struct snd_soc_dapm_widget * w ,
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- struct snd_kcontrol * kcontrol ,
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- int event )
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- {
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- struct snd_soc_component * component = snd_soc_dapm_to_component (w -> dapm );
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- struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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- u32 tx_reg0 , tx_reg1 ;
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-
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- if (test_bit (WSA_MACRO_TX0 , & wsa -> active_ch_mask [WSA_MACRO_AIF_VI ])) {
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- tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL ;
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- tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL ;
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- } else if (test_bit (WSA_MACRO_TX1 , & wsa -> active_ch_mask [WSA_MACRO_AIF_VI ])) {
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- tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL ;
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- tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL ;
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- }
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-
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- switch (event ) {
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- case SND_SOC_DAPM_POST_PMU :
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- /* Enable V&I sensing */
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+ if (enable ) {
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+ /* Enable V&I sensing */
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_RESET_MASK ,
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CDC_WSA_TX_SPKR_PROT_RESET );
@@ -1485,10 +1472,10 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
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CDC_WSA_TX_SPKR_PROT_RESET );
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK ,
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- CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K );
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+ val );
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snd_soc_component_update_bits (component , tx_reg1 ,
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CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK ,
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- CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K );
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+ val );
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK ,
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CDC_WSA_TX_SPKR_PROT_CLK_ENABLE );
@@ -1501,9 +1488,7 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits (component , tx_reg1 ,
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CDC_WSA_TX_SPKR_PROT_RESET_MASK ,
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CDC_WSA_TX_SPKR_PROT_NO_RESET );
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- break ;
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- case SND_SOC_DAPM_POST_PMD :
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- /* Disable V&I sensing */
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+ } else {
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snd_soc_component_update_bits (component , tx_reg0 ,
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CDC_WSA_TX_SPKR_PROT_RESET_MASK ,
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CDC_WSA_TX_SPKR_PROT_RESET );
@@ -1516,6 +1501,72 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
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snd_soc_component_update_bits (component , tx_reg1 ,
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CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK ,
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CDC_WSA_TX_SPKR_PROT_CLK_DISABLE );
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+ }
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+ }
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+
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+ static void wsa_macro_enable_disable_vi_feedback (struct snd_soc_component * component ,
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+ bool enable , u32 rate )
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+ {
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+ struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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+
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+ if (test_bit (WSA_MACRO_TX0 , & wsa -> active_ch_mask [WSA_MACRO_AIF_VI ]))
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+ wsa_macro_enable_disable_vi_sense (component , enable ,
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+ CDC_WSA_TX0_SPKR_PROT_PATH_CTL ,
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+ CDC_WSA_TX1_SPKR_PROT_PATH_CTL , rate );
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+
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+ if (test_bit (WSA_MACRO_TX1 , & wsa -> active_ch_mask [WSA_MACRO_AIF_VI ]))
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+ wsa_macro_enable_disable_vi_sense (component , enable ,
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+ CDC_WSA_TX2_SPKR_PROT_PATH_CTL ,
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+ CDC_WSA_TX3_SPKR_PROT_PATH_CTL , rate );
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+ }
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+
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+ static int wsa_macro_mclk_event (struct snd_soc_dapm_widget * w ,
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+ struct snd_kcontrol * kcontrol , int event )
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+ {
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+ struct snd_soc_component * component = snd_soc_dapm_to_component (w -> dapm );
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+ struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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+
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+ wsa_macro_mclk_enable (wsa , event == SND_SOC_DAPM_PRE_PMU );
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+ return 0 ;
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+ }
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+
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+ static int wsa_macro_enable_vi_feedback (struct snd_soc_dapm_widget * w ,
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+ struct snd_kcontrol * kcontrol ,
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+ int event )
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+ {
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+ struct snd_soc_component * component = snd_soc_dapm_to_component (w -> dapm );
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+ struct wsa_macro * wsa = snd_soc_component_get_drvdata (component );
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+ u32 rate_val ;
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+
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+ switch (wsa -> pcm_rate_vi ) {
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+ case 8000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K ;
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+ break ;
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+ case 16000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_16K ;
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+ break ;
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+ case 24000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_24K ;
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+ break ;
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+ case 32000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_32K ;
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+ break ;
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+ case 48000 :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_48K ;
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+ break ;
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+ default :
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+ rate_val = CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K ;
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+ break ;
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+ }
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+
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+ switch (event ) {
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+ case SND_SOC_DAPM_POST_PMU :
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+ /* Enable V&I sensing */
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+ wsa_macro_enable_disable_vi_feedback (component , true, rate_val );
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+ break ;
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+ case SND_SOC_DAPM_POST_PMD :
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+ /* Disable V&I sensing */
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+ wsa_macro_enable_disable_vi_feedback (component , false, rate_val );
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break ;
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}
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