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Merge pull request vhda#216 from vhda/github-runner
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name: Verification flow
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on:
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push:
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branches:
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- master
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- github-runner
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pull_request:
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branches:
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- master
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jobs:
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Run:
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runs-on: ubuntu-22.04
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steps:
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- name: Checkout code
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uses: actions/checkout@v2
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- name: Run tests
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id: run_tests
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run: make V=1 all > make.log 2>&1
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- name: Upload log
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uses: actions/upload-artifact@v3
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if: failure()
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with:
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name: logfiles
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path: |
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make.log
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test-efm.log
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test-syntax.log

Makefile

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SILENT_1 =
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SHELL = /bin/bash -o pipefail
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VIM = vim -u test/test_vimrc -U none -T dumb -E --cmd "set runtimepath+=${PWD}"
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VIM = vim -u test/test_vimrc -U NONE -i NONE -T dumb -E --cmd "set runtimepath+=${PWD}"
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.PHONY: help test test-fold test-indent test-efm
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-c 'source test/functions.vim' \
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-c 'source test/run_test.vim' \
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-c 'call RunTestEfm()' | \
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tee test-efm.log | grep "^Error format test"
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tee test-efm.log
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test-syntax:
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$(SILENT) $(VIM) \
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-c 'source test/functions.vim' \
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-c 'source test/run_test.vim' \
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-c 'call RunTestSyntax()' | tr -d '[]' | \
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tee test-syntax.log | grep "^Syntax test"
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tee test-syntax.log
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performance:
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$(SILENT) time $(VIM) \

README.md

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# Vim Syntax Plugin for Verilog and SystemVerilog
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[![Build Status](https://travis-ci.org/vhda/verilog_systemverilog.vim.svg?branch=master)](https://travis-ci.org/vhda/verilog_systemverilog.vim)
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[![Build Status](https://github.com/vhda/verilog_systemverilog.vim/actions/workflows/verification-flow.yml/badge.svg?branch=master)](https://github.com/vhda/verilog_systemverilog.vim/actions/workflows/verification-flow.yml)
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## About
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