Merge pull request vhda#206 from vhda/indent/standalone_blocks

Indent: Allow disabling of standalone blocks

Author: vhda

autoload/verilog_systemverilog.vim

@@ -601,7 +601,8 @@ function verilog_systemverilog#CompleteCommand(lead, command, cursor)
           \ 'method',
           \ 'preproc',
           \ 'conditional',
-          \ 'eos'
+          \ 'eos',
+          \ 'standalone'
           \ ]
     for item in current_values
       call filter(valid_completions, 'v:val !=# item')

doc/tags

@@ -9,6 +9,7 @@
 :VerilogReturnInstance	verilog_systemverilog.txt	/*:VerilogReturnInstance*
 b:verilog_disable_indent_lst	verilog_systemverilog.txt	/*b:verilog_disable_indent_lst*
 b:verilog_indent_assign_fix	verilog_systemverilog.txt	/*b:verilog_indent_assign_fix*
+b:verilog_indent_block_on_keyword	verilog_systemverilog.txt	/*b:verilog_indent_block_on_keyword*
 b:verilog_indent_width	verilog_systemverilog.txt	/*b:verilog_indent_width*
 b:verilog_syntax_custom	verilog_systemverilog.txt	/*b:verilog_syntax_custom*
 b:verilog_syntax_fold_lst	verilog_systemverilog.txt	/*b:verilog_syntax_fold_lst*
@@ -20,6 +21,7 @@ g:verilog_efm_level	verilog_systemverilog.txt	/*g:verilog_efm_level*
 g:verilog_efm_quickfix_clean	verilog_systemverilog.txt	/*g:verilog_efm_quickfix_clean*
 g:verilog_efm_uvm_lst	verilog_systemverilog.txt	/*g:verilog_efm_uvm_lst*
 g:verilog_indent_assign_fix	verilog_systemverilog.txt	/*g:verilog_indent_assign_fix*
+g:verilog_indent_block_on_keyword	verilog_systemverilog.txt	/*g:verilog_indent_block_on_keyword*
 g:verilog_indent_width	verilog_systemverilog.txt	/*g:verilog_indent_width*
 g:verilog_navigate_split	verilog_systemverilog.txt	/*g:verilog_navigate_split*
 g:verilog_navigate_split_close	verilog_systemverilog.txt	/*g:verilog_navigate_split_close*

doc/verilog_systemverilog.txt

@@ -384,10 +384,43 @@ Example:
     let b:verilog_indent_assign_fix = 1
 <
 
+         *b:verilog_indent_block_on_keyword* *g:verilog_indent_block_on_keyword*
+b:verilog_indent_block_on_keyword~
+g:verilog_indent_block_on_keyword~
+Default: undefined
+
+    Always indent lines following a block start on the "begin" keyword.
+    By default, the indentation script will use the indent of the line where
+    the block starts:
+>
+        case (value)
+            default : begin
+                x <= y;
+                y <= z;
+            end
+        endcase
+<
+    When this option is enabled the indentation will be offset to the start of
+    the "begin" keyword, as following:
+>
+        case (value)
+            default : begin
+                          x <= y;
+                          y <= z;
+                      end
+        endcase
+<
+
+Example:
+
+>
+    let b:verilog_indent_block_on_keyword = 1
+<
+
                    *b:verilog_disable_indent_lst* *g:verilog_disable_indent_lst*
 b:verilog_disable_indent_lst~
 g:verilog_disable_indent_lst~
-Default: "eos"
+Default: "eos,standalone"
 
     Disables indent for specific Verilog/SystemVerilog contexts.
     The following contexts are supported:
@@ -404,25 +437,26 @@ Default: "eos"
         - `preproc`
         - `conditional`
         - `eos`
+        - `standalone`
 
-Example:
+Examples:
 
 >
     let g:verilog_disable_indent_lst = "module,class,interface"
 <
     Disabling indentation of `conditional` will change the following:
 >
-    // Default indent
-    assign a = cond ? b :
-                      c ;
-    // Disabling 'conditional'
-    assign a = cond ? b :
-               c ;
+        // Default indent
+        assign a = cond ? b :
+                          c ;
+        // Disabling 'conditional'
+        assign a = cond ? b :
+                   c ;
 <
 
     Disabling indentation of `eos` will affect how the closing parentheses of
     modules, functions, tasks, etc. are indented.
-    By default:
+    When enabled:
 >
         module mod(
             input wire a,
@@ -437,6 +471,23 @@ Example:
         );
 <
 
+    Disabling indentation of `standalone` will affect how standalone blocks,
+    like begin..end or {..} are indented.
+    When enabled:
+>
+        if (expr)
+            begin
+                func();
+            end
+<
+    When disabled:
+>
+        if (expr)
+        begin
+            func();
+        end
+<
+
     Note: The commands |:VerilogIndentAdd| and |:VerilogIndentRemove| are
     provided to allow an easier management of this variable.
 

indent/verilog_systemverilog.vim

@@ -51,7 +51,7 @@ let s:vlog_define         = '^\s*`define\>'
 let s:vlog_case           = '\<case[zx]\?\>\s*('
 let s:vlog_join           = '\<join\(_any\|_none\)\?\>'
 
-let s:vlog_block_decl     = '\(\<\(while\|if\|foreach\|for\)\>\s*(\)\|\<\(else\|do\)\>\|' . s:vlog_always
+let s:vlog_block_decl     = '\(\<\(while\|if\|foreach\|for\|repeat\)\>\s*(\)\|\<\(initial\|forever\|else\|do\)\>\|' . s:vlog_always
 
 let s:vlog_context_end    = '\<end\(package\|function\|class\|module\|group\|generate\|program\|property\|sequence\|clocking\|interface\|task\)\>\|`endif\>'
 
@@ -126,7 +126,15 @@ function! GetVerilogSystemVerilogIndent()
     elseif s:curr_line =~ '^\s*\<endclass\>'
       return indent(s:SearchForBlockStart('\<class\>' , '', '\<endclass\>' , v:lnum, 0))
     elseif s:curr_line =~ '^\s*\<end\>'
-      return indent(s:SearchForBlockStart('\<begin\>' , '', '\<end\>'      , v:lnum, 1))
+      let l:start_lnum = s:SearchForBlockStart('\<begin\>' , '', '\<end\>'      , v:lnum, 1)
+      let l:start_indent = indent(l:start_lnum)
+      if (verilog_systemverilog#VariableExists("verilog_indent_block_on_keyword"))
+        let l:block_offset = match(getline(l:start_lnum)[l:start_indent:], 'begin')
+        call verilog_systemverilog#Verbose('Return indent to start of block keyword (offset=' . l:block_offset . ')')
+        return l:start_indent + l:block_offset
+      else
+        return l:start_indent
+      endif
     elseif s:curr_line =~ '^\s*\<endcase\>'
       return indent(s:SearchForBlockStart(s:vlog_case , '', '\<endcase\>'  , v:lnum, 0))
     endif
@@ -202,7 +210,7 @@ function! s:SearchForBlockStart(start_wd, mid_wd, end_wd, current_line_no, skip_
   endif
 
   let l:lnum = searchpair(a:start_wd, a:mid_wd, a:end_wd, 'bnW', l:skip_arg)
-  call verilog_systemverilog#Verbose('SearchForBlockStart: returning l:lnum ' . l:lnum)
+  call verilog_systemverilog#Verbose('SearchForBlockStart: ' . a:start_wd . ' returning l:lnum ' . l:lnum)
   return l:lnum
 endfunction
 
@@ -290,7 +298,12 @@ function! s:GetContextIndent()
 
     if l:line =~ '\<begin\>' && l:line !~ '\<begin\>.*\<end\>'
       call verilog_systemverilog#Verbose("Inside a 'begin end' block.")
-      return indent(l:lnum) + s:offset + l:open_offset
+      let l:block_offset = 0
+      if (verilog_systemverilog#VariableExists("verilog_indent_block_on_keyword"))
+        call verilog_systemverilog#Verbose("Matching start of block keyword")
+        let l:block_offset = match(l:line[indent(l:lnum):], 'begin')
+      endif
+      return indent(l:lnum) + s:offset + l:open_offset + l:block_offset
     elseif l:line =~ '^\s*\<fork\>'
       call verilog_systemverilog#Verbose("Inside a 'fork join' block.")
       return indent(l:lnum) + s:offset + l:open_offset
@@ -357,15 +370,20 @@ function! s:GetContextIndent()
       call verilog_systemverilog#Verbose("'begin'..'end' pair.")
       return indent(l:lnum)
     elseif l:oneline_mode == 1 && l:line =~ s:vlog_block_decl && l:line !~ '\<begin\>.*\<end\>'
+      if index(s:verilog_disable_indent, 'standalone') < 0
+        let l:standalone = s:offset
+      else
+        let l:standalone = 0
+      endif
       if s:curr_line =~ '^\s*\<begin\>'
         call verilog_systemverilog#Verbose("Standalone 'begin' after block declaration.")
-        return indent(l:lnum)
+        return indent(l:lnum) + l:standalone
       elseif s:curr_line =~ '^\s*{\s*$' && l:cbracket_level == 0
         call verilog_systemverilog#Verbose("Standalone '{' after block declaration.")
-        return indent(l:lnum)
+        return indent(l:lnum) + l:standalone
       elseif s:curr_line =~ '^\s*(\s*$' && l:bracket_level == 0
         call verilog_systemverilog#Verbose("Standalone '(' after block declaration.")
-        return indent(l:lnum)
+        return indent(l:lnum) + l:standalone
       else
         call verilog_systemverilog#Verbose("Indenting a single line block.")
         return indent(l:lnum) + s:offset + l:open_offset

plugin/verilog_systemverilog.vim

@@ -1,5 +1,5 @@
 " Global plugin settings
-let g:verilog_disable_indent_lst="eos"
+let g:verilog_disable_indent_lst="eos,standalone"
 
 " Command definitions
 command! -nargs=* VerilogErrorFormat call verilog_systemverilog#VerilogErrorFormat(<f-args>)

test/functions.vim

@@ -63,11 +63,11 @@ function! TestIndent()
     endwhile
 
     if (fail == 1)
-        echo 'Indent test failed:'
+        echo 'Indent test failed (' . g:verilog_disable_indent_lst . '):'
         echo fail_lines
         return 1
     else
-        echo 'Indent test passed'
+        echo 'Indent test passed (' . g:verilog_disable_indent_lst . ')'
         return 0
     endif