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first version of map generator
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‎README.md

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# csr-map-generator
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Generator for CSR mapping module
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Generator for CSR (Control/Status Registers) mapping module
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Can be useful for ASIC/FPGA designers.
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Using Jinja2 ( http://jinja.pocoo.org/ ) and Python of course.
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Have fun!
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‎csr_map_generator.py

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#!/usr/bin/env python
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from jinja2 import Template
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class Reg( ):
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def __init__( self, num, name ):
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self.num = '{:X}'.format( num )
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self.name = name
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self.name_lowcase = self.name.lower()
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self.bits = []
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def add_bits( self, reg_bits ):
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self.bits.append( reg_bits )
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class RegBits( ):
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def __init__( self, bit_msb, bit_lsb, name, mode = "RW", init_value = 0 ):
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self.bit_msb = bit_msb
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self.bit_lsb = bit_lsb
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self.width = bit_msb - bit_lsb + 1
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self.name = name
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self.name_lowcase = self.name.lower()
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self.mode = mode
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self.init_value = '{:X}'.format( init_value )
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# bit modes:
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# RO - read only
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# RO_CONST - read only, constant value
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# RO_LH - read only, latch high
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# RO_LL - read only, latch low
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# RW - read and write
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# RW_SC - read and write, self clear
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assert self.mode in ["RO", "RO_CONST", "RO_LH", "RO_LL", "RW", "RW_SC" ], "Unknown bit mode"
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if self.mode in ["RO_LH", "RO_LL", "RW_SC"]:
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assert self.width == 1, "Wrong width for this bit mod"
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self.port_signal_input = self.mode in ["RO", "RO_LH", "RO_LL"]
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self.port_signal_output = self.mode in ["RW", "RW_SC"]
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self.need_port_signal = self.port_signal_input or self.port_signal_output
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csr_map_template = Template(u"""
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{%- macro reg_name( r ) -%}
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reg_{{r.num}}_{{r.name_lowcase}}
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{%- endmacro %}
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{%- macro reg_name_bits( r, b ) -%}
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reg_{{r.num}}_{{r.name_lowcase}}___{{b.name_lowcase}}
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{%- endmacro %}
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{%- macro bit_init_value( b ) -%}
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{{b.width}}'h{{b.init_value}}
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{%- endmacro %}
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{%- macro signal( width ) -%}
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[{{width-1}}:0]
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{%- endmacro %}
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{%- macro print_port_signal( dir, width, name, eol="," ) -%}
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{{ " %-12s %-10s %-10s" | format( dir, signal( width ), name+eol ) }}
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{%- endmacro %}
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// Generated using CSR map generator
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// https://github.com/johan92/csr-map-generator
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module {{module_name}}(
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{%- for p in data %}
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// Register {{p.name}} signals
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{%- for b in p.bits %}
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{%- if b.port_signal_input %}
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{{print_port_signal( "input", b.width, b.name_lowcase )}}
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{%- elif b.port_signal_output %}
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{{print_port_signal( "output", b.width, b.name_lowcase )}}
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{%- endif %}
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{%- endfor %}
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{% endfor %}
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// CSR interface
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{{print_port_signal( "input", 1, "reg_clk_i" ) }}
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{{print_port_signal( "input", 1, "reg_rst_i" ) }}
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{{print_port_signal( "input", reg_d_w, "reg_wr_data_i" ) }}
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{{print_port_signal( "input", 1, "reg_wr_en_i" ) }}
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{{print_port_signal( "input", 1, "reg_rd_en_i" ) }}
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{{print_port_signal( "input", reg_a_w, "reg_addr_i" ) }}
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{{print_port_signal( "output", reg_d_w, "reg_rd_data_o", "" ) }}
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);
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{%- for p in data %}
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// ******************************************
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// Register {{p.name}}
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// ******************************************
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logic [{{reg_d_w-1}}:0] {{reg_name( p )}}_read;
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{%- for b in p.bits %}
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{%- if b.mode != "RO" %}
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logic [{{b.width-1}}:0] {{reg_name_bits( p, b )}} = {{bit_init_value( b )}};
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{%- endif %}
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{%- endfor %}
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{% for b in p.bits %}
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{%- if b.port_signal_output %}
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always_ff @( posedge reg_clk_i or posedge reg_rst_i )
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if( reg_rst_i )
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{{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
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else
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if( reg_wr_en_i && ( reg_addr_i == {{reg_a_w}}'h{{p.num}} ) )
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{{reg_name_bits( p, b )}} <= reg_wr_data_i[{{b.bit_msb}}:{{b.bit_lsb}}];
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{%-if b.mode == "RW_SC" %}
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else
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{{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
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{% endif %}
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{%- endif %}
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{%- if b.mode == "RO_LH" or b.mode == "RO_LL" %}
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always_ff @( posedge reg_clk_i or posedge reg_rst_i )
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if( reg_rst_i )
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{{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
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else
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if( reg_rd_en_i && ( reg_addr_i == {{reg_a_w}}'h{{p.num}} ) )
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{{reg_name_bits( p, b )}} <= {{bit_init_value( b )}};
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else
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{%- if b.mode == "RO_LL" %}
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if( {{b.name_lowcase}} == '0 )
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{{reg_name_bits( p, b )}} <= '1;
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{%- elif b.mode == "RO_LH" %}
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if( {{b.name_lowcase}} == '1 )
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{{reg_name_bits( p, b )}} <= '1;
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{%- endif %}
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{% endif %}
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{% endfor %}
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// assigning to output
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{%- for b in p.bits %}
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{%- if b.port_signal_output %}
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assign {{b.name_lowcase}} = {{reg_name_bits( p, b )}};
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{%- endif %}
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{%- endfor %}
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// assigning to read data
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{%- macro print_in_always_comb( r, b, _right_value ) -%}
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{%- if b == "" -%}
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{{ " %s%-7s = %s;" | format( reg_name( r ) + "_read", "", _right_value ) }}
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{%- else -%}
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{{ " %s%-7s = %s;" | format( reg_name( r ) + "_read", "["+b.bit_msb|string+":"+b.bit_lsb|string+"]" , _right_value ) }}
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{%- endif %}
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{%- endmacro %}
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always_comb
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begin
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{{print_in_always_comb( p, "", reg_d_w|string+"'h0" ) }}
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{%- for b in p.bits %}
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{%- if b.mode == "RO" %}
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{{print_in_always_comb( p, b, b.name_lowcase )}}
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{%- else %}
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{{print_in_always_comb( p, b, reg_name_bits( p, b ) )}}
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{%- endif %}
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{%- endfor %}
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end
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{%- endfor %}
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// ******* Reading stuff *******
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logic [{{reg_d_w-1}}:0] reg_rd_data;
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always_ff @( posedge reg_clk_i or posedge reg_rst_i )
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if( reg_rst_i )
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reg_rd_data <= {{reg_d_w}}'h0;
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else
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if( reg_rd_en_i )
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begin
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case( reg_addr_i )
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{% for p in data %}
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{{reg_a_w}}'h{{p.num}}:
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begin
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reg_rd_data <= {{reg_name( p )}}_read;
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end
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{% endfor %}
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default:
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begin
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reg_rd_data <= {{reg_d_w}}'h0;
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end
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endcase
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end
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assign reg_rd_data_o = reg_rd_data;
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endmodule
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""")
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if __name__ == "__main__":
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r0 = Reg( 0x0, "FLOW_GEN")
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r0.add_bits( RegBits( 7, 0, "flow_num", "RW" ) )
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r0.add_bits( RegBits( 15, 15, "flow_en" , "RW" ) )
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r0.add_bits( RegBits( 17, 17, "flow_reset", "RW_SC" ) )
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r0.add_bits( RegBits( 21, 21, "flow_error", "RO_LH" ) )
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r1 = Reg( 0x1, "STAT" )
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r1.add_bits( RegBits( 10, 0, "stat_addr", "RW", 0x15 ) )
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r1.add_bits( RegBits( 15, 15, "stat_rd_en", "RW" ) )
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r1.add_bits( RegBits( 25, 16, "stat_counter", "RO" ) )
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r1.add_bits( RegBits( 31, 30, "stat_version", "RO_CONST", 0x3 ) )
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reg_l = [r0, r1]
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res = csr_map_template.render(
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module_name = "my_csr_map",
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reg_d_w = 32,
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reg_a_w = 8,
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data = reg_l
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)
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print res

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