From 83bb6fd4c81ad49d3217584337824e69702f909e Mon Sep 17 00:00:00 2001
From: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Date: Wed, 28 Sep 2022 16:25:23 +0100
Subject: [PATCH] s390x: Fix regalloc checker error (#4973)

For ShiftRR and VecShiftRR, if shift_reg is zero_reg(), the
instruction does not actually use any register value.

Fixes #4969
---
 cranelift/codegen/src/isa/s390x/inst/mod.rs | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs
index 68cc20af9185..a28c8913edc7 100644
--- a/cranelift/codegen/src/isa/s390x/inst/mod.rs
+++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs
@@ -539,7 +539,9 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
         } => {
             collector.reg_def(rd);
             collector.reg_use(rn);
-            collector.reg_use(shift_reg);
+            if shift_reg != zero_reg() {
+                collector.reg_use(shift_reg);
+            }
         }
         &Inst::RxSBG { rd, rn, .. } => {
             collector.reg_mod(rd);
@@ -744,7 +746,9 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
         } => {
             collector.reg_def(rd);
             collector.reg_use(rn);
-            collector.reg_use(shift_reg);
+            if shift_reg != zero_reg() {
+                collector.reg_use(shift_reg);
+            }
         }
         &Inst::VecSelect { rd, rn, rm, ra, .. } => {
             collector.reg_def(rd);