Merge pull request #410 from infastin/model

jaypipes · web-flow · commit b2e06de36a81 · 2025-03-18T21:16:42.000Z
Add more attributes that match CPU model on Linux
diff --git a/pkg/cpu/cpu_linux.go b/pkg/cpu/cpu_linux.go
@@ -101,6 +101,12 @@ func processorsGet(ctx *context.Context) []*Processor {
 			}
 			if len(lp.Attrs["model name"]) != 0 {
 				proc.Model = lp.Attrs["model name"]
+			} else if len(lp.Attrs["Processor"]) != 0 { // ARM
+				proc.Model = lp.Attrs["Processor"]
+			} else if len(lp.Attrs["cpu model"]) != 0 { // MIPS, ARM
+				proc.Model = lp.Attrs["cpu model"]
+			} else if len(lp.Attrs["Model Name"]) != 0 { // LoongArch
+				proc.Model = lp.Attrs["Model Name"]
 			} else if len(lp.Attrs["uarch"]) != 0 { // SiFive
 				proc.Model = lp.Attrs["uarch"]
 			}

Original file line number	Diff line number	Diff line change
`@@ -101,6 +101,12 @@ func processorsGet(ctx context.Context) []Processor {`
`101`	`101`	`}`
`102`	`102`	`if len(lp.Attrs["model name"]) != 0 {`
`103`	`103`	`proc.Model = lp.Attrs["model name"]`
	`104`	`+ } else if len(lp.Attrs["Processor"]) != 0 { // ARM`
	`105`	`+ proc.Model = lp.Attrs["Processor"]`
	`106`	`+ } else if len(lp.Attrs["cpu model"]) != 0 { // MIPS, ARM`
	`107`	`+ proc.Model = lp.Attrs["cpu model"]`
	`108`	`+ } else if len(lp.Attrs["Model Name"]) != 0 { // LoongArch`
	`109`	`+ proc.Model = lp.Attrs["Model Name"]`
`104`	`110`	`} else if len(lp.Attrs["uarch"]) != 0 { // SiFive`
`105`	`111`	`proc.Model = lp.Attrs["uarch"]`
`106`	`112`	`}`