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[SYCL] Make default project directory match default executable name (#8532)
Currently, the default output directory is "<file_name>.prj" when no "-o" flag is specified. This makes it annoying for the user to run a design compiled for simulation since the "a.out" executable will look for a "a.prj" directory which would not exist. By making the default project named "a.prj", we solve this issue.
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3 files changed

+14
-14
lines changed

3 files changed

+14
-14
lines changed

clang/lib/Driver/ToolChains/SYCL.cpp

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@
99
#include "CommonArgs.h"
1010
#include "clang/Driver/Compilation.h"
1111
#include "clang/Driver/Driver.h"
12-
#include "clang/Driver/InputInfo.h"
1312
#include "clang/Driver/DriverDiagnostic.h"
13+
#include "clang/Driver/InputInfo.h"
1414
#include "clang/Driver/Options.h"
1515
#include "llvm/Support/CommandLine.h"
1616
#include "llvm/Support/FileSystem.h"
@@ -270,8 +270,9 @@ const char *SYCL::Linker::constructLLVMLinkCommand(
270270
// TODO: temporary workaround for a problem with warnings reported by
271271
// llvm-link when driver links LLVM modules with empty modules
272272
CmdArgs.push_back("--suppress-warnings");
273-
C.addCommand(std::make_unique<Command>(
274-
JA, *this, ResponseFileSupport::AtFileUTF8(), Exec, CmdArgs, std::nullopt));
273+
C.addCommand(std::make_unique<Command>(JA, *this,
274+
ResponseFileSupport::AtFileUTF8(),
275+
Exec, CmdArgs, std::nullopt));
275276
};
276277

277278
// Add an intermediate output file.
@@ -312,8 +313,9 @@ void SYCL::Linker::constructLlcCommand(Compilation &C, const JobAction &JA,
312313
SmallString<128> LlcPath(C.getDriver().Dir);
313314
llvm::sys::path::append(LlcPath, "llc");
314315
const char *Llc = C.getArgs().MakeArgString(LlcPath);
315-
C.addCommand(std::make_unique<Command>(
316-
JA, *this, ResponseFileSupport::AtFileUTF8(), Llc, LlcArgs, std::nullopt));
316+
C.addCommand(std::make_unique<Command>(JA, *this,
317+
ResponseFileSupport::AtFileUTF8(), Llc,
318+
LlcArgs, std::nullopt));
317319
}
318320

319321
// For SYCL the inputs of the linker job are SPIR-V binaries and output is
@@ -552,10 +554,8 @@ void SYCL::fpga::BackendCompiler::ConstructJob(
552554
const char *FolderName = Args.MakeArgString(FN);
553555
ReportOptArg += FolderName;
554556
} else {
555-
// Output directory is based off of the first object name as captured
556-
// above.
557-
if (!CreatedReportName.empty())
558-
ReportOptArg += CreatedReportName;
557+
// Default output directory should match default output executable name
558+
ReportOptArg += "a.prj";
559559
}
560560
if (!ReportOptArg.empty())
561561
CmdArgs.push_back(C.getArgs().MakeArgString(

clang/test/Driver/sycl-offload-intelfpga-link.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,10 @@
7171
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocx-intel-unknown" "-input={{.*}}" "-check-section"
7272
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocr-intel-unknown" "-input={{.*}}" "-check-section"
7373
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown" "-input=[[INPUT:.+\.a]]" "-output=[[OUTPUT2:.+\.aocr]]" "-unbundle"
74-
// CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--out-increment={{.*}}-aocr.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-output-report-folder={{.*}}-aocr.prj" "-g"
74+
// CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--out-increment=a.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-output-report-folder=a.prj" "-g"
7575
// CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]"
7676
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "-batch" "[[OUTPUT4]]"
77-
// CHK-FPGA-LINK-LIB-EARLY: llvm-foreach{{.*}} "--out-ext=aocr" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocr]]" "--out-replace=[[OUTPUT3]]" "--out-increment={{.*}}-aocr.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-rtl" "-output-report-folder={{.*}}-aocr.prj" "-g"
77+
// CHK-FPGA-LINK-LIB-EARLY: llvm-foreach{{.*}} "--out-ext=aocr" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocr]]" "--out-replace=[[OUTPUT3]]" "--out-increment=a.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-rtl" "-output-report-folder=a.prj" "-g"
7878
// CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]"
7979
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr-intel-unknown" "-kind=sycl" "-batch" "[[OUTPUT4]]"
8080
// CHK-FPGA-LINK-LIB: llc{{.*}} "-filetype=obj" "-o" "[[OUTPUT5:.+\.o]]"

clang/test/Driver/sycl-offload-intelfpga.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@
208208
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT2 %s
209209
// RUN: %clang_cl -### -fsycl -fintelfpga -Xshardware %t_dir/dummy.cpp 2>&1 \
210210
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT2 %s
211-
// CHK-FPGA-REPORT-OPT2: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d" "-output-report-folder={{.*}}dummy.prj"
211+
// CHK-FPGA-REPORT-OPT2: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d" "-output-report-folder={{.*}}a.prj"
212212
// CHK-FPGA-REPORT-OPT2-NOT: aoc{{.*}} "-sycl" {{.*}}_dir{{.*}}
213213

214214
/// -fintelfpga dependency files from multiple source
@@ -217,7 +217,7 @@
217217
// RUN: | FileCheck -check-prefix=CHK-FPGA-MULTI-DEPS %s
218218
// RUN: %clang_cl -### -fsycl -fintelfpga -Xshardware %t_dir/dummy.cpp dummy2.cpp 2>&1 \
219219
// RUN: | FileCheck -check-prefix=CHK-FPGA-MULTI-DEPS %s
220-
// CHK-FPGA-MULTI-DEPS: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d,{{.+}}dummy2-{{.+}}.d" "-output-report-folder={{.*}}dummy.prj"
220+
// CHK-FPGA-MULTI-DEPS: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d,{{.+}}dummy2-{{.+}}.d" "-output-report-folder={{.*}}a.prj"
221221

222222
/// -fintelfpga output report file should be based on first input (src/obj)
223223
// RUN: mkdir -p %t_dir
@@ -233,7 +233,7 @@
233233
// RUN: | FileCheck -check-prefix=CHK-FPGA-REPORT-NAME %s
234234
// RUN: %clang_cl -### -fsycl -fintelfpga -Xshardware %t_dir/dummy2.cpp %t_dir/dummy1.o 2>&1 \
235235
// RUN: | FileCheck -check-prefix=CHK-FPGA-REPORT-NAME %s
236-
// CHK-FPGA-REPORT-NAME: aoc{{.*}} "-sycl"{{.*}} "-output-report-folder={{.*}}dummy2.prj"
236+
// CHK-FPGA-REPORT-NAME: aoc{{.*}} "-sycl"{{.*}} "-output-report-folder={{.*}}a.prj"
237237

238238
/// Check for implied options with -Xshardware (-g -O0)
239239
/// Expectation is for -O0 to not be used with -Xshardware

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