@@ -1022,7 +1022,7 @@ void BankConflictPass::setupBankConflictsForBBTGL(G4_BB *bb,
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} else {
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setupBankConflictsforMad(inst);
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}
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- } else if (gra.kernel.getOption(vISA_forceBCR) && !forGlobal &&
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+ } else if (gra.forceBCR && !forGlobal &&
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inst->getNumSrc() == 2) {
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threeSourceInstNum++;
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setupBankConflictsforMad(inst);
@@ -3499,7 +3499,7 @@ bool Augmentation::markNonDefaultMaskDef() {
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nonDefaultMaskDefFound = true;
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}
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- if (kernel.getOption(vISA_forceBCR ) &&
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+ if ((gra.favorBCR || gra.forceBCR ) &&
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gra.getBankConflict(dcl) != BANK_CONFLICT_NONE) {
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gra.setAugmentationMask(dcl, AugmentationMasks::NonDefault);
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nonDefaultMaskDefFound = true;
@@ -6723,7 +6723,7 @@ bool GraphColor::assignColors(ColorHeuristic colorHeuristicGRF,
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// pass) then abort on spill
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//
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if ((heuristic == ROUND_ROBIN ||
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- (doBankConflict && !kernel.getOption(vISA_forceBCR) )) &&
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+ (doBankConflict && !gra.forceBCR )) &&
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(lr->getRegKind() == G4_GRF || lr->getRegKind() == G4_FLAG)) {
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return false;
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} else if (kernel.fg.isPseudoDcl(dcl)) {
@@ -7345,11 +7345,9 @@ bool GraphColor::regAlloc(bool doBankConflictReduction,
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return false;
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}
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- if (!kernel.getOption(vISA_forceBCR)) {
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- if (!success && doBankConflictReduction) {
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- resetTemporaryRegisterAssignments();
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- assignColors(FIRST_FIT);
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- }
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+ if (!success && doBankConflictReduction && !gra.forceBCR) {
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+ resetTemporaryRegisterAssignments();
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+ assignColors(FIRST_FIT);
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}
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}
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} else {
@@ -10111,6 +10109,16 @@ bool GlobalRA::tryHybridRA() {
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return true;
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}
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+ //Skip hybridRA if BCR is needed
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+ if (favorBCR) {
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+ lra.undoLocalRAAssignments(true);
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+ // Restore alignment in case LRA modified it
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+ copyAlignment();
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+ //reset favorBCR
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+ favorBCR = false;
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+ return false;
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+ }
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+
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if (useHybridRAwithSpill) {
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insertPhyRegDecls();
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} else {
@@ -10431,14 +10439,14 @@ std::pair<bool, bool> GlobalRA::bankConflict() {
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bool doBankConflictReduction = false, highInternalConflict = false;
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if (builder.getOption(vISA_LocalBankConflictReduction) &&
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builder.hasBankCollision()) {
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- bool reduceBCInRR = false;
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- bool reduceBCInTAandFF = false;
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+ bool reduceBC = false;
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+ bool threeSouceBCR = false;
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BankConflictPass bc(*this, true);
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- reduceBCInRR = bc.setupBankConflictsForKernel(
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- true, reduceBCInTAandFF , SECOND_HALF_BANK_START_GRF * 2,
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+ reduceBC = bc.setupBankConflictsForKernel(
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+ true, threeSouceBCR , SECOND_HALF_BANK_START_GRF * 2,
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highInternalConflict);
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- doBankConflictReduction = reduceBCInRR && reduceBCInTAandFF ;
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+ doBankConflictReduction = reduceBC && threeSouceBCR ;
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}
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return std::make_pair(doBankConflictReduction, highInternalConflict);
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}
@@ -10769,11 +10777,8 @@ GlobalRA::insertSpillCode(bool enableSpillSpaceCompression,
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bool GlobalRA::rerunGRAIter(bool rerunGRA)
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{
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- if (getIterNo() == 0 && (rerunGRA || kernel.getOption(vISA_forceBCR))) {
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- if (kernel.getOption(vISA_forceBCR)) {
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- // FIXME: We shouldn't modify options. Use local bool flag instead.
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- kernel.getOptions()->setOption(vISA_forceBCR, false);
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- }
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+ if (getIterNo() == 0 && (rerunGRA || forceBCR)) {
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+ forceBCR = false;
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return true;
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}
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return false;
@@ -10991,6 +10996,15 @@ int GlobalRA::coloringRegAlloc() {
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if (!fastCompile) {
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rpe.run();
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writeVerboseRPEStats(rpe);
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+
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+ // If the register pressure is less than TotalGRF - 16, mostly the
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+ // BCR register allocation will success. In this case we do favor BCR
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+ // register allocation in augmentation and assignColors and VRT GRF
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+ // increasing
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+ favorBCR |= doBankConflictReduction && kernel.useAutoGRFSelection() &&
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+ builder.favorBCR() && kernel.getOption(vISA_RoundRobin) &&
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+ !hasStackCall &&
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+ (rpe.getMaxRP() < kernel.getNumRegTotal() - 16);
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}
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GraphColor coloring(liveAnalysis, false, forceSpill);
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