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weiyu-chengfxbot
weiyu-chen
authored and
gfxbot
committed
refactor code for handling the number of physical flag registers
Change-Id: I724cf150497088b794f1ef5db79a8089eec2db32
1 parent c9c4f7a commit 4b2c014

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11 files changed

+116
-131
lines changed

11 files changed

+116
-131
lines changed

‎visa/DebugInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -820,7 +820,7 @@ void KernelDebugInfo::emitRegisterMapping()
820820
if( !isSpilled )
821821
{
822822
unsigned int regNum, subRegNum;
823-
regNum = (dcl->getRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F0) ? 0 : 1;
823+
regNum = dcl->getRegVar()->getPhyReg()->asAreg()->getFlagNum();
824824
subRegNum = dcl->getRegVar()->getPhyRegOff();
825825
varMap->physicalType = VARMAP_PREG_FILE_FLAG;
826826
varMap->Mapping.Register.regNum = static_cast<uint16_t>(regNum);

‎visa/FlowGraph.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3385,7 +3385,7 @@ void FlowGraph::addSaveRestorePseudoDeclares(IR_Builder& builder)
33853385
for (auto callSite : callSites)
33863386
{
33873387
char *name = builder.getNameString(mem, 64, builder.getIsKernel() ? "k%d_SFLAG_%d" : "f%d_SFLAG_%d", builder.getCUnitId(), j);
3388-
G4_Declare* saveFLAG = builder.createDeclareNoLookup(name, G4_FLAG, (unsigned short)getNumFlagRegisters(), 1, Type_UW);
3388+
G4_Declare* saveFLAG = builder.createDeclareNoLookup(name, G4_FLAG, (uint16_t)builder.getNumFlagRegisters(), 1, Type_UW);
33893389
pseudoFlagDclList.push_back(saveFLAG);
33903390
callSite->asCFInst()->setAssocPseudoFlagSave(saveFLAG->getRegVar());
33913391
j++;

‎visa/G4_Opcode.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -410,7 +410,6 @@ enum G4_AccRegSel
410410

411411
// global functions
412412
inline unsigned int getNumAddrRegisters(void) { return 16; }
413-
inline unsigned int getNumFlagRegisters(void) { return 4; }
414413
extern short Operand_Type_Rank(G4_Type type);
415414
uint8_t roundDownPow2(uint8_t n);
416415
bool isPow2(uint8_t n);

‎visa/Gen4_IR.cpp

Lines changed: 5 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -4383,18 +4383,15 @@ void G4_DstRegRegion::computeLeftBound()
43834383
}
43844384
}
43854385

4386-
if (base != NULL && base->isFlag())
4386+
if (base && base->isFlag())
43874387
{
43884388
if( base->isRegVar() )
43894389
{
43904390
if (base->asRegVar()->getPhyReg())
43914391
{
43924392
left_bound = base->asRegVar()->getPhyRegOff() * 16; // the bound of flag register is in unit of BIT
43934393
left_bound += subRegOff * 16;
4394-
if (base->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F1)
4395-
{
4396-
left_bound += 32;
4397-
}
4394+
left_bound += base->asRegVar()->getPhyReg()->asAreg()->getFlagNum() * 32;
43984395
}
43994396
else
44004397
{
@@ -4404,9 +4401,7 @@ void G4_DstRegRegion::computeLeftBound()
44044401
else
44054402
{
44064403
left_bound = subRegOff * 16;
4407-
if( base->asAreg()->getArchRegType() == AREG_F1 ){
4408-
left_bound += 32;
4409-
}
4404+
left_bound += base->asAreg()->getFlagNum() * 32;
44104405
}
44114406

44124407
byteOffset = left_bound / 8;
@@ -6064,10 +6059,7 @@ void G4_SrcRegRegion::computeLeftBound()
60646059
{
60656060
left_bound = base->asRegVar()->getPhyRegOff() * 16; // the bound of flag register is in unit of BIT
60666061
left_bound += subRegOff * 16;
6067-
if (base->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F1 )
6068-
{
6069-
left_bound += 32;
6070-
}
6062+
left_bound += base->asRegVar()->getPhyReg()->asAreg()->getFlagNum() * 32;
60716063
}
60726064
else
60736065
{
@@ -6077,10 +6069,7 @@ void G4_SrcRegRegion::computeLeftBound()
60776069
else
60786070
{
60796071
left_bound = subRegOff * 16;
6080-
if (base->asAreg()->getArchRegType() == AREG_F1 )
6081-
{
6082-
left_bound += 32;
6083-
}
6072+
left_bound += base->asAreg()->getFlagNum() * 32;
60846073
}
60856074

60866075
right_bound = 0;

‎visa/Gen4_IR.hpp

Lines changed: 63 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -2581,9 +2581,18 @@ class G4_Areg final : public G4_VarBase
25812581
void *operator new(size_t sz, Mem_Manager& m) {return m.alloc(sz);}
25822582
void emit(std::ostream& output, bool symbolreg=false);
25832583

2584-
bool isNullReg() const { return getArchRegType() == AREG_NULL; }
2585-
bool isFlag() const { return getArchRegType() == AREG_F0 ||
2586-
getArchRegType() == AREG_F1; }
2584+
bool isNullReg() const { return getArchRegType() == AREG_NULL; }
2585+
bool isFlag() const
2586+
{
2587+
switch (getArchRegType())
2588+
{
2589+
case AREG_F0:
2590+
case AREG_F1:
2591+
return true;
2592+
default:
2593+
return false;
2594+
}
2595+
}
25872596
bool isIpReg() const { return getArchRegType() == AREG_IP; }
25882597
bool isA0() const { return getArchRegType() == AREG_A0; }
25892598
bool isNReg() const { return getArchRegType() == AREG_N0 ||
@@ -2604,6 +2613,12 @@ class G4_Areg final : public G4_VarBase
26042613
{
26052614
unsigned short rNum = UNDEFINED_SHORT;
26062615
valid = true;
2616+
2617+
if (isFlag())
2618+
{
2619+
return getFlagNum();
2620+
}
2621+
26072622
switch (getArchRegType()) {
26082623
case AREG_NULL:
26092624
case AREG_A0:
@@ -2615,15 +2630,13 @@ class G4_Areg final : public G4_VarBase
26152630
case AREG_CR0:
26162631
case AREG_TM0:
26172632
case AREG_N0:
2618-
case AREG_F0:
26192633
case AREG_IP:
26202634
case AREG_TDR0:
26212635
case AREG_SP:
26222636
rNum = 0;
26232637
break;
26242638
case AREG_ACC1:
26252639
case AREG_N1:
2626-
case AREG_F1:
26272640
rNum = 1;
26282641
break;
26292642
default:
@@ -2643,6 +2656,20 @@ class G4_Areg final : public G4_VarBase
26432656
}
26442657
return rIndNum;
26452658
}
2659+
2660+
int getFlagNum() const
2661+
{
2662+
switch (getArchRegType())
2663+
{
2664+
case AREG_F0:
2665+
return 0;
2666+
case AREG_F1:
2667+
return 1;
2668+
default:
2669+
assert(false && "should only be called on flag ARF");
2670+
return -1;
2671+
}
2672+
}
26462673
};
26472674

26482675
class G4_Imm : public G4_Operand
@@ -3426,23 +3453,20 @@ class G4_Predicate final : public G4_Operand
34263453
control(ctrl), align16Control(PRED_ALIGN16_DEFAULT)
34273454
{
34283455
top_dcl = getBase()->asRegVar()->getDeclare();
3429-
3456+
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
34303457
if (getBase()->asRegVar()->getPhyReg())
34313458
{
34323459
left_bound = srOff * 16;
3433-
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
3460+
34343461
byteOffset = srOff * 2;
34353462

3436-
if (getBase()->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F1)
3437-
{
3438-
left_bound += 32;
3439-
byteOffset += 4;
3440-
}
3463+
auto flagNum = getBase()->asRegVar()->getPhyReg()->asAreg()->getFlagNum();
3464+
left_bound += flagNum * 32;
3465+
byteOffset += flagNum * 4;
34413466
}
34423467
else
34433468
{
34443469
left_bound = 0;
3445-
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
34463470
byteOffset = 0;
34473471
}
34483472
}
@@ -3456,15 +3480,7 @@ class G4_Predicate final : public G4_Operand
34563480
unsigned short getRegOff()
34573481
{
34583482
MUST_BE_TRUE(getBase()->isAreg(), ERROR_INTERNAL_ARGUMENT);
3459-
3460-
if (getBase()->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F0)
3461-
{
3462-
return 0;
3463-
}
3464-
else
3465-
{
3466-
return 1;
3467-
}
3483+
return getBase()->asRegVar()->getPhyReg()->asAreg()->getFlagNum();
34683484
}
34693485

34703486
G4_PredState getState() { return state; }
@@ -3549,20 +3565,19 @@ class G4_CondMod final : public G4_Operand
35493565
if (flag != nullptr)
35503566
{
35513567
top_dcl = getBase()->asRegVar()->getDeclare();
3552-
3568+
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
35533569
if (getBase()->asRegVar()->getPhyReg())
35543570
{
35553571
left_bound = off * 16;
3556-
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
35573572
byteOffset = off * 2;
3558-
if (flag->asAreg()->getArchRegType() == AREG_F1) {
3559-
left_bound += 32;
3560-
byteOffset += 4;
3561-
}
3573+
3574+
auto flagNum = getBase()->asRegVar()->getPhyReg()->asAreg()->getFlagNum();
3575+
left_bound += flagNum * 32;
3576+
byteOffset += flagNum * 4;
35623577
}
3563-
else {
3578+
else
3579+
{
35643580
left_bound = 0;
3565-
MUST_BE_TRUE(flag->isFlag(), ERROR_INTERNAL_ARGUMENT);
35663581
byteOffset = 0;
35673582
}
35683583
}
@@ -3573,18 +3588,11 @@ class G4_CondMod final : public G4_Operand
35733588
G4_CondMod(G4_CondMod &cMod);
35743589
void *operator new(size_t sz, Mem_Manager& m) {return m.alloc(sz);}
35753590
G4_CondModifier getMod() { return mod; }
3576-
unsigned short getRegOff() {
3591+
unsigned short getRegOff() const
3592+
{
35773593
MUST_BE_TRUE(getBase()->isAreg(), ERROR_INTERNAL_ARGUMENT);
35783594
MUST_BE_TRUE(getBase()->asRegVar()->getPhyReg(), "getRegOff is called for non-PhyReg");
3579-
3580-
if (getBase()->asRegVar()->getPhyReg()->asAreg()->getArchRegType() == AREG_F0)
3581-
{
3582-
return 0;
3583-
}
3584-
else
3585-
{
3586-
return 1;
3587-
}
3595+
return getBase()->asRegVar()->getPhyReg()->asAreg()->getFlagNum();
35883596
}
35893597
unsigned short getSubRegOff() { return subRegOff; }
35903598
bool sameCondMod(G4_CondMod& prd);
@@ -3972,6 +3980,21 @@ class PhyRegPool
39723980
G4_Areg* getF1Reg() { return ARF_Table[AREG_F1]; }
39733981
G4_Areg* getTDRReg() { return ARF_Table[AREG_TDR0]; }
39743982
G4_Areg* getSPReg() { return ARF_Table[AREG_SP]; }
3983+
3984+
// map int to flag areg
3985+
G4_Areg* getFlagAreg(int flagNum)
3986+
{
3987+
switch (flagNum)
3988+
{
3989+
case 0:
3990+
return getF0Reg();
3991+
case 1:
3992+
return getF1Reg();
3993+
default:
3994+
assert(false && "unexpected flag register value");
3995+
return nullptr;
3996+
}
3997+
}
39753998
};
39763999

39774000
inline int G4_INST::getNumSrc() const

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