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weiyu-chenpaigeale
weiyu-chen
authored and
paigeale
committed
make gen11-related vISA code open source
Change-Id: Ic4d3fb0e5ddae9500c098c6403de548ba0c9221d
1 parent 8294ade commit 414c458

22 files changed

+447
-41
lines changed

‎visa/BinaryEncodingCNL.cpp

+47-2
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,24 @@ static inline int GetOperandSrcHDLImmType(G4_Type srcType)
152152
default: MUST_BE_TRUE(false, "invalid type"); break;
153153
}
154154
}
155+
else
156+
{
157+
switch (srcType) {
158+
case Type_UD: type = G11HDL::SRCIMMTYPE_UD; break;
159+
case Type_D: type = G11HDL::SRCIMMTYPE_D; break;
160+
case Type_UW: type = G11HDL::SRCIMMTYPE_UW; break;
161+
case Type_W: type = G11HDL::SRCIMMTYPE_W; break;
162+
case Type_UV: type = G11HDL::SRCIMMTYPE_UV; break;
163+
case Type_VF: type = G11HDL::SRCIMMTYPE_VF; break;
164+
case Type_V: type = G11HDL::SRCIMMTYPE_V; break;
165+
case Type_F: type = G11HDL::SRCIMMTYPE_F; break;
166+
case Type_UQ: type = G11HDL::SRCIMMTYPE_UQ; break;
167+
case Type_Q: type = G11HDL::SRCIMMTYPE_Q; break;
168+
case Type_DF: type = G11HDL::SRCIMMTYPE_DF; break;
169+
case Type_HF: type = G11HDL::SRCIMMTYPE_HF; break;
170+
default: MUST_BE_TRUE(false, "invalid type"); break;
171+
}
172+
}
155173
return type;
156174
}
157175

@@ -179,6 +197,24 @@ static inline int GetOperandSrcHDLType(G4_Type regType)
179197
default: MUST_BE_TRUE(false, "invalid type"); break;
180198
}
181199
}
200+
else
201+
{
202+
switch(regType)
203+
{
204+
case Type_UD: type = G11HDL::SRCTYPE_UD; break;
205+
case Type_D: type = G11HDL::SRCTYPE_D; break;
206+
case Type_UW: type = G11HDL::SRCTYPE_UW; break;
207+
case Type_W: type = G11HDL::SRCTYPE_W; break;
208+
case Type_UB: type = G11HDL::SRCTYPE_UB; break;
209+
case Type_B: type = G11HDL::SRCTYPE_B; break;
210+
case Type_DF: type = G11HDL::SRCTYPE_DF; break;
211+
case Type_F: type = G11HDL::SRCTYPE_F; break;
212+
case Type_UQ: type = G11HDL::SRCTYPE_UQ; break;
213+
case Type_Q: type = G11HDL::SRCTYPE_Q; break;
214+
case Type_HF: type = G11HDL::SRCTYPE_HF; break;
215+
default: MUST_BE_TRUE(false, "invalid type"); break;
216+
}
217+
}
182218
return type;
183219
}
184220

@@ -201,6 +237,14 @@ void BinaryEncodingCNL::EncodeOpCode(G4_INST* inst,
201237
G9HDL::EU_OPCODE BinaryEncodingCNL::getEUOpcode(G4_opcode g4opc)
202238
{
203239

240+
switch (g4opc)
241+
{
242+
// GEN11 specific
243+
case G4_ror: return G9HDL::EU_OPCODE_ROR;
244+
case G4_rol: return G9HDL::EU_OPCODE_ROL;
245+
case G4_dp4a: return G9HDL::EU_OPCODE_DP4A;
246+
default: break;
247+
}
204248

205249
return (G9HDL::EU_OPCODE)BinaryEncodingBase::getEUOpcode(g4opc);
206250
}
@@ -2078,7 +2122,7 @@ BinaryEncodingCNL::Status BinaryEncodingCNL::DoAllEncodingJMPI(G4_INST* inst)
20782122

20792123
//hardcode:
20802124
brOneSrc.GetOperandControl().SetDestinationRegisterFile(G9HDL::REGFILE_ARF);
2081-
brOneSrc.GetOperandControl().SetDestinationDataType(G9HDL::DSTTYPE_UD);
2125+
brOneSrc.GetOperandControl().SetDestinationDataType(getGenxPlatform() == GENX_CNL ? G9HDL::DSTTYPE_UD : G11HDL::DSTTYPE_UD);
20822126
brOneSrc.GetOperandControl().SetDestinationAddressingMode(G9HDL::ADDRMODE_DIRECT);
20832127

20842128
//FIXME: bxml does not have arch reg file enumerations
@@ -2417,7 +2461,8 @@ void BinaryEncodingCNL::DoAll()
24172461
BDWCompactSubRegTable.AddIndex1(IVBCompactSubRegTable[i] & 0x1F, i);
24182462
BDWCompactSubRegTable.AddIndex2(IVBCompactSubRegTable[i] & 0x3FF, i);
24192463
if (getGenxPlatform() > GENX_CNL)
2420-
{
2464+
{
2465+
BDWCompactDataTypeTableStr.AddIndex(ICLCompactDataTypeTable[i], i);
24212466
}
24222467
else
24232468
{

‎visa/BinaryEncodingCNL.h

+41
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,8 @@ typedef uint64_t QWORD;
8080
#pragma pack(push, 1)
8181
#include "IGfxHwEuIsaCNL.h"
8282

83+
#include "IGfxHwEuIsaICL.h"
84+
8385

8486
/// \brief Class encapsulating encoding machinery using new auto-generated headers
8587
///
@@ -352,6 +354,45 @@ class DstBuilder
352354
}
353355
else
354356
{
357+
switch (regType)
358+
{ //BXML bug Line 851: bitrange 5-8, should be: 37-40
359+
case Type_UD:
360+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UD);
361+
break;
362+
case Type_D:
363+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_D);
364+
break;
365+
case Type_UW:
366+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UW);
367+
break;
368+
case Type_W:
369+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_W);
370+
break;
371+
case Type_UB:
372+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UB);
373+
break;
374+
case Type_B:
375+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_B);
376+
break;
377+
case Type_DF:
378+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_DF);
379+
break;
380+
case Type_F:
381+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_F);
382+
break;
383+
case Type_UQ:
384+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_UQ);
385+
break;
386+
case Type_Q:
387+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_Q);
388+
break;
389+
case Type_HF:
390+
opnds.SetDestinationDataType(G11HDL::DSTTYPE_HF);
391+
break;
392+
default:
393+
MUST_BE_TRUE(false, "Encoding error: destination type unknown");
394+
break;
395+
}
355396
}
356397
}
357398

‎visa/BinaryEncodingIGA.cpp

+16
Original file line numberDiff line numberDiff line change
@@ -48,6 +48,13 @@ static Platform getIGAInternalPlatform(TARGET_PLATFORM genxPlatform)
4848
case GENX_BXT:
4949
platform = Platform::GEN9;
5050
break;
51+
case GENX_CNL:
52+
platform = Platform::GEN10;
53+
break;
54+
case GENX_ICL:
55+
case GENX_ICLLP:
56+
platform = Platform::GEN11;
57+
break;
5158
default:
5259
break;
5360
}
@@ -128,6 +135,12 @@ iga::Op BinaryEncodingIGA::getIGAOp(G4_opcode op, G4_INST *inst) const
128135
case G4_asr:
129136
igaOp = iga::Op::ASR;
130137
break;
138+
case G4_ror:
139+
igaOp = iga::Op::ROR;
140+
break;
141+
case G4_rol:
142+
igaOp = iga::Op::ROL;
143+
break;
131144
case G4_cmp:
132145
igaOp = iga::Op::CMP;
133146
break;
@@ -285,6 +298,9 @@ iga::Op BinaryEncodingIGA::getIGAOp(G4_opcode op, G4_INST *inst) const
285298
case G4_dp2:
286299
igaOp = iga::Op::DP2;
287300
break;
301+
case G4_dp4a:
302+
igaOp = iga::Op::DP4A;
303+
break;
288304
case G4_line:
289305
igaOp = iga::Op::LINE;
290306
break;

‎visa/BuildCISAIRImpl.cpp

+21
Original file line numberDiff line numberDiff line change
@@ -246,6 +246,24 @@ void CISA_IR_Builder::InitVisaWaTable(TARGET_PLATFORM platform, Stepping step)
246246
VISA_WA_ENABLE(m_pWaTable, WaNoSimd16TernarySrc0Imm);
247247
}
248248

249+
// WA for future platforms
250+
if (platform == GENX_ICLLP || platform == GENX_ICL)
251+
{
252+
VISA_WA_ENABLE(m_pWaTable, Wa_1406306137);
253+
}
254+
if (platform == GENX_ICLLP && (step == Step_A || step == Step_B))
255+
{
256+
VISA_WA_ENABLE(m_pWaTable, Wa_2201674230);
257+
}
258+
switch (platform)
259+
{
260+
case GENX_ICLLP:
261+
case GENX_ICL:
262+
VISA_WA_ENABLE(m_pWaTable, Wa_1406950495);
263+
break;
264+
default:
265+
break;
266+
}
249267
}
250268

251269
// note that this will break if we have more than one builder active,
@@ -723,6 +741,9 @@ void CISA_IR_Builder::emitFCPatchFile()
723741
case GENX_CHV: return cm::patch::PP_CHV;
724742
case GENX_SKL: return cm::patch::PP_SKL;
725743
case GENX_BXT: return cm::patch::PP_BXT;
744+
case GENX_CNL: return cm::patch::PP_CNL;
745+
case GENX_ICL: return cm::patch::PP_ICL;
746+
case GENX_ICLLP: return cm::patch::PP_ICLLP;
726747
default:
727748
break;
728749
}

‎visa/CISA.l

+6
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,12 @@ and|or|xor|shl|shr|asr {
178178
return BINARY_LOGIC_OP;
179179
}
180180

181+
rol|ror {
182+
TRACE("\n** Binary Logic INST ");
183+
CISAlval.opcode = str2opcode(yytext);
184+
return BINARY_LOGIC_OP;
185+
}
186+
181187

182188
addc|subb {
183189
TRACE("\n** MATH INST ");

‎visa/Common_BinaryEncoding.h

+35
Original file line numberDiff line numberDiff line change
@@ -596,6 +596,41 @@ static uint32_t BDWCompactDataTypeTable[COMPACT_TABLE_SIZE]=
596596
0x0004B248, //001001011001001001000
597597
};
598598

599+
static uint32_t ICLCompactDataTypeTable[COMPACT_TABLE_SIZE] =
600+
{
601+
0x40001, // 001000000000000000001
602+
0x40040, // 001000000000001000000
603+
0x40041, // 001000000000001000001
604+
0x400C1, // 001000000000011000001
605+
0x40165, // 001000000000101100101
606+
0x40BE5, // 001000000101111100101
607+
0x40941, // 001000000100101000001
608+
0x40945, // 001000000100101000101
609+
0x40965, // 001000000100101100101
610+
0x41041, // 001000001000001000001
611+
0x43040, // 001000011000001000000
612+
0x43041, // 001000011000001000001
613+
0x45145, // 001000101000101000101
614+
0x47144, // 001000111000101000100
615+
0x47145, // 001000111000101000101
616+
0x64965, // 001100100100101100101
617+
0x65925, // 001100101100100100101
618+
0x65964, // 001100101100101100100
619+
0x65965, // 001100101100101100101
620+
0x67964, // 001100111100101100100
621+
0x0040C, // 000000000010000001100
622+
0x40065, // 001000000000001100101
623+
0x40145, // 001000000000101000101
624+
0x41040, // 001000001000001000000
625+
0x45144, // 001000101000101000100
626+
0x47104, // 001000111000100000100
627+
0x49209, // 001001001001000001001
628+
0x6F965, // 001101111100101100101
629+
0x67965, // 001100111100101100101
630+
0x4F34C, // 001001111001101001100
631+
0x49248, // 001001001001001001000
632+
0x4B248, // 001001011001001001000
633+
};
599634

600635
// ControlIndex Compact Instruction Field Mappings 3 Source Operands BDW/CHV
601636
static uint32_t BDWCompactControlTable3Src[COMPACT_TABLE_SIZE_3SRC]=

‎visa/Common_ISA_util.cpp

+6
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,8 @@ G4_opcode Get_G4_Opcode_From_Common_ISA_Opcode( ISA_Opcode opcode )
120120
return G4_dp4;
121121
case ISA_DPH:
122122
return G4_dph;
123+
case ISA_DP4A:
124+
return G4_dp4a;
123125
case ISA_EXP:
124126
return G4_math;
125127
case ISA_FRC:
@@ -178,6 +180,10 @@ G4_opcode Get_G4_Opcode_From_Common_ISA_Opcode( ISA_Opcode opcode )
178180
return G4_shr;
179181
case ISA_ASR:
180182
return G4_asr;
183+
case ISA_ROL:
184+
return G4_rol;
185+
case ISA_ROR:
186+
return G4_ror;
181187
case ISA_BFE:
182188
return G4_bfe;
183189
case ISA_BFI:

‎visa/Common_ISA_util.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,7 @@ int Get_PreDefined_Surf_Index( int index );
158158

159159
inline bool isShiftOp(ISA_Opcode op)
160160
{
161-
return op == ISA_SHL || op == ISA_SHR || op == ISA_ASR;
161+
return op == ISA_SHL || op == ISA_SHR || op == ISA_ASR || op == ISA_ROL || op == ISA_ROR;
162162
}
163163

164164

‎visa/FlowGraph.cpp

+4
Original file line numberDiff line numberDiff line change
@@ -3964,6 +3964,10 @@ static iga_gen_t getIGAPlatform()
39643964
case GENX_CNL:
39653965
platform = IGA_GEN10;
39663966
break;
3967+
case GENX_ICL:
3968+
case GENX_ICLLP:
3969+
platform = IGA_GEN11;
3970+
break;
39673971
default:
39683972
break;
39693973
}

‎visa/G4Instruction.def

+4-1
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,8 @@ HANDLE_INST( shl, 2, 1, InstTypeArith, GENX_BDW, \
103103
HANDLE_INST( asr, 2, 1, InstTypeArith, GENX_BDW, \
104104
ATTR_NONE )
105105

106+
HANDLE_INST( ror, 2, 1, InstTypeArith, GENX_ICL, ATTR_NONE )
107+
HANDLE_INST( rol, 2, 1, InstTypeArith, GENX_ICL, ATTR_NONE )
106108

107109
HANDLE_INST( math, 2, 1, InstTypeArith, GENX_BDW, \
108110
ATTR_NONE )
@@ -132,7 +134,8 @@ HANDLE_INST( addc, 2, 1, InstTypeArith, GENX_BDW, \
132134
ATTR_NONE )
133135
HANDLE_INST( subb, 2, 1, InstTypeArith, GENX_BDW, \
134136
ATTR_NONE )
135-
137+
138+
HANDLE_INST( dp4a, 3, 1, InstTypeArith, GENX_ICL, ATTR_NONE )
136139

137140
HANDLE_INST( madm , 3, 1, InstTypeArith, GENX_BDW, \
138141
ATTR_NONE )

‎visa/Gen4_IR.cpp

+8
Original file line numberDiff line numberDiff line change
@@ -7011,6 +7011,9 @@ bool G4_INST::canSupportSaturate() const
70117011
case G4_not:
70127012
case G4_or:
70137013
case G4_xor:
7014+
case G4_rol:
7015+
case G4_ror:
7016+
case G4_dp4a:
70147017
case G4_smov:
70157018
return false;
70167019
default:
@@ -7065,6 +7068,7 @@ bool G4_INST::canSupportCondMod(const IR_Builder& builder) const
70657068
(op == G4_dp3) ||
70667069
(op == G4_dp4) ||
70677070
(op == G4_dph) ||
7071+
(op == G4_dp4a) ||
70687072
(op == G4_line) ||
70697073
(op == G4_lrp) ||
70707074
(op == G4_lzd) ||
@@ -7572,6 +7576,8 @@ bool G4_INST::canDstBeAcc(const IR_Builder& builder) const
75727576
case G4_mad:
75737577
case G4_csel:
75747578
return builder.canMadHaveAcc();
7579+
case G4_dp4a:
7580+
return builder.relaxedACCRestrictions2();
75757581
default:
75767582
return false;
75777583
}
@@ -7711,6 +7717,8 @@ bool G4_INST::canSrcBeAcc(int srcId, const IR_Builder& builder) const
77117717
return src->getModifier() == Mod_src_undef;
77127718
case G4_pln:
77137719
return builder.doPlane() && src->getModifier() == Mod_src_undef;
7720+
case G4_dp4a:
7721+
return builder.relaxedACCRestrictions2();
77147722
default:
77157723
return false;
77167724
}

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