Fix a few register regioning issues for 64b instructions on MTL platform

There are a few bug in fix64bInst() which will generate invalid instructions:
Bug #1:
(P09.0) mov (4)     r[A00(0,1), 0]<1>:df  conv96(0,1)<0;1,0>:df
After HWConformity =>
(W&P09.0) mov (1)   TV(0,0)<1>:df  conv96(0,1)<0;1,0>:df // do anything as only 2nd channel enabled
(W) mov (2)   r[A00(0,1), 0]<1>:ud  TV(0,0)<0;2,1>:ud // do all as it's noMask
Bug #2:
mov (8|M8)  reduceSrc_0(2,0)<1>:df  V0210(0,8)<1;1,0>:w
After HWConformity =>
mov (8|M8)    TV56(0,0)<4>:w  V0210(0,8)<1;1,0>:w
mov (8|M8)    TV57(0,0)<1>:df  TV56(0,0)<16;4,4>:w
(W) mov (16)  reduceSrc_0(2,0)<1>:ud  TV57(0,0)<1;1,0>:ud  // noMask is incorrect here

There are two functions which are fix64bInst() and fixUnalignedRegions() to check
the register regioning issue for 64b instructions. fix64bInst() is for all platforms
which have no 64b regioning(CHV, BXT, ICLLP, XeLP, DG2, MTL, ARL). And fixUnalignedRegions()
is for Xe_XeHPSDV+ platforms. So, there are duplicated fixes for some platforms like
DG2, MTL and ARL. We should avoid invoking fix64bInst() for Xe_XeHPSDV+ platforms, and let
fixUnalignedRegions() to fix it later. With this change, above bugs can be fixed.

(cherry picked from commit 620c74c)

Author: fangliu2020

visa/HWConformity.cpp

@@ -5776,8 +5776,12 @@ void HWConformity::conformBB(G4_BB *bb) {
       fixVxHFloat64b(i, bb);
     }
 
-    if (fix64bInst(i, bb)) {
-      continue;
+    if (builder.supportFloatOr64bRegioning()) {
+      // This function is for pre-Xe_XeHPSDV platforms. Xe_XeHPSDV+ platforms
+      // should be fixed in fixUnalignedRegions() later.
+      if (fix64bInst(i, bb)) {
+        continue;
+      }
     }
 
 #ifdef _DEBUG
@@ -5840,6 +5844,15 @@ void HWConformity::conformBB(G4_BB *bb) {
     }
   }
 
+  // Do immdiate Address offset OOB check as previous fixes may generate
+  // invalid ImmAddrOffset.
+  for (auto iter = bb->begin(), iterEnd = bb->end(); iter != iterEnd; ++iter) {
+    fixImmAddrOffsetOOB(iter, bb);
+#ifdef _DEBUG
+    verifyG4Kernel(kernel, Optimizer::PI_HWConformityChk, false);
+#endif
+  }
+
   if (builder.getNativeExecSize() <= g4::SIMD8) {
     return;
   }
@@ -5933,15 +5946,6 @@ void HWConformity::conformBB(G4_BB *bb) {
 #endif
     }
   }
-
-  // Immdiate Address offset OOB check should be put at the end of conformBB
-  // as previous fixes may generate invalid ImmAddrOffset.
-  for (auto iter = bb->begin(), iterEnd = bb->end(); iter != iterEnd; ++iter) {
-    fixImmAddrOffsetOOB(iter, bb);
-#ifdef _DEBUG
-    verifyG4Kernel(kernel, Optimizer::PI_HWConformityChk, false);
-#endif
-  }
 }
 
 //
@@ -9842,7 +9846,9 @@ void HWConformity::fixImmAddrOffsetOOB(INST_LIST_ITER it, G4_BB *bb) {
     //  add(execSize) A(0,0)<1>:uw  A(0,0)<1;1,0>:uw  imm:w
     auto addrDst = builder.createDst(var->getBase(), 0, sregOff, 1, Type_UW);
     auto addrSrc = builder.createSrc(var->getBase(), 0, sregOff,
-                                     builder.getRegionStride1(), Type_UW);
+                                     execSize == 1 ? builder.getRegionScalar()
+                                                   : builder.getRegionStride1(),
+                                     Type_UW);
     auto immSrc = builder.createImm(imm, Type_W);
     auto addrAddInst = builder.createInternalInst(
         nullptr, G4_add, nullptr, g4::NOSAT, G4_ExecSize(execSize), addrDst,