Use load_ugm instruction for predication of an untyped atomic

Current implementation uses send.smpl ld_lz instruction to lookup an accumulator
value of untyped atomic. Adding a mode to use load_ugm instruction instead.

Author: eternastudento

IGC/Compiler/CustomSafeOptPass.cpp

@@ -7194,21 +7194,24 @@ void InsertBranchOpt::atomicSplitOpt(Function& F, int mode)
 {
     enum Mode
     {
-        Disable = 0x0,    // Disabled IGC\EnableAtomicBranch = 0x0
-        ZeroAdd = BIT(0), // Enabled IGC\EnableAtomicBranch = 0x1
-        UMax = BIT(1),    // Enabled IGC\EnableAtomicBranch = 0x2
-        UMin = BIT(2)     // Enabled IGC\EnableAtomicBranch = 0x4
+        Disable = 0x0,          // Disabled IGC\EnableAtomicBranch = 0x0
+        ZeroAdd = BIT(0),       // Enabled IGC\EnableAtomicBranch = 0x1
+        UMax = BIT(1),          // Enabled IGC\EnableAtomicBranch = 0x2
+        UMin = BIT(2),          // Enabled IGC\EnableAtomicBranch = 0x4
+        UntypedUgmLoad = BIT(3) // Enabled IGC\EnableAtomicBranch = 0x8
     };
 
-    // Allow both modes to be applied
-    bool zeroAddMode = ( ( mode & ZeroAdd ) == ZeroAdd );
-    bool umaxMode = ( ( mode & UMax ) == UMax );
-    bool uminMode = ( ( mode & UMin ) == UMin );
+    // Allow several modes to be applied
+    const bool zeroAddMode = ( ( mode & ZeroAdd ) == ZeroAdd );
+    const bool umaxMode = ( ( mode & UMax ) == UMax );
+    const bool uminMode = ( ( mode & UMin ) == UMin );
+    const bool untypedUgmLoadMode = ( ( mode & UntypedUgmLoad ) == UntypedUgmLoad );
 
-    auto createReadFromAtomic = []( IRBuilder<>& builder, Instruction* inst, bool isTyped )
+    auto createReadFromAtomic = [=]( IRBuilder<>& builder, Instruction* inst, bool isTyped )
         {
             Constant* zero = ConstantInt::get( inst->getType(), 0 );
             Instruction* NewInst = nullptr;
+
             if( isTyped )
             {
                 Function* pLdIntrinsic = llvm::GenISAIntrinsic::getDeclaration(
@@ -7228,27 +7231,49 @@ void InsertBranchOpt::atomicSplitOpt(Function& F, int mode)
             {
                 std::vector<Type*> types;
                 std::vector<Value*> ld_FunctionArgList;
-
+                Function* pLdIntrinsic;
                 Value* resourcePtr = inst->getOperand( 0 );
-                types.push_back( IGCLLVM::FixedVectorType::get( builder.getFloatTy(), 4 ) );
-                types.push_back( resourcePtr->getType() );//Paired resource
-                types.push_back( resourcePtr->getType() );//Resource
 
+                // Generate load.ugm instruction
+                if ( untypedUgmLoadMode )
+                {
+                    alignment_t alignment = (alignment_t) (inst->getType()->getScalarSizeInBits() / 8);
+
+                    types.push_back( IGCLLVM::FixedVectorType::get( builder.getFloatTy(), 4 ) );
+                    types.push_back( resourcePtr->getType() );
+                    pLdIntrinsic = GenISAIntrinsic::getDeclaration(
+                        inst->getModule(),
+                        GenISAIntrinsic::GenISA_ldrawvector_indexed,
+                        types );
+
+                    ld_FunctionArgList.push_back( resourcePtr );
+                    ld_FunctionArgList.push_back( inst->getOperand( 1 ) );
+                    ld_FunctionArgList.push_back( builder.getInt32( (uint32_t) alignment ) ); // alignment
+                    ld_FunctionArgList.push_back( builder.getInt1( true ) ); // volatile
+                }
+                // Generate send.smpl ld_lz instruction
+                else
+                {
+                    types.push_back( IGCLLVM::FixedVectorType::get( builder.getFloatTy(), 4 ) );
+                    types.push_back( resourcePtr->getType() );//Paired resource
+                    types.push_back( resourcePtr->getType() );//Resource
+
+                    pLdIntrinsic = GenISAIntrinsic::getDeclaration(
+                        inst->getModule(),
+                        GenISAIntrinsic::GenISA_ldptr,
+                        types );
+
+                    ld_FunctionArgList.push_back( inst->getOperand( 1 ) );    //coordinates x
+                    ld_FunctionArgList.push_back( zero );                   //coordinates y
+                    ld_FunctionArgList.push_back( zero );                   //coordinates z
+                    ld_FunctionArgList.push_back( zero );                   //lod
+                    ld_FunctionArgList.push_back( llvm::UndefValue::get( resourcePtr->getType() ) );
+                    ld_FunctionArgList.push_back( resourcePtr );    //src buffer
+                    ld_FunctionArgList.push_back( zero );                   //immediate offset u
+                    ld_FunctionArgList.push_back( zero );                   //immediate offset v
+                    ld_FunctionArgList.push_back( zero );                   //immediate offset w
+                }
 
-                Function* pLdIntrinsic = GenISAIntrinsic::getDeclaration(
-                    inst->getModule(),
-                    GenISAIntrinsic::GenISA_ldptr,
-                    types );
-
-                ld_FunctionArgList.push_back( inst->getOperand( 1 ) );    //coordinates x
-                ld_FunctionArgList.push_back( zero );                   //coordinates y
-                ld_FunctionArgList.push_back( zero );                   //coordinates z
-                ld_FunctionArgList.push_back( zero );                   //lod
-                ld_FunctionArgList.push_back( llvm::UndefValue::get( inst->getOperand( 0 )->getType() ) );
-                ld_FunctionArgList.push_back( inst->getOperand( 0 ) );    //src buffer
-                ld_FunctionArgList.push_back( zero );                   //immediate offset u
-                ld_FunctionArgList.push_back( zero );                   //immediate offset v
-                ld_FunctionArgList.push_back( zero );                   //immediate offset w
                 NewInst = builder.CreateCall( pLdIntrinsic, ld_FunctionArgList );
             }
 

IGC/common/igc_flags.h

@@ -234,7 +234,7 @@ DECLARE_IGC_REGKEY(debugString, LLVMCommandLine,        0,     "applies LLVM com
 DECLARE_IGC_REGKEY(debugString, SelectiveHashOptions,   0,     "applies options to hash range via string", false)
 DECLARE_IGC_REGKEY(bool, DisableDX9LowPrecision,        true,  "Disables HF in DX9.", false)
 DECLARE_IGC_REGKEY(bool, EnablePingPongTextureOpt,      true,  "Enables the Ping Pong texture optimization which is used only for Compute Shaders for back to back dispatches", false)
-DECLARE_IGC_REGKEY(DWORD,EnableAtomicBranch,            0,     "Bitmask to enable Atomic branch optimization that predicates atomic with if/else. 1: if Val == 0 ignore iadd/sub/umax 0. 2: checks if memory is lower than Val for umax. 4: checks if memory if greater than Val for umin.", false)
+DECLARE_IGC_REGKEY(DWORD,EnableAtomicBranch,            0,     "Bitmask to enable Atomic branch optimization that predicates atomic with if/else. 1: if Val == 0 ignore iadd/sub/umax 0. 2: checks if memory is lower than Val for umax. 4: checks if memory if greater than Val for umin. 8: generate load_ugm for untyped atomics, otherwise ld_lz", false)
 DECLARE_IGC_REGKEY(bool, EnableThreeWayLoadSpiltOpt,    false, "Enable three way load spilt opt.", false)
 DECLARE_IGC_REGKEY(bool, EnableSamplerChannelReturn,    true,  "Setting this to 1/true adds a compiler switch to enable using header to return selective channels from sampler", false)
 DECLARE_IGC_REGKEY(bool, EnableThreadCombiningOpt,      true,  "Enables the thread combining optimization which is used only for Compute Shaders for combining a number of software threads to dispatch smaller number of hardware threads", false)