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weiyu-chensys_zuul
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Convert VF to F when we insert a legalizing move as VF is not a valid destination type.
Change-Id: Ifb882d302a96cd9dae6552fba55f8d97c1fd3a98
1 parent ac2cc85 commit 15fd68c

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+10
-25
lines changed

1 file changed

+10
-25
lines changed

visa/HWConformity.cpp

Lines changed: 10 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -710,7 +710,7 @@ void HWConformity::fixImmAndARFSrc(INST_LIST_ITER it, G4_BB *bb)
710710
src2 = inst->getSrc(2);
711711

712712
/* Check for usage of two constants in binary operations */
713-
if (src0 != NULL && (src0->isImm() || src0->isAddrExp()) && inst->getNumSrc() == 2)
713+
if (src0 && (src0->isImm() || src0->isAddrExp()) && inst->getNumSrc() == 2)
714714
{
715715
if (INST_COMMUTATIVE(inst->opcode()) && !src1->isImm())
716716
{
@@ -753,26 +753,18 @@ void HWConformity::fixImmAndARFSrc(INST_LIST_ITER it, G4_BB *bb)
753753
*/
754754
else if (inst->opcode() == G4_sel && !src1->isImm())
755755
{
756-
bool SwapOpnd = false;
757756
G4_CondMod *cond = inst->getCondMod();
758-
if (cond != NULL)
757+
if (cond)
759758
{
760759
switch (cond->getMod())
761760
{
762761
case Mod_ne:
763-
{
764762
inst->setCondMod(builder.createCondMod(Mod_e, cond->getBase(), 0));
765-
SwapOpnd = true;
766763
break;
767-
}
768764
case Mod_e:
769-
{
770765
inst->setCondMod(builder.createCondMod(Mod_ne, cond->getBase(), 0));
771-
SwapOpnd = true;
772766
break;
773-
}
774767
default:
775-
SwapOpnd = true;
776768
break;
777769
}
778770
}
@@ -783,21 +775,10 @@ void HWConformity::fixImmAndARFSrc(INST_LIST_ITER it, G4_BB *bb)
783775
G4_PredState reverse = pred->getState() == PredState_Minus ? PredState_Plus : PredState_Minus;
784776
inst->setPredicate(builder.createPredicate(
785777
reverse, pred->getBase(), pred->getSubRegOff(), pred->getControl()));
786-
SwapOpnd = true;
787-
}
788-
789-
if (SwapOpnd)
790-
{
791-
inst->setSrc(src1, 0);
792-
inst->setSrc(src0, 1);
793-
inst->swapDefUse();
794-
}
795-
else
796-
{
797-
G4_Type tmpType = getNonVectorType(src0->getType());
798-
G4_Operand* newSrc0 = insertMovBefore(it, 0, tmpType, bb);
799-
inst->setSrc(newSrc0, 0);
800778
}
779+
inst->setSrc(src1, 0);
780+
inst->setSrc(src0, 1);
781+
inst->swapDefUse();
801782
}
802783
else if (!inst->isMath())
803784
{
@@ -823,6 +804,7 @@ void HWConformity::fixImmAndARFSrc(INST_LIST_ITER it, G4_BB *bb)
823804
{
824805
newSrc = builder.createImmWithLowerType(res, resultType);
825806

807+
// change instruction into a MOV
826808
// change instruction into a MOV
827809
inst->setOpcode(G4_mov);
828810
inst->setSrc(newSrc, 0);
@@ -841,7 +823,9 @@ void HWConformity::fixImmAndARFSrc(INST_LIST_ITER it, G4_BB *bb)
841823
inst->swapDefUse();
842824
src0 = inst->getSrc(0);
843825
src1 = inst->getSrc(1);
826+
// this needs to fall through as we still need move for src0
844827
}
828+
845829
if (INST_COMMUTATIVE(inst->opcode()) && src0->isAddrExp() && src1->isImm())
846830
{
847831
// The original IR has both addr expr and immediate
@@ -862,7 +846,8 @@ void HWConformity::fixImmAndARFSrc(INST_LIST_ITER it, G4_BB *bb)
862846
}
863847
else
864848
{
865-
G4_Type newSrcType = inst->needsDWType() ? (IS_UNSIGNED_INT(src0->getType()) ? Type_UD : Type_D) : src0->getType();
849+
G4_Type newSrcType = inst->needsDWType() ? (IS_UNSIGNED_INT(src0->getType()) ? Type_UD : Type_D) :
850+
getNonVectorType(src0->getType());
866851
inst->setSrc(insertMovBefore(it, 0, newSrcType, bb), 0);
867852
}
868853
}

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