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@@ -15,7 +15,9 @@ These goals should define the future development of the library.
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- It does not need to exactly replicate the syntax and oddities of SystemVerilog, but it must adhere to the principle of declariative randomization.
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- Repeatable, i.e. works deterministically with the same seed.
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- Fast. Or at least as fast as can be expected from a Python library rather than say C/C++.
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- Originally, the creation of the library was motivated by [`pyvsc`](https://github.com/fvutils/pyvsc). `pyvsc` is feature-rich and user-friendly for those with an SV background, but not fast enough for production usage.
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- Originally, the creation of the library was motivated by [`pyvsc`](https://github.com/fvutils/pyvsc).
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-`pyvsc` is feature-rich and user-friendly for those with an SV background, but we found it was not fast enough for production usage.
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- This library aims to achieve at least a 10x speedup over `pyvsc`. See the `benchmarks/` directory or run `python -m benchmarks` for testing.
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## Motivation
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Why bother with a Python library for this? Why not just use procedural randomization?
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